hw/char/exynos4210_uart.c

   1 /*
   2  *  Exynos4210 UART Emulation
   3  *
   4  *  Copyright (C) 2011 Samsung Electronics Co Ltd.
   5  *    Maksim Kozlov, <m.kozlov@samsung.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License as published by the
   9  *  Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/sysbus.h"
  24 #include "qemu/error-report.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/char.h"
  27
  28 #include "hw/arm/exynos4210.h"
  29
  30 #undef DEBUG_UART
  31 #undef DEBUG_UART_EXTEND
  32 #undef DEBUG_IRQ
  33 #undef DEBUG_Rx_DATA
  34 #undef DEBUG_Tx_DATA
  35
  36 #define DEBUG_UART            0
  37 #define DEBUG_UART_EXTEND     0
  38 #define DEBUG_IRQ             0
  39 #define DEBUG_Rx_DATA         0
  40 #define DEBUG_Tx_DATA         0
  41
  42 #if DEBUG_UART
  43 #define  PRINT_DEBUG(fmt, args...)  \
  44         do { \
  45             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  46         } while (0)
  47
  48 #if DEBUG_UART_EXTEND
  49 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  50         do { \
  51             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  52         } while (0)
  53 #else
  54 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  55         do {} while (0)
  56 #endif /* EXTEND */
  57
  58 #else
  59 #define  PRINT_DEBUG(fmt, args...)  \
  60         do {} while (0)
  61 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  62         do {} while (0)
  63 #endif
  64
  65 #define  PRINT_ERROR(fmt, args...) \
  66         do { \
  67             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  68         } while (0)
  69
  70 /*
  71  *  Offsets for UART registers relative to SFR base address
  72  *  for UARTn
  73  *
  74  */
  75 #define ULCON      0x0000 /* Line Control             */
  76 #define UCON       0x0004 /* Control                  */
  77 #define UFCON      0x0008 /* FIFO Control             */
  78 #define UMCON      0x000C /* Modem Control            */
  79 #define UTRSTAT    0x0010 /* Tx/Rx Status             */
  80 #define UERSTAT    0x0014 /* UART Error Status        */
  81 #define UFSTAT     0x0018 /* FIFO Status              */
  82 #define UMSTAT     0x001C /* Modem Status             */
  83 #define UTXH       0x0020 /* Transmit Buffer          */
  84 #define URXH       0x0024 /* Receive Buffer           */
  85 #define UBRDIV     0x0028 /* Baud Rate Divisor        */
  86 #define UFRACVAL   0x002C /* Divisor Fractional Value */
  87 #define UINTP      0x0030 /* Interrupt Pending        */
  88 #define UINTSP     0x0034 /* Interrupt Source Pending */
  89 #define UINTM      0x0038 /* Interrupt Mask           */
  90
  91 /*
  92  * for indexing register in the uint32_t array
  93  *
  94  * 'reg' - register offset (see offsets definitions above)
  95  *
  96  */
  97 #define I_(reg) (reg / sizeof(uint32_t))
  98
  99 typedef struct Exynos4210UartReg {
 100     const char         *name; /* the only reason is the debug output */
 101     hwaddr  offset;
 102     uint32_t            reset_value;
 103 } Exynos4210UartReg;
 104
 105 static Exynos4210UartReg exynos4210_uart_regs[] = {
 106     {"ULCON",    ULCON,    0x00000000},
 107     {"UCON",     UCON,     0x00003000},
 108     {"UFCON",    UFCON,    0x00000000},
 109     {"UMCON",    UMCON,    0x00000000},
 110     {"UTRSTAT",  UTRSTAT,  0x00000006}, /* RO */
 111     {"UERSTAT",  UERSTAT,  0x00000000}, /* RO */
 112     {"UFSTAT",   UFSTAT,   0x00000000}, /* RO */
 113     {"UMSTAT",   UMSTAT,   0x00000000}, /* RO */
 114     {"UTXH",     UTXH,     0x5c5c5c5c}, /* WO, undefined reset value*/
 115     {"URXH",     URXH,     0x00000000}, /* RO */
 116     {"UBRDIV",   UBRDIV,   0x00000000},
 117     {"UFRACVAL", UFRACVAL, 0x00000000},
 118     {"UINTP",    UINTP,    0x00000000},
 119     {"UINTSP",   UINTSP,   0x00000000},
 120     {"UINTM",    UINTM,    0x00000000},
 121 };
 122
 123 #define EXYNOS4210_UART_REGS_MEM_SIZE    0x3C
 124
 125 /* UART FIFO Control */
 126 #define UFCON_FIFO_ENABLE                    0x1
 127 #define UFCON_Rx_FIFO_RESET                  0x2
 128 #define UFCON_Tx_FIFO_RESET                  0x4
 129 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT    8
 130 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
 131 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT    4
 132 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
 133
 134 /* Uart FIFO Status */
 135 #define UFSTAT_Rx_FIFO_COUNT        0xff
 136 #define UFSTAT_Rx_FIFO_FULL         0x100
 137 #define UFSTAT_Rx_FIFO_ERROR        0x200
 138 #define UFSTAT_Tx_FIFO_COUNT_SHIFT  16
 139 #define UFSTAT_Tx_FIFO_COUNT        (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
 140 #define UFSTAT_Tx_FIFO_FULL_SHIFT   24
 141 #define UFSTAT_Tx_FIFO_FULL         (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
 142
 143 /* UART Interrupt Source Pending */
 144 #define UINTSP_RXD      0x1 /* Receive interrupt  */
 145 #define UINTSP_ERROR    0x2 /* Error interrupt    */
 146 #define UINTSP_TXD      0x4 /* Transmit interrupt */
 147 #define UINTSP_MODEM    0x8 /* Modem interrupt    */
 148
 149 /* UART Line Control */
 150 #define ULCON_IR_MODE_SHIFT   6
 151 #define ULCON_PARITY_SHIFT    3
 152 #define ULCON_STOP_BIT_SHIFT  1
 153
 154 /* UART Tx/Rx Status */
 155 #define UTRSTAT_TRANSMITTER_EMPTY       0x4
 156 #define UTRSTAT_Tx_BUFFER_EMPTY         0x2
 157 #define UTRSTAT_Rx_BUFFER_DATA_READY    0x1
 158
 159 /* UART Error Status */
 160 #define UERSTAT_OVERRUN  0x1
 161 #define UERSTAT_PARITY   0x2
 162 #define UERSTAT_FRAME    0x4
 163 #define UERSTAT_BREAK    0x8
 164
 165 typedef struct {
 166     uint8_t    *data;
 167     uint32_t    sp, rp; /* store and retrieve pointers */
 168     uint32_t    size;
 169 } Exynos4210UartFIFO;
 170
 171 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
 172 #define EXYNOS4210_UART(obj) \
 173     OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
 174
 175 typedef struct Exynos4210UartState {
 176     SysBusDevice parent_obj;
 177
 178     MemoryRegion iomem;
 179
 180     uint32_t             reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
 181     Exynos4210UartFIFO   rx;
 182     Exynos4210UartFIFO   tx;
 183
 184     CharBackend       chr;
 185     qemu_irq          irq;
 186
 187     uint32_t channel;
 188
 189 } Exynos4210UartState;
 190
 191
 192 #if DEBUG_UART
 193 /* Used only for debugging inside PRINT_DEBUG_... macros */
 194 static const char *exynos4210_uart_regname(hwaddr  offset)
 195 {
 196
 197     int i;
 198
 199     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 200         if (offset == exynos4210_uart_regs[i].offset) {
 201             return exynos4210_uart_regs[i].name;
 202         }
 203     }
 204
 205     return NULL;
 206 }
 207 #endif
 208
 209
 210 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
 211 {
 212     q->data[q->sp] = ch;
 213     q->sp = (q->sp + 1) % q->size;
 214 }
 215
 216 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
 217 {
 218     uint8_t ret = q->data[q->rp];
 219     q->rp = (q->rp + 1) % q->size;
 220     return  ret;
 221 }
 222
 223 static int fifo_elements_number(Exynos4210UartFIFO *q)
 224 {
 225     if (q->sp < q->rp) {
 226         return q->size - q->rp + q->sp;
 227     }
 228
 229     return q->sp - q->rp;
 230 }
 231
 232 static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
 233 {
 234     return q->size - fifo_elements_number(q);
 235 }
 236
 237 static void fifo_reset(Exynos4210UartFIFO *q)
 238 {
 239     g_free(q->data);
 240     q->data = NULL;
 241
 242     q->data = (uint8_t *)g_malloc0(q->size);
 243
 244     q->sp = 0;
 245     q->rp = 0;
 246 }
 247
 248 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
 249 {
 250     uint32_t level = 0;
 251     uint32_t reg;
 252
 253     reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
 254             UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
 255
 256     switch (s->channel) {
 257     case 0:
 258         level = reg * 32;
 259         break;
 260     case 1:
 261     case 4:
 262         level = reg * 8;
 263         break;
 264     case 2:
 265     case 3:
 266         level = reg * 2;
 267         break;
 268     default:
 269         level = 0;
 270         PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
 271     }
 272
 273     return level;
 274 }
 275
 276 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
 277 {
 278     /*
 279      * The Tx interrupt is always requested if the number of data in the
 280      * transmit FIFO is smaller than the trigger level.
 281      */
 282     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 283
 284         uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
 285                 UFSTAT_Tx_FIFO_COUNT_SHIFT;
 286
 287         if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
 288             s->reg[I_(UINTSP)] |= UINTSP_TXD;
 289         }
 290     }
 291
 292     s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
 293
 294     if (s->reg[I_(UINTP)]) {
 295         qemu_irq_raise(s->irq);
 296
 297 #if DEBUG_IRQ
 298         fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
 299                 s->channel, s->reg[I_(UINTP)]);
 300 #endif
 301
 302     } else {
 303         qemu_irq_lower(s->irq);
 304     }
 305 }
 306
 307 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
 308 {
 309     int speed, parity, data_bits, stop_bits;
 310     QEMUSerialSetParams ssp;
 311     uint64_t uclk_rate;
 312
 313     if (s->reg[I_(UBRDIV)] == 0) {
 314         return;
 315     }
 316
 317     if (s->reg[I_(ULCON)] & 0x20) {
 318         if (s->reg[I_(ULCON)] & 0x28) {
 319             parity = 'E';
 320         } else {
 321             parity = 'O';
 322         }
 323     } else {
 324         parity = 'N';
 325     }
 326
 327     if (s->reg[I_(ULCON)] & 0x4) {
 328         stop_bits = 2;
 329     } else {
 330         stop_bits = 1;
 331     }
 332
 333     data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
 334
 335     uclk_rate = 24000000;
 336
 337     speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
 338             (s->reg[I_(UFRACVAL)] & 0x7) + 16);
 339
 340     ssp.speed     = speed;
 341     ssp.parity    = parity;
 342     ssp.data_bits = data_bits;
 343     ssp.stop_bits = stop_bits;
 344
 345     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 346
 347     PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
 348                 s->channel, speed, parity, data_bits, stop_bits);
 349 }
 350
 351 static void exynos4210_uart_write(void *opaque, hwaddr offset,
 352                                uint64_t val, unsigned size)
 353 {
 354     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 355     uint8_t ch;
 356
 357     PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
 358         offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
 359
 360     switch (offset) {
 361     case ULCON:
 362     case UBRDIV:
 363     case UFRACVAL:
 364         s->reg[I_(offset)] = val;
 365         exynos4210_uart_update_parameters(s);
 366         break;
 367     case UFCON:
 368         s->reg[I_(UFCON)] = val;
 369         if (val & UFCON_Rx_FIFO_RESET) {
 370             fifo_reset(&s->rx);
 371             s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
 372             PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
 373         }
 374         if (val & UFCON_Tx_FIFO_RESET) {
 375             fifo_reset(&s->tx);
 376             s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
 377             PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
 378         }
 379         break;
 380
 381     case UTXH:
 382         if (qemu_chr_fe_get_driver(&s->chr)) {
 383             s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
 384                     UTRSTAT_Tx_BUFFER_EMPTY);
 385             ch = (uint8_t)val;
 386             /* XXX this blocks entire thread. Rewrite to use
 387              * qemu_chr_fe_write and background I/O callbacks */
 388             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 389 #if DEBUG_Tx_DATA
 390             fprintf(stderr, "%c", ch);
 391 #endif
 392             s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
 393                     UTRSTAT_Tx_BUFFER_EMPTY;
 394             s->reg[I_(UINTSP)]  |= UINTSP_TXD;
 395             exynos4210_uart_update_irq(s);
 396         }
 397         break;
 398
 399     case UINTP:
 400         s->reg[I_(UINTP)] &= ~val;
 401         s->reg[I_(UINTSP)] &= ~val;
 402         PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
 403                     s->channel, offset, s->reg[I_(UINTP)]);
 404         exynos4210_uart_update_irq(s);
 405         break;
 406     case UTRSTAT:
 407     case UERSTAT:
 408     case UFSTAT:
 409     case UMSTAT:
 410     case URXH:
 411         PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
 412                     s->channel, exynos4210_uart_regname(offset), offset);
 413         break;
 414     case UINTSP:
 415         s->reg[I_(UINTSP)]  &= ~val;
 416         break;
 417     case UINTM:
 418         s->reg[I_(UINTM)] = val;
 419         exynos4210_uart_update_irq(s);
 420         break;
 421     case UCON:
 422     case UMCON:
 423     default:
 424         s->reg[I_(offset)] = val;
 425         break;
 426     }
 427 }
 428 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
 429                                   unsigned size)
 430 {
 431     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 432     uint32_t res;
 433
 434     switch (offset) {
 435     case UERSTAT: /* Read Only */
 436         res = s->reg[I_(UERSTAT)];
 437         s->reg[I_(UERSTAT)] = 0;
 438         return res;
 439     case UFSTAT: /* Read Only */
 440         s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
 441         if (fifo_empty_elements_number(&s->rx) == 0) {
 442             s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
 443             s->reg[I_(UFSTAT)] &= ~0xff;
 444         }
 445         return s->reg[I_(UFSTAT)];
 446     case URXH:
 447         if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 448             if (fifo_elements_number(&s->rx)) {
 449                 res = fifo_retrieve(&s->rx);
 450 #if DEBUG_Rx_DATA
 451                 fprintf(stderr, "%c", res);
 452 #endif
 453                 if (!fifo_elements_number(&s->rx)) {
 454                     s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 455                 } else {
 456                     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 457                 }
 458             } else {
 459                 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 460                 exynos4210_uart_update_irq(s);
 461                 res = 0;
 462             }
 463         } else {
 464             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 465             res = s->reg[I_(URXH)];
 466         }
 467         return res;
 468     case UTXH:
 469         PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
 470                     s->channel, exynos4210_uart_regname(offset), offset);
 471         break;
 472     default:
 473         return s->reg[I_(offset)];
 474     }
 475
 476     return 0;
 477 }
 478
 479 static const MemoryRegionOps exynos4210_uart_ops = {
 480     .read = exynos4210_uart_read,
 481     .write = exynos4210_uart_write,
 482     .endianness = DEVICE_NATIVE_ENDIAN,
 483     .valid = {
 484         .max_access_size = 4,
 485         .unaligned = false
 486     },
 487 };
 488
 489 static int exynos4210_uart_can_receive(void *opaque)
 490 {
 491     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 492
 493     return fifo_empty_elements_number(&s->rx);
 494 }
 495
 496
 497 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
 498 {
 499     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 500     int i;
 501
 502     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 503         if (fifo_empty_elements_number(&s->rx) < size) {
 504             for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
 505                 fifo_store(&s->rx, buf[i]);
 506             }
 507             s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 508             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 509         } else {
 510             for (i = 0; i < size; i++) {
 511                 fifo_store(&s->rx, buf[i]);
 512             }
 513             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 514         }
 515         /* XXX: Around here we maybe should check Rx trigger level */
 516         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 517     } else {
 518         s->reg[I_(URXH)] = buf[0];
 519         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 520         s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 521     }
 522
 523     exynos4210_uart_update_irq(s);
 524 }
 525
 526
 527 static void exynos4210_uart_event(void *opaque, int event)
 528 {
 529     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 530
 531     if (event == CHR_EVENT_BREAK) {
 532         /* When the RxDn is held in logic 0, then a null byte is pushed into the
 533          * fifo */
 534         fifo_store(&s->rx, '\0');
 535         s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
 536         exynos4210_uart_update_irq(s);
 537     }
 538 }
 539
 540
 541 static void exynos4210_uart_reset(DeviceState *dev)
 542 {
 543     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 544     int i;
 545
 546     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 547         s->reg[I_(exynos4210_uart_regs[i].offset)] =
 548                 exynos4210_uart_regs[i].reset_value;
 549     }
 550
 551     fifo_reset(&s->rx);
 552     fifo_reset(&s->tx);
 553
 554     PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
 555 }
 556
 557 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
 558     .name = "exynos4210.uart.fifo",
 559     .version_id = 1,
 560     .minimum_version_id = 1,
 561     .fields = (VMStateField[]) {
 562         VMSTATE_UINT32(sp, Exynos4210UartFIFO),
 563         VMSTATE_UINT32(rp, Exynos4210UartFIFO),
 564         VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size),
 565         VMSTATE_END_OF_LIST()
 566     }
 567 };
 568
 569 static const VMStateDescription vmstate_exynos4210_uart = {
 570     .name = "exynos4210.uart",
 571     .version_id = 1,
 572     .minimum_version_id = 1,
 573     .fields = (VMStateField[]) {
 574         VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
 575                        vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
 576         VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
 577                              EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
 578         VMSTATE_END_OF_LIST()
 579     }
 580 };
 581
 582 DeviceState *exynos4210_uart_create(hwaddr addr,
 583                                     int fifo_size,
 584                                     int channel,
 585                                     Chardev *chr,
 586                                     qemu_irq irq)
 587 {
 588     DeviceState  *dev;
 589     SysBusDevice *bus;
 590
 591     const char chr_name[] = "serial";
 592     char label[ARRAY_SIZE(chr_name) + 1];
 593
 594     dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
 595
 596     if (!chr) {
 597         if (channel >= MAX_SERIAL_PORTS) {
 598             error_report("Only %d serial ports are supported by QEMU",
 599                          MAX_SERIAL_PORTS);
 600             exit(1);
 601         }
 602         chr = serial_hds[channel];
 603         if (!chr) {
 604             snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
 605             chr = qemu_chr_new(label, "null");
 606             if (!(chr)) {
 607                 error_report("Can't assign serial port to UART%d", channel);
 608                 exit(1);
 609             }
 610         }
 611     }
 612
 613     qdev_prop_set_chr(dev, "chardev", chr);
 614     qdev_prop_set_uint32(dev, "channel", channel);
 615     qdev_prop_set_uint32(dev, "rx-size", fifo_size);
 616     qdev_prop_set_uint32(dev, "tx-size", fifo_size);
 617
 618     bus = SYS_BUS_DEVICE(dev);
 619     qdev_init_nofail(dev);
 620     if (addr != (hwaddr)-1) {
 621         sysbus_mmio_map(bus, 0, addr);
 622     }
 623     sysbus_connect_irq(bus, 0, irq);
 624
 625     return dev;
 626 }
 627
 628 static void exynos4210_uart_init(Object *obj)
 629 {
 630     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 631     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 632
 633     /* memory mapping */
 634     memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
 635                           "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
 636     sysbus_init_mmio(dev, &s->iomem);
 637
 638     sysbus_init_irq(dev, &s->irq);
 639 }
 640
 641 static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
 642 {
 643     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 644
 645     qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
 646                              exynos4210_uart_receive, exynos4210_uart_event,
 647                              s, NULL, true);
 648 }
 649
 650 static Property exynos4210_uart_properties[] = {
 651     DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
 652     DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
 653     DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
 654     DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
 655     DEFINE_PROP_END_OF_LIST(),
 656 };
 657
 658 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
 659 {
 660     DeviceClass *dc = DEVICE_CLASS(klass);
 661
 662     dc->realize = exynos4210_uart_realize;
 663     dc->reset = exynos4210_uart_reset;
 664     dc->props = exynos4210_uart_properties;
 665     dc->vmsd = &vmstate_exynos4210_uart;
 666 }
 667
 668 static const TypeInfo exynos4210_uart_info = {
 669     .name          = TYPE_EXYNOS4210_UART,
 670     .parent        = TYPE_SYS_BUS_DEVICE,
 671     .instance_size = sizeof(Exynos4210UartState),
 672     .instance_init = exynos4210_uart_init,
 673     .class_init    = exynos4210_uart_class_init,
 674 };
 675
 676 static void exynos4210_uart_register(void)
 677 {
 678     type_register_static(&exynos4210_uart_info);
 679 }
 680
 681 type_init(exynos4210_uart_register)