2 * Exynos4210 UART Emulation
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/char.h"
28 #include "hw/arm/exynos4210.h"
31 #undef DEBUG_UART_EXTEND
37 #define DEBUG_UART_EXTEND 0
39 #define DEBUG_Rx_DATA 0
40 #define DEBUG_Tx_DATA 0
43 #define PRINT_DEBUG(fmt, args...) \
45 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
49 #define PRINT_DEBUG_EXTEND(fmt, args...) \
51 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
54 #define PRINT_DEBUG_EXTEND(fmt, args...) \
59 #define PRINT_DEBUG(fmt, args...) \
61 #define PRINT_DEBUG_EXTEND(fmt, args...) \
65 #define PRINT_ERROR(fmt, args...) \
67 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
71 * Offsets for UART registers relative to SFR base address
75 #define ULCON 0x0000 /* Line Control */
76 #define UCON 0x0004 /* Control */
77 #define UFCON 0x0008 /* FIFO Control */
78 #define UMCON 0x000C /* Modem Control */
79 #define UTRSTAT 0x0010 /* Tx/Rx Status */
80 #define UERSTAT 0x0014 /* UART Error Status */
81 #define UFSTAT 0x0018 /* FIFO Status */
82 #define UMSTAT 0x001C /* Modem Status */
83 #define UTXH 0x0020 /* Transmit Buffer */
84 #define URXH 0x0024 /* Receive Buffer */
85 #define UBRDIV 0x0028 /* Baud Rate Divisor */
86 #define UFRACVAL 0x002C /* Divisor Fractional Value */
87 #define UINTP 0x0030 /* Interrupt Pending */
88 #define UINTSP 0x0034 /* Interrupt Source Pending */
89 #define UINTM 0x0038 /* Interrupt Mask */
92 * for indexing register in the uint32_t array
94 * 'reg' - register offset (see offsets definitions above)
97 #define I_(reg) (reg / sizeof(uint32_t))
99 typedef struct Exynos4210UartReg
{
100 const char *name
; /* the only reason is the debug output */
102 uint32_t reset_value
;
105 static Exynos4210UartReg exynos4210_uart_regs
[] = {
106 {"ULCON", ULCON
, 0x00000000},
107 {"UCON", UCON
, 0x00003000},
108 {"UFCON", UFCON
, 0x00000000},
109 {"UMCON", UMCON
, 0x00000000},
110 {"UTRSTAT", UTRSTAT
, 0x00000006}, /* RO */
111 {"UERSTAT", UERSTAT
, 0x00000000}, /* RO */
112 {"UFSTAT", UFSTAT
, 0x00000000}, /* RO */
113 {"UMSTAT", UMSTAT
, 0x00000000}, /* RO */
114 {"UTXH", UTXH
, 0x5c5c5c5c}, /* WO, undefined reset value*/
115 {"URXH", URXH
, 0x00000000}, /* RO */
116 {"UBRDIV", UBRDIV
, 0x00000000},
117 {"UFRACVAL", UFRACVAL
, 0x00000000},
118 {"UINTP", UINTP
, 0x00000000},
119 {"UINTSP", UINTSP
, 0x00000000},
120 {"UINTM", UINTM
, 0x00000000},
123 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
125 /* UART FIFO Control */
126 #define UFCON_FIFO_ENABLE 0x1
127 #define UFCON_Rx_FIFO_RESET 0x2
128 #define UFCON_Tx_FIFO_RESET 0x4
129 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
130 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
131 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
132 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
134 /* Uart FIFO Status */
135 #define UFSTAT_Rx_FIFO_COUNT 0xff
136 #define UFSTAT_Rx_FIFO_FULL 0x100
137 #define UFSTAT_Rx_FIFO_ERROR 0x200
138 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
139 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
140 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
141 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
143 /* UART Interrupt Source Pending */
144 #define UINTSP_RXD 0x1 /* Receive interrupt */
145 #define UINTSP_ERROR 0x2 /* Error interrupt */
146 #define UINTSP_TXD 0x4 /* Transmit interrupt */
147 #define UINTSP_MODEM 0x8 /* Modem interrupt */
149 /* UART Line Control */
150 #define ULCON_IR_MODE_SHIFT 6
151 #define ULCON_PARITY_SHIFT 3
152 #define ULCON_STOP_BIT_SHIFT 1
154 /* UART Tx/Rx Status */
155 #define UTRSTAT_TRANSMITTER_EMPTY 0x4
156 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
157 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
159 /* UART Error Status */
160 #define UERSTAT_OVERRUN 0x1
161 #define UERSTAT_PARITY 0x2
162 #define UERSTAT_FRAME 0x4
163 #define UERSTAT_BREAK 0x8
167 uint32_t sp
, rp
; /* store and retrieve pointers */
169 } Exynos4210UartFIFO
;
171 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
172 #define EXYNOS4210_UART(obj) \
173 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
175 typedef struct Exynos4210UartState
{
176 SysBusDevice parent_obj
;
180 uint32_t reg
[EXYNOS4210_UART_REGS_MEM_SIZE
/ sizeof(uint32_t)];
181 Exynos4210UartFIFO rx
;
182 Exynos4210UartFIFO tx
;
189 } Exynos4210UartState
;
193 /* Used only for debugging inside PRINT_DEBUG_... macros */
194 static const char *exynos4210_uart_regname(hwaddr offset
)
199 for (i
= 0; i
< ARRAY_SIZE(exynos4210_uart_regs
); i
++) {
200 if (offset
== exynos4210_uart_regs
[i
].offset
) {
201 return exynos4210_uart_regs
[i
].name
;
210 static void fifo_store(Exynos4210UartFIFO
*q
, uint8_t ch
)
213 q
->sp
= (q
->sp
+ 1) % q
->size
;
216 static uint8_t fifo_retrieve(Exynos4210UartFIFO
*q
)
218 uint8_t ret
= q
->data
[q
->rp
];
219 q
->rp
= (q
->rp
+ 1) % q
->size
;
223 static int fifo_elements_number(Exynos4210UartFIFO
*q
)
226 return q
->size
- q
->rp
+ q
->sp
;
229 return q
->sp
- q
->rp
;
232 static int fifo_empty_elements_number(Exynos4210UartFIFO
*q
)
234 return q
->size
- fifo_elements_number(q
);
237 static void fifo_reset(Exynos4210UartFIFO
*q
)
242 q
->data
= (uint8_t *)g_malloc0(q
->size
);
248 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState
*s
)
253 reg
= (s
->reg
[I_(UFCON
)] & UFCON_Tx_FIFO_TRIGGER_LEVEL
) >>
254 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT
;
256 switch (s
->channel
) {
270 PRINT_ERROR("Wrong UART channel number: %d\n", s
->channel
);
276 static void exynos4210_uart_update_irq(Exynos4210UartState
*s
)
279 * The Tx interrupt is always requested if the number of data in the
280 * transmit FIFO is smaller than the trigger level.
282 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
284 uint32_t count
= (s
->reg
[I_(UFSTAT
)] & UFSTAT_Tx_FIFO_COUNT
) >>
285 UFSTAT_Tx_FIFO_COUNT_SHIFT
;
287 if (count
<= exynos4210_uart_Tx_FIFO_trigger_level(s
)) {
288 s
->reg
[I_(UINTSP
)] |= UINTSP_TXD
;
292 s
->reg
[I_(UINTP
)] = s
->reg
[I_(UINTSP
)] & ~s
->reg
[I_(UINTM
)];
294 if (s
->reg
[I_(UINTP
)]) {
295 qemu_irq_raise(s
->irq
);
298 fprintf(stderr
, "UART%d: IRQ has been raised: %08x\n",
299 s
->channel
, s
->reg
[I_(UINTP
)]);
303 qemu_irq_lower(s
->irq
);
307 static void exynos4210_uart_update_parameters(Exynos4210UartState
*s
)
309 int speed
, parity
, data_bits
, stop_bits
;
310 QEMUSerialSetParams ssp
;
313 if (s
->reg
[I_(UBRDIV
)] == 0) {
317 if (s
->reg
[I_(ULCON
)] & 0x20) {
318 if (s
->reg
[I_(ULCON
)] & 0x28) {
327 if (s
->reg
[I_(ULCON
)] & 0x4) {
333 data_bits
= (s
->reg
[I_(ULCON
)] & 0x3) + 5;
335 uclk_rate
= 24000000;
337 speed
= uclk_rate
/ ((16 * (s
->reg
[I_(UBRDIV
)]) & 0xffff) +
338 (s
->reg
[I_(UFRACVAL
)] & 0x7) + 16);
342 ssp
.data_bits
= data_bits
;
343 ssp
.stop_bits
= stop_bits
;
345 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
347 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
348 s
->channel
, speed
, parity
, data_bits
, stop_bits
);
351 static void exynos4210_uart_write(void *opaque
, hwaddr offset
,
352 uint64_t val
, unsigned size
)
354 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
357 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s
->channel
,
358 offset
, exynos4210_uart_regname(offset
), (long long unsigned int)val
);
364 s
->reg
[I_(offset
)] = val
;
365 exynos4210_uart_update_parameters(s
);
368 s
->reg
[I_(UFCON
)] = val
;
369 if (val
& UFCON_Rx_FIFO_RESET
) {
371 s
->reg
[I_(UFCON
)] &= ~UFCON_Rx_FIFO_RESET
;
372 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s
->channel
);
374 if (val
& UFCON_Tx_FIFO_RESET
) {
376 s
->reg
[I_(UFCON
)] &= ~UFCON_Tx_FIFO_RESET
;
377 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s
->channel
);
382 if (qemu_chr_fe_get_driver(&s
->chr
)) {
383 s
->reg
[I_(UTRSTAT
)] &= ~(UTRSTAT_TRANSMITTER_EMPTY
|
384 UTRSTAT_Tx_BUFFER_EMPTY
);
386 /* XXX this blocks entire thread. Rewrite to use
387 * qemu_chr_fe_write and background I/O callbacks */
388 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
390 fprintf(stderr
, "%c", ch
);
392 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_TRANSMITTER_EMPTY
|
393 UTRSTAT_Tx_BUFFER_EMPTY
;
394 s
->reg
[I_(UINTSP
)] |= UINTSP_TXD
;
395 exynos4210_uart_update_irq(s
);
400 s
->reg
[I_(UINTP
)] &= ~val
;
401 s
->reg
[I_(UINTSP
)] &= ~val
;
402 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
403 s
->channel
, offset
, s
->reg
[I_(UINTP
)]);
404 exynos4210_uart_update_irq(s
);
411 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
412 s
->channel
, exynos4210_uart_regname(offset
), offset
);
415 s
->reg
[I_(UINTSP
)] &= ~val
;
418 s
->reg
[I_(UINTM
)] = val
;
419 exynos4210_uart_update_irq(s
);
424 s
->reg
[I_(offset
)] = val
;
428 static uint64_t exynos4210_uart_read(void *opaque
, hwaddr offset
,
431 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
435 case UERSTAT
: /* Read Only */
436 res
= s
->reg
[I_(UERSTAT
)];
437 s
->reg
[I_(UERSTAT
)] = 0;
439 case UFSTAT
: /* Read Only */
440 s
->reg
[I_(UFSTAT
)] = fifo_elements_number(&s
->rx
) & 0xff;
441 if (fifo_empty_elements_number(&s
->rx
) == 0) {
442 s
->reg
[I_(UFSTAT
)] |= UFSTAT_Rx_FIFO_FULL
;
443 s
->reg
[I_(UFSTAT
)] &= ~0xff;
445 return s
->reg
[I_(UFSTAT
)];
447 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
448 if (fifo_elements_number(&s
->rx
)) {
449 res
= fifo_retrieve(&s
->rx
);
451 fprintf(stderr
, "%c", res
);
453 if (!fifo_elements_number(&s
->rx
)) {
454 s
->reg
[I_(UTRSTAT
)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY
;
456 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
459 s
->reg
[I_(UINTSP
)] |= UINTSP_ERROR
;
460 exynos4210_uart_update_irq(s
);
464 s
->reg
[I_(UTRSTAT
)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY
;
465 res
= s
->reg
[I_(URXH
)];
469 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
470 s
->channel
, exynos4210_uart_regname(offset
), offset
);
473 return s
->reg
[I_(offset
)];
479 static const MemoryRegionOps exynos4210_uart_ops
= {
480 .read
= exynos4210_uart_read
,
481 .write
= exynos4210_uart_write
,
482 .endianness
= DEVICE_NATIVE_ENDIAN
,
484 .max_access_size
= 4,
489 static int exynos4210_uart_can_receive(void *opaque
)
491 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
493 return fifo_empty_elements_number(&s
->rx
);
497 static void exynos4210_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
499 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
502 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
503 if (fifo_empty_elements_number(&s
->rx
) < size
) {
504 for (i
= 0; i
< fifo_empty_elements_number(&s
->rx
); i
++) {
505 fifo_store(&s
->rx
, buf
[i
]);
507 s
->reg
[I_(UINTSP
)] |= UINTSP_ERROR
;
508 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
510 for (i
= 0; i
< size
; i
++) {
511 fifo_store(&s
->rx
, buf
[i
]);
513 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
515 /* XXX: Around here we maybe should check Rx trigger level */
516 s
->reg
[I_(UINTSP
)] |= UINTSP_RXD
;
518 s
->reg
[I_(URXH
)] = buf
[0];
519 s
->reg
[I_(UINTSP
)] |= UINTSP_RXD
;
520 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
523 exynos4210_uart_update_irq(s
);
527 static void exynos4210_uart_event(void *opaque
, int event
)
529 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
531 if (event
== CHR_EVENT_BREAK
) {
532 /* When the RxDn is held in logic 0, then a null byte is pushed into the
534 fifo_store(&s
->rx
, '\0');
535 s
->reg
[I_(UERSTAT
)] |= UERSTAT_BREAK
;
536 exynos4210_uart_update_irq(s
);
541 static void exynos4210_uart_reset(DeviceState
*dev
)
543 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
546 for (i
= 0; i
< ARRAY_SIZE(exynos4210_uart_regs
); i
++) {
547 s
->reg
[I_(exynos4210_uart_regs
[i
].offset
)] =
548 exynos4210_uart_regs
[i
].reset_value
;
554 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s
->channel
, s
->rx
.size
);
557 static const VMStateDescription vmstate_exynos4210_uart_fifo
= {
558 .name
= "exynos4210.uart.fifo",
560 .minimum_version_id
= 1,
561 .fields
= (VMStateField
[]) {
562 VMSTATE_UINT32(sp
, Exynos4210UartFIFO
),
563 VMSTATE_UINT32(rp
, Exynos4210UartFIFO
),
564 VMSTATE_VBUFFER_UINT32(data
, Exynos4210UartFIFO
, 1, NULL
, size
),
565 VMSTATE_END_OF_LIST()
569 static const VMStateDescription vmstate_exynos4210_uart
= {
570 .name
= "exynos4210.uart",
572 .minimum_version_id
= 1,
573 .fields
= (VMStateField
[]) {
574 VMSTATE_STRUCT(rx
, Exynos4210UartState
, 1,
575 vmstate_exynos4210_uart_fifo
, Exynos4210UartFIFO
),
576 VMSTATE_UINT32_ARRAY(reg
, Exynos4210UartState
,
577 EXYNOS4210_UART_REGS_MEM_SIZE
/ sizeof(uint32_t)),
578 VMSTATE_END_OF_LIST()
582 DeviceState
*exynos4210_uart_create(hwaddr addr
,
591 const char chr_name
[] = "serial";
592 char label
[ARRAY_SIZE(chr_name
) + 1];
594 dev
= qdev_create(NULL
, TYPE_EXYNOS4210_UART
);
597 if (channel
>= MAX_SERIAL_PORTS
) {
598 error_report("Only %d serial ports are supported by QEMU",
602 chr
= serial_hds
[channel
];
604 snprintf(label
, ARRAY_SIZE(label
), "%s%d", chr_name
, channel
);
605 chr
= qemu_chr_new(label
, "null");
607 error_report("Can't assign serial port to UART%d", channel
);
613 qdev_prop_set_chr(dev
, "chardev", chr
);
614 qdev_prop_set_uint32(dev
, "channel", channel
);
615 qdev_prop_set_uint32(dev
, "rx-size", fifo_size
);
616 qdev_prop_set_uint32(dev
, "tx-size", fifo_size
);
618 bus
= SYS_BUS_DEVICE(dev
);
619 qdev_init_nofail(dev
);
620 if (addr
!= (hwaddr
)-1) {
621 sysbus_mmio_map(bus
, 0, addr
);
623 sysbus_connect_irq(bus
, 0, irq
);
628 static void exynos4210_uart_init(Object
*obj
)
630 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
631 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
634 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_uart_ops
, s
,
635 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE
);
636 sysbus_init_mmio(dev
, &s
->iomem
);
638 sysbus_init_irq(dev
, &s
->irq
);
641 static void exynos4210_uart_realize(DeviceState
*dev
, Error
**errp
)
643 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
645 qemu_chr_fe_set_handlers(&s
->chr
, exynos4210_uart_can_receive
,
646 exynos4210_uart_receive
, exynos4210_uart_event
,
650 static Property exynos4210_uart_properties
[] = {
651 DEFINE_PROP_CHR("chardev", Exynos4210UartState
, chr
),
652 DEFINE_PROP_UINT32("channel", Exynos4210UartState
, channel
, 0),
653 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState
, rx
.size
, 16),
654 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState
, tx
.size
, 16),
655 DEFINE_PROP_END_OF_LIST(),
658 static void exynos4210_uart_class_init(ObjectClass
*klass
, void *data
)
660 DeviceClass
*dc
= DEVICE_CLASS(klass
);
662 dc
->realize
= exynos4210_uart_realize
;
663 dc
->reset
= exynos4210_uart_reset
;
664 dc
->props
= exynos4210_uart_properties
;
665 dc
->vmsd
= &vmstate_exynos4210_uart
;
668 static const TypeInfo exynos4210_uart_info
= {
669 .name
= TYPE_EXYNOS4210_UART
,
670 .parent
= TYPE_SYS_BUS_DEVICE
,
671 .instance_size
= sizeof(Exynos4210UartState
),
672 .instance_init
= exynos4210_uart_init
,
673 .class_init
= exynos4210_uart_class_init
,
676 static void exynos4210_uart_register(void)
678 type_register_static(&exynos4210_uart_info
);
681 type_init(exynos4210_uart_register
)