4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
37 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
39 ARMCPU
*cpu
= ARM_CPU(cs
);
41 cpu
->env
.regs
[15] = value
;
44 static bool arm_cpu_has_work(CPUState
*cs
)
46 ARMCPU
*cpu
= ARM_CPU(cs
);
48 return (cpu
->power_state
!= PSCI_OFF
)
49 && cs
->interrupt_request
&
50 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB
);
55 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
58 /* We currently only support registering a single hook function */
59 assert(!cpu
->el_change_hook
);
60 cpu
->el_change_hook
= hook
;
61 cpu
->el_change_hook_opaque
= opaque
;
64 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
66 /* Reset a single ARMCPRegInfo register */
67 ARMCPRegInfo
*ri
= value
;
70 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
75 ri
->resetfn(&cpu
->env
, ri
);
79 /* A zero offset is never possible as it would be regs[0]
80 * so we use it to indicate that reset is being handled elsewhere.
81 * This is basically only used for fields in non-core coprocessors
82 * (like the pxa2xx ones).
84 if (!ri
->fieldoffset
) {
88 if (cpreg_field_is_64bit(ri
)) {
89 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
91 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
95 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
97 /* Purely an assertion check: we've already done reset once,
98 * so now check that running the reset for the cpreg doesn't
99 * change its value. This traps bugs where two different cpregs
100 * both try to reset the same state field but to different values.
102 ARMCPRegInfo
*ri
= value
;
103 ARMCPU
*cpu
= opaque
;
104 uint64_t oldvalue
, newvalue
;
106 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
110 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
111 cp_reg_reset(key
, value
, opaque
);
112 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
113 assert(oldvalue
== newvalue
);
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState
*s
)
119 ARMCPU
*cpu
= ARM_CPU(s
);
120 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
121 CPUARMState
*env
= &cpu
->env
;
123 acc
->parent_reset(s
);
125 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
127 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
128 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
130 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
131 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
132 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
133 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
135 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
136 s
->halted
= cpu
->start_powered_off
;
138 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
139 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
142 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
143 /* 64 bit CPUs always start in 64 bit mode */
145 #if defined(CONFIG_USER_ONLY)
146 env
->pstate
= PSTATE_MODE_EL0t
;
147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
148 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
149 /* and to the FP/Neon instructions */
150 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
152 /* Reset into the highest available EL */
153 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
154 env
->pstate
= PSTATE_MODE_EL3h
;
155 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
156 env
->pstate
= PSTATE_MODE_EL2h
;
158 env
->pstate
= PSTATE_MODE_EL1h
;
160 env
->pc
= cpu
->rvbar
;
163 #if defined(CONFIG_USER_ONLY)
164 /* Userspace expects access to cp10 and cp11 for FP/Neon */
165 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
169 #if defined(CONFIG_USER_ONLY)
170 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
171 /* For user mode we must enable access to coprocessors */
172 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
173 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
174 env
->cp15
.c15_cpar
= 3;
175 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
176 env
->cp15
.c15_cpar
= 1;
179 /* SVC mode with interrupts disabled. */
180 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
181 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
183 if (arm_feature(env
, ARM_FEATURE_M
)) {
184 uint32_t initial_msp
; /* Loaded from 0x0 */
185 uint32_t initial_pc
; /* Loaded from 0x4 */
188 /* For M profile we store FAULTMASK and PRIMASK in the
189 * PSTATE F and I bits; these are both clear at reset.
191 env
->daif
&= ~(PSTATE_I
| PSTATE_F
);
193 /* The reset value of this bit is IMPDEF, but ARM recommends
194 * that it resets to 1, so QEMU always does that rather than making
195 * it dependent on CPU model.
197 env
->v7m
.ccr
= R_V7M_CCR_STKALIGN_MASK
;
199 /* Unlike A/R profile, M profile defines the reset LR value */
200 env
->regs
[14] = 0xffffffff;
202 /* Load the initial SP and PC from the vector table at address 0 */
205 /* Address zero is covered by ROM which hasn't yet been
206 * copied into physical memory.
208 initial_msp
= ldl_p(rom
);
209 initial_pc
= ldl_p(rom
+ 4);
211 /* Address zero not covered by a ROM blob, or the ROM blob
212 * is in non-modifiable memory and this is a second reset after
213 * it got copied into memory. In the latter case, rom_ptr
214 * will return a NULL pointer and we should use ldl_phys instead.
216 initial_msp
= ldl_phys(s
->as
, 0);
217 initial_pc
= ldl_phys(s
->as
, 4);
220 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
221 env
->regs
[15] = initial_pc
& ~1;
222 env
->thumb
= initial_pc
& 1;
225 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
226 * executing as AArch32 then check if highvecs are enabled and
227 * adjust the PC accordingly.
229 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
230 env
->regs
[15] = 0xFFFF0000;
233 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
235 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
236 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
237 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
238 set_float_detect_tininess(float_tininess_before_rounding
,
239 &env
->vfp
.fp_status
);
240 set_float_detect_tininess(float_tininess_before_rounding
,
241 &env
->vfp
.standard_fp_status
);
242 #ifndef CONFIG_USER_ONLY
244 kvm_arm_reset_vcpu(cpu
);
248 hw_breakpoint_update_all(cpu
);
249 hw_watchpoint_update_all(cpu
);
252 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
254 CPUClass
*cc
= CPU_GET_CLASS(cs
);
255 CPUARMState
*env
= cs
->env_ptr
;
256 uint32_t cur_el
= arm_current_el(env
);
257 bool secure
= arm_is_secure(env
);
262 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
264 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
265 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
266 cs
->exception_index
= excp_idx
;
267 env
->exception
.target_el
= target_el
;
268 cc
->do_interrupt(cs
);
272 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
274 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
275 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
276 cs
->exception_index
= excp_idx
;
277 env
->exception
.target_el
= target_el
;
278 cc
->do_interrupt(cs
);
282 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
283 excp_idx
= EXCP_VIRQ
;
285 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
286 cs
->exception_index
= excp_idx
;
287 env
->exception
.target_el
= target_el
;
288 cc
->do_interrupt(cs
);
292 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
293 excp_idx
= EXCP_VFIQ
;
295 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
296 cs
->exception_index
= excp_idx
;
297 env
->exception
.target_el
= target_el
;
298 cc
->do_interrupt(cs
);
306 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
307 static void arm_v7m_unassigned_access(CPUState
*cpu
, hwaddr addr
,
308 bool is_write
, bool is_exec
, int opaque
,
311 ARMCPU
*arm
= ARM_CPU(cpu
);
312 CPUARMState
*env
= &arm
->env
;
314 /* ARMv7-M interrupt return works by loading a magic value into the PC.
315 * On real hardware the load causes the return to occur. The qemu
316 * implementation performs the jump normally, then does the exception
317 * return by throwing a special exception when when the CPU tries to
318 * execute code at the magic address.
320 if (env
->v7m
.exception
!= 0 && addr
>= 0xfffffff0 && is_exec
) {
321 cpu
->exception_index
= EXCP_EXCEPTION_EXIT
;
325 /* In real hardware an attempt to access parts of the address space
326 * with nothing there will usually cause an external abort.
327 * However our QEMU board models are often missing device models where
328 * the guest can boot anyway with the default read-as-zero/writes-ignored
329 * behaviour that you get without a QEMU unassigned_access hook.
330 * So just return here to retain that default behaviour.
334 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
336 CPUClass
*cc
= CPU_GET_CLASS(cs
);
337 ARMCPU
*cpu
= ARM_CPU(cs
);
338 CPUARMState
*env
= &cpu
->env
;
342 if (interrupt_request
& CPU_INTERRUPT_FIQ
343 && !(env
->daif
& PSTATE_F
)) {
344 cs
->exception_index
= EXCP_FIQ
;
345 cc
->do_interrupt(cs
);
348 /* ARMv7-M interrupt return works by loading a magic value
349 * into the PC. On real hardware the load causes the
350 * return to occur. The qemu implementation performs the
351 * jump normally, then does the exception return when the
352 * CPU tries to execute code at the magic address.
353 * This will cause the magic PC value to be pushed to
354 * the stack if an interrupt occurred at the wrong time.
355 * We avoid this by disabling interrupts when
356 * pc contains a magic address.
358 if (interrupt_request
& CPU_INTERRUPT_HARD
359 && !(env
->daif
& PSTATE_I
)
360 && (env
->regs
[15] < 0xfffffff0)) {
361 cs
->exception_index
= EXCP_IRQ
;
362 cc
->do_interrupt(cs
);
369 #ifndef CONFIG_USER_ONLY
370 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
372 ARMCPU
*cpu
= opaque
;
373 CPUARMState
*env
= &cpu
->env
;
374 CPUState
*cs
= CPU(cpu
);
375 static const int mask
[] = {
376 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
377 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
378 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
379 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
385 assert(arm_feature(env
, ARM_FEATURE_EL2
));
390 cpu_interrupt(cs
, mask
[irq
]);
392 cpu_reset_interrupt(cs
, mask
[irq
]);
396 g_assert_not_reached();
400 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
403 ARMCPU
*cpu
= opaque
;
404 CPUState
*cs
= CPU(cpu
);
405 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
409 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
412 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
415 g_assert_not_reached();
417 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
418 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
422 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
424 ARMCPU
*cpu
= ARM_CPU(cs
);
425 CPUARMState
*env
= &cpu
->env
;
427 cpu_synchronize_state(cs
);
428 return arm_cpu_data_is_big_endian(env
);
433 static inline void set_feature(CPUARMState
*env
, int feature
)
435 env
->features
|= 1ULL << feature
;
438 static inline void unset_feature(CPUARMState
*env
, int feature
)
440 env
->features
&= ~(1ULL << feature
);
444 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
446 return print_insn_arm(pc
| 1, info
);
449 static int arm_read_memory_func(bfd_vma memaddr
, bfd_byte
*b
,
450 int length
, struct disassemble_info
*info
)
452 assert(info
->read_memory_inner_func
);
453 assert((info
->flags
& INSN_ARM_BE32
) == 0 || length
== 2 || length
== 4);
455 if ((info
->flags
& INSN_ARM_BE32
) != 0 && length
== 2) {
456 assert(info
->endian
== BFD_ENDIAN_LITTLE
);
457 return info
->read_memory_inner_func(memaddr
^ 2, (bfd_byte
*)b
, 2,
460 return info
->read_memory_inner_func(memaddr
, b
, length
, info
);
464 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
466 ARMCPU
*ac
= ARM_CPU(cpu
);
467 CPUARMState
*env
= &ac
->env
;
470 /* We might not be compiled with the A64 disassembler
471 * because it needs a C++ compiler. Leave print_insn
472 * unset in this case to use the caller default behaviour.
474 #if defined(CONFIG_ARM_A64_DIS)
475 info
->print_insn
= print_insn_arm_a64
;
477 } else if (env
->thumb
) {
478 info
->print_insn
= print_insn_thumb1
;
480 info
->print_insn
= print_insn_arm
;
482 if (bswap_code(arm_sctlr_b(env
))) {
483 #ifdef TARGET_WORDS_BIGENDIAN
484 info
->endian
= BFD_ENDIAN_LITTLE
;
486 info
->endian
= BFD_ENDIAN_BIG
;
489 if (info
->read_memory_inner_func
== NULL
) {
490 info
->read_memory_inner_func
= info
->read_memory_func
;
491 info
->read_memory_func
= arm_read_memory_func
;
493 info
->flags
&= ~INSN_ARM_BE32
;
494 if (arm_sctlr_b(env
)) {
495 info
->flags
|= INSN_ARM_BE32
;
499 static void arm_cpu_initfn(Object
*obj
)
501 CPUState
*cs
= CPU(obj
);
502 ARMCPU
*cpu
= ARM_CPU(obj
);
505 cs
->env_ptr
= &cpu
->env
;
506 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
509 #ifndef CONFIG_USER_ONLY
510 /* Our inbound IRQ and FIQ lines */
512 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
513 * the same interface as non-KVM CPUs.
515 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
517 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
520 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
521 arm_gt_ptimer_cb
, cpu
);
522 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
523 arm_gt_vtimer_cb
, cpu
);
524 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
525 arm_gt_htimer_cb
, cpu
);
526 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
527 arm_gt_stimer_cb
, cpu
);
528 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
529 ARRAY_SIZE(cpu
->gt_timer_outputs
));
531 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
532 "gicv3-maintenance-interrupt", 1);
535 /* DTB consumers generally don't in fact care what the 'compatible'
536 * string is, so always provide some string and trust that a hypothetical
537 * picky DTB consumer will also provide a helpful error message.
539 cpu
->dtb_compatible
= "qemu,unknown";
540 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
541 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
544 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
547 arm_translate_init();
552 static Property arm_cpu_reset_cbar_property
=
553 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
555 static Property arm_cpu_reset_hivecs_property
=
556 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
558 static Property arm_cpu_rvbar_property
=
559 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
561 static Property arm_cpu_has_el2_property
=
562 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
564 static Property arm_cpu_has_el3_property
=
565 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
567 static Property arm_cpu_cfgend_property
=
568 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
570 /* use property name "pmu" to match other archs and virt tools */
571 static Property arm_cpu_has_pmu_property
=
572 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
574 static Property arm_cpu_has_mpu_property
=
575 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
577 static Property arm_cpu_pmsav7_dregion_property
=
578 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU
, pmsav7_dregion
, 16);
580 static void arm_cpu_post_init(Object
*obj
)
582 ARMCPU
*cpu
= ARM_CPU(obj
);
584 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
585 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
586 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
590 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
591 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
595 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
596 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
600 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
601 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
602 * prevent "has_el3" from existing on CPUs which cannot support EL3.
604 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
607 #ifndef CONFIG_USER_ONLY
608 object_property_add_link(obj
, "secure-memory",
610 (Object
**)&cpu
->secure_memory
,
611 qdev_prop_allow_set_link_before_realize
,
612 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
617 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
618 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
622 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
623 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
627 if (arm_feature(&cpu
->env
, ARM_FEATURE_MPU
)) {
628 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
630 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
631 qdev_property_add_static(DEVICE(obj
),
632 &arm_cpu_pmsav7_dregion_property
,
637 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
641 static void arm_cpu_finalizefn(Object
*obj
)
643 ARMCPU
*cpu
= ARM_CPU(obj
);
644 g_hash_table_destroy(cpu
->cp_regs
);
647 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
649 CPUState
*cs
= CPU(dev
);
650 ARMCPU
*cpu
= ARM_CPU(dev
);
651 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
652 CPUARMState
*env
= &cpu
->env
;
654 Error
*local_err
= NULL
;
656 cpu_exec_realizefn(cs
, &local_err
);
657 if (local_err
!= NULL
) {
658 error_propagate(errp
, local_err
);
662 /* Some features automatically imply others: */
663 if (arm_feature(env
, ARM_FEATURE_V8
)) {
664 set_feature(env
, ARM_FEATURE_V7
);
665 set_feature(env
, ARM_FEATURE_ARM_DIV
);
666 set_feature(env
, ARM_FEATURE_LPAE
);
668 if (arm_feature(env
, ARM_FEATURE_V7
)) {
669 set_feature(env
, ARM_FEATURE_VAPA
);
670 set_feature(env
, ARM_FEATURE_THUMB2
);
671 set_feature(env
, ARM_FEATURE_MPIDR
);
672 if (!arm_feature(env
, ARM_FEATURE_M
)) {
673 set_feature(env
, ARM_FEATURE_V6K
);
675 set_feature(env
, ARM_FEATURE_V6
);
678 /* Always define VBAR for V7 CPUs even if it doesn't exist in
679 * non-EL3 configs. This is needed by some legacy boards.
681 set_feature(env
, ARM_FEATURE_VBAR
);
683 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
684 set_feature(env
, ARM_FEATURE_V6
);
685 set_feature(env
, ARM_FEATURE_MVFR
);
687 if (arm_feature(env
, ARM_FEATURE_V6
)) {
688 set_feature(env
, ARM_FEATURE_V5
);
689 if (!arm_feature(env
, ARM_FEATURE_M
)) {
690 set_feature(env
, ARM_FEATURE_AUXCR
);
693 if (arm_feature(env
, ARM_FEATURE_V5
)) {
694 set_feature(env
, ARM_FEATURE_V4T
);
696 if (arm_feature(env
, ARM_FEATURE_M
)) {
697 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
699 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
700 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
702 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
703 set_feature(env
, ARM_FEATURE_VFP3
);
704 set_feature(env
, ARM_FEATURE_VFP_FP16
);
706 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
707 set_feature(env
, ARM_FEATURE_VFP
);
709 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
710 set_feature(env
, ARM_FEATURE_V7MP
);
711 set_feature(env
, ARM_FEATURE_PXN
);
713 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
714 set_feature(env
, ARM_FEATURE_CBAR
);
716 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
717 !arm_feature(env
, ARM_FEATURE_M
)) {
718 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
721 if (arm_feature(env
, ARM_FEATURE_V7
) &&
722 !arm_feature(env
, ARM_FEATURE_M
) &&
723 !arm_feature(env
, ARM_FEATURE_MPU
)) {
724 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
729 /* For CPUs which might have tiny 1K pages, or which have an
730 * MPU and might have small region sizes, stick with 1K pages.
734 if (!set_preferred_target_page_bits(pagebits
)) {
735 /* This can only ever happen for hotplugging a CPU, or if
736 * the board code incorrectly creates a CPU which it has
737 * promised via minimum_page_size that it will not.
739 error_setg(errp
, "This CPU requires a smaller page size than the "
744 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
745 * We don't support setting cluster ID ([16..23]) (known as Aff2
746 * in later ARM ARM versions), or any of the higher affinity level fields,
747 * so these bits always RAZ.
749 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
750 uint32_t Aff1
= cs
->cpu_index
/ ARM_DEFAULT_CPUS_PER_CLUSTER
;
751 uint32_t Aff0
= cs
->cpu_index
% ARM_DEFAULT_CPUS_PER_CLUSTER
;
752 cpu
->mp_affinity
= (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
755 if (cpu
->reset_hivecs
) {
756 cpu
->reset_sctlr
|= (1 << 13);
760 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
761 cpu
->reset_sctlr
|= SCTLR_EE
;
763 cpu
->reset_sctlr
|= SCTLR_B
;
768 /* If the has_el3 CPU property is disabled then we need to disable the
771 unset_feature(env
, ARM_FEATURE_EL3
);
773 /* Disable the security extension feature bits in the processor feature
774 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
776 cpu
->id_pfr1
&= ~0xf0;
777 cpu
->id_aa64pfr0
&= ~0xf000;
781 unset_feature(env
, ARM_FEATURE_EL2
);
785 cpu
->has_pmu
= false;
786 unset_feature(env
, ARM_FEATURE_PMU
);
789 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
790 /* Disable the hypervisor feature bits in the processor feature
791 * registers if we don't have EL2. These are id_pfr1[15:12] and
792 * id_aa64pfr0_el1[11:8].
794 cpu
->id_aa64pfr0
&= ~0xf00;
795 cpu
->id_pfr1
&= ~0xf000;
799 unset_feature(env
, ARM_FEATURE_MPU
);
802 if (arm_feature(env
, ARM_FEATURE_MPU
) &&
803 arm_feature(env
, ARM_FEATURE_V7
)) {
804 uint32_t nr
= cpu
->pmsav7_dregion
;
807 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
812 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
813 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
814 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
818 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
819 set_feature(env
, ARM_FEATURE_VBAR
);
822 register_cp_regs_for_features(cpu
);
823 arm_cpu_register_gdb_regs_for_features(cpu
);
825 init_cpreg_list(cpu
);
827 #ifndef CONFIG_USER_ONLY
837 if (!cpu
->secure_memory
) {
838 cpu
->secure_memory
= cs
->memory
;
840 as
= address_space_init_shareable(cpu
->secure_memory
,
841 "cpu-secure-memory");
842 cpu_address_space_init(cs
, as
, ARMASIdx_S
);
844 cpu_address_space_init(cs
,
845 address_space_init_shareable(cs
->memory
,
853 acc
->parent_realize(dev
, errp
);
856 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
866 cpuname
= g_strsplit(cpu_model
, ",", 1);
867 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
868 oc
= object_class_by_name(typename
);
871 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
872 object_class_is_abstract(oc
)) {
878 /* CPU models. These are not needed for the AArch64 linux-user build. */
879 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
881 static void arm926_initfn(Object
*obj
)
883 ARMCPU
*cpu
= ARM_CPU(obj
);
885 cpu
->dtb_compatible
= "arm,arm926";
886 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
887 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
888 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
889 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
890 cpu
->midr
= 0x41069265;
891 cpu
->reset_fpsid
= 0x41011090;
892 cpu
->ctr
= 0x1dd20d2;
893 cpu
->reset_sctlr
= 0x00090078;
896 static void arm946_initfn(Object
*obj
)
898 ARMCPU
*cpu
= ARM_CPU(obj
);
900 cpu
->dtb_compatible
= "arm,arm946";
901 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
902 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
903 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
904 cpu
->midr
= 0x41059461;
905 cpu
->ctr
= 0x0f004006;
906 cpu
->reset_sctlr
= 0x00000078;
909 static void arm1026_initfn(Object
*obj
)
911 ARMCPU
*cpu
= ARM_CPU(obj
);
913 cpu
->dtb_compatible
= "arm,arm1026";
914 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
915 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
916 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
917 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
918 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
919 cpu
->midr
= 0x4106a262;
920 cpu
->reset_fpsid
= 0x410110a0;
921 cpu
->ctr
= 0x1dd20d2;
922 cpu
->reset_sctlr
= 0x00090078;
923 cpu
->reset_auxcr
= 1;
925 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
926 ARMCPRegInfo ifar
= {
927 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
929 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
932 define_one_arm_cp_reg(cpu
, &ifar
);
936 static void arm1136_r2_initfn(Object
*obj
)
938 ARMCPU
*cpu
= ARM_CPU(obj
);
939 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
940 * older core than plain "arm1136". In particular this does not
941 * have the v6K features.
942 * These ID register values are correct for 1136 but may be wrong
943 * for 1136_r2 (in particular r0p2 does not actually implement most
944 * of the ID registers).
947 cpu
->dtb_compatible
= "arm,arm1136";
948 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
949 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
950 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
951 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
952 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
953 cpu
->midr
= 0x4107b362;
954 cpu
->reset_fpsid
= 0x410120b4;
955 cpu
->mvfr0
= 0x11111111;
956 cpu
->mvfr1
= 0x00000000;
957 cpu
->ctr
= 0x1dd20d2;
958 cpu
->reset_sctlr
= 0x00050078;
959 cpu
->id_pfr0
= 0x111;
963 cpu
->id_mmfr0
= 0x01130003;
964 cpu
->id_mmfr1
= 0x10030302;
965 cpu
->id_mmfr2
= 0x01222110;
966 cpu
->id_isar0
= 0x00140011;
967 cpu
->id_isar1
= 0x12002111;
968 cpu
->id_isar2
= 0x11231111;
969 cpu
->id_isar3
= 0x01102131;
970 cpu
->id_isar4
= 0x141;
971 cpu
->reset_auxcr
= 7;
974 static void arm1136_initfn(Object
*obj
)
976 ARMCPU
*cpu
= ARM_CPU(obj
);
978 cpu
->dtb_compatible
= "arm,arm1136";
979 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
980 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
981 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
982 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
983 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
984 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
985 cpu
->midr
= 0x4117b363;
986 cpu
->reset_fpsid
= 0x410120b4;
987 cpu
->mvfr0
= 0x11111111;
988 cpu
->mvfr1
= 0x00000000;
989 cpu
->ctr
= 0x1dd20d2;
990 cpu
->reset_sctlr
= 0x00050078;
991 cpu
->id_pfr0
= 0x111;
995 cpu
->id_mmfr0
= 0x01130003;
996 cpu
->id_mmfr1
= 0x10030302;
997 cpu
->id_mmfr2
= 0x01222110;
998 cpu
->id_isar0
= 0x00140011;
999 cpu
->id_isar1
= 0x12002111;
1000 cpu
->id_isar2
= 0x11231111;
1001 cpu
->id_isar3
= 0x01102131;
1002 cpu
->id_isar4
= 0x141;
1003 cpu
->reset_auxcr
= 7;
1006 static void arm1176_initfn(Object
*obj
)
1008 ARMCPU
*cpu
= ARM_CPU(obj
);
1010 cpu
->dtb_compatible
= "arm,arm1176";
1011 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1012 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1013 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1014 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1015 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1016 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1017 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1018 cpu
->midr
= 0x410fb767;
1019 cpu
->reset_fpsid
= 0x410120b5;
1020 cpu
->mvfr0
= 0x11111111;
1021 cpu
->mvfr1
= 0x00000000;
1022 cpu
->ctr
= 0x1dd20d2;
1023 cpu
->reset_sctlr
= 0x00050078;
1024 cpu
->id_pfr0
= 0x111;
1025 cpu
->id_pfr1
= 0x11;
1026 cpu
->id_dfr0
= 0x33;
1028 cpu
->id_mmfr0
= 0x01130003;
1029 cpu
->id_mmfr1
= 0x10030302;
1030 cpu
->id_mmfr2
= 0x01222100;
1031 cpu
->id_isar0
= 0x0140011;
1032 cpu
->id_isar1
= 0x12002111;
1033 cpu
->id_isar2
= 0x11231121;
1034 cpu
->id_isar3
= 0x01102131;
1035 cpu
->id_isar4
= 0x01141;
1036 cpu
->reset_auxcr
= 7;
1039 static void arm11mpcore_initfn(Object
*obj
)
1041 ARMCPU
*cpu
= ARM_CPU(obj
);
1043 cpu
->dtb_compatible
= "arm,arm11mpcore";
1044 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1045 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1046 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1047 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1048 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1049 cpu
->midr
= 0x410fb022;
1050 cpu
->reset_fpsid
= 0x410120b4;
1051 cpu
->mvfr0
= 0x11111111;
1052 cpu
->mvfr1
= 0x00000000;
1053 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1054 cpu
->id_pfr0
= 0x111;
1058 cpu
->id_mmfr0
= 0x01100103;
1059 cpu
->id_mmfr1
= 0x10020302;
1060 cpu
->id_mmfr2
= 0x01222000;
1061 cpu
->id_isar0
= 0x00100011;
1062 cpu
->id_isar1
= 0x12002111;
1063 cpu
->id_isar2
= 0x11221011;
1064 cpu
->id_isar3
= 0x01102131;
1065 cpu
->id_isar4
= 0x141;
1066 cpu
->reset_auxcr
= 1;
1069 static void cortex_m3_initfn(Object
*obj
)
1071 ARMCPU
*cpu
= ARM_CPU(obj
);
1072 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1073 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1074 cpu
->midr
= 0x410fc231;
1077 static void cortex_m4_initfn(Object
*obj
)
1079 ARMCPU
*cpu
= ARM_CPU(obj
);
1081 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1082 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1083 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1084 cpu
->midr
= 0x410fc240; /* r0p0 */
1086 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1088 CPUClass
*cc
= CPU_CLASS(oc
);
1090 #ifndef CONFIG_USER_ONLY
1091 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1094 cc
->do_unassigned_access
= arm_v7m_unassigned_access
;
1095 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1098 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1099 /* Dummy the TCM region regs for the moment */
1100 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1101 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1102 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1103 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1107 static void cortex_r5_initfn(Object
*obj
)
1109 ARMCPU
*cpu
= ARM_CPU(obj
);
1111 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1112 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1113 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1114 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1115 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
1116 cpu
->midr
= 0x411fc153; /* r1p3 */
1117 cpu
->id_pfr0
= 0x0131;
1118 cpu
->id_pfr1
= 0x001;
1119 cpu
->id_dfr0
= 0x010400;
1121 cpu
->id_mmfr0
= 0x0210030;
1122 cpu
->id_mmfr1
= 0x00000000;
1123 cpu
->id_mmfr2
= 0x01200000;
1124 cpu
->id_mmfr3
= 0x0211;
1125 cpu
->id_isar0
= 0x2101111;
1126 cpu
->id_isar1
= 0x13112111;
1127 cpu
->id_isar2
= 0x21232141;
1128 cpu
->id_isar3
= 0x01112131;
1129 cpu
->id_isar4
= 0x0010142;
1130 cpu
->id_isar5
= 0x0;
1131 cpu
->mp_is_up
= true;
1132 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1135 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1136 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1137 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1138 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1139 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1143 static void cortex_a8_initfn(Object
*obj
)
1145 ARMCPU
*cpu
= ARM_CPU(obj
);
1147 cpu
->dtb_compatible
= "arm,cortex-a8";
1148 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1149 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1150 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1151 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1152 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1153 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1154 cpu
->midr
= 0x410fc080;
1155 cpu
->reset_fpsid
= 0x410330c0;
1156 cpu
->mvfr0
= 0x11110222;
1157 cpu
->mvfr1
= 0x00011111;
1158 cpu
->ctr
= 0x82048004;
1159 cpu
->reset_sctlr
= 0x00c50078;
1160 cpu
->id_pfr0
= 0x1031;
1161 cpu
->id_pfr1
= 0x11;
1162 cpu
->id_dfr0
= 0x400;
1164 cpu
->id_mmfr0
= 0x31100003;
1165 cpu
->id_mmfr1
= 0x20000000;
1166 cpu
->id_mmfr2
= 0x01202000;
1167 cpu
->id_mmfr3
= 0x11;
1168 cpu
->id_isar0
= 0x00101111;
1169 cpu
->id_isar1
= 0x12112111;
1170 cpu
->id_isar2
= 0x21232031;
1171 cpu
->id_isar3
= 0x11112131;
1172 cpu
->id_isar4
= 0x00111142;
1173 cpu
->dbgdidr
= 0x15141000;
1174 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1175 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1176 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1177 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1178 cpu
->reset_auxcr
= 2;
1179 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1182 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1183 /* power_control should be set to maximum latency. Again,
1184 * default to 0 and set by private hook
1186 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1187 .access
= PL1_RW
, .resetvalue
= 0,
1188 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1189 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1190 .access
= PL1_RW
, .resetvalue
= 0,
1191 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1192 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1193 .access
= PL1_RW
, .resetvalue
= 0,
1194 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1195 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1196 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1197 /* TLB lockdown control */
1198 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1199 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1200 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1201 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1202 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1203 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1204 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1205 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1206 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1207 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1211 static void cortex_a9_initfn(Object
*obj
)
1213 ARMCPU
*cpu
= ARM_CPU(obj
);
1215 cpu
->dtb_compatible
= "arm,cortex-a9";
1216 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1217 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1218 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1219 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1220 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1221 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1222 /* Note that A9 supports the MP extensions even for
1223 * A9UP and single-core A9MP (which are both different
1224 * and valid configurations; we don't model A9UP).
1226 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1227 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1228 cpu
->midr
= 0x410fc090;
1229 cpu
->reset_fpsid
= 0x41033090;
1230 cpu
->mvfr0
= 0x11110222;
1231 cpu
->mvfr1
= 0x01111111;
1232 cpu
->ctr
= 0x80038003;
1233 cpu
->reset_sctlr
= 0x00c50078;
1234 cpu
->id_pfr0
= 0x1031;
1235 cpu
->id_pfr1
= 0x11;
1236 cpu
->id_dfr0
= 0x000;
1238 cpu
->id_mmfr0
= 0x00100103;
1239 cpu
->id_mmfr1
= 0x20000000;
1240 cpu
->id_mmfr2
= 0x01230000;
1241 cpu
->id_mmfr3
= 0x00002111;
1242 cpu
->id_isar0
= 0x00101111;
1243 cpu
->id_isar1
= 0x13112111;
1244 cpu
->id_isar2
= 0x21232041;
1245 cpu
->id_isar3
= 0x11112131;
1246 cpu
->id_isar4
= 0x00111142;
1247 cpu
->dbgdidr
= 0x35141000;
1248 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1249 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1250 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1251 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1254 #ifndef CONFIG_USER_ONLY
1255 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1257 /* Linux wants the number of processors from here.
1258 * Might as well set the interrupt-controller bit too.
1260 return ((smp_cpus
- 1) << 24) | (1 << 23);
1264 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1265 #ifndef CONFIG_USER_ONLY
1266 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1267 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1268 .writefn
= arm_cp_write_ignore
, },
1270 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1271 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1275 static void cortex_a7_initfn(Object
*obj
)
1277 ARMCPU
*cpu
= ARM_CPU(obj
);
1279 cpu
->dtb_compatible
= "arm,cortex-a7";
1280 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1281 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1282 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1283 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1284 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1285 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1286 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1287 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1288 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1289 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1290 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1291 cpu
->midr
= 0x410fc075;
1292 cpu
->reset_fpsid
= 0x41023075;
1293 cpu
->mvfr0
= 0x10110222;
1294 cpu
->mvfr1
= 0x11111111;
1295 cpu
->ctr
= 0x84448003;
1296 cpu
->reset_sctlr
= 0x00c50078;
1297 cpu
->id_pfr0
= 0x00001131;
1298 cpu
->id_pfr1
= 0x00011011;
1299 cpu
->id_dfr0
= 0x02010555;
1300 cpu
->pmceid0
= 0x00000000;
1301 cpu
->pmceid1
= 0x00000000;
1302 cpu
->id_afr0
= 0x00000000;
1303 cpu
->id_mmfr0
= 0x10101105;
1304 cpu
->id_mmfr1
= 0x40000000;
1305 cpu
->id_mmfr2
= 0x01240000;
1306 cpu
->id_mmfr3
= 0x02102211;
1307 cpu
->id_isar0
= 0x01101110;
1308 cpu
->id_isar1
= 0x13112111;
1309 cpu
->id_isar2
= 0x21232041;
1310 cpu
->id_isar3
= 0x11112131;
1311 cpu
->id_isar4
= 0x10011142;
1312 cpu
->dbgdidr
= 0x3515f005;
1313 cpu
->clidr
= 0x0a200023;
1314 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1315 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1316 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1317 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1320 static void cortex_a15_initfn(Object
*obj
)
1322 ARMCPU
*cpu
= ARM_CPU(obj
);
1324 cpu
->dtb_compatible
= "arm,cortex-a15";
1325 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1326 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1327 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1328 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1329 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1330 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1331 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1332 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1333 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1334 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1335 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1336 cpu
->midr
= 0x412fc0f1;
1337 cpu
->reset_fpsid
= 0x410430f0;
1338 cpu
->mvfr0
= 0x10110222;
1339 cpu
->mvfr1
= 0x11111111;
1340 cpu
->ctr
= 0x8444c004;
1341 cpu
->reset_sctlr
= 0x00c50078;
1342 cpu
->id_pfr0
= 0x00001131;
1343 cpu
->id_pfr1
= 0x00011011;
1344 cpu
->id_dfr0
= 0x02010555;
1345 cpu
->pmceid0
= 0x0000000;
1346 cpu
->pmceid1
= 0x00000000;
1347 cpu
->id_afr0
= 0x00000000;
1348 cpu
->id_mmfr0
= 0x10201105;
1349 cpu
->id_mmfr1
= 0x20000000;
1350 cpu
->id_mmfr2
= 0x01240000;
1351 cpu
->id_mmfr3
= 0x02102211;
1352 cpu
->id_isar0
= 0x02101110;
1353 cpu
->id_isar1
= 0x13112111;
1354 cpu
->id_isar2
= 0x21232041;
1355 cpu
->id_isar3
= 0x11112131;
1356 cpu
->id_isar4
= 0x10011142;
1357 cpu
->dbgdidr
= 0x3515f021;
1358 cpu
->clidr
= 0x0a200023;
1359 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1360 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1361 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1362 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1365 static void ti925t_initfn(Object
*obj
)
1367 ARMCPU
*cpu
= ARM_CPU(obj
);
1368 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1369 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1370 cpu
->midr
= ARM_CPUID_TI925T
;
1371 cpu
->ctr
= 0x5109149;
1372 cpu
->reset_sctlr
= 0x00000070;
1375 static void sa1100_initfn(Object
*obj
)
1377 ARMCPU
*cpu
= ARM_CPU(obj
);
1379 cpu
->dtb_compatible
= "intel,sa1100";
1380 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1381 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1382 cpu
->midr
= 0x4401A11B;
1383 cpu
->reset_sctlr
= 0x00000070;
1386 static void sa1110_initfn(Object
*obj
)
1388 ARMCPU
*cpu
= ARM_CPU(obj
);
1389 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1390 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1391 cpu
->midr
= 0x6901B119;
1392 cpu
->reset_sctlr
= 0x00000070;
1395 static void pxa250_initfn(Object
*obj
)
1397 ARMCPU
*cpu
= ARM_CPU(obj
);
1399 cpu
->dtb_compatible
= "marvell,xscale";
1400 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1401 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1402 cpu
->midr
= 0x69052100;
1403 cpu
->ctr
= 0xd172172;
1404 cpu
->reset_sctlr
= 0x00000078;
1407 static void pxa255_initfn(Object
*obj
)
1409 ARMCPU
*cpu
= ARM_CPU(obj
);
1411 cpu
->dtb_compatible
= "marvell,xscale";
1412 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1413 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1414 cpu
->midr
= 0x69052d00;
1415 cpu
->ctr
= 0xd172172;
1416 cpu
->reset_sctlr
= 0x00000078;
1419 static void pxa260_initfn(Object
*obj
)
1421 ARMCPU
*cpu
= ARM_CPU(obj
);
1423 cpu
->dtb_compatible
= "marvell,xscale";
1424 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1425 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1426 cpu
->midr
= 0x69052903;
1427 cpu
->ctr
= 0xd172172;
1428 cpu
->reset_sctlr
= 0x00000078;
1431 static void pxa261_initfn(Object
*obj
)
1433 ARMCPU
*cpu
= ARM_CPU(obj
);
1435 cpu
->dtb_compatible
= "marvell,xscale";
1436 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1437 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1438 cpu
->midr
= 0x69052d05;
1439 cpu
->ctr
= 0xd172172;
1440 cpu
->reset_sctlr
= 0x00000078;
1443 static void pxa262_initfn(Object
*obj
)
1445 ARMCPU
*cpu
= ARM_CPU(obj
);
1447 cpu
->dtb_compatible
= "marvell,xscale";
1448 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1449 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1450 cpu
->midr
= 0x69052d06;
1451 cpu
->ctr
= 0xd172172;
1452 cpu
->reset_sctlr
= 0x00000078;
1455 static void pxa270a0_initfn(Object
*obj
)
1457 ARMCPU
*cpu
= ARM_CPU(obj
);
1459 cpu
->dtb_compatible
= "marvell,xscale";
1460 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1461 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1462 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1463 cpu
->midr
= 0x69054110;
1464 cpu
->ctr
= 0xd172172;
1465 cpu
->reset_sctlr
= 0x00000078;
1468 static void pxa270a1_initfn(Object
*obj
)
1470 ARMCPU
*cpu
= ARM_CPU(obj
);
1472 cpu
->dtb_compatible
= "marvell,xscale";
1473 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1474 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1475 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1476 cpu
->midr
= 0x69054111;
1477 cpu
->ctr
= 0xd172172;
1478 cpu
->reset_sctlr
= 0x00000078;
1481 static void pxa270b0_initfn(Object
*obj
)
1483 ARMCPU
*cpu
= ARM_CPU(obj
);
1485 cpu
->dtb_compatible
= "marvell,xscale";
1486 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1487 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1488 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1489 cpu
->midr
= 0x69054112;
1490 cpu
->ctr
= 0xd172172;
1491 cpu
->reset_sctlr
= 0x00000078;
1494 static void pxa270b1_initfn(Object
*obj
)
1496 ARMCPU
*cpu
= ARM_CPU(obj
);
1498 cpu
->dtb_compatible
= "marvell,xscale";
1499 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1500 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1501 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1502 cpu
->midr
= 0x69054113;
1503 cpu
->ctr
= 0xd172172;
1504 cpu
->reset_sctlr
= 0x00000078;
1507 static void pxa270c0_initfn(Object
*obj
)
1509 ARMCPU
*cpu
= ARM_CPU(obj
);
1511 cpu
->dtb_compatible
= "marvell,xscale";
1512 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1513 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1514 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1515 cpu
->midr
= 0x69054114;
1516 cpu
->ctr
= 0xd172172;
1517 cpu
->reset_sctlr
= 0x00000078;
1520 static void pxa270c5_initfn(Object
*obj
)
1522 ARMCPU
*cpu
= ARM_CPU(obj
);
1524 cpu
->dtb_compatible
= "marvell,xscale";
1525 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1526 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1527 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1528 cpu
->midr
= 0x69054117;
1529 cpu
->ctr
= 0xd172172;
1530 cpu
->reset_sctlr
= 0x00000078;
1533 #ifdef CONFIG_USER_ONLY
1534 static void arm_any_initfn(Object
*obj
)
1536 ARMCPU
*cpu
= ARM_CPU(obj
);
1537 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1538 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1539 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1540 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1541 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1542 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1543 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1544 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1545 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1546 cpu
->midr
= 0xffffffff;
1550 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1552 typedef struct ARMCPUInfo
{
1554 void (*initfn
)(Object
*obj
);
1555 void (*class_init
)(ObjectClass
*oc
, void *data
);
1558 static const ARMCPUInfo arm_cpus
[] = {
1559 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1560 { .name
= "arm926", .initfn
= arm926_initfn
},
1561 { .name
= "arm946", .initfn
= arm946_initfn
},
1562 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1563 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1564 * older core than plain "arm1136". In particular this does not
1565 * have the v6K features.
1567 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1568 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1569 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1570 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1571 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1572 .class_init
= arm_v7m_class_init
},
1573 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1574 .class_init
= arm_v7m_class_init
},
1575 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1576 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1577 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1578 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1579 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1580 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1581 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1582 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1583 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1584 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1585 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1586 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1587 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1588 /* "pxa270" is an alias for "pxa270-a0" */
1589 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1590 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1591 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1592 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1593 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1594 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1595 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1596 #ifdef CONFIG_USER_ONLY
1597 { .name
= "any", .initfn
= arm_any_initfn
},
1603 static Property arm_cpu_properties
[] = {
1604 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1605 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1606 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1607 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1608 mp_affinity
, ARM64_AFFINITY_INVALID
),
1609 DEFINE_PROP_END_OF_LIST()
1612 #ifdef CONFIG_USER_ONLY
1613 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1616 ARMCPU
*cpu
= ARM_CPU(cs
);
1617 CPUARMState
*env
= &cpu
->env
;
1619 env
->exception
.vaddress
= address
;
1621 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1623 cs
->exception_index
= EXCP_DATA_ABORT
;
1629 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1631 ARMCPU
*cpu
= ARM_CPU(cs
);
1632 CPUARMState
*env
= &cpu
->env
;
1634 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1635 return g_strdup("iwmmxt");
1637 return g_strdup("arm");
1640 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1642 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1643 CPUClass
*cc
= CPU_CLASS(acc
);
1644 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1646 acc
->parent_realize
= dc
->realize
;
1647 dc
->realize
= arm_cpu_realizefn
;
1648 dc
->props
= arm_cpu_properties
;
1650 acc
->parent_reset
= cc
->reset
;
1651 cc
->reset
= arm_cpu_reset
;
1653 cc
->class_by_name
= arm_cpu_class_by_name
;
1654 cc
->has_work
= arm_cpu_has_work
;
1655 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1656 cc
->dump_state
= arm_cpu_dump_state
;
1657 cc
->set_pc
= arm_cpu_set_pc
;
1658 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1659 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1660 #ifdef CONFIG_USER_ONLY
1661 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1663 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1664 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1665 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1666 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1667 cc
->vmsd
= &vmstate_arm_cpu
;
1668 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1669 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1670 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1672 cc
->gdb_num_core_regs
= 26;
1673 cc
->gdb_core_xml_file
= "arm-core.xml";
1674 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1675 cc
->gdb_stop_before_watchpoint
= true;
1676 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1677 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1678 #if !defined(CONFIG_USER_ONLY)
1679 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1682 cc
->disas_set_info
= arm_disas_set_info
;
1685 static void cpu_register(const ARMCPUInfo
*info
)
1687 TypeInfo type_info
= {
1688 .parent
= TYPE_ARM_CPU
,
1689 .instance_size
= sizeof(ARMCPU
),
1690 .instance_init
= info
->initfn
,
1691 .class_size
= sizeof(ARMCPUClass
),
1692 .class_init
= info
->class_init
,
1695 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1696 type_register(&type_info
);
1697 g_free((void *)type_info
.name
);
1700 static const TypeInfo arm_cpu_type_info
= {
1701 .name
= TYPE_ARM_CPU
,
1703 .instance_size
= sizeof(ARMCPU
),
1704 .instance_init
= arm_cpu_initfn
,
1705 .instance_post_init
= arm_cpu_post_init
,
1706 .instance_finalize
= arm_cpu_finalizefn
,
1708 .class_size
= sizeof(ARMCPUClass
),
1709 .class_init
= arm_cpu_class_init
,
1712 static void arm_cpu_register_types(void)
1714 const ARMCPUInfo
*info
= arm_cpus
;
1716 type_register_static(&arm_cpu_type_info
);
1718 while (info
->name
) {
1724 type_init(arm_cpu_register_types
)