rocker: forbid to change world type
[qemu/kevin.git] / target-arm / helper-a64.c
blobc7bfb4d8f7218668d827e7fe03afea651ccafaec
1 /*
2 * AArch64 specific helpers
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/gdbstub.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/bitops.h"
27 #include "internals.h"
28 #include "qemu/crc32c.h"
29 #include <zlib.h> /* For crc32 */
31 /* C2.4.7 Multiply and divide */
32 /* special cases for 0 and LLONG_MIN are mandated by the standard */
33 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
35 if (den == 0) {
36 return 0;
38 return num / den;
41 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
43 if (den == 0) {
44 return 0;
46 if (num == LLONG_MIN && den == -1) {
47 return LLONG_MIN;
49 return num / den;
52 uint64_t HELPER(clz64)(uint64_t x)
54 return clz64(x);
57 uint64_t HELPER(cls64)(uint64_t x)
59 return clrsb64(x);
62 uint32_t HELPER(cls32)(uint32_t x)
64 return clrsb32(x);
67 uint32_t HELPER(clz32)(uint32_t x)
69 return clz32(x);
72 uint64_t HELPER(rbit64)(uint64_t x)
74 return revbit64(x);
77 /* Convert a softfloat float_relation_ (as returned by
78 * the float*_compare functions) to the correct ARM
79 * NZCV flag state.
81 static inline uint32_t float_rel_to_flags(int res)
83 uint64_t flags;
84 switch (res) {
85 case float_relation_equal:
86 flags = PSTATE_Z | PSTATE_C;
87 break;
88 case float_relation_less:
89 flags = PSTATE_N;
90 break;
91 case float_relation_greater:
92 flags = PSTATE_C;
93 break;
94 case float_relation_unordered:
95 default:
96 flags = PSTATE_C | PSTATE_V;
97 break;
99 return flags;
102 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
104 return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
107 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
109 return float_rel_to_flags(float32_compare(x, y, fp_status));
112 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
114 return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
117 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
119 return float_rel_to_flags(float64_compare(x, y, fp_status));
122 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
124 float_status *fpst = fpstp;
126 a = float32_squash_input_denormal(a, fpst);
127 b = float32_squash_input_denormal(b, fpst);
129 if ((float32_is_zero(a) && float32_is_infinity(b)) ||
130 (float32_is_infinity(a) && float32_is_zero(b))) {
131 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
132 return make_float32((1U << 30) |
133 ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
135 return float32_mul(a, b, fpst);
138 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
140 float_status *fpst = fpstp;
142 a = float64_squash_input_denormal(a, fpst);
143 b = float64_squash_input_denormal(b, fpst);
145 if ((float64_is_zero(a) && float64_is_infinity(b)) ||
146 (float64_is_infinity(a) && float64_is_zero(b))) {
147 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
148 return make_float64((1ULL << 62) |
149 ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
151 return float64_mul(a, b, fpst);
154 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
155 uint32_t rn, uint32_t numregs)
157 /* Helper function for SIMD TBL and TBX. We have to do the table
158 * lookup part for the 64 bits worth of indices we're passed in.
159 * result is the initial results vector (either zeroes for TBL
160 * or some guest values for TBX), rn the register number where
161 * the table starts, and numregs the number of registers in the table.
162 * We return the results of the lookups.
164 int shift;
166 for (shift = 0; shift < 64; shift += 8) {
167 int index = extract64(indices, shift, 8);
168 if (index < 16 * numregs) {
169 /* Convert index (a byte offset into the virtual table
170 * which is a series of 128-bit vectors concatenated)
171 * into the correct vfp.regs[] element plus a bit offset
172 * into that element, bearing in mind that the table
173 * can wrap around from V31 to V0.
175 int elt = (rn * 2 + (index >> 3)) % 64;
176 int bitidx = (index & 7) * 8;
177 uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
179 result = deposit64(result, shift, 8, val);
182 return result;
185 /* 64bit/double versions of the neon float compare functions */
186 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
188 float_status *fpst = fpstp;
189 return -float64_eq_quiet(a, b, fpst);
192 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
194 float_status *fpst = fpstp;
195 return -float64_le(b, a, fpst);
198 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
200 float_status *fpst = fpstp;
201 return -float64_lt(b, a, fpst);
204 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
205 * versions, these do a fully fused multiply-add or
206 * multiply-add-and-halve.
208 #define float32_two make_float32(0x40000000)
209 #define float32_three make_float32(0x40400000)
210 #define float32_one_point_five make_float32(0x3fc00000)
212 #define float64_two make_float64(0x4000000000000000ULL)
213 #define float64_three make_float64(0x4008000000000000ULL)
214 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
216 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
218 float_status *fpst = fpstp;
220 a = float32_squash_input_denormal(a, fpst);
221 b = float32_squash_input_denormal(b, fpst);
223 a = float32_chs(a);
224 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
225 (float32_is_infinity(b) && float32_is_zero(a))) {
226 return float32_two;
228 return float32_muladd(a, b, float32_two, 0, fpst);
231 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
233 float_status *fpst = fpstp;
235 a = float64_squash_input_denormal(a, fpst);
236 b = float64_squash_input_denormal(b, fpst);
238 a = float64_chs(a);
239 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
240 (float64_is_infinity(b) && float64_is_zero(a))) {
241 return float64_two;
243 return float64_muladd(a, b, float64_two, 0, fpst);
246 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
248 float_status *fpst = fpstp;
250 a = float32_squash_input_denormal(a, fpst);
251 b = float32_squash_input_denormal(b, fpst);
253 a = float32_chs(a);
254 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
255 (float32_is_infinity(b) && float32_is_zero(a))) {
256 return float32_one_point_five;
258 return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
261 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
263 float_status *fpst = fpstp;
265 a = float64_squash_input_denormal(a, fpst);
266 b = float64_squash_input_denormal(b, fpst);
268 a = float64_chs(a);
269 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
270 (float64_is_infinity(b) && float64_is_zero(a))) {
271 return float64_one_point_five;
273 return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
276 /* Pairwise long add: add pairs of adjacent elements into
277 * double-width elements in the result (eg _s8 is an 8x8->16 op)
279 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
281 uint64_t nsignmask = 0x0080008000800080ULL;
282 uint64_t wsignmask = 0x8000800080008000ULL;
283 uint64_t elementmask = 0x00ff00ff00ff00ffULL;
284 uint64_t tmp1, tmp2;
285 uint64_t res, signres;
287 /* Extract odd elements, sign extend each to a 16 bit field */
288 tmp1 = a & elementmask;
289 tmp1 ^= nsignmask;
290 tmp1 |= wsignmask;
291 tmp1 = (tmp1 - nsignmask) ^ wsignmask;
292 /* Ditto for the even elements */
293 tmp2 = (a >> 8) & elementmask;
294 tmp2 ^= nsignmask;
295 tmp2 |= wsignmask;
296 tmp2 = (tmp2 - nsignmask) ^ wsignmask;
298 /* calculate the result by summing bits 0..14, 16..22, etc,
299 * and then adjusting the sign bits 15, 23, etc manually.
300 * This ensures the addition can't overflow the 16 bit field.
302 signres = (tmp1 ^ tmp2) & wsignmask;
303 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
304 res ^= signres;
306 return res;
309 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
311 uint64_t tmp;
313 tmp = a & 0x00ff00ff00ff00ffULL;
314 tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
315 return tmp;
318 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
320 int32_t reslo, reshi;
322 reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
323 reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
325 return (uint32_t)reslo | (((uint64_t)reshi) << 32);
328 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
330 uint64_t tmp;
332 tmp = a & 0x0000ffff0000ffffULL;
333 tmp += (a >> 16) & 0x0000ffff0000ffffULL;
334 return tmp;
337 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
338 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
340 float_status *fpst = fpstp;
341 uint32_t val32, sbit;
342 int32_t exp;
344 if (float32_is_any_nan(a)) {
345 float32 nan = a;
346 if (float32_is_signaling_nan(a)) {
347 float_raise(float_flag_invalid, fpst);
348 nan = float32_maybe_silence_nan(a);
350 if (fpst->default_nan_mode) {
351 nan = float32_default_nan;
353 return nan;
356 val32 = float32_val(a);
357 sbit = 0x80000000ULL & val32;
358 exp = extract32(val32, 23, 8);
360 if (exp == 0) {
361 return make_float32(sbit | (0xfe << 23));
362 } else {
363 return make_float32(sbit | (~exp & 0xff) << 23);
367 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
369 float_status *fpst = fpstp;
370 uint64_t val64, sbit;
371 int64_t exp;
373 if (float64_is_any_nan(a)) {
374 float64 nan = a;
375 if (float64_is_signaling_nan(a)) {
376 float_raise(float_flag_invalid, fpst);
377 nan = float64_maybe_silence_nan(a);
379 if (fpst->default_nan_mode) {
380 nan = float64_default_nan;
382 return nan;
385 val64 = float64_val(a);
386 sbit = 0x8000000000000000ULL & val64;
387 exp = extract64(float64_val(a), 52, 11);
389 if (exp == 0) {
390 return make_float64(sbit | (0x7feULL << 52));
391 } else {
392 return make_float64(sbit | (~exp & 0x7ffULL) << 52);
396 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
398 /* Von Neumann rounding is implemented by using round-to-zero
399 * and then setting the LSB of the result if Inexact was raised.
401 float32 r;
402 float_status *fpst = &env->vfp.fp_status;
403 float_status tstat = *fpst;
404 int exflags;
406 set_float_rounding_mode(float_round_to_zero, &tstat);
407 set_float_exception_flags(0, &tstat);
408 r = float64_to_float32(a, &tstat);
409 r = float32_maybe_silence_nan(r);
410 exflags = get_float_exception_flags(&tstat);
411 if (exflags & float_flag_inexact) {
412 r = make_float32(float32_val(r) | 1);
414 exflags |= get_float_exception_flags(fpst);
415 set_float_exception_flags(exflags, fpst);
416 return r;
419 /* 64-bit versions of the CRC helpers. Note that although the operation
420 * (and the prototypes of crc32c() and crc32() mean that only the bottom
421 * 32 bits of the accumulator and result are used, we pass and return
422 * uint64_t for convenience of the generated code. Unlike the 32-bit
423 * instruction set versions, val may genuinely have 64 bits of data in it.
424 * The upper bytes of val (above the number specified by 'bytes') must have
425 * been zeroed out by the caller.
427 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
429 uint8_t buf[8];
431 stq_le_p(buf, val);
433 /* zlib crc32 converts the accumulator and output to one's complement. */
434 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
437 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
439 uint8_t buf[8];
441 stq_le_p(buf, val);
443 /* Linux crc32c converts the output to one's complement. */
444 return crc32c(acc, buf, bytes) ^ 0xffffffff;