2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/internals.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/acpi/generic_event_device.h"
80 #include "hw/virtio/virtio-md-pci.h"
81 #include "hw/virtio/virtio-iommu.h"
82 #include "hw/char/pl011.h"
83 #include "qemu/guest-random.h"
85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
89 MachineClass *mc = MACHINE_CLASS(oc); \
90 virt_machine_##major##_##minor##_options(mc); \
91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
96 static const TypeInfo machvirt_##major##_##minor##_info = { \
97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
98 .parent = TYPE_VIRT_MACHINE, \
99 .class_init = virt_##major##_##minor##_class_init, \
101 static void machvirt_machine_##major##_##minor##_init(void) \
103 type_register_static(&machvirt_##major##_##minor##_info); \
105 type_init(machvirt_machine_##major##_##minor##_init);
107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
109 #define DEFINE_VIRT_MACHINE(major, minor) \
110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
113 /* Number of external interrupt lines to configure the GIC with */
116 #define PLATFORM_BUS_NUM_IRQS 64
118 /* Legacy RAM limit in GB (< version 4.0) */
119 #define LEGACY_RAMLIMIT_GB 255
120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
122 /* Addresses and sizes of our components.
123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
124 * 128MB..256MB is used for miscellaneous device I/O.
125 * 256MB..1GB is reserved for possible future PCI support (ie where the
126 * PCI memory window will go if we add a PCI host controller).
127 * 1GB and up is RAM (which may happily spill over into the
128 * high memory region beyond 4GB).
129 * This represents a compromise between how much RAM can be given to
130 * a 32 bit VM and leaving space for expansion and in particular for PCI.
131 * Note that devices should generally be placed at multiples of 0x10000,
132 * to accommodate guests using 64K pages.
134 static const MemMapEntry base_memmap
[] = {
135 /* Space up to 0x8000000 is reserved for a boot ROM */
136 [VIRT_FLASH
] = { 0, 0x08000000 },
137 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
139 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
140 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
141 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
142 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
143 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
145 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
146 /* This redistributor space allows up to 2*64kB*123 CPUs */
147 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
148 [VIRT_UART
] = { 0x09000000, 0x00001000 },
149 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
150 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
151 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
152 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
153 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
154 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
155 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
156 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
157 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
158 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
159 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
161 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
162 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
163 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
164 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
165 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
166 /* Actual RAM size depends on initial RAM and device memory settings */
167 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
171 * Highmem IO Regions: This memory map is floating, located after the RAM.
172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
173 * top of the RAM, so that its base get the same alignment as the size,
174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
176 * Note the extended_memmap is sized so that it eventually also includes the
177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
178 * index of base_memmap).
180 * The memory map for these Highmem IO Regions can be in legacy or compact
181 * layout, depending on 'compact-highmem' property. With legacy layout, the
182 * PA space for one specific region is always reserved, even if the region
183 * has been disabled or doesn't fit into the PA space. However, the PA space
184 * for the region won't be reserved in these circumstances with compact layout.
186 static MemMapEntry extended_memmap
[] = {
187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
188 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
189 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
190 /* Second PCIe window */
191 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
194 static const int a15irqmap
[] = {
197 [VIRT_PCIE
] = 3, /* ... to 6 */
199 [VIRT_SECURE_UART
] = 8,
201 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
202 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
203 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
204 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
207 static const char *valid_cpus
[] = {
209 ARM_CPU_TYPE_NAME("cortex-a7"),
210 ARM_CPU_TYPE_NAME("cortex-a15"),
211 ARM_CPU_TYPE_NAME("cortex-a35"),
212 ARM_CPU_TYPE_NAME("cortex-a55"),
213 ARM_CPU_TYPE_NAME("cortex-a72"),
214 ARM_CPU_TYPE_NAME("cortex-a76"),
215 ARM_CPU_TYPE_NAME("cortex-a710"),
216 ARM_CPU_TYPE_NAME("a64fx"),
217 ARM_CPU_TYPE_NAME("neoverse-n1"),
218 ARM_CPU_TYPE_NAME("neoverse-v1"),
219 ARM_CPU_TYPE_NAME("neoverse-n2"),
221 ARM_CPU_TYPE_NAME("cortex-a53"),
222 ARM_CPU_TYPE_NAME("cortex-a57"),
223 ARM_CPU_TYPE_NAME("host"),
224 ARM_CPU_TYPE_NAME("max"),
227 static bool cpu_type_valid(const char *cpu
)
231 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
232 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
239 static void create_randomness(MachineState
*ms
, const char *node
)
246 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
249 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
250 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
253 static void create_fdt(VirtMachineState
*vms
)
255 MachineState
*ms
= MACHINE(vms
);
256 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
257 void *fdt
= create_device_tree(&vms
->fdt_size
);
260 error_report("create_device_tree() failed");
267 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
268 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
269 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
270 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
272 /* /chosen must exist for load_dtb to fill in necessary properties later */
273 qemu_fdt_add_subnode(fdt
, "/chosen");
274 if (vms
->dtb_randomness
) {
275 create_randomness(ms
, "/chosen");
279 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
280 if (vms
->dtb_randomness
) {
281 create_randomness(ms
, "/secure-chosen");
285 /* Clock node, for the benefit of the UART. The kernel device tree
286 * binding documentation claims the PL011 node clock properties are
287 * optional but in practice if you omit them the kernel refuses to
288 * probe for the device.
290 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
291 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
292 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
293 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
294 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
295 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
297 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
299 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
300 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
301 uint32_t *matrix
= g_malloc0(size
);
304 for (i
= 0; i
< nb_numa_nodes
; i
++) {
305 for (j
= 0; j
< nb_numa_nodes
; j
++) {
306 idx
= (i
* nb_numa_nodes
+ j
) * 3;
307 matrix
[idx
+ 0] = cpu_to_be32(i
);
308 matrix
[idx
+ 1] = cpu_to_be32(j
);
310 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
314 qemu_fdt_add_subnode(fdt
, "/distance-map");
315 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
316 "numa-distance-map-v1");
317 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
323 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
325 /* On real hardware these interrupts are level-triggered.
326 * On KVM they were edge-triggered before host kernel version 4.4,
327 * and level-triggered afterwards.
328 * On emulated QEMU they are level-triggered.
330 * Getting the DTB info about them wrong is awkward for some
332 * pre-4.8 ignore the DT and leave the interrupt configured
333 * with whatever the GIC reset value (or the bootloader) left it at
334 * 4.8 before rc6 honour the incorrect data by programming it back
335 * into the GIC, causing problems
336 * 4.8rc6 and later ignore the DT and always write "level triggered"
339 * For backwards-compatibility, virt-2.8 and earlier will continue
340 * to say these are edge-triggered, but later machines will report
341 * the correct information.
344 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
345 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
346 MachineState
*ms
= MACHINE(vms
);
348 if (vmc
->claim_edge_triggered_timers
) {
349 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
352 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
353 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
354 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
355 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
358 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
360 armcpu
= ARM_CPU(qemu_get_cpu(0));
361 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
362 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
363 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
364 compat
, sizeof(compat
));
366 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
369 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
370 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
371 GIC_FDT_IRQ_TYPE_PPI
,
372 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
373 GIC_FDT_IRQ_TYPE_PPI
,
374 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
375 GIC_FDT_IRQ_TYPE_PPI
,
376 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
377 GIC_FDT_IRQ_TYPE_PPI
,
378 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
381 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
385 const MachineState
*ms
= MACHINE(vms
);
386 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
387 int smp_cpus
= ms
->smp
.cpus
;
390 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
391 * On ARM v8 64-bit systems value should be set to 2,
392 * that corresponds to the MPIDR_EL1 register size.
393 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
394 * in the system, #address-cells can be set to 1, since
395 * MPIDR_EL1[63:32] bits are not used for CPUs
398 * Here we actually don't know whether our system is 32- or 64-bit one.
399 * The simplest way to go is to examine affinity IDs of all our CPUs. If
400 * at least one of them has Aff3 populated, we set #address-cells to 2.
402 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
403 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
405 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
411 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
412 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
413 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
415 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
416 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
417 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
418 CPUState
*cs
= CPU(armcpu
);
420 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
421 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
422 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
423 armcpu
->dtb_compatible
);
425 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
426 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
427 "enable-method", "psci");
430 if (addr_cells
== 2) {
431 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
432 armcpu
->mp_affinity
);
434 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
435 armcpu
->mp_affinity
);
438 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
439 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
440 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
443 if (!vmc
->no_cpu_topology
) {
444 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
445 qemu_fdt_alloc_phandle(ms
->fdt
));
451 if (!vmc
->no_cpu_topology
) {
453 * Add vCPU topology description through fdt node cpu-map.
455 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
456 * In a SMP system, the hierarchy of CPUs can be defined through
457 * four entities that are used to describe the layout of CPUs in
458 * the system: socket/cluster/core/thread.
460 * A socket node represents the boundary of system physical package
461 * and its child nodes must be one or more cluster nodes. A system
462 * can contain several layers of clustering within a single physical
463 * package and cluster nodes can be contained in parent cluster nodes.
465 * Note: currently we only support one layer of clustering within
466 * each physical package.
468 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
470 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
471 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
474 if (ms
->smp
.threads
> 1) {
475 map_path
= g_strdup_printf(
476 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
477 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
478 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
479 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
480 cpu
% ms
->smp
.threads
);
482 map_path
= g_strdup_printf(
483 "/cpus/cpu-map/socket%d/cluster%d/core%d",
484 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
485 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
486 cpu
% ms
->smp
.cores
);
488 qemu_fdt_add_path(ms
->fdt
, map_path
);
489 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
497 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
500 MachineState
*ms
= MACHINE(vms
);
502 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
503 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
504 vms
->memmap
[VIRT_GIC_ITS
].base
);
505 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
506 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
508 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
509 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
510 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
511 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
512 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
513 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
517 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
519 MachineState
*ms
= MACHINE(vms
);
522 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
523 vms
->memmap
[VIRT_GIC_V2M
].base
);
524 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
525 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
526 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
527 "arm,gic-v2m-frame");
528 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
529 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
530 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
531 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
532 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
536 static void fdt_add_gic_node(VirtMachineState
*vms
)
538 MachineState
*ms
= MACHINE(vms
);
541 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
542 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
544 nodename
= g_strdup_printf("/intc@%" PRIx64
,
545 vms
->memmap
[VIRT_GIC_DIST
].base
);
546 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
547 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
548 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
549 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
550 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
551 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
552 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
553 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
555 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
558 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
559 "#redistributor-regions", nb_redist_regions
);
561 if (nb_redist_regions
== 1) {
562 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
563 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
564 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
565 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
566 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
568 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
569 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
570 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
571 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
572 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
573 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
574 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
578 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
579 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
580 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
583 /* 'cortex-a15-gic' means 'GIC v2' */
584 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
585 "arm,cortex-a15-gic");
587 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
588 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
589 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
590 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
591 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
593 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
594 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
595 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
596 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
597 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
598 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
599 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
600 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
601 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
602 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
603 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
604 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
608 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
612 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
614 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
615 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
616 MachineState
*ms
= MACHINE(vms
);
618 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
619 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
623 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
624 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
625 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
626 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
629 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
630 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
631 const char compat
[] = "arm,armv8-pmuv3";
632 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
633 compat
, sizeof(compat
));
634 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
635 GIC_FDT_IRQ_TYPE_PPI
,
636 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
640 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
643 MachineState
*ms
= MACHINE(vms
);
644 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
645 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
648 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
651 if (ms
->nvdimms_state
->is_enabled
) {
652 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
655 dev
= qdev_new(TYPE_ACPI_GED
);
656 qdev_prop_set_uint32(dev
, "ged-event", event
);
657 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
659 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
660 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
661 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
666 static void create_its(VirtMachineState
*vms
)
668 const char *itsclass
= its_class_name();
671 if (!strcmp(itsclass
, "arm-gicv3-its")) {
678 /* Do nothing if not supported */
682 dev
= qdev_new(itsclass
);
684 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
686 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
687 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
689 fdt_add_its_gic_node(vms
);
690 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
693 static void create_v2m(VirtMachineState
*vms
)
696 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
699 dev
= qdev_new("arm-gicv2m");
700 qdev_prop_set_uint32(dev
, "base-spi", irq
);
701 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
702 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
703 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
705 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
706 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
707 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
710 fdt_add_v2m_gic_node(vms
);
711 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
714 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
716 MachineState
*ms
= MACHINE(vms
);
717 /* We create a standalone GIC */
718 SysBusDevice
*gicbusdev
;
721 unsigned int smp_cpus
= ms
->smp
.cpus
;
722 uint32_t nb_redist_regions
= 0;
725 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
726 gictype
= gic_class_name();
728 gictype
= gicv3_class_name();
731 switch (vms
->gic_version
) {
732 case VIRT_GIC_VERSION_2
:
735 case VIRT_GIC_VERSION_3
:
738 case VIRT_GIC_VERSION_4
:
742 g_assert_not_reached();
744 vms
->gic
= qdev_new(gictype
);
745 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
746 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
747 /* Note that the num-irq property counts both internal and external
748 * interrupts; there are always 32 of the former (mandated by GIC spec).
750 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
751 if (!kvm_irqchip_in_kernel()) {
752 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
755 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
756 QList
*redist_region_count
;
757 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
758 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
760 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
762 redist_region_count
= qlist_new();
763 qlist_append_int(redist_region_count
, redist0_count
);
764 if (nb_redist_regions
== 2) {
765 uint32_t redist1_capacity
=
766 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
768 qlist_append_int(redist_region_count
,
769 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
771 qdev_prop_set_array(vms
->gic
, "redist-region-count",
772 redist_region_count
);
774 if (!kvm_irqchip_in_kernel()) {
776 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
777 OBJECT(mem
), &error_fatal
);
778 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
782 if (!kvm_irqchip_in_kernel()) {
783 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
787 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
788 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
789 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
790 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
791 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
792 if (nb_redist_regions
== 2) {
793 sysbus_mmio_map(gicbusdev
, 2,
794 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
797 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
799 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
800 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
804 /* Wire the outputs from each CPU's generic timer and the GICv3
805 * maintenance interrupt signal to the appropriate GIC PPI inputs,
806 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
808 for (i
= 0; i
< smp_cpus
; i
++) {
809 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
810 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
811 /* Mapping from the output timer irq lines from the CPU to the
812 * GIC PPI inputs we use for the virt board.
814 const int timer_irq
[] = {
815 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
816 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
817 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
818 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
821 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
822 qdev_connect_gpio_out(cpudev
, irq
,
823 qdev_get_gpio_in(vms
->gic
,
824 intidbase
+ timer_irq
[irq
]));
827 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
828 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
829 intidbase
+ ARCH_GIC_MAINT_IRQ
);
830 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
832 } else if (vms
->virt
) {
833 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
834 intidbase
+ ARCH_GIC_MAINT_IRQ
);
835 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
838 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
839 qdev_get_gpio_in(vms
->gic
, intidbase
842 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
843 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
844 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
845 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
846 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
847 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
848 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
851 fdt_add_gic_node(vms
);
853 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
855 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
860 static void create_uart(const VirtMachineState
*vms
, int uart
,
861 MemoryRegion
*mem
, Chardev
*chr
)
864 hwaddr base
= vms
->memmap
[uart
].base
;
865 hwaddr size
= vms
->memmap
[uart
].size
;
866 int irq
= vms
->irqmap
[uart
];
867 const char compat
[] = "arm,pl011\0arm,primecell";
868 const char clocknames
[] = "uartclk\0apb_pclk";
869 DeviceState
*dev
= qdev_new(TYPE_PL011
);
870 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
871 MachineState
*ms
= MACHINE(vms
);
873 qdev_prop_set_chr(dev
, "chardev", chr
);
874 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
875 memory_region_add_subregion(mem
, base
,
876 sysbus_mmio_get_region(s
, 0));
877 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
879 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
880 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
881 /* Note that we can't use setprop_string because of the embedded NUL */
882 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
883 compat
, sizeof(compat
));
884 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
886 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
887 GIC_FDT_IRQ_TYPE_SPI
, irq
,
888 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
889 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
890 vms
->clock_phandle
, vms
->clock_phandle
);
891 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
892 clocknames
, sizeof(clocknames
));
894 if (uart
== VIRT_UART
) {
895 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
897 /* Mark as not usable by the normal world */
898 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
899 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
901 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
908 static void create_rtc(const VirtMachineState
*vms
)
911 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
912 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
913 int irq
= vms
->irqmap
[VIRT_RTC
];
914 const char compat
[] = "arm,pl031\0arm,primecell";
915 MachineState
*ms
= MACHINE(vms
);
917 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
919 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
920 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
921 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
922 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
924 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
925 GIC_FDT_IRQ_TYPE_SPI
, irq
,
926 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
927 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
928 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
932 static DeviceState
*gpio_key_dev
;
933 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
935 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
938 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
940 /* use gpio Pin 3 for power button event */
941 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
945 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
948 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
949 qdev_get_gpio_in(pl061_dev
, 3));
951 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
952 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
954 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
955 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
956 "label", "GPIO Key Poweroff");
957 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
959 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
960 "gpios", phandle
, 3, 0);
963 #define SECURE_GPIO_POWEROFF 0
964 #define SECURE_GPIO_RESET 1
966 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
969 DeviceState
*gpio_pwr_dev
;
972 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
974 /* connect secure pl061 to gpio-pwr */
975 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
976 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
977 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
978 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
980 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
981 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
983 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
984 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
985 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
986 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
989 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
990 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
992 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
993 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
994 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
995 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
999 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
1003 DeviceState
*pl061_dev
;
1004 hwaddr base
= vms
->memmap
[gpio
].base
;
1005 hwaddr size
= vms
->memmap
[gpio
].size
;
1006 int irq
= vms
->irqmap
[gpio
];
1007 const char compat
[] = "arm,pl061\0arm,primecell";
1009 MachineState
*ms
= MACHINE(vms
);
1011 pl061_dev
= qdev_new("pl061");
1012 /* Pull lines down to 0 if not driven by the PL061 */
1013 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1014 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1015 s
= SYS_BUS_DEVICE(pl061_dev
);
1016 sysbus_realize_and_unref(s
, &error_fatal
);
1017 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1018 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1020 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1021 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1022 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1023 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1025 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1026 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1027 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1028 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1029 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1030 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1031 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1032 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1033 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1035 if (gpio
!= VIRT_GPIO
) {
1036 /* Mark as not usable by the normal world */
1037 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1038 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1042 /* Child gpio devices */
1043 if (gpio
== VIRT_GPIO
) {
1044 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1046 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1050 static void create_virtio_devices(const VirtMachineState
*vms
)
1053 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1054 MachineState
*ms
= MACHINE(vms
);
1056 /* We create the transports in forwards order. Since qbus_realize()
1057 * prepends (not appends) new child buses, the incrementing loop below will
1058 * create a list of virtio-mmio buses with decreasing base addresses.
1060 * When a -device option is processed from the command line,
1061 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1062 * order. The upshot is that -device options in increasing command line
1063 * order are mapped to virtio-mmio buses with decreasing base addresses.
1065 * When this code was originally written, that arrangement ensured that the
1066 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1067 * the first -device on the command line. (The end-to-end order is a
1068 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1069 * guest kernel's name-to-address assignment strategy.)
1071 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1072 * the message, if not necessarily the code, of commit 70161ff336.
1073 * Therefore the loop now establishes the inverse of the original intent.
1075 * Unfortunately, we can't counteract the kernel change by reversing the
1076 * loop; it would break existing command lines.
1078 * In any case, the kernel makes no guarantee about the stability of
1079 * enumeration order of virtio devices (as demonstrated by it changing
1080 * between kernel versions). For reliable and stable identification
1081 * of disks users must use UUIDs or similar mechanisms.
1083 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1084 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1085 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1087 sysbus_create_simple("virtio-mmio", base
,
1088 qdev_get_gpio_in(vms
->gic
, irq
));
1091 /* We add dtb nodes in reverse order so that they appear in the finished
1092 * device tree lowest address first.
1094 * Note that this mapping is independent of the loop above. The previous
1095 * loop influences virtio device to virtio transport assignment, whereas
1096 * this loop controls how virtio transports are laid out in the dtb.
1098 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1100 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1101 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1103 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1104 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1105 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1106 "compatible", "virtio,mmio");
1107 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1109 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1110 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1111 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1112 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1117 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1119 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1121 const char *alias_prop_name
)
1124 * Create a single flash device. We use the same parameters as
1125 * the flash devices on the Versatile Express board.
1127 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1129 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1130 qdev_prop_set_uint8(dev
, "width", 4);
1131 qdev_prop_set_uint8(dev
, "device-width", 2);
1132 qdev_prop_set_bit(dev
, "big-endian", false);
1133 qdev_prop_set_uint16(dev
, "id0", 0x89);
1134 qdev_prop_set_uint16(dev
, "id1", 0x18);
1135 qdev_prop_set_uint16(dev
, "id2", 0x00);
1136 qdev_prop_set_uint16(dev
, "id3", 0x00);
1137 qdev_prop_set_string(dev
, "name", name
);
1138 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1139 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1140 OBJECT(dev
), "drive");
1141 return PFLASH_CFI01(dev
);
1144 static void virt_flash_create(VirtMachineState
*vms
)
1146 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1147 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1150 static void virt_flash_map1(PFlashCFI01
*flash
,
1151 hwaddr base
, hwaddr size
,
1152 MemoryRegion
*sysmem
)
1154 DeviceState
*dev
= DEVICE(flash
);
1156 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1157 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1158 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1159 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1161 memory_region_add_subregion(sysmem
, base
,
1162 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1166 static void virt_flash_map(VirtMachineState
*vms
,
1167 MemoryRegion
*sysmem
,
1168 MemoryRegion
*secure_sysmem
)
1171 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1172 * sysmem is the system memory space. secure_sysmem is the secure view
1173 * of the system, and the first flash device should be made visible only
1174 * there. The second flash device is visible to both secure and nonsecure.
1175 * If sysmem == secure_sysmem this means there is no separate Secure
1176 * address space and both flash devices are generally visible.
1178 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1179 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1181 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1183 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1187 static void virt_flash_fdt(VirtMachineState
*vms
,
1188 MemoryRegion
*sysmem
,
1189 MemoryRegion
*secure_sysmem
)
1191 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1192 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1193 MachineState
*ms
= MACHINE(vms
);
1196 if (sysmem
== secure_sysmem
) {
1197 /* Report both flash devices as a single node in the DT */
1198 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1199 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1200 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1201 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1202 2, flashbase
, 2, flashsize
,
1203 2, flashbase
+ flashsize
, 2, flashsize
);
1204 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1208 * Report the devices as separate nodes so we can mark one as
1209 * only visible to the secure world.
1211 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1212 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1213 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1214 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1215 2, flashbase
, 2, flashsize
);
1216 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1217 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1218 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1221 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1222 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1223 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1224 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1225 2, flashbase
+ flashsize
, 2, flashsize
);
1226 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1231 static bool virt_firmware_init(VirtMachineState
*vms
,
1232 MemoryRegion
*sysmem
,
1233 MemoryRegion
*secure_sysmem
)
1236 const char *bios_name
;
1237 BlockBackend
*pflash_blk0
;
1239 /* Map legacy -drive if=pflash to machine properties */
1240 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1241 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1242 drive_get(IF_PFLASH
, 0, i
));
1245 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1247 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1249 bios_name
= MACHINE(vms
)->firmware
;
1256 error_report("The contents of the first flash device may be "
1257 "specified with -bios or with -drive if=pflash... "
1258 "but you cannot use both options at once");
1262 /* Fall back to -bios */
1264 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1266 error_report("Could not find ROM image '%s'", bios_name
);
1269 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1270 image_size
= load_image_mr(fname
, mr
);
1272 if (image_size
< 0) {
1273 error_report("Could not load ROM image '%s'", bios_name
);
1278 return pflash_blk0
|| bios_name
;
1281 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1283 MachineState
*ms
= MACHINE(vms
);
1284 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1285 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1289 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1290 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1292 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1293 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1294 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1295 "compatible", "qemu,fw-cfg-mmio");
1296 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1298 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1303 static void create_pcie_irq_map(const MachineState
*ms
,
1304 uint32_t gic_phandle
,
1305 int first_irq
, const char *nodename
)
1308 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1309 uint32_t *irq_map
= full_irq_map
;
1311 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1312 for (pin
= 0; pin
< 4; pin
++) {
1313 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1314 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1315 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1319 devfn
<< 8, 0, 0, /* devfn */
1320 pin
+ 1, /* PCI pin */
1321 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1323 /* Convert map to big endian */
1324 for (i
= 0; i
< 10; i
++) {
1325 irq_map
[i
] = cpu_to_be32(map
[i
]);
1331 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1332 full_irq_map
, sizeof(full_irq_map
));
1334 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1335 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1340 static void create_smmu(const VirtMachineState
*vms
,
1344 const char compat
[] = "arm,smmu-v3";
1345 int irq
= vms
->irqmap
[VIRT_SMMU
];
1347 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1348 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1349 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1351 MachineState
*ms
= MACHINE(vms
);
1353 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1357 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1359 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1361 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1362 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1363 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1364 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1365 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1368 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1369 qemu_fdt_add_subnode(ms
->fdt
, node
);
1370 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1371 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1373 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1374 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1375 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1376 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1377 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1379 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1382 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1384 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1386 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1390 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1392 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1393 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1394 MachineState
*ms
= MACHINE(vms
);
1397 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1399 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1400 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1401 qemu_fdt_add_subnode(ms
->fdt
, node
);
1402 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1403 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1404 1, bdf
<< 8, 1, 0, 1, 0,
1407 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1408 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1411 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1412 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1413 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1416 static void create_pcie(VirtMachineState
*vms
)
1418 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1419 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1420 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1421 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1422 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1423 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1424 hwaddr base_ecam
, size_ecam
;
1425 hwaddr base
= base_mmio
;
1427 int irq
= vms
->irqmap
[VIRT_PCIE
];
1428 MemoryRegion
*mmio_alias
;
1429 MemoryRegion
*mmio_reg
;
1430 MemoryRegion
*ecam_alias
;
1431 MemoryRegion
*ecam_reg
;
1436 MachineState
*ms
= MACHINE(vms
);
1437 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1439 dev
= qdev_new(TYPE_GPEX_HOST
);
1440 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1442 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1443 base_ecam
= vms
->memmap
[ecam_id
].base
;
1444 size_ecam
= vms
->memmap
[ecam_id
].size
;
1445 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1446 /* Map only the first size_ecam bytes of ECAM space */
1447 ecam_alias
= g_new0(MemoryRegion
, 1);
1448 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1449 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1450 ecam_reg
, 0, size_ecam
);
1451 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1453 /* Map the MMIO window into system address space so as to expose
1454 * the section of PCI MMIO space which starts at the same base address
1455 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1458 mmio_alias
= g_new0(MemoryRegion
, 1);
1459 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1460 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1461 mmio_reg
, base_mmio
, size_mmio
);
1462 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1464 if (vms
->highmem_mmio
) {
1465 /* Map high MMIO space */
1466 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1468 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1469 mmio_reg
, base_mmio_high
, size_mmio_high
);
1470 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1474 /* Map IO port space */
1475 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1477 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1478 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1479 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1480 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1483 pci
= PCI_HOST_BRIDGE(dev
);
1484 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1485 vms
->bus
= pci
->bus
;
1487 for (i
= 0; i
< nb_nics
; i
++) {
1488 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
1492 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1493 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1494 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1495 "compatible", "pci-host-ecam-generic");
1496 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1497 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1498 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1499 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1500 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1502 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1504 if (vms
->msi_phandle
) {
1505 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1506 0, vms
->msi_phandle
, 0, 0x10000);
1509 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1510 2, base_ecam
, 2, size_ecam
);
1512 if (vms
->highmem_mmio
) {
1513 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1514 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1515 2, base_pio
, 2, size_pio
,
1516 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1517 2, base_mmio
, 2, size_mmio
,
1518 1, FDT_PCI_RANGE_MMIO_64BIT
,
1520 2, base_mmio_high
, 2, size_mmio_high
);
1522 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1523 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1524 2, base_pio
, 2, size_pio
,
1525 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1526 2, base_mmio
, 2, size_mmio
);
1529 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1530 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1533 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1535 switch (vms
->iommu
) {
1536 case VIRT_IOMMU_SMMUV3
:
1537 create_smmu(vms
, vms
->bus
);
1538 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1539 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1542 g_assert_not_reached();
1547 static void create_platform_bus(VirtMachineState
*vms
)
1552 MemoryRegion
*sysmem
= get_system_memory();
1554 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1555 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1556 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1557 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1558 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1559 vms
->platform_bus_dev
= dev
;
1561 s
= SYS_BUS_DEVICE(dev
);
1562 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1563 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1564 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1567 memory_region_add_subregion(sysmem
,
1568 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1569 sysbus_mmio_get_region(s
, 0));
1572 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1573 hwaddr base
, hwaddr size
,
1576 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1578 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1579 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1582 static void create_secure_ram(VirtMachineState
*vms
,
1583 MemoryRegion
*secure_sysmem
,
1584 MemoryRegion
*secure_tag_sysmem
)
1586 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1588 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1589 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1590 MachineState
*ms
= MACHINE(vms
);
1592 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1594 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1596 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1597 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1598 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1599 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1600 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1601 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1603 if (secure_tag_sysmem
) {
1604 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1610 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1612 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1614 MachineState
*ms
= MACHINE(board
);
1617 *fdt_size
= board
->fdt_size
;
1621 static void virt_build_smbios(VirtMachineState
*vms
)
1623 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1624 MachineState
*ms
= MACHINE(vms
);
1625 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1626 uint8_t *smbios_tables
, *smbios_anchor
;
1627 size_t smbios_tables_len
, smbios_anchor_len
;
1628 struct smbios_phys_mem_area mem_array
;
1629 const char *product
= "QEMU Virtual Machine";
1631 if (kvm_enabled()) {
1632 product
= "KVM Virtual Machine";
1635 smbios_set_defaults("QEMU", product
,
1636 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1637 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1639 /* build the array of physical mem area from base_memmap */
1640 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1641 mem_array
.length
= ms
->ram_size
;
1643 smbios_get_tables(ms
, &mem_array
, 1,
1644 &smbios_tables
, &smbios_tables_len
,
1645 &smbios_anchor
, &smbios_anchor_len
,
1648 if (smbios_anchor
) {
1649 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1650 smbios_tables
, smbios_tables_len
);
1651 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1652 smbios_anchor
, smbios_anchor_len
);
1657 void virt_machine_done(Notifier
*notifier
, void *data
)
1659 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1661 MachineState
*ms
= MACHINE(vms
);
1662 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1663 struct arm_boot_info
*info
= &vms
->bootinfo
;
1664 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1667 * If the user provided a dtb, we assume the dynamic sysbus nodes
1668 * already are integrated there. This corresponds to a use case where
1669 * the dynamic sysbus nodes are complex and their generation is not yet
1670 * supported. In that case the user can take charge of the guest dt
1671 * while qemu takes charge of the qom stuff.
1673 if (info
->dtb_filename
== NULL
) {
1674 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1675 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1676 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1677 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1679 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1683 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1685 virt_acpi_setup(vms
);
1686 virt_build_smbios(vms
);
1689 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1691 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1692 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1694 if (!vmc
->disallow_affinity_adjustment
) {
1695 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1696 * GIC's target-list limitations. 32-bit KVM hosts currently
1697 * always create clusters of 4 CPUs, but that is expected to
1698 * change when they gain support for gicv3. When KVM is enabled
1699 * it will override the changes we make here, therefore our
1700 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1701 * and to improve SGI efficiency.
1703 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1704 clustersz
= GIC_TARGETLIST_BITS
;
1706 clustersz
= GICV3_TARGETLIST_BITS
;
1709 return arm_cpu_mp_affinity(idx
, clustersz
);
1712 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1715 bool *enabled_array
[] = {
1716 &vms
->highmem_redists
,
1721 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1722 ARRAY_SIZE(enabled_array
));
1723 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1725 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1728 static void virt_set_high_memmap(VirtMachineState
*vms
,
1729 hwaddr base
, int pa_bits
)
1731 hwaddr region_base
, region_size
;
1732 bool *region_enabled
, fits
;
1735 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1736 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1737 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1738 region_size
= extended_memmap
[i
].size
;
1740 vms
->memmap
[i
].base
= region_base
;
1741 vms
->memmap
[i
].size
= region_size
;
1744 * Check each device to see if it fits in the PA space,
1745 * moving highest_gpa as we go. For compatibility, move
1746 * highest_gpa for disabled fitting devices as well, if
1747 * the compact layout has been disabled.
1749 * For each device that doesn't fit, disable it.
1751 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1752 *region_enabled
&= fits
;
1753 if (vms
->highmem_compact
&& !*region_enabled
) {
1757 base
= region_base
+ region_size
;
1759 vms
->highest_gpa
= base
- 1;
1764 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1766 MachineState
*ms
= MACHINE(vms
);
1767 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1770 vms
->memmap
= extended_memmap
;
1772 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1773 vms
->memmap
[i
] = base_memmap
[i
];
1776 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1777 error_report("unsupported number of memory slots: %"PRIu64
,
1783 * !highmem is exactly the same as limiting the PA space to 32bit,
1784 * irrespective of the underlying capabilities of the HW.
1786 if (!vms
->highmem
) {
1791 * We compute the base of the high IO region depending on the
1792 * amount of initial and device memory. The device memory start/size
1793 * is aligned on 1GiB. We never put the high IO region below 256GiB
1794 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1795 * The device region size assumes 1GiB page max alignment per slot.
1797 device_memory_base
=
1798 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1799 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1801 /* Base address of the high IO region */
1802 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1803 if (memtop
> BIT_ULL(pa_bits
)) {
1804 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1805 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1808 if (base
< device_memory_base
) {
1809 error_report("maxmem/slots too huge");
1812 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1813 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1816 /* We know for sure that at least the memory fits in the PA space */
1817 vms
->highest_gpa
= memtop
- 1;
1819 virt_set_high_memmap(vms
, base
, pa_bits
);
1821 if (device_memory_size
> 0) {
1822 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1826 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1827 VirtGICType gic_version
,
1829 unsigned int max_cpus
)
1831 /* Convert host/max/nosel to GIC version number */
1832 switch (gic_version
) {
1833 case VIRT_GIC_VERSION_HOST
:
1834 if (!kvm_enabled()) {
1835 error_report("gic-version=host requires KVM");
1839 /* For KVM, gic-version=host means gic-version=max */
1840 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1841 gics_supported
, max_cpus
);
1842 case VIRT_GIC_VERSION_MAX
:
1843 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1844 gic_version
= VIRT_GIC_VERSION_4
;
1845 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1846 gic_version
= VIRT_GIC_VERSION_3
;
1848 gic_version
= VIRT_GIC_VERSION_2
;
1851 case VIRT_GIC_VERSION_NOSEL
:
1852 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1853 max_cpus
<= GIC_NCPU
) {
1854 gic_version
= VIRT_GIC_VERSION_2
;
1855 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1857 * in case the host does not support v2 emulation or
1858 * the end-user requested more than 8 VCPUs we now default
1859 * to v3. In any case defaulting to v2 would be broken.
1861 gic_version
= VIRT_GIC_VERSION_3
;
1862 } else if (max_cpus
> GIC_NCPU
) {
1863 error_report("%s only supports GICv2 emulation but more than 8 "
1864 "vcpus are requested", accel_name
);
1868 case VIRT_GIC_VERSION_2
:
1869 case VIRT_GIC_VERSION_3
:
1870 case VIRT_GIC_VERSION_4
:
1874 /* Check chosen version is effectively supported */
1875 switch (gic_version
) {
1876 case VIRT_GIC_VERSION_2
:
1877 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1878 error_report("%s does not support GICv2 emulation", accel_name
);
1882 case VIRT_GIC_VERSION_3
:
1883 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1884 error_report("%s does not support GICv3 emulation", accel_name
);
1888 case VIRT_GIC_VERSION_4
:
1889 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1890 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1896 error_report("logic error in finalize_gic_version");
1905 * finalize_gic_version - Determines the final gic_version
1906 * according to the gic-version property
1908 * Default GIC type is v2
1910 static void finalize_gic_version(VirtMachineState
*vms
)
1912 const char *accel_name
= current_accel_name();
1913 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1914 int gics_supported
= 0;
1916 /* Determine which GIC versions the current environment supports */
1917 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1918 int probe_bitmap
= kvm_arm_vgic_probe();
1920 if (!probe_bitmap
) {
1921 error_report("Unable to determine GIC version supported by host");
1925 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1926 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1928 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1929 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1931 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1932 /* KVM w/o kernel irqchip can only deal with GICv2 */
1933 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1934 accel_name
= "KVM with kernel-irqchip=off";
1935 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1936 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1937 if (module_object_class_by_name("arm-gicv3")) {
1938 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1940 /* GICv4 only makes sense if CPU has EL2 */
1941 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1945 error_report("Unsupported accelerator, can not determine GIC support");
1950 * Then convert helpers like host/max to concrete GIC versions and ensure
1951 * the desired version is supported
1953 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1954 gics_supported
, max_cpus
);
1958 * virt_cpu_post_init() must be called after the CPUs have
1959 * been realized and the GIC has been created.
1961 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1963 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1964 bool aarch64
, pmu
, steal_time
;
1967 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1968 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1969 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1970 "kvm-steal-time", NULL
);
1972 if (kvm_enabled()) {
1973 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1974 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1977 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1978 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1980 /* The memory region size must be a multiple of host page size. */
1981 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1983 if (pvtime_size
> pvtime_reg_size
) {
1984 error_report("pvtime requires a %" HWADDR_PRId
1985 " byte memory region for %d CPUs,"
1986 " but only %" HWADDR_PRId
" has been reserved",
1987 pvtime_size
, max_cpus
, pvtime_reg_size
);
1991 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1992 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1997 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1998 if (kvm_irqchip_in_kernel()) {
1999 kvm_arm_pmu_set_irq(cpu
, VIRTUAL_PMU_IRQ
);
2001 kvm_arm_pmu_init(cpu
);
2004 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
2005 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
2009 if (aarch64
&& vms
->highmem
) {
2010 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2011 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2013 if (pamax
< requested_pa_size
) {
2014 error_report("VCPU supports less PA bits (%d) than "
2015 "requested by the memory map (%d)",
2016 pamax
, requested_pa_size
);
2023 static void machvirt_init(MachineState
*machine
)
2025 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2026 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2027 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2028 const CPUArchIdList
*possible_cpus
;
2029 MemoryRegion
*sysmem
= get_system_memory();
2030 MemoryRegion
*secure_sysmem
= NULL
;
2031 MemoryRegion
*tag_sysmem
= NULL
;
2032 MemoryRegion
*secure_tag_sysmem
= NULL
;
2033 int n
, virt_max_cpus
;
2034 bool firmware_loaded
;
2035 bool aarch64
= true;
2036 bool has_ged
= !vmc
->no_ged
;
2037 unsigned int smp_cpus
= machine
->smp
.cpus
;
2038 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2040 if (!cpu_type_valid(machine
->cpu_type
)) {
2041 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2045 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2048 * In accelerated mode, the memory map is computed earlier in kvm_type()
2049 * to create a VM with the right number of IPA bits.
2057 * Instantiate a temporary CPU object to find out about what
2058 * we are about to deal with. Once this is done, get rid of
2061 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2062 armcpu
= ARM_CPU(cpuobj
);
2064 pa_bits
= arm_pamax(armcpu
);
2066 object_unref(cpuobj
);
2068 virt_set_memmap(vms
, pa_bits
);
2071 /* We can probe only here because during property set
2072 * KVM is not available yet
2074 finalize_gic_version(vms
);
2078 * The Secure view of the world is the same as the NonSecure,
2079 * but with a few extra devices. Create it as a container region
2080 * containing the system memory at low priority; any secure-only
2081 * devices go in at higher priority and take precedence.
2083 secure_sysmem
= g_new(MemoryRegion
, 1);
2084 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2086 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2089 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2090 secure_sysmem
?: sysmem
);
2092 /* If we have an EL3 boot ROM then the assumption is that it will
2093 * implement PSCI itself, so disable QEMU's internal implementation
2094 * so it doesn't get in the way. Instead of starting secondary
2095 * CPUs in PSCI powerdown state we will start them all running and
2096 * let the boot ROM sort them out.
2097 * The usual case is that we do use QEMU's PSCI implementation;
2098 * if the guest has EL2 then we will use SMC as the conduit,
2099 * and otherwise we will use HVC (for backwards compatibility and
2100 * because if we're using KVM then we must use HVC).
2102 if (vms
->secure
&& firmware_loaded
) {
2103 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2104 } else if (vms
->virt
) {
2105 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2107 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2111 * The maximum number of CPUs depends on the GIC version, or on how
2112 * many redistributors we can fit into the memory map (which in turn
2113 * depends on whether this is a GICv3 or v4).
2115 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2116 virt_max_cpus
= GIC_NCPU
;
2118 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2119 if (vms
->highmem_redists
) {
2120 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2124 if (max_cpus
> virt_max_cpus
) {
2125 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2126 "supported by machine 'mach-virt' (%d)",
2127 max_cpus
, virt_max_cpus
);
2128 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2129 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2135 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2136 error_report("mach-virt: %s does not support providing "
2137 "Security extensions (TrustZone) to the guest CPU",
2138 current_accel_name());
2142 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2143 error_report("mach-virt: %s does not support providing "
2144 "Virtualization extensions to the guest CPU",
2145 current_accel_name());
2149 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2150 error_report("mach-virt: %s does not support providing "
2151 "MTE to the guest CPU",
2152 current_accel_name());
2158 assert(possible_cpus
->len
== max_cpus
);
2159 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2163 if (n
>= smp_cpus
) {
2167 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2168 object_property_set_int(cpuobj
, "mp-affinity",
2169 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2174 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2177 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2180 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2183 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2184 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2187 if (vmc
->kvm_no_adjvtime
&&
2188 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2189 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2192 if (vmc
->no_kvm_steal_time
&&
2193 object_property_find(cpuobj
, "kvm-steal-time")) {
2194 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2197 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2198 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2201 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2202 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2205 if (object_property_find(cpuobj
, "reset-cbar")) {
2206 object_property_set_int(cpuobj
, "reset-cbar",
2207 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2211 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2214 object_property_set_link(cpuobj
, "secure-memory",
2215 OBJECT(secure_sysmem
), &error_abort
);
2219 /* Create the memory region only once, but link to all cpus. */
2222 * The property exists only if MemTag is supported.
2223 * If it is, we must allocate the ram to back that up.
2225 if (!object_property_find(cpuobj
, "tag-memory")) {
2226 error_report("MTE requested, but not supported "
2227 "by the guest CPU");
2231 tag_sysmem
= g_new(MemoryRegion
, 1);
2232 memory_region_init(tag_sysmem
, OBJECT(machine
),
2233 "tag-memory", UINT64_MAX
/ 32);
2236 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2237 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2238 "secure-tag-memory", UINT64_MAX
/ 32);
2240 /* As with ram, secure-tag takes precedence over tag. */
2241 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2246 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2249 object_property_set_link(cpuobj
, "secure-tag-memory",
2250 OBJECT(secure_tag_sysmem
),
2255 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2256 object_unref(cpuobj
);
2258 fdt_add_timer_nodes(vms
);
2259 fdt_add_cpu_nodes(vms
);
2261 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2264 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2266 create_gic(vms
, sysmem
);
2268 virt_cpu_post_init(vms
, sysmem
);
2270 fdt_add_pmu_nodes(vms
);
2272 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2275 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2276 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2280 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2281 machine
->ram_size
, "mach-virt.tag");
2284 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2290 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2291 vms
->acpi_dev
= create_acpi_ged(vms
);
2293 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2296 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2297 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2300 /* connect powerdown request */
2301 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2302 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2304 /* Create mmio transports, so the user can create virtio backends
2305 * (which will be automatically plugged in to the transports). If
2306 * no backend is created the transport will just sit harmlessly idle.
2308 create_virtio_devices(vms
);
2310 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2311 rom_set_fw(vms
->fw_cfg
);
2313 create_platform_bus(vms
);
2315 if (machine
->nvdimms_state
->is_enabled
) {
2316 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2317 .space_id
= AML_AS_SYSTEM_MEMORY
,
2318 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2319 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2322 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2323 arm_virt_nvdimm_acpi_dsmio
,
2324 vms
->fw_cfg
, OBJECT(vms
));
2327 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2328 vms
->bootinfo
.board_id
= -1;
2329 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2330 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2331 vms
->bootinfo
.skip_dtb_autoload
= true;
2332 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2333 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2334 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2336 vms
->machine_done
.notify
= virt_machine_done
;
2337 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2340 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2342 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2347 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2349 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2351 vms
->secure
= value
;
2354 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2356 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2361 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2363 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2368 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2370 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2372 return vms
->highmem
;
2375 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2377 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2379 vms
->highmem
= value
;
2382 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2384 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2386 return vms
->highmem_compact
;
2389 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2391 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2393 vms
->highmem_compact
= value
;
2396 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2398 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2400 return vms
->highmem_redists
;
2403 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2405 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2407 vms
->highmem_redists
= value
;
2410 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2412 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2414 return vms
->highmem_ecam
;
2417 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2419 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2421 vms
->highmem_ecam
= value
;
2424 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2426 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2428 return vms
->highmem_mmio
;
2431 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2433 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2435 vms
->highmem_mmio
= value
;
2439 static bool virt_get_its(Object
*obj
, Error
**errp
)
2441 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2446 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2448 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2453 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2455 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2457 return vms
->dtb_randomness
;
2460 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2462 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2464 vms
->dtb_randomness
= value
;
2467 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2469 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2471 return g_strdup(vms
->oem_id
);
2474 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2476 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2477 size_t len
= strlen(value
);
2481 "User specified oem-id value is bigger than 6 bytes in size");
2485 strncpy(vms
->oem_id
, value
, 6);
2488 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2490 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2492 return g_strdup(vms
->oem_table_id
);
2495 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2498 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2499 size_t len
= strlen(value
);
2503 "User specified oem-table-id value is bigger than 8 bytes in size");
2506 strncpy(vms
->oem_table_id
, value
, 8);
2510 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2512 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2518 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2519 void *opaque
, Error
**errp
)
2521 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2522 OnOffAuto acpi
= vms
->acpi
;
2524 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2527 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2528 void *opaque
, Error
**errp
)
2530 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2532 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2535 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2537 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2542 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2544 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2549 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2551 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2556 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2558 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2563 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2565 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2568 switch (vms
->gic_version
) {
2569 case VIRT_GIC_VERSION_4
:
2572 case VIRT_GIC_VERSION_3
:
2579 return g_strdup(val
);
2582 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2584 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2586 if (!strcmp(value
, "4")) {
2587 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2588 } else if (!strcmp(value
, "3")) {
2589 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2590 } else if (!strcmp(value
, "2")) {
2591 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2592 } else if (!strcmp(value
, "host")) {
2593 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2594 } else if (!strcmp(value
, "max")) {
2595 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2597 error_setg(errp
, "Invalid gic-version value");
2598 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2602 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2604 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2606 switch (vms
->iommu
) {
2607 case VIRT_IOMMU_NONE
:
2608 return g_strdup("none");
2609 case VIRT_IOMMU_SMMUV3
:
2610 return g_strdup("smmuv3");
2612 g_assert_not_reached();
2616 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2618 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2620 if (!strcmp(value
, "smmuv3")) {
2621 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2622 } else if (!strcmp(value
, "none")) {
2623 vms
->iommu
= VIRT_IOMMU_NONE
;
2625 error_setg(errp
, "Invalid iommu value");
2626 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2630 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2632 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2634 return vms
->default_bus_bypass_iommu
;
2637 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2640 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2642 vms
->default_bus_bypass_iommu
= value
;
2645 static CpuInstanceProperties
2646 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2648 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2649 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2651 assert(cpu_index
< possible_cpus
->len
);
2652 return possible_cpus
->cpus
[cpu_index
].props
;
2655 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2657 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2659 return socket_id
% ms
->numa_state
->num_nodes
;
2662 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2665 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2666 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2667 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2669 if (ms
->possible_cpus
) {
2670 assert(ms
->possible_cpus
->len
== max_cpus
);
2671 return ms
->possible_cpus
;
2674 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2675 sizeof(CPUArchId
) * max_cpus
);
2676 ms
->possible_cpus
->len
= max_cpus
;
2677 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2678 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2679 ms
->possible_cpus
->cpus
[n
].arch_id
=
2680 virt_cpu_mp_affinity(vms
, n
);
2682 assert(!mc
->smp_props
.dies_supported
);
2683 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2684 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2685 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2686 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2687 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2688 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2689 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2690 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2691 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2692 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2693 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2694 n
% ms
->smp
.threads
;
2696 return ms
->possible_cpus
;
2699 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2702 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2703 const MachineState
*ms
= MACHINE(hotplug_dev
);
2704 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2706 if (!vms
->acpi_dev
) {
2708 "memory hotplug is not enabled: missing acpi-ged device");
2713 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2717 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2718 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2722 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2725 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2726 DeviceState
*dev
, Error
**errp
)
2728 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2729 MachineState
*ms
= MACHINE(hotplug_dev
);
2730 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2732 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2735 nvdimm_plug(ms
->nvdimms_state
);
2738 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2742 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2743 DeviceState
*dev
, Error
**errp
)
2745 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2747 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2748 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2749 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2750 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2751 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2752 hwaddr db_start
= 0, db_end
= 0;
2753 QList
*reserved_regions
;
2754 char *resv_prop_str
;
2756 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2757 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2761 switch (vms
->msi_controller
) {
2762 case VIRT_MSI_CTRL_NONE
:
2764 case VIRT_MSI_CTRL_ITS
:
2765 /* GITS_TRANSLATER page */
2766 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2767 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2768 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2770 case VIRT_MSI_CTRL_GICV2M
:
2771 /* MSI_SETSPI_NS page */
2772 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2773 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2776 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2778 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2780 reserved_regions
= qlist_new();
2781 qlist_append_str(reserved_regions
, resv_prop_str
);
2782 qdev_prop_set_array(dev
, "reserved-regions", reserved_regions
);
2783 g_free(resv_prop_str
);
2787 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2788 DeviceState
*dev
, Error
**errp
)
2790 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2792 if (vms
->platform_bus_dev
) {
2793 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2795 if (device_is_dynamic_sysbus(mc
, dev
)) {
2796 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2797 SYS_BUS_DEVICE(dev
));
2801 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2802 virt_memory_plug(hotplug_dev
, dev
, errp
);
2803 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2804 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2807 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2808 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2810 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2811 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2812 create_virtio_iommu_dt_bindings(vms
);
2816 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2817 DeviceState
*dev
, Error
**errp
)
2819 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2821 if (!vms
->acpi_dev
) {
2823 "memory hotplug is not enabled: missing acpi-ged device");
2827 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2828 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2832 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2836 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2837 DeviceState
*dev
, Error
**errp
)
2839 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2840 Error
*local_err
= NULL
;
2842 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2847 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2848 qdev_unrealize(dev
);
2851 error_propagate(errp
, local_err
);
2854 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2855 DeviceState
*dev
, Error
**errp
)
2857 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2858 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2859 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2860 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2863 error_setg(errp
, "device unplug request for unsupported device"
2864 " type: %s", object_get_typename(OBJECT(dev
)));
2868 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2869 DeviceState
*dev
, Error
**errp
)
2871 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2872 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2873 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2874 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2876 error_setg(errp
, "virt: device unplug for unsupported device"
2877 " type: %s", object_get_typename(OBJECT(dev
)));
2881 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2884 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2886 if (device_is_dynamic_sysbus(mc
, dev
) ||
2887 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2888 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2889 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2890 return HOTPLUG_HANDLER(machine
);
2896 * for arm64 kvm_type [7-0] encodes the requested number of bits
2897 * in the IPA address space
2899 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2901 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2902 int max_vm_pa_size
, requested_pa_size
;
2905 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2907 /* we freeze the memory map to compute the highest gpa */
2908 virt_set_memmap(vms
, max_vm_pa_size
);
2910 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2913 * KVM requires the IPA size to be at least 32 bits.
2915 if (requested_pa_size
< 32) {
2916 requested_pa_size
= 32;
2919 if (requested_pa_size
> max_vm_pa_size
) {
2920 error_report("-m and ,maxmem option values "
2921 "require an IPA range (%d bits) larger than "
2922 "the one supported by the host (%d bits)",
2923 requested_pa_size
, max_vm_pa_size
);
2927 * We return the requested PA log size, unless KVM only supports
2928 * the implicit legacy 40b IPA setting, in which case the kvm_type
2931 return fixed_ipa
? 0 : requested_pa_size
;
2934 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2936 MachineClass
*mc
= MACHINE_CLASS(oc
);
2937 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2939 mc
->init
= machvirt_init
;
2940 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2941 * The value may be reduced later when we have more information about the
2942 * configuration of the particular instance.
2945 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2946 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2947 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2948 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2950 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2952 mc
->block_default_type
= IF_VIRTIO
;
2954 mc
->pci_allow_0_address
= true;
2955 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2956 mc
->minimum_page_bits
= 12;
2957 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2958 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2960 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2962 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
2964 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2965 mc
->kvm_type
= virt_kvm_type
;
2966 assert(!mc
->get_hotplug_handler
);
2967 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2968 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2969 hc
->plug
= virt_machine_device_plug_cb
;
2970 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2971 hc
->unplug
= virt_machine_device_unplug_cb
;
2972 mc
->nvdimm_supported
= true;
2973 mc
->smp_props
.clusters_supported
= true;
2974 mc
->auto_enable_numa_with_memhp
= true;
2975 mc
->auto_enable_numa_with_memdev
= true;
2976 /* platform instead of architectural choice */
2977 mc
->cpu_cluster_has_numa_boundary
= true;
2978 mc
->default_ram_id
= "mach-virt.ram";
2979 mc
->default_nic
= "virtio-net-pci";
2981 object_class_property_add(oc
, "acpi", "OnOffAuto",
2982 virt_get_acpi
, virt_set_acpi
,
2984 object_class_property_set_description(oc
, "acpi",
2986 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2988 object_class_property_set_description(oc
, "secure",
2989 "Set on/off to enable/disable the ARM "
2990 "Security Extensions (TrustZone)");
2992 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2994 object_class_property_set_description(oc
, "virtualization",
2995 "Set on/off to enable/disable emulating a "
2996 "guest CPU which implements the ARM "
2997 "Virtualization Extensions");
2999 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
3001 object_class_property_set_description(oc
, "highmem",
3002 "Set on/off to enable/disable using "
3003 "physical address space above 32 bits");
3005 object_class_property_add_bool(oc
, "compact-highmem",
3006 virt_get_compact_highmem
,
3007 virt_set_compact_highmem
);
3008 object_class_property_set_description(oc
, "compact-highmem",
3009 "Set on/off to enable/disable compact "
3010 "layout for high memory regions");
3012 object_class_property_add_bool(oc
, "highmem-redists",
3013 virt_get_highmem_redists
,
3014 virt_set_highmem_redists
);
3015 object_class_property_set_description(oc
, "highmem-redists",
3016 "Set on/off to enable/disable high "
3017 "memory region for GICv3 or GICv4 "
3020 object_class_property_add_bool(oc
, "highmem-ecam",
3021 virt_get_highmem_ecam
,
3022 virt_set_highmem_ecam
);
3023 object_class_property_set_description(oc
, "highmem-ecam",
3024 "Set on/off to enable/disable high "
3025 "memory region for PCI ECAM");
3027 object_class_property_add_bool(oc
, "highmem-mmio",
3028 virt_get_highmem_mmio
,
3029 virt_set_highmem_mmio
);
3030 object_class_property_set_description(oc
, "highmem-mmio",
3031 "Set on/off to enable/disable high "
3032 "memory region for PCI MMIO");
3034 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3035 virt_set_gic_version
);
3036 object_class_property_set_description(oc
, "gic-version",
3038 "Valid values are 2, 3, 4, host and max");
3040 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3041 object_class_property_set_description(oc
, "iommu",
3042 "Set the IOMMU type. "
3043 "Valid values are none and smmuv3");
3045 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3046 virt_get_default_bus_bypass_iommu
,
3047 virt_set_default_bus_bypass_iommu
);
3048 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3049 "Set on/off to enable/disable "
3050 "bypass_iommu for default root bus");
3052 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3054 object_class_property_set_description(oc
, "ras",
3055 "Set on/off to enable/disable reporting host memory errors "
3056 "to a KVM guest using ACPI and guest external abort exceptions");
3058 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3059 object_class_property_set_description(oc
, "mte",
3060 "Set on/off to enable/disable emulating a "
3061 "guest CPU which implements the ARM "
3062 "Memory Tagging Extension");
3064 object_class_property_add_bool(oc
, "its", virt_get_its
,
3066 object_class_property_set_description(oc
, "its",
3067 "Set on/off to enable/disable "
3068 "ITS instantiation");
3070 object_class_property_add_bool(oc
, "dtb-randomness",
3071 virt_get_dtb_randomness
,
3072 virt_set_dtb_randomness
);
3073 object_class_property_set_description(oc
, "dtb-randomness",
3074 "Set off to disable passing random or "
3075 "non-deterministic dtb nodes to guest");
3077 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3078 virt_get_dtb_randomness
,
3079 virt_set_dtb_randomness
);
3080 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3081 "Deprecated synonym of dtb-randomness");
3083 object_class_property_add_str(oc
, "x-oem-id",
3086 object_class_property_set_description(oc
, "x-oem-id",
3087 "Override the default value of field OEMID "
3088 "in ACPI table header."
3089 "The string may be up to 6 bytes in size");
3092 object_class_property_add_str(oc
, "x-oem-table-id",
3093 virt_get_oem_table_id
,
3094 virt_set_oem_table_id
);
3095 object_class_property_set_description(oc
, "x-oem-table-id",
3096 "Override the default value of field OEM Table ID "
3097 "in ACPI table header."
3098 "The string may be up to 8 bytes in size");
3102 static void virt_instance_init(Object
*obj
)
3104 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3105 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3107 /* EL3 is disabled by default on virt: this makes us consistent
3108 * between KVM and TCG for this board, and it also allows us to
3109 * boot UEFI blobs which assume no TrustZone support.
3111 vms
->secure
= false;
3113 /* EL2 is also disabled by default, for similar reasons */
3116 /* High memory is enabled by default */
3117 vms
->highmem
= true;
3118 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3119 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3121 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3122 vms
->highmem_mmio
= true;
3123 vms
->highmem_redists
= true;
3128 /* Default allows ITS instantiation */
3131 if (vmc
->no_tcg_its
) {
3132 vms
->tcg_its
= false;
3134 vms
->tcg_its
= true;
3138 /* Default disallows iommu instantiation */
3139 vms
->iommu
= VIRT_IOMMU_NONE
;
3141 /* The default root bus is attached to iommu by default */
3142 vms
->default_bus_bypass_iommu
= false;
3144 /* Default disallows RAS instantiation */
3147 /* MTE is disabled by default. */
3150 /* Supply kaslr-seed and rng-seed by default */
3151 vms
->dtb_randomness
= true;
3153 vms
->irqmap
= a15irqmap
;
3155 virt_flash_create(vms
);
3157 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3158 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3161 static const TypeInfo virt_machine_info
= {
3162 .name
= TYPE_VIRT_MACHINE
,
3163 .parent
= TYPE_MACHINE
,
3165 .instance_size
= sizeof(VirtMachineState
),
3166 .class_size
= sizeof(VirtMachineClass
),
3167 .class_init
= virt_machine_class_init
,
3168 .instance_init
= virt_instance_init
,
3169 .interfaces
= (InterfaceInfo
[]) {
3170 { TYPE_HOTPLUG_HANDLER
},
3175 static void machvirt_machine_init(void)
3177 type_register_static(&virt_machine_info
);
3179 type_init(machvirt_machine_init
);
3181 static void virt_machine_8_2_options(MachineClass
*mc
)
3184 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3186 static void virt_machine_8_1_options(MachineClass
*mc
)
3188 virt_machine_8_2_options(mc
);
3189 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3191 DEFINE_VIRT_MACHINE(8, 1)
3193 static void virt_machine_8_0_options(MachineClass
*mc
)
3195 virt_machine_8_1_options(mc
);
3196 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3198 DEFINE_VIRT_MACHINE(8, 0)
3200 static void virt_machine_7_2_options(MachineClass
*mc
)
3202 virt_machine_8_0_options(mc
);
3203 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3205 DEFINE_VIRT_MACHINE(7, 2)
3207 static void virt_machine_7_1_options(MachineClass
*mc
)
3209 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3211 virt_machine_7_2_options(mc
);
3212 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3213 /* Compact layout for high memory regions was introduced with 7.2 */
3214 vmc
->no_highmem_compact
= true;
3216 DEFINE_VIRT_MACHINE(7, 1)
3218 static void virt_machine_7_0_options(MachineClass
*mc
)
3220 virt_machine_7_1_options(mc
);
3221 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3223 DEFINE_VIRT_MACHINE(7, 0)
3225 static void virt_machine_6_2_options(MachineClass
*mc
)
3227 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3229 virt_machine_7_0_options(mc
);
3230 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3231 vmc
->no_tcg_lpa2
= true;
3233 DEFINE_VIRT_MACHINE(6, 2)
3235 static void virt_machine_6_1_options(MachineClass
*mc
)
3237 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3239 virt_machine_6_2_options(mc
);
3240 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3241 mc
->smp_props
.prefer_sockets
= true;
3242 vmc
->no_cpu_topology
= true;
3244 /* qemu ITS was introduced with 6.2 */
3245 vmc
->no_tcg_its
= true;
3247 DEFINE_VIRT_MACHINE(6, 1)
3249 static void virt_machine_6_0_options(MachineClass
*mc
)
3251 virt_machine_6_1_options(mc
);
3252 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3254 DEFINE_VIRT_MACHINE(6, 0)
3256 static void virt_machine_5_2_options(MachineClass
*mc
)
3258 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3260 virt_machine_6_0_options(mc
);
3261 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3262 vmc
->no_secure_gpio
= true;
3264 DEFINE_VIRT_MACHINE(5, 2)
3266 static void virt_machine_5_1_options(MachineClass
*mc
)
3268 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3270 virt_machine_5_2_options(mc
);
3271 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3272 vmc
->no_kvm_steal_time
= true;
3274 DEFINE_VIRT_MACHINE(5, 1)
3276 static void virt_machine_5_0_options(MachineClass
*mc
)
3278 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3280 virt_machine_5_1_options(mc
);
3281 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3282 mc
->numa_mem_supported
= true;
3283 vmc
->acpi_expose_flash
= true;
3284 mc
->auto_enable_numa_with_memdev
= false;
3286 DEFINE_VIRT_MACHINE(5, 0)
3288 static void virt_machine_4_2_options(MachineClass
*mc
)
3290 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3292 virt_machine_5_0_options(mc
);
3293 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3294 vmc
->kvm_no_adjvtime
= true;
3296 DEFINE_VIRT_MACHINE(4, 2)
3298 static void virt_machine_4_1_options(MachineClass
*mc
)
3300 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3302 virt_machine_4_2_options(mc
);
3303 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3305 mc
->auto_enable_numa_with_memhp
= false;
3307 DEFINE_VIRT_MACHINE(4, 1)
3309 static void virt_machine_4_0_options(MachineClass
*mc
)
3311 virt_machine_4_1_options(mc
);
3312 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3314 DEFINE_VIRT_MACHINE(4, 0)
3316 static void virt_machine_3_1_options(MachineClass
*mc
)
3318 virt_machine_4_0_options(mc
);
3319 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3321 DEFINE_VIRT_MACHINE(3, 1)
3323 static void virt_machine_3_0_options(MachineClass
*mc
)
3325 virt_machine_3_1_options(mc
);
3326 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3328 DEFINE_VIRT_MACHINE(3, 0)
3330 static void virt_machine_2_12_options(MachineClass
*mc
)
3332 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3334 virt_machine_3_0_options(mc
);
3335 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3336 vmc
->no_highmem_ecam
= true;
3339 DEFINE_VIRT_MACHINE(2, 12)
3341 static void virt_machine_2_11_options(MachineClass
*mc
)
3343 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3345 virt_machine_2_12_options(mc
);
3346 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3347 vmc
->smbios_old_sys_ver
= true;
3349 DEFINE_VIRT_MACHINE(2, 11)
3351 static void virt_machine_2_10_options(MachineClass
*mc
)
3353 virt_machine_2_11_options(mc
);
3354 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3355 /* before 2.11 we never faulted accesses to bad addresses */
3356 mc
->ignore_memory_transaction_failures
= true;
3358 DEFINE_VIRT_MACHINE(2, 10)
3360 static void virt_machine_2_9_options(MachineClass
*mc
)
3362 virt_machine_2_10_options(mc
);
3363 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3365 DEFINE_VIRT_MACHINE(2, 9)
3367 static void virt_machine_2_8_options(MachineClass
*mc
)
3369 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3371 virt_machine_2_9_options(mc
);
3372 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3373 /* For 2.8 and earlier we falsely claimed in the DT that
3374 * our timers were edge-triggered, not level-triggered.
3376 vmc
->claim_edge_triggered_timers
= true;
3378 DEFINE_VIRT_MACHINE(2, 8)
3380 static void virt_machine_2_7_options(MachineClass
*mc
)
3382 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3384 virt_machine_2_8_options(mc
);
3385 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3386 /* ITS was introduced with 2.8 */
3388 /* Stick with 1K pages for migration compatibility */
3389 mc
->minimum_page_bits
= 0;
3391 DEFINE_VIRT_MACHINE(2, 7)
3393 static void virt_machine_2_6_options(MachineClass
*mc
)
3395 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3397 virt_machine_2_7_options(mc
);
3398 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3399 vmc
->disallow_affinity_adjustment
= true;
3400 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3403 DEFINE_VIRT_MACHINE(2, 6)