s390x/pci: bypass vfio DMA counting when using cdev
[qemu/kevin.git] / hw / arm / sbsa-ref.c
blobf3c970469396b2fe2897c2ce537099c8c3bd9a1e
1 /*
2 * ARM SBSA Reference Platform emulation
4 * Copyright (c) 2018 Linaro Limited
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/datadir.h"
23 #include "qapi/error.h"
24 #include "qemu/error-report.h"
25 #include "qemu/units.h"
26 #include "sysemu/device_tree.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/sysemu.h"
31 #include "exec/hwaddr.h"
32 #include "kvm_arm.h"
33 #include "hw/arm/boot.h"
34 #include "hw/arm/bsa.h"
35 #include "hw/arm/fdt.h"
36 #include "hw/arm/smmuv3.h"
37 #include "hw/block/flash.h"
38 #include "hw/boards.h"
39 #include "hw/ide/internal.h"
40 #include "hw/ide/ahci_internal.h"
41 #include "hw/intc/arm_gicv3_common.h"
42 #include "hw/intc/arm_gicv3_its_common.h"
43 #include "hw/loader.h"
44 #include "hw/pci-host/gpex.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/usb.h"
47 #include "hw/usb/xhci.h"
48 #include "hw/char/pl011.h"
49 #include "hw/watchdog/sbsa_gwdt.h"
50 #include "net/net.h"
51 #include "qapi/qmp/qlist.h"
52 #include "qom/object.h"
54 #define RAMLIMIT_GB 8192
55 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
57 #define NUM_IRQS 256
58 #define NUM_SMMU_IRQS 4
59 #define NUM_SATA_PORTS 6
61 enum {
62 SBSA_FLASH,
63 SBSA_MEM,
64 SBSA_CPUPERIPHS,
65 SBSA_GIC_DIST,
66 SBSA_GIC_REDIST,
67 SBSA_GIC_ITS,
68 SBSA_SECURE_EC,
69 SBSA_GWDT_WS0,
70 SBSA_GWDT_REFRESH,
71 SBSA_GWDT_CONTROL,
72 SBSA_SMMU,
73 SBSA_UART,
74 SBSA_RTC,
75 SBSA_PCIE,
76 SBSA_PCIE_MMIO,
77 SBSA_PCIE_MMIO_HIGH,
78 SBSA_PCIE_PIO,
79 SBSA_PCIE_ECAM,
80 SBSA_GPIO,
81 SBSA_SECURE_UART,
82 SBSA_SECURE_UART_MM,
83 SBSA_SECURE_MEM,
84 SBSA_AHCI,
85 SBSA_XHCI,
88 struct SBSAMachineState {
89 MachineState parent;
90 struct arm_boot_info bootinfo;
91 int smp_cpus;
92 void *fdt;
93 int fdt_size;
94 int psci_conduit;
95 DeviceState *gic;
96 PFlashCFI01 *flash[2];
99 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
100 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE)
102 static const MemMapEntry sbsa_ref_memmap[] = {
103 /* 512M boot ROM */
104 [SBSA_FLASH] = { 0, 0x20000000 },
105 /* 512M secure memory */
106 [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
107 /* Space reserved for CPU peripheral devices */
108 [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
109 [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
110 [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
111 [SBSA_GIC_ITS] = { 0x44081000, 0x00020000 },
112 [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
113 [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
114 [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
115 [SBSA_UART] = { 0x60000000, 0x00001000 },
116 [SBSA_RTC] = { 0x60010000, 0x00001000 },
117 [SBSA_GPIO] = { 0x60020000, 0x00001000 },
118 [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
119 [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
120 [SBSA_SMMU] = { 0x60050000, 0x00020000 },
121 /* Space here reserved for more SMMUs */
122 [SBSA_AHCI] = { 0x60100000, 0x00010000 },
123 [SBSA_XHCI] = { 0x60110000, 0x00010000 },
124 /* Space here reserved for other devices */
125 [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
126 /* 32-bit address PCIE MMIO space */
127 [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
128 /* 256M PCIE ECAM space */
129 [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
130 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
131 [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
132 [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
135 static const int sbsa_ref_irqmap[] = {
136 [SBSA_UART] = 1,
137 [SBSA_RTC] = 2,
138 [SBSA_PCIE] = 3, /* ... to 6 */
139 [SBSA_GPIO] = 7,
140 [SBSA_SECURE_UART] = 8,
141 [SBSA_SECURE_UART_MM] = 9,
142 [SBSA_AHCI] = 10,
143 [SBSA_XHCI] = 11,
144 [SBSA_SMMU] = 12, /* ... to 15 */
145 [SBSA_GWDT_WS0] = 16,
148 static const char * const valid_cpus[] = {
149 ARM_CPU_TYPE_NAME("cortex-a57"),
150 ARM_CPU_TYPE_NAME("cortex-a72"),
151 ARM_CPU_TYPE_NAME("neoverse-n1"),
152 ARM_CPU_TYPE_NAME("neoverse-v1"),
153 ARM_CPU_TYPE_NAME("neoverse-n2"),
154 ARM_CPU_TYPE_NAME("max"),
157 static bool cpu_type_valid(const char *cpu)
159 int i;
161 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
162 if (strcmp(cpu, valid_cpus[i]) == 0) {
163 return true;
166 return false;
169 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
171 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
172 return arm_cpu_mp_affinity(idx, clustersz);
175 static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
177 char *nodename;
179 nodename = g_strdup_printf("/intc");
180 qemu_fdt_add_subnode(sms->fdt, nodename);
181 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
182 2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
183 2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
184 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
185 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
187 nodename = g_strdup_printf("/intc/its");
188 qemu_fdt_add_subnode(sms->fdt, nodename);
189 qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
190 2, sbsa_ref_memmap[SBSA_GIC_ITS].base,
191 2, sbsa_ref_memmap[SBSA_GIC_ITS].size);
193 g_free(nodename);
197 * Firmware on this machine only uses ACPI table to load OS, these limited
198 * device tree nodes are just to let firmware know the info which varies from
199 * command line parameters, so it is not necessary to be fully compatible
200 * with the kernel CPU and NUMA binding rules.
202 static void create_fdt(SBSAMachineState *sms)
204 void *fdt = create_device_tree(&sms->fdt_size);
205 const MachineState *ms = MACHINE(sms);
206 int nb_numa_nodes = ms->numa_state->num_nodes;
207 int cpu;
209 if (!fdt) {
210 error_report("create_device_tree() failed");
211 exit(1);
214 sms->fdt = fdt;
216 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref");
217 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
218 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
221 * This versioning scheme is for informing platform fw only. It is neither:
222 * - A QEMU versioned machine type; a given version of QEMU will emulate
223 * a given version of the platform.
224 * - A reflection of level of SBSA (now SystemReady SR) support provided.
226 * machine-version-major: updated when changes breaking fw compatibility
227 * are introduced.
228 * machine-version-minor: updated when features are added that don't break
229 * fw compatibility.
231 qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
232 qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3);
234 if (ms->numa_state->have_numa_distance) {
235 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
236 uint32_t *matrix = g_malloc0(size);
237 int idx, i, j;
239 for (i = 0; i < nb_numa_nodes; i++) {
240 for (j = 0; j < nb_numa_nodes; j++) {
241 idx = (i * nb_numa_nodes + j) * 3;
242 matrix[idx + 0] = cpu_to_be32(i);
243 matrix[idx + 1] = cpu_to_be32(j);
244 matrix[idx + 2] =
245 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
249 qemu_fdt_add_subnode(fdt, "/distance-map");
250 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
251 matrix, size);
252 g_free(matrix);
256 * From Documentation/devicetree/bindings/arm/cpus.yaml
257 * On ARM v8 64-bit systems this property is required
258 * and matches the MPIDR_EL1 register affinity bits.
260 * * If cpus node's #address-cells property is set to 2
262 * The first reg cell bits [7:0] must be set to
263 * bits [39:32] of MPIDR_EL1.
265 * The second reg cell bits [23:0] must be set to
266 * bits [23:0] of MPIDR_EL1.
268 qemu_fdt_add_subnode(sms->fdt, "/cpus");
269 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2);
270 qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0);
272 for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
273 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
274 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
275 CPUState *cs = CPU(armcpu);
276 uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
278 qemu_fdt_add_subnode(sms->fdt, nodename);
279 qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr);
281 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
282 qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id",
283 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
286 g_free(nodename);
289 sbsa_fdt_add_gic_node(sms);
292 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
294 static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms,
295 const char *name,
296 const char *alias_prop_name)
299 * Create a single flash device. We use the same parameters as
300 * the flash devices on the Versatile Express board.
302 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
304 qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE);
305 qdev_prop_set_uint8(dev, "width", 4);
306 qdev_prop_set_uint8(dev, "device-width", 2);
307 qdev_prop_set_bit(dev, "big-endian", false);
308 qdev_prop_set_uint16(dev, "id0", 0x89);
309 qdev_prop_set_uint16(dev, "id1", 0x18);
310 qdev_prop_set_uint16(dev, "id2", 0x00);
311 qdev_prop_set_uint16(dev, "id3", 0x00);
312 qdev_prop_set_string(dev, "name", name);
313 object_property_add_child(OBJECT(sms), name, OBJECT(dev));
314 object_property_add_alias(OBJECT(sms), alias_prop_name,
315 OBJECT(dev), "drive");
316 return PFLASH_CFI01(dev);
319 static void sbsa_flash_create(SBSAMachineState *sms)
321 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0");
322 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1");
325 static void sbsa_flash_map1(PFlashCFI01 *flash,
326 hwaddr base, hwaddr size,
327 MemoryRegion *sysmem)
329 DeviceState *dev = DEVICE(flash);
331 assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE));
332 assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX);
333 qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE);
334 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
336 memory_region_add_subregion(sysmem, base,
337 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
338 0));
341 static void sbsa_flash_map(SBSAMachineState *sms,
342 MemoryRegion *sysmem,
343 MemoryRegion *secure_sysmem)
346 * Map two flash devices to fill the SBSA_FLASH space in the memmap.
347 * sysmem is the system memory space. secure_sysmem is the secure view
348 * of the system, and the first flash device should be made visible only
349 * there. The second flash device is visible to both secure and nonsecure.
351 hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2;
352 hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base;
354 sbsa_flash_map1(sms->flash[0], flashbase, flashsize,
355 secure_sysmem);
356 sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize,
357 sysmem);
360 static bool sbsa_firmware_init(SBSAMachineState *sms,
361 MemoryRegion *sysmem,
362 MemoryRegion *secure_sysmem)
364 const char *bios_name;
365 int i;
366 BlockBackend *pflash_blk0;
368 /* Map legacy -drive if=pflash to machine properties */
369 for (i = 0; i < ARRAY_SIZE(sms->flash); i++) {
370 pflash_cfi01_legacy_drive(sms->flash[i],
371 drive_get(IF_PFLASH, 0, i));
374 sbsa_flash_map(sms, sysmem, secure_sysmem);
376 pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
378 bios_name = MACHINE(sms)->firmware;
379 if (bios_name) {
380 char *fname;
381 MemoryRegion *mr;
382 int image_size;
384 if (pflash_blk0) {
385 error_report("The contents of the first flash device may be "
386 "specified with -bios or with -drive if=pflash... "
387 "but you cannot use both options at once");
388 exit(1);
391 /* Fall back to -bios */
393 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
394 if (!fname) {
395 error_report("Could not find ROM image '%s'", bios_name);
396 exit(1);
398 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0);
399 image_size = load_image_mr(fname, mr);
400 g_free(fname);
401 if (image_size < 0) {
402 error_report("Could not load ROM image '%s'", bios_name);
403 exit(1);
407 return pflash_blk0 || bios_name;
410 static void create_secure_ram(SBSAMachineState *sms,
411 MemoryRegion *secure_sysmem)
413 MemoryRegion *secram = g_new(MemoryRegion, 1);
414 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base;
415 hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size;
417 memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size,
418 &error_fatal);
419 memory_region_add_subregion(secure_sysmem, base, secram);
422 static void create_its(SBSAMachineState *sms)
424 const char *itsclass = its_class_name();
425 DeviceState *dev;
427 dev = qdev_new(itsclass);
429 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
430 &error_abort);
431 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
432 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
435 static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
437 unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
438 SysBusDevice *gicbusdev;
439 const char *gictype;
440 uint32_t redist0_capacity, redist0_count;
441 QList *redist_region_count;
442 int i;
444 gictype = gicv3_class_name();
446 sms->gic = qdev_new(gictype);
447 qdev_prop_set_uint32(sms->gic, "revision", 3);
448 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
450 * Note that the num-irq property counts both internal and external
451 * interrupts; there are always 32 of the former (mandated by GIC spec).
453 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
454 qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
456 redist0_capacity =
457 sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
458 redist0_count = MIN(smp_cpus, redist0_capacity);
460 redist_region_count = qlist_new();
461 qlist_append_int(redist_region_count, redist0_count);
462 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count);
464 object_property_set_link(OBJECT(sms->gic), "sysmem",
465 OBJECT(mem), &error_fatal);
466 qdev_prop_set_bit(sms->gic, "has-lpi", true);
468 gicbusdev = SYS_BUS_DEVICE(sms->gic);
469 sysbus_realize_and_unref(gicbusdev, &error_fatal);
470 sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
471 sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
474 * Wire the outputs from each CPU's generic timer and the GICv3
475 * maintenance interrupt signal to the appropriate GIC PPI inputs,
476 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
478 for (i = 0; i < smp_cpus; i++) {
479 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
480 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
481 int irq;
483 * Mapping from the output timer irq lines from the CPU to the
484 * GIC PPI inputs used for this board.
486 const int timer_irq[] = {
487 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
488 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
489 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
490 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
491 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
494 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
495 qdev_connect_gpio_out(cpudev, irq,
496 qdev_get_gpio_in(sms->gic,
497 intidbase + timer_irq[irq]));
500 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
501 qdev_get_gpio_in(sms->gic,
502 intidbase
503 + ARCH_GIC_MAINT_IRQ));
505 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
506 qdev_get_gpio_in(sms->gic,
507 intidbase
508 + VIRTUAL_PMU_IRQ));
510 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
511 sysbus_connect_irq(gicbusdev, i + smp_cpus,
512 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
513 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
514 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
515 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
516 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
518 create_its(sms);
521 static void create_uart(const SBSAMachineState *sms, int uart,
522 MemoryRegion *mem, Chardev *chr)
524 hwaddr base = sbsa_ref_memmap[uart].base;
525 int irq = sbsa_ref_irqmap[uart];
526 DeviceState *dev = qdev_new(TYPE_PL011);
527 SysBusDevice *s = SYS_BUS_DEVICE(dev);
529 qdev_prop_set_chr(dev, "chardev", chr);
530 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
531 memory_region_add_subregion(mem, base,
532 sysbus_mmio_get_region(s, 0));
533 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
536 static void create_rtc(const SBSAMachineState *sms)
538 hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
539 int irq = sbsa_ref_irqmap[SBSA_RTC];
541 sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
544 static void create_wdt(const SBSAMachineState *sms)
546 hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base;
547 hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
548 DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
549 SysBusDevice *s = SYS_BUS_DEVICE(dev);
550 int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
552 sysbus_realize_and_unref(s, &error_fatal);
553 sysbus_mmio_map(s, 0, rbase);
554 sysbus_mmio_map(s, 1, cbase);
555 sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
558 static DeviceState *gpio_key_dev;
559 static void sbsa_ref_powerdown_req(Notifier *n, void *opaque)
561 /* use gpio Pin 3 for power button event */
562 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
565 static Notifier sbsa_ref_powerdown_notifier = {
566 .notify = sbsa_ref_powerdown_req
569 static void create_gpio(const SBSAMachineState *sms)
571 DeviceState *pl061_dev;
572 hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
573 int irq = sbsa_ref_irqmap[SBSA_GPIO];
575 pl061_dev = sysbus_create_simple("pl061", base,
576 qdev_get_gpio_in(sms->gic, irq));
578 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
579 qdev_get_gpio_in(pl061_dev, 3));
581 /* connect powerdown request */
582 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
585 static void create_ahci(const SBSAMachineState *sms)
587 hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
588 int irq = sbsa_ref_irqmap[SBSA_AHCI];
589 DeviceState *dev;
590 DriveInfo *hd[NUM_SATA_PORTS];
591 SysbusAHCIState *sysahci;
592 AHCIState *ahci;
593 int i;
595 dev = qdev_new("sysbus-ahci");
596 qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
597 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
598 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
599 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
601 sysahci = SYSBUS_AHCI(dev);
602 ahci = &sysahci->ahci;
603 ide_drive_get(hd, ARRAY_SIZE(hd));
604 for (i = 0; i < ahci->ports; i++) {
605 if (hd[i] == NULL) {
606 continue;
608 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
612 static void create_xhci(const SBSAMachineState *sms)
614 hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
615 int irq = sbsa_ref_irqmap[SBSA_XHCI];
616 DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
617 qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
619 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
620 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
621 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
624 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
626 hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
627 int irq = sbsa_ref_irqmap[SBSA_SMMU];
628 DeviceState *dev;
629 int i;
631 dev = qdev_new(TYPE_ARM_SMMUV3);
633 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
634 &error_abort);
635 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
636 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
637 for (i = 0; i < NUM_SMMU_IRQS; i++) {
638 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
639 qdev_get_gpio_in(sms->gic, irq + i));
643 static void create_pcie(SBSAMachineState *sms)
645 hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
646 hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
647 hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
648 hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
649 hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
650 hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
651 hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
652 int irq = sbsa_ref_irqmap[SBSA_PCIE];
653 MachineClass *mc = MACHINE_GET_CLASS(sms);
654 MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
655 MemoryRegion *ecam_alias, *ecam_reg;
656 DeviceState *dev;
657 PCIHostState *pci;
658 int i;
660 dev = qdev_new(TYPE_GPEX_HOST);
661 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
663 /* Map ECAM space */
664 ecam_alias = g_new0(MemoryRegion, 1);
665 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
666 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
667 ecam_reg, 0, size_ecam);
668 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
670 /* Map the MMIO space */
671 mmio_alias = g_new0(MemoryRegion, 1);
672 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
673 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
674 mmio_reg, base_mmio, size_mmio);
675 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
677 /* Map the MMIO_HIGH space */
678 mmio_alias_high = g_new0(MemoryRegion, 1);
679 memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
680 mmio_reg, base_mmio_high, size_mmio_high);
681 memory_region_add_subregion(get_system_memory(), base_mmio_high,
682 mmio_alias_high);
684 /* Map IO port space */
685 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
687 for (i = 0; i < GPEX_NUM_IRQS; i++) {
688 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
689 qdev_get_gpio_in(sms->gic, irq + i));
690 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
693 pci = PCI_HOST_BRIDGE(dev);
694 if (pci->bus) {
695 for (i = 0; i < nb_nics; i++) {
696 pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL);
700 pci_create_simple(pci->bus, -1, "bochs-display");
702 create_smmu(sms, pci->bus);
705 static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
707 const SBSAMachineState *board = container_of(binfo, SBSAMachineState,
708 bootinfo);
710 *fdt_size = board->fdt_size;
711 return board->fdt;
714 static void create_secure_ec(MemoryRegion *mem)
716 hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base;
717 DeviceState *dev = qdev_new("sbsa-ec");
718 SysBusDevice *s = SYS_BUS_DEVICE(dev);
720 memory_region_add_subregion(mem, base,
721 sysbus_mmio_get_region(s, 0));
724 static void sbsa_ref_init(MachineState *machine)
726 unsigned int smp_cpus = machine->smp.cpus;
727 unsigned int max_cpus = machine->smp.max_cpus;
728 SBSAMachineState *sms = SBSA_MACHINE(machine);
729 MachineClass *mc = MACHINE_GET_CLASS(machine);
730 MemoryRegion *sysmem = get_system_memory();
731 MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1);
732 bool firmware_loaded;
733 const CPUArchIdList *possible_cpus;
734 int n, sbsa_max_cpus;
736 if (!cpu_type_valid(machine->cpu_type)) {
737 error_report("sbsa-ref: CPU type %s not supported", machine->cpu_type);
738 exit(1);
741 if (kvm_enabled()) {
742 error_report("sbsa-ref: KVM is not supported for this machine");
743 exit(1);
747 * The Secure view of the world is the same as the NonSecure,
748 * but with a few extra devices. Create it as a container region
749 * containing the system memory at low priority; any secure-only
750 * devices go in at higher priority and take precedence.
752 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
753 UINT64_MAX);
754 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
756 firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem);
759 * This machine has EL3 enabled, external firmware should supply PSCI
760 * implementation, so the QEMU's internal PSCI is disabled.
762 sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
764 sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
766 if (max_cpus > sbsa_max_cpus) {
767 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
768 "supported by machine 'sbsa-ref' (%d)",
769 max_cpus, sbsa_max_cpus);
770 exit(1);
773 sms->smp_cpus = smp_cpus;
775 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) {
776 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB);
777 exit(1);
780 possible_cpus = mc->possible_cpu_arch_ids(machine);
781 for (n = 0; n < possible_cpus->len; n++) {
782 Object *cpuobj;
783 CPUState *cs;
785 if (n >= smp_cpus) {
786 break;
789 cpuobj = object_new(possible_cpus->cpus[n].type);
790 object_property_set_int(cpuobj, "mp-affinity",
791 possible_cpus->cpus[n].arch_id, NULL);
793 cs = CPU(cpuobj);
794 cs->cpu_index = n;
796 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
797 &error_fatal);
799 if (object_property_find(cpuobj, "reset-cbar")) {
800 object_property_set_int(cpuobj, "reset-cbar",
801 sbsa_ref_memmap[SBSA_CPUPERIPHS].base,
802 &error_abort);
805 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
806 &error_abort);
808 object_property_set_link(cpuobj, "secure-memory",
809 OBJECT(secure_sysmem), &error_abort);
811 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
812 object_unref(cpuobj);
815 memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base,
816 machine->ram);
818 create_fdt(sms);
820 create_secure_ram(sms, secure_sysmem);
822 create_gic(sms, sysmem);
824 create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
825 create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
826 /* Second secure UART for RAS and MM from EL0 */
827 create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
829 create_rtc(sms);
831 create_wdt(sms);
833 create_gpio(sms);
835 create_ahci(sms);
837 create_xhci(sms);
839 create_pcie(sms);
841 create_secure_ec(secure_sysmem);
843 sms->bootinfo.ram_size = machine->ram_size;
844 sms->bootinfo.board_id = -1;
845 sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
846 sms->bootinfo.get_dtb = sbsa_ref_dtb;
847 sms->bootinfo.firmware_loaded = firmware_loaded;
848 arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
851 static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
853 unsigned int max_cpus = ms->smp.max_cpus;
854 SBSAMachineState *sms = SBSA_MACHINE(ms);
855 int n;
857 if (ms->possible_cpus) {
858 assert(ms->possible_cpus->len == max_cpus);
859 return ms->possible_cpus;
862 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
863 sizeof(CPUArchId) * max_cpus);
864 ms->possible_cpus->len = max_cpus;
865 for (n = 0; n < ms->possible_cpus->len; n++) {
866 ms->possible_cpus->cpus[n].type = ms->cpu_type;
867 ms->possible_cpus->cpus[n].arch_id =
868 sbsa_ref_cpu_mp_affinity(sms, n);
869 ms->possible_cpus->cpus[n].props.has_thread_id = true;
870 ms->possible_cpus->cpus[n].props.thread_id = n;
872 return ms->possible_cpus;
875 static CpuInstanceProperties
876 sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
878 MachineClass *mc = MACHINE_GET_CLASS(ms);
879 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
881 assert(cpu_index < possible_cpus->len);
882 return possible_cpus->cpus[cpu_index].props;
885 static int64_t
886 sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx)
888 return idx % ms->numa_state->num_nodes;
891 static void sbsa_ref_instance_init(Object *obj)
893 SBSAMachineState *sms = SBSA_MACHINE(obj);
895 sbsa_flash_create(sms);
898 static void sbsa_ref_class_init(ObjectClass *oc, void *data)
900 MachineClass *mc = MACHINE_CLASS(oc);
902 mc->init = sbsa_ref_init;
903 mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine";
904 mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n1");
905 mc->max_cpus = 512;
906 mc->pci_allow_0_address = true;
907 mc->minimum_page_bits = 12;
908 mc->block_default_type = IF_IDE;
909 mc->no_cdrom = 1;
910 mc->default_nic = "e1000e";
911 mc->default_ram_size = 1 * GiB;
912 mc->default_ram_id = "sbsa-ref.ram";
913 mc->default_cpus = 4;
914 mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids;
915 mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props;
916 mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id;
917 /* platform instead of architectural choice */
918 mc->cpu_cluster_has_numa_boundary = true;
921 static const TypeInfo sbsa_ref_info = {
922 .name = TYPE_SBSA_MACHINE,
923 .parent = TYPE_MACHINE,
924 .instance_init = sbsa_ref_instance_init,
925 .class_init = sbsa_ref_class_init,
926 .instance_size = sizeof(SBSAMachineState),
929 static void sbsa_ref_machine_init(void)
931 type_register_static(&sbsa_ref_info);
934 type_init(sbsa_ref_machine_init);