2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/reset.h"
18 #include "migration/vmstate.h"
19 #include "monitor/monitor.h"
20 #include "hw/ppc/fdt.h"
21 #include "hw/ppc/spapr.h"
22 #include "hw/ppc/spapr_cpu_core.h"
23 #include "hw/ppc/spapr_xive.h"
24 #include "hw/ppc/xive.h"
25 #include "hw/ppc/xive_regs.h"
26 #include "hw/qdev-properties.h"
29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
30 * use for the ESB pages and the TIMA pages
32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
36 * The allocation of VP blocks is a complex operation in OPAL and the
37 * VP identifiers have a relation with the number of HW chips, the
38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
39 * controller model does not have the same constraints and can use a
40 * simple mapping scheme of the CPU vcpu_id
42 * These identifiers are never returned to the OS.
45 #define SPAPR_XIVE_NVT_BASE 0x400
48 * sPAPR NVT and END indexing helpers
50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
52 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
55 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
56 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
61 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
65 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
69 static int spapr_xive_target_to_nvt(uint32_t target
,
70 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
72 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
78 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
86 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
87 uint32_t *out_server
, uint8_t *out_prio
)
90 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
93 *out_server
= end_idx
>> 3;
97 *out_prio
= end_idx
& 0x7;
102 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
108 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
112 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
116 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
117 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
119 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
125 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
130 * On sPAPR machines, use a simplified output for the XIVE END
131 * structure dumping only the information related to the OS EQ.
133 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
136 uint64_t qaddr_base
= xive_end_qaddr(end
);
137 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
138 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
139 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
140 uint32_t qentries
= 1 << (qsize
+ 10);
141 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
142 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
144 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
145 spapr_xive_nvt_to_target(0, nvt
),
146 priority
, qindex
, qentries
, qaddr_base
, qgen
);
148 xive_end_queue_pic_print_info(end
, 6, mon
);
151 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
153 XiveSource
*xsrc
= &xive
->source
;
156 if (kvm_irqchip_in_kernel()) {
157 Error
*local_err
= NULL
;
159 kvmppc_xive_synchronize_state(xive
, &local_err
);
161 error_report_err(local_err
);
166 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
168 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
169 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
170 XiveEAS
*eas
= &xive
->eat
[i
];
172 if (!xive_eas_is_valid(eas
)) {
176 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
177 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
178 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
179 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
180 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
181 xive_eas_is_masked(eas
) ? "M" : " ",
182 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
184 if (!xive_eas_is_masked(eas
)) {
185 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
188 assert(end_idx
< xive
->nr_ends
);
189 end
= &xive
->endt
[end_idx
];
191 if (xive_end_is_valid(end
)) {
192 spapr_xive_end_pic_print_info(xive
, end
, mon
);
195 monitor_printf(mon
, "\n");
199 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
201 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
202 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
204 /* Disable the END ESBs until a guest OS makes use of them */
205 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
208 static void spapr_xive_end_reset(XiveEND
*end
)
210 memset(end
, 0, sizeof(*end
));
212 /* switch off the escalation and notification ESBs */
213 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
216 static void spapr_xive_reset(void *dev
)
218 SpaprXive
*xive
= SPAPR_XIVE(dev
);
222 * The XiveSource has its own reset handler, which mask off all
226 /* Mask all valid EASs in the IRQ number space. */
227 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
228 XiveEAS
*eas
= &xive
->eat
[i
];
229 if (xive_eas_is_valid(eas
)) {
230 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
237 for (i
= 0; i
< xive
->nr_ends
; i
++) {
238 spapr_xive_end_reset(&xive
->endt
[i
]);
242 static void spapr_xive_instance_init(Object
*obj
)
244 SpaprXive
*xive
= SPAPR_XIVE(obj
);
246 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
247 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
249 object_initialize_child(obj
, "end_source", &xive
->end_source
,
250 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
253 /* Not connected to the KVM XIVE device */
257 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
259 SpaprXive
*xive
= SPAPR_XIVE(dev
);
260 XiveSource
*xsrc
= &xive
->source
;
261 XiveENDSource
*end_xsrc
= &xive
->end_source
;
262 Error
*local_err
= NULL
;
264 if (!xive
->nr_irqs
) {
265 error_setg(errp
, "Number of interrupt needs to be greater 0");
269 if (!xive
->nr_ends
) {
270 error_setg(errp
, "Number of interrupt needs to be greater 0");
275 * Initialize the internal sources, for IPIs and virtual devices.
277 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
279 object_property_set_link(OBJECT(xsrc
), OBJECT(xive
), "xive",
281 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
283 error_propagate(errp
, local_err
);
286 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
289 * Initialize the END ESB source
291 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
293 object_property_set_link(OBJECT(end_xsrc
), OBJECT(xive
), "xive",
295 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
297 error_propagate(errp
, local_err
);
300 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
302 /* Set the mapping address of the END ESB pages after the source ESBs */
303 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
306 * Allocate the routing tables
308 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
309 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
311 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
312 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
314 qemu_register_reset(spapr_xive_reset
, dev
);
316 /* TIMA initialization */
317 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
318 "xive.tima", 4ull << TM_SHIFT
);
319 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
322 * Map all regions. These will be enabled or disabled at reset and
323 * can also be overridden by KVM memory regions if active
325 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
326 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
327 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
330 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
331 uint32_t eas_idx
, XiveEAS
*eas
)
333 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
335 if (eas_idx
>= xive
->nr_irqs
) {
339 *eas
= xive
->eat
[eas_idx
];
343 static int spapr_xive_get_end(XiveRouter
*xrtr
,
344 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
346 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
348 if (end_idx
>= xive
->nr_ends
) {
352 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
356 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
357 uint32_t end_idx
, XiveEND
*end
,
360 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
362 if (end_idx
>= xive
->nr_ends
) {
366 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
370 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
371 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
373 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
374 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
377 /* TODO: should we assert() if we can find a NVT ? */
382 * sPAPR does not maintain a NVT table. Return that the NVT is
383 * valid if we have found a matching CPU
385 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
389 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
390 uint32_t nvt_idx
, XiveNVT
*nvt
,
394 * We don't need to write back to the NVTs because the sPAPR
395 * machine should never hit a non-scheduled NVT. It should never
398 g_assert_not_reached();
401 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
403 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
405 return spapr_cpu_state(cpu
)->tctx
;
408 static const VMStateDescription vmstate_spapr_xive_end
= {
409 .name
= TYPE_SPAPR_XIVE
"/end",
411 .minimum_version_id
= 1,
412 .fields
= (VMStateField
[]) {
413 VMSTATE_UINT32(w0
, XiveEND
),
414 VMSTATE_UINT32(w1
, XiveEND
),
415 VMSTATE_UINT32(w2
, XiveEND
),
416 VMSTATE_UINT32(w3
, XiveEND
),
417 VMSTATE_UINT32(w4
, XiveEND
),
418 VMSTATE_UINT32(w5
, XiveEND
),
419 VMSTATE_UINT32(w6
, XiveEND
),
420 VMSTATE_UINT32(w7
, XiveEND
),
421 VMSTATE_END_OF_LIST()
425 static const VMStateDescription vmstate_spapr_xive_eas
= {
426 .name
= TYPE_SPAPR_XIVE
"/eas",
428 .minimum_version_id
= 1,
429 .fields
= (VMStateField
[]) {
430 VMSTATE_UINT64(w
, XiveEAS
),
431 VMSTATE_END_OF_LIST()
435 static int vmstate_spapr_xive_pre_save(void *opaque
)
437 if (kvm_irqchip_in_kernel()) {
438 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
445 * Called by the sPAPR IRQ backend 'post_load' method at the machine
448 static int spapr_xive_post_load(SpaprInterruptController
*intc
, int version_id
)
450 if (kvm_irqchip_in_kernel()) {
451 return kvmppc_xive_post_load(SPAPR_XIVE(intc
), version_id
);
457 static const VMStateDescription vmstate_spapr_xive
= {
458 .name
= TYPE_SPAPR_XIVE
,
460 .minimum_version_id
= 1,
461 .pre_save
= vmstate_spapr_xive_pre_save
,
462 .post_load
= NULL
, /* handled at the machine level */
463 .fields
= (VMStateField
[]) {
464 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
465 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
466 vmstate_spapr_xive_eas
, XiveEAS
),
467 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
468 vmstate_spapr_xive_end
, XiveEND
),
469 VMSTATE_END_OF_LIST()
473 static int spapr_xive_claim_irq(SpaprInterruptController
*intc
, int lisn
,
474 bool lsi
, Error
**errp
)
476 SpaprXive
*xive
= SPAPR_XIVE(intc
);
477 XiveSource
*xsrc
= &xive
->source
;
479 assert(lisn
< xive
->nr_irqs
);
481 if (xive_eas_is_valid(&xive
->eat
[lisn
])) {
482 error_setg(errp
, "IRQ %d is not free", lisn
);
487 * Set default values when allocating an IRQ number
489 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
491 xive_source_irq_set_lsi(xsrc
, lisn
);
494 if (kvm_irqchip_in_kernel()) {
495 return kvmppc_xive_source_reset_one(xsrc
, lisn
, errp
);
501 static void spapr_xive_free_irq(SpaprInterruptController
*intc
, int lisn
)
503 SpaprXive
*xive
= SPAPR_XIVE(intc
);
504 assert(lisn
< xive
->nr_irqs
);
506 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
509 static Property spapr_xive_properties
[] = {
510 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
511 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
512 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
513 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
514 DEFINE_PROP_END_OF_LIST(),
517 static int spapr_xive_cpu_intc_create(SpaprInterruptController
*intc
,
518 PowerPCCPU
*cpu
, Error
**errp
)
520 SpaprXive
*xive
= SPAPR_XIVE(intc
);
522 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
524 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(xive
), errp
);
529 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
533 static void xive_tctx_set_os_cam(XiveTCTX
*tctx
, uint32_t os_cam
)
535 uint32_t qw1w2
= cpu_to_be32(TM_QW1W2_VO
| os_cam
);
536 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
539 static void spapr_xive_cpu_intc_reset(SpaprInterruptController
*intc
,
542 XiveTCTX
*tctx
= spapr_cpu_state(cpu
)->tctx
;
546 xive_tctx_reset(tctx
);
549 * When a Virtual Processor is scheduled to run on a HW thread,
550 * the hypervisor pushes its identifier in the OS CAM line.
551 * Emulate the same behavior under QEMU.
553 spapr_xive_cpu_to_nvt(cpu
, &nvt_blk
, &nvt_idx
);
555 xive_tctx_set_os_cam(tctx
, xive_nvt_cam_line(nvt_blk
, nvt_idx
));
558 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController
*intc
,
561 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
563 xive_tctx_destroy(spapr_cpu
->tctx
);
564 spapr_cpu
->tctx
= NULL
;
567 static void spapr_xive_set_irq(SpaprInterruptController
*intc
, int irq
, int val
)
569 SpaprXive
*xive
= SPAPR_XIVE(intc
);
571 if (kvm_irqchip_in_kernel()) {
572 kvmppc_xive_source_set_irq(&xive
->source
, irq
, val
);
574 xive_source_set_irq(&xive
->source
, irq
, val
);
578 static void spapr_xive_print_info(SpaprInterruptController
*intc
, Monitor
*mon
)
580 SpaprXive
*xive
= SPAPR_XIVE(intc
);
584 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
586 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
589 spapr_xive_pic_print_info(xive
, mon
);
592 static void spapr_xive_dt(SpaprInterruptController
*intc
, uint32_t nr_servers
,
593 void *fdt
, uint32_t phandle
)
595 SpaprXive
*xive
= SPAPR_XIVE(intc
);
597 uint64_t timas
[2 * 2];
598 /* Interrupt number ranges for the IPIs */
599 uint32_t lisn_ranges
[] = {
601 cpu_to_be32(nr_servers
),
604 * EQ size - the sizes of pages supported by the system 4K, 64K,
605 * 2M, 16M. We only advertise 64K for the moment.
607 uint32_t eq_sizes
[] = {
608 cpu_to_be32(16), /* 64K */
611 * The following array is in sync with the reserved priorities
612 * defined by the 'spapr_xive_priority_is_reserved' routine.
614 uint32_t plat_res_int_priorities
[] = {
615 cpu_to_be32(7), /* start */
616 cpu_to_be32(0xf8), /* count */
619 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
620 timas
[0] = cpu_to_be64(xive
->tm_base
+
621 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
622 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
623 timas
[2] = cpu_to_be64(xive
->tm_base
+
624 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
625 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
627 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
629 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
630 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
632 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
633 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
635 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
636 sizeof(lisn_ranges
)));
638 /* For Linux to link the LSIs to the interrupt controller. */
639 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
640 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
643 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
644 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
647 * The "ibm,plat-res-int-priorities" property defines the priority
648 * ranges reserved by the hypervisor
650 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
651 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));
654 static int spapr_xive_activate(SpaprInterruptController
*intc
, Error
**errp
)
656 SpaprXive
*xive
= SPAPR_XIVE(intc
);
659 int rc
= spapr_irq_init_kvm(kvmppc_xive_connect
, intc
, errp
);
665 /* Activate the XIVE MMIOs */
666 spapr_xive_mmio_set_enabled(xive
, true);
671 static void spapr_xive_deactivate(SpaprInterruptController
*intc
)
673 SpaprXive
*xive
= SPAPR_XIVE(intc
);
675 spapr_xive_mmio_set_enabled(xive
, false);
677 if (kvm_irqchip_in_kernel()) {
678 kvmppc_xive_disconnect(intc
);
682 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
684 DeviceClass
*dc
= DEVICE_CLASS(klass
);
685 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
686 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_CLASS(klass
);
688 dc
->desc
= "sPAPR XIVE Interrupt Controller";
689 dc
->props
= spapr_xive_properties
;
690 dc
->realize
= spapr_xive_realize
;
691 dc
->vmsd
= &vmstate_spapr_xive
;
693 xrc
->get_eas
= spapr_xive_get_eas
;
694 xrc
->get_end
= spapr_xive_get_end
;
695 xrc
->write_end
= spapr_xive_write_end
;
696 xrc
->get_nvt
= spapr_xive_get_nvt
;
697 xrc
->write_nvt
= spapr_xive_write_nvt
;
698 xrc
->get_tctx
= spapr_xive_get_tctx
;
700 sicc
->activate
= spapr_xive_activate
;
701 sicc
->deactivate
= spapr_xive_deactivate
;
702 sicc
->cpu_intc_create
= spapr_xive_cpu_intc_create
;
703 sicc
->cpu_intc_reset
= spapr_xive_cpu_intc_reset
;
704 sicc
->cpu_intc_destroy
= spapr_xive_cpu_intc_destroy
;
705 sicc
->claim_irq
= spapr_xive_claim_irq
;
706 sicc
->free_irq
= spapr_xive_free_irq
;
707 sicc
->set_irq
= spapr_xive_set_irq
;
708 sicc
->print_info
= spapr_xive_print_info
;
709 sicc
->dt
= spapr_xive_dt
;
710 sicc
->post_load
= spapr_xive_post_load
;
713 static const TypeInfo spapr_xive_info
= {
714 .name
= TYPE_SPAPR_XIVE
,
715 .parent
= TYPE_XIVE_ROUTER
,
716 .instance_init
= spapr_xive_instance_init
,
717 .instance_size
= sizeof(SpaprXive
),
718 .class_init
= spapr_xive_class_init
,
719 .interfaces
= (InterfaceInfo
[]) {
725 static void spapr_xive_register_types(void)
727 type_register_static(&spapr_xive_info
);
730 type_init(spapr_xive_register_types
)
735 * The terminology used by the XIVE hcalls is the following :
738 * EQ Event Queue assigned by OS to receive event data
739 * ESB page for source interrupt management
740 * LISN Logical Interrupt Source Number identifying a source in the
742 * EISN Effective Interrupt Source Number used by guest OS to
743 * identify source in the guest
745 * The EAS, END, NVT structures are not exposed.
749 * Linux hosts under OPAL reserve priority 7 for their own escalation
750 * interrupts (DD2.X POWER9). So we only allow the guest to use
753 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
758 case 7: /* OPAL escalation queue */
765 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
766 * real address of the MMIO page through which the Event State Buffer
767 * entry associated with the value of the "lisn" parameter is managed.
773 * - R5: "lisn" is per "interrupts", "interrupt-map", or
774 * "ibm,xive-lisn-ranges" properties, or as returned by the
775 * ibm,query-interrupt-source-number RTAS call, or as returned
776 * by the H_ALLOCATE_VAS_WINDOW hcall
780 * Bits 0-59: Reserved
781 * Bit 60: H_INT_ESB must be used for Event State Buffer
783 * Bit 61: 1 == LSI 0 == MSI
784 * Bit 62: the full function page supports trigger
785 * Bit 63: Store EOI Supported
786 * - R5: Logical Real address of full function Event State Buffer
787 * management page, -1 if H_INT_ESB hcall flag is set to 1.
788 * - R6: Logical Real Address of trigger only Event State Buffer
789 * management page or -1.
790 * - R7: Power of 2 page size for the ESB management pages returned in
794 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
795 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
796 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
798 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
800 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
801 SpaprMachineState
*spapr
,
805 SpaprXive
*xive
= spapr
->xive
;
806 XiveSource
*xsrc
= &xive
->source
;
807 target_ulong flags
= args
[0];
808 target_ulong lisn
= args
[1];
810 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
818 if (lisn
>= xive
->nr_irqs
) {
819 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
824 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
825 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
831 * All sources are emulated under the main XIVE object and share
832 * the same characteristics.
835 if (!xive_source_esb_has_2page(xsrc
)) {
836 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
838 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
839 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
843 * Force the use of the H_INT_ESB hcall in case of an LSI
844 * interrupt. This is necessary under KVM to re-trigger the
845 * interrupt if the level is still asserted
847 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
848 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
851 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
852 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
857 if (xive_source_esb_has_2page(xsrc
) &&
858 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
859 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
864 if (xive_source_esb_has_2page(xsrc
)) {
865 args
[3] = xsrc
->esb_shift
- 1;
867 args
[3] = xsrc
->esb_shift
;
874 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
875 * Interrupt Source to a target. The Logical Interrupt Source is
876 * designated with the "lisn" parameter and the target is designated
877 * with the "target" and "priority" parameters. Upon return from the
878 * hcall(), no additional interrupts will be directed to the old EQ.
883 * Bits 0-61: Reserved
884 * Bit 62: set the "eisn" in the EAS
885 * Bit 63: masks the interrupt source in the hardware interrupt
886 * control structure. An interrupt masked by this mechanism will
887 * be dropped, but it's source state bits will still be
888 * set. There is no race-free way of unmasking and restoring the
889 * source. Thus this should only be used in interrupts that are
890 * also masked at the source, and only in cases where the
891 * interrupt is not meant to be used for a large amount of time
892 * because no valid target exists for it for example
893 * - R5: "lisn" is per "interrupts", "interrupt-map", or
894 * "ibm,xive-lisn-ranges" properties, or as returned by the
895 * ibm,query-interrupt-source-number RTAS call, or as returned by
896 * the H_ALLOCATE_VAS_WINDOW hcall
897 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
898 * "ibm,ppc-interrupt-gserver#s"
899 * - R7: "priority" is a valid priority not in
900 * "ibm,plat-res-int-priorities"
901 * - R8: "eisn" is the guest EISN associated with the "lisn"
907 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
908 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
910 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
911 SpaprMachineState
*spapr
,
915 SpaprXive
*xive
= spapr
->xive
;
916 XiveEAS eas
, new_eas
;
917 target_ulong flags
= args
[0];
918 target_ulong lisn
= args
[1];
919 target_ulong target
= args
[2];
920 target_ulong priority
= args
[3];
921 target_ulong eisn
= args
[4];
925 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
929 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
933 if (lisn
>= xive
->nr_irqs
) {
934 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
939 eas
= xive
->eat
[lisn
];
940 if (!xive_eas_is_valid(&eas
)) {
941 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
946 /* priority 0xff is used to reset the EAS */
947 if (priority
== 0xff) {
948 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
952 if (flags
& SPAPR_XIVE_SRC_MASK
) {
953 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
955 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
958 if (spapr_xive_priority_is_reserved(priority
)) {
959 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
960 " is reserved\n", priority
);
965 * Validate that "target" is part of the list of threads allocated
966 * to the partition. For that, find the END corresponding to the
969 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
973 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
974 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
976 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
977 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
980 if (kvm_irqchip_in_kernel()) {
981 Error
*local_err
= NULL
;
983 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
985 error_report_err(local_err
);
991 xive
->eat
[lisn
] = new_eas
;
996 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
997 * target/priority pair is assigned to the specified Logical Interrupt
1003 * Bits 0-63 Reserved
1004 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1005 * "ibm,xive-lisn-ranges" properties, or as returned by the
1006 * ibm,query-interrupt-source-number RTAS call, or as
1007 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1010 * - R4: Target to which the specified Logical Interrupt Source is
1012 * - R5: Priority to which the specified Logical Interrupt Source is
1014 * - R6: EISN for the specified Logical Interrupt Source (this will be
1015 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
1017 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
1018 SpaprMachineState
*spapr
,
1019 target_ulong opcode
,
1022 SpaprXive
*xive
= spapr
->xive
;
1023 target_ulong flags
= args
[0];
1024 target_ulong lisn
= args
[1];
1028 uint32_t end_idx
, nvt_idx
;
1030 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1038 if (lisn
>= xive
->nr_irqs
) {
1039 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1044 eas
= xive
->eat
[lisn
];
1045 if (!xive_eas_is_valid(&eas
)) {
1046 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1051 /* EAS_END_BLOCK is unused on sPAPR */
1052 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
1054 assert(end_idx
< xive
->nr_ends
);
1055 end
= &xive
->endt
[end_idx
];
1057 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1058 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1059 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
1061 if (xive_eas_is_masked(&eas
)) {
1064 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1067 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
1073 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
1074 * address of the notification management page associated with the
1075 * specified target and priority.
1080 * Bits 0-63 Reserved
1081 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1082 * "ibm,ppc-interrupt-gserver#s"
1083 * - R6: "priority" is a valid priority not in
1084 * "ibm,plat-res-int-priorities"
1087 * - R4: Logical real address of notification page
1088 * - R5: Power of 2 page size of the notification page
1090 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
1091 SpaprMachineState
*spapr
,
1092 target_ulong opcode
,
1095 SpaprXive
*xive
= spapr
->xive
;
1096 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1097 target_ulong flags
= args
[0];
1098 target_ulong target
= args
[1];
1099 target_ulong priority
= args
[2];
1104 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1113 * H_STATE should be returned if a H_INT_RESET is in progress.
1114 * This is not needed when running the emulation under QEMU
1117 if (spapr_xive_priority_is_reserved(priority
)) {
1118 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1119 " is reserved\n", priority
);
1124 * Validate that "target" is part of the list of threads allocated
1125 * to the partition. For that, find the END corresponding to the
1128 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1132 assert(end_idx
< xive
->nr_ends
);
1133 end
= &xive
->endt
[end_idx
];
1135 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
1136 if (xive_end_is_enqueue(end
)) {
1137 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1146 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
1147 * a given "target" and "priority". It is also used to set the
1148 * notification config associated with the EQ. An EQ size of 0 is
1149 * used to reset the EQ config for a given target and priority. If
1150 * resetting the EQ config, the END associated with the given "target"
1151 * and "priority" will be changed to disable queueing.
1153 * Upon return from the hcall(), no additional interrupts will be
1154 * directed to the old EQ (if one was set). The old EQ (if one was
1155 * set) should be investigated for interrupts that occurred prior to
1156 * or during the hcall().
1161 * Bits 0-62: Reserved
1162 * Bit 63: Unconditional Notify (n) per the XIVE spec
1163 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1164 * "ibm,ppc-interrupt-gserver#s"
1165 * - R6: "priority" is a valid priority not in
1166 * "ibm,plat-res-int-priorities"
1167 * - R7: "eventQueue": The logical real address of the start of the EQ
1168 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1174 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1176 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1177 SpaprMachineState
*spapr
,
1178 target_ulong opcode
,
1181 SpaprXive
*xive
= spapr
->xive
;
1182 target_ulong flags
= args
[0];
1183 target_ulong target
= args
[1];
1184 target_ulong priority
= args
[2];
1185 target_ulong qpage
= args
[3];
1186 target_ulong qsize
= args
[4];
1188 uint8_t end_blk
, nvt_blk
;
1189 uint32_t end_idx
, nvt_idx
;
1191 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1195 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1200 * H_STATE should be returned if a H_INT_RESET is in progress.
1201 * This is not needed when running the emulation under QEMU
1204 if (spapr_xive_priority_is_reserved(priority
)) {
1205 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1206 " is reserved\n", priority
);
1211 * Validate that "target" is part of the list of threads allocated
1212 * to the partition. For that, find the END corresponding to the
1216 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1220 assert(end_idx
< xive
->nr_ends
);
1221 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1228 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1229 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1230 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1231 qpage
, (hwaddr
)1 << qsize
);
1234 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1235 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1236 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1237 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1240 /* reset queue and disable queueing */
1241 spapr_xive_end_reset(&end
);
1245 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1251 hwaddr plen
= 1 << qsize
;
1255 * Validate the guest EQ. We should also check that the queue
1256 * has been zeroed by the OS.
1258 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1259 MEMTXATTRS_UNSPECIFIED
);
1260 if (plen
!= 1 << qsize
) {
1261 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1262 HWADDR_PRIx
"\n", qpage
);
1265 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1268 /* "target" should have been validated above */
1269 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1270 g_assert_not_reached();
1274 * Ensure the priority and target are correctly set (they will not
1275 * be right after allocation)
1277 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1278 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1279 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1281 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1282 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1284 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1288 * The generation bit for the END starts at 1 and The END page
1289 * offset counter starts at 0.
1291 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1292 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1293 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1296 * TODO: issue syncs required to ensure all in-flight interrupts
1297 * are complete on the old END
1301 if (kvm_irqchip_in_kernel()) {
1302 Error
*local_err
= NULL
;
1304 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1306 error_report_err(local_err
);
1312 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1317 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1318 * target and priority.
1323 * Bits 0-62: Reserved
1324 * Bit 63: Debug: Return debug data
1325 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1326 * "ibm,ppc-interrupt-gserver#s"
1327 * - R6: "priority" is a valid priority not in
1328 * "ibm,plat-res-int-priorities"
1332 * Bits 0-61: Reserved
1333 * Bit 62: The value of Event Queue Generation Number (g) per
1334 * the XIVE spec if "Debug" = 1
1335 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1336 * - R5: The logical real address of the start of the EQ
1337 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1338 * - R7: The value of Event Queue Offset Counter per XIVE spec
1339 * if "Debug" = 1, else 0
1343 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1345 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1346 SpaprMachineState
*spapr
,
1347 target_ulong opcode
,
1350 SpaprXive
*xive
= spapr
->xive
;
1351 target_ulong flags
= args
[0];
1352 target_ulong target
= args
[1];
1353 target_ulong priority
= args
[2];
1358 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1362 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1367 * H_STATE should be returned if a H_INT_RESET is in progress.
1368 * This is not needed when running the emulation under QEMU
1371 if (spapr_xive_priority_is_reserved(priority
)) {
1372 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1373 " is reserved\n", priority
);
1378 * Validate that "target" is part of the list of threads allocated
1379 * to the partition. For that, find the END corresponding to the
1382 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1386 assert(end_idx
< xive
->nr_ends
);
1387 end
= &xive
->endt
[end_idx
];
1390 if (xive_end_is_notify(end
)) {
1391 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1394 if (xive_end_is_enqueue(end
)) {
1395 args
[1] = xive_end_qaddr(end
);
1396 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1402 if (kvm_irqchip_in_kernel()) {
1403 Error
*local_err
= NULL
;
1405 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1407 error_report_err(local_err
);
1412 /* TODO: do we need any locking on the END ? */
1413 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1414 /* Load the event queue generation number into the return flags */
1415 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1417 /* Load R7 with the event queue offset counter */
1418 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1427 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1428 * reporting cache line pair for the calling thread. The reporting
1429 * cache lines will contain the OS interrupt context when the OS
1430 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1431 * interrupt. The reporting cache lines can be reset by inputting -1
1432 * in "reportingLine". Issuing the CI store byte without reporting
1433 * cache lines registered will result in the data not being accessible
1439 * Bits 0-63: Reserved
1440 * - R5: "reportingLine": The logical real address of the reporting cache
1446 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1447 SpaprMachineState
*spapr
,
1448 target_ulong opcode
,
1451 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1456 * H_STATE should be returned if a H_INT_RESET is in progress.
1457 * This is not needed when running the emulation under QEMU
1460 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1465 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1466 * real address of the reporting cache line pair set for the input
1467 * "target". If no reporting cache line pair has been set, -1 is
1473 * Bits 0-63: Reserved
1474 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1475 * "ibm,ppc-interrupt-gserver#s"
1476 * - R6: "reportingLine": The logical real address of the reporting
1480 * - R4: The logical real address of the reporting line if set, else -1
1482 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1483 SpaprMachineState
*spapr
,
1484 target_ulong opcode
,
1487 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1492 * H_STATE should be returned if a H_INT_RESET is in progress.
1493 * This is not needed when running the emulation under QEMU
1496 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1501 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1502 * page for the input "lisn". This hcall is only supported for LISNs
1503 * that have the ESB hcall flag set to 1 when returned from hcall()
1504 * H_INT_GET_SOURCE_INFO.
1509 * Bits 0-62: Reserved
1510 * bit 63: Store: Store=1, store operation, else load operation
1511 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1512 * "ibm,xive-lisn-ranges" properties, or as returned by the
1513 * ibm,query-interrupt-source-number RTAS call, or as
1514 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1515 * - R6: "esbOffset" is the offset into the ESB page for the load or
1517 * - R7: "storeData" is the data to write for a store operation
1520 * - R4: The value of the load if load operation, else -1
1523 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1525 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1526 SpaprMachineState
*spapr
,
1527 target_ulong opcode
,
1530 SpaprXive
*xive
= spapr
->xive
;
1532 target_ulong flags
= args
[0];
1533 target_ulong lisn
= args
[1];
1534 target_ulong offset
= args
[2];
1535 target_ulong data
= args
[3];
1537 XiveSource
*xsrc
= &xive
->source
;
1539 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1543 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1547 if (lisn
>= xive
->nr_irqs
) {
1548 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1553 eas
= xive
->eat
[lisn
];
1554 if (!xive_eas_is_valid(&eas
)) {
1555 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1560 if (offset
> (1ull << xsrc
->esb_shift
)) {
1564 if (kvm_irqchip_in_kernel()) {
1565 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1566 flags
& SPAPR_XIVE_ESB_STORE
);
1568 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1570 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1571 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1572 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1573 HWADDR_PRIx
"\n", mmio_addr
);
1576 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1582 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1583 * ensure any in flight events for the input lisn are in the event
1589 * Bits 0-63: Reserved
1590 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1591 * "ibm,xive-lisn-ranges" properties, or as returned by the
1592 * ibm,query-interrupt-source-number RTAS call, or as
1593 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1598 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1599 SpaprMachineState
*spapr
,
1600 target_ulong opcode
,
1603 SpaprXive
*xive
= spapr
->xive
;
1605 target_ulong flags
= args
[0];
1606 target_ulong lisn
= args
[1];
1608 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1616 if (lisn
>= xive
->nr_irqs
) {
1617 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1622 eas
= xive
->eat
[lisn
];
1623 if (!xive_eas_is_valid(&eas
)) {
1624 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1630 * H_STATE should be returned if a H_INT_RESET is in progress.
1631 * This is not needed when running the emulation under QEMU
1635 * This is not real hardware. Nothing to be done unless when
1639 if (kvm_irqchip_in_kernel()) {
1640 Error
*local_err
= NULL
;
1642 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1644 error_report_err(local_err
);
1652 * The H_INT_RESET hcall() is used to reset all of the partition's
1653 * interrupt exploitation structures to their initial state. This
1654 * means losing all previously set interrupt state set via
1655 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1660 * Bits 0-63: Reserved
1665 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1666 SpaprMachineState
*spapr
,
1667 target_ulong opcode
,
1670 SpaprXive
*xive
= spapr
->xive
;
1671 target_ulong flags
= args
[0];
1673 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1681 device_reset(DEVICE(xive
));
1683 if (kvm_irqchip_in_kernel()) {
1684 Error
*local_err
= NULL
;
1686 kvmppc_xive_reset(xive
, &local_err
);
1688 error_report_err(local_err
);
1695 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1697 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1698 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1699 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1700 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1701 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1702 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1703 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1704 h_int_set_os_reporting_line
);
1705 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1706 h_int_get_os_reporting_line
);
1707 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1708 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1709 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);