softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #define DATA_SIZE (1 << SHIFT)
  20
  21 #if DATA_SIZE == 8
  22 #define SUFFIX q
  23 #define USUFFIX q
  24 #define DATA_TYPE uint64_t
  25 #elif DATA_SIZE == 4
  26 #define SUFFIX l
  27 #define USUFFIX l
  28 #define DATA_TYPE uint32_t
  29 #elif DATA_SIZE == 2
  30 #define SUFFIX w
  31 #define USUFFIX uw
  32 #define DATA_TYPE uint16_t
  33 #elif DATA_SIZE == 1
  34 #define SUFFIX b
  35 #define USUFFIX ub
  36 #define DATA_TYPE uint8_t
  37 #else
  38 #error unsupported data size
  39 #endif
  40
  41 #ifdef SOFTMMU_CODE_ACCESS
  42 #define READ_ACCESS_TYPE 2
  43 #define ADDR_READ addr_code
  44 #else
  45 #define READ_ACCESS_TYPE 0
  46 #define ADDR_READ addr_read
  47 #endif
  48
  49 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  50                                                         int mmu_idx,
  51                                                         void *retaddr);
  52 static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
  53                                               target_ulong addr,
  54                                               void *retaddr)
  55 {
  56     DATA_TYPE res;
  57     int index;
  58     index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
  59     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
  60     env->mem_io_pc = (unsigned long)retaddr;
  61     if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
  62             && !can_do_io(env)) {
  63         cpu_io_recompile(env, retaddr);
  64     }
  65
  66     env->mem_io_vaddr = addr;
  67 #if SHIFT <= 2
  68     res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
  69 #else
  70 #ifdef TARGET_WORDS_BIGENDIAN
  71     res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
  72     res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
  73 #else
  74     res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
  75     res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
  76 #endif
  77 #endif /* SHIFT > 2 */
  78     return res;
  79 }
  80
  81 /* handle all cases except unaligned access which span two pages */
  82 DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  83                                                       int mmu_idx)
  84 {
  85     DATA_TYPE res;
  86     int index;
  87     target_ulong tlb_addr;
  88     target_phys_addr_t addend;
  89     void *retaddr;
  90
  91     /* test if there is match for unaligned or IO access */
  92     /* XXX: could done more in memory macro in a non portable way */
  93     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  94  redo:
  95     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
  96     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  97         if (tlb_addr & ~TARGET_PAGE_MASK) {
  98             /* IO access */
  99             if ((addr & (DATA_SIZE - 1)) != 0)
 100                 goto do_unaligned_access;
 101             retaddr = GETPC();
 102             addend = env->iotlb[mmu_idx][index];
 103             res = glue(io_read, SUFFIX)(addend, addr, retaddr);
 104         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 105             /* slow unaligned access (it spans two pages or IO) */
 106         do_unaligned_access:
 107             retaddr = GETPC();
 108 #ifdef ALIGNED_ONLY
 109             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 110 #endif
 111             res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
 112                                                          mmu_idx, retaddr);
 113         } else {
 114             /* unaligned/aligned access in the same page */
 115 #ifdef ALIGNED_ONLY
 116             if ((addr & (DATA_SIZE - 1)) != 0) {
 117                 retaddr = GETPC();
 118                 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 119             }
 120 #endif
 121             addend = env->tlb_table[mmu_idx][index].addend;
 122             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
 123         }
 124     } else {
 125         /* the page is not in the TLB : fill it */
 126         retaddr = GETPC();
 127 #ifdef ALIGNED_ONLY
 128         if ((addr & (DATA_SIZE - 1)) != 0)
 129             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 130 #endif
 131         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 132         goto redo;
 133     }
 134     return res;
 135 }
 136
 137 /* handle all unaligned cases */
 138 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
 139                                                         int mmu_idx,
 140                                                         void *retaddr)
 141 {
 142     DATA_TYPE res, res1, res2;
 143     int index, shift;
 144     target_phys_addr_t addend;
 145     target_ulong tlb_addr, addr1, addr2;
 146
 147     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 148  redo:
 149     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 150     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 151         if (tlb_addr & ~TARGET_PAGE_MASK) {
 152             /* IO access */
 153             if ((addr & (DATA_SIZE - 1)) != 0)
 154                 goto do_unaligned_access;
 155             addend = env->iotlb[mmu_idx][index];
 156             res = glue(io_read, SUFFIX)(addend, addr, retaddr);
 157         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 158         do_unaligned_access:
 159             /* slow unaligned access (it spans two pages) */
 160             addr1 = addr & ~(DATA_SIZE - 1);
 161             addr2 = addr1 + DATA_SIZE;
 162             res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
 163                                                           mmu_idx, retaddr);
 164             res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
 165                                                           mmu_idx, retaddr);
 166             shift = (addr & (DATA_SIZE - 1)) * 8;
 167 #ifdef TARGET_WORDS_BIGENDIAN
 168             res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 169 #else
 170             res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 171 #endif
 172             res = (DATA_TYPE)res;
 173         } else {
 174             /* unaligned/aligned access in the same page */
 175             addend = env->tlb_table[mmu_idx][index].addend;
 176             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
 177         }
 178     } else {
 179         /* the page is not in the TLB : fill it */
 180         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
 181         goto redo;
 182     }
 183     return res;
 184 }
 185
 186 #ifndef SOFTMMU_CODE_ACCESS
 187
 188 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 189                                                    DATA_TYPE val,
 190                                                    int mmu_idx,
 191                                                    void *retaddr);
 192
 193 static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
 194                                           DATA_TYPE val,
 195                                           target_ulong addr,
 196                                           void *retaddr)
 197 {
 198     int index;
 199     index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
 200     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 201     if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
 202             && !can_do_io(env)) {
 203         cpu_io_recompile(env, retaddr);
 204     }
 205
 206     env->mem_io_vaddr = addr;
 207     env->mem_io_pc = (unsigned long)retaddr;
 208 #if SHIFT <= 2
 209     io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
 210 #else
 211 #ifdef TARGET_WORDS_BIGENDIAN
 212     io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
 213     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
 214 #else
 215     io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
 216     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
 217 #endif
 218 #endif /* SHIFT > 2 */
 219 }
 220
 221 void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 222                                                  DATA_TYPE val,
 223                                                  int mmu_idx)
 224 {
 225     target_phys_addr_t addend;
 226     target_ulong tlb_addr;
 227     void *retaddr;
 228     int index;
 229
 230     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 231  redo:
 232     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 233     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 234         if (tlb_addr & ~TARGET_PAGE_MASK) {
 235             /* IO access */
 236             if ((addr & (DATA_SIZE - 1)) != 0)
 237                 goto do_unaligned_access;
 238             retaddr = GETPC();
 239             addend = env->iotlb[mmu_idx][index];
 240             glue(io_write, SUFFIX)(addend, val, addr, retaddr);
 241         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 242         do_unaligned_access:
 243             retaddr = GETPC();
 244 #ifdef ALIGNED_ONLY
 245             do_unaligned_access(addr, 1, mmu_idx, retaddr);
 246 #endif
 247             glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
 248                                                    mmu_idx, retaddr);
 249         } else {
 250             /* aligned/unaligned access in the same page */
 251 #ifdef ALIGNED_ONLY
 252             if ((addr & (DATA_SIZE - 1)) != 0) {
 253                 retaddr = GETPC();
 254                 do_unaligned_access(addr, 1, mmu_idx, retaddr);
 255             }
 256 #endif
 257             addend = env->tlb_table[mmu_idx][index].addend;
 258             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
 259         }
 260     } else {
 261         /* the page is not in the TLB : fill it */
 262         retaddr = GETPC();
 263 #ifdef ALIGNED_ONLY
 264         if ((addr & (DATA_SIZE - 1)) != 0)
 265             do_unaligned_access(addr, 1, mmu_idx, retaddr);
 266 #endif
 267         tlb_fill(addr, 1, mmu_idx, retaddr);
 268         goto redo;
 269     }
 270 }
 271
 272 /* handles all unaligned cases */
 273 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 274                                                    DATA_TYPE val,
 275                                                    int mmu_idx,
 276                                                    void *retaddr)
 277 {
 278     target_phys_addr_t addend;
 279     target_ulong tlb_addr;
 280     int index, i;
 281
 282     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 283  redo:
 284     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 285     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 286         if (tlb_addr & ~TARGET_PAGE_MASK) {
 287             /* IO access */
 288             if ((addr & (DATA_SIZE - 1)) != 0)
 289                 goto do_unaligned_access;
 290             addend = env->iotlb[mmu_idx][index];
 291             glue(io_write, SUFFIX)(addend, val, addr, retaddr);
 292         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 293         do_unaligned_access:
 294             /* XXX: not efficient, but simple */
 295             /* Note: relies on the fact that tlb_fill() does not remove the
 296              * previous page from the TLB cache.  */
 297             for(i = DATA_SIZE - 1; i >= 0; i--) {
 298 #ifdef TARGET_WORDS_BIGENDIAN
 299                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
 300                                           mmu_idx, retaddr);
 301 #else
 302                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
 303                                           mmu_idx, retaddr);
 304 #endif
 305             }
 306         } else {
 307             /* aligned/unaligned access in the same page */
 308             addend = env->tlb_table[mmu_idx][index].addend;
 309             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
 310         }
 311     } else {
 312         /* the page is not in the TLB : fill it */
 313         tlb_fill(addr, 1, mmu_idx, retaddr);
 314         goto redo;
 315     }
 316 }
 317
 318 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 319
 320 #undef READ_ACCESS_TYPE
 321 #undef SHIFT
 322 #undef DATA_TYPE
 323 #undef SUFFIX
 324 #undef USUFFIX
 325 #undef DATA_SIZE
 326 #undef ADDR_READ