4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * splitted out ioport related stuffs from vl.c.
28 #include "exec/ioport.h"
30 #include "exec/memory.h"
31 #include "exec/address-spaces.h"
33 //#define DEBUG_IOPORT
36 # define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
38 # define LOG_IOPORT(...) do { } while (0)
41 typedef struct MemoryRegionPortioList
{
44 MemoryRegionPortio ports
[];
45 } MemoryRegionPortioList
;
47 static uint64_t unassigned_io_read(void *opaque
, hwaddr addr
, unsigned size
)
52 static void unassigned_io_write(void *opaque
, hwaddr addr
, uint64_t val
,
57 const MemoryRegionOps unassigned_io_ops
= {
58 .read
= unassigned_io_read
,
59 .write
= unassigned_io_write
,
60 .endianness
= DEVICE_NATIVE_ENDIAN
,
63 void cpu_outb(pio_addr_t addr
, uint8_t val
)
65 LOG_IOPORT("outb: %04"FMT_pioaddr
" %02"PRIx8
"\n", addr
, val
);
66 trace_cpu_out(addr
, val
);
67 address_space_write(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
,
71 void cpu_outw(pio_addr_t addr
, uint16_t val
)
75 LOG_IOPORT("outw: %04"FMT_pioaddr
" %04"PRIx16
"\n", addr
, val
);
76 trace_cpu_out(addr
, val
);
78 address_space_write(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
,
82 void cpu_outl(pio_addr_t addr
, uint32_t val
)
86 LOG_IOPORT("outl: %04"FMT_pioaddr
" %08"PRIx32
"\n", addr
, val
);
87 trace_cpu_out(addr
, val
);
89 address_space_write(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
,
93 uint8_t cpu_inb(pio_addr_t addr
)
97 address_space_read(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
,
99 trace_cpu_in(addr
, val
);
100 LOG_IOPORT("inb : %04"FMT_pioaddr
" %02"PRIx8
"\n", addr
, val
);
104 uint16_t cpu_inw(pio_addr_t addr
)
109 address_space_read(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
, buf
, 2);
111 trace_cpu_in(addr
, val
);
112 LOG_IOPORT("inw : %04"FMT_pioaddr
" %04"PRIx16
"\n", addr
, val
);
116 uint32_t cpu_inl(pio_addr_t addr
)
121 address_space_read(&address_space_io
, addr
, MEMTXATTRS_UNSPECIFIED
, buf
, 4);
123 trace_cpu_in(addr
, val
);
124 LOG_IOPORT("inl : %04"FMT_pioaddr
" %08"PRIx32
"\n", addr
, val
);
128 void portio_list_init(PortioList
*piolist
,
130 const MemoryRegionPortio
*callbacks
,
131 void *opaque
, const char *name
)
135 while (callbacks
[n
].size
) {
139 piolist
->ports
= callbacks
;
141 piolist
->regions
= g_new0(MemoryRegion
*, n
);
142 piolist
->address_space
= NULL
;
143 piolist
->opaque
= opaque
;
144 piolist
->owner
= owner
;
145 piolist
->name
= name
;
146 piolist
->flush_coalesced_mmio
= false;
149 void portio_list_set_flush_coalesced(PortioList
*piolist
)
151 piolist
->flush_coalesced_mmio
= true;
154 void portio_list_destroy(PortioList
*piolist
)
156 MemoryRegionPortioList
*mrpio
;
159 for (i
= 0; i
< piolist
->nr
; ++i
) {
160 mrpio
= container_of(piolist
->regions
[i
], MemoryRegionPortioList
, mr
);
161 object_unparent(OBJECT(&mrpio
->mr
));
164 g_free(piolist
->regions
);
167 static const MemoryRegionPortio
*find_portio(MemoryRegionPortioList
*mrpio
,
168 uint64_t offset
, unsigned size
,
171 const MemoryRegionPortio
*mrp
;
173 for (mrp
= mrpio
->ports
; mrp
->size
; ++mrp
) {
174 if (offset
>= mrp
->offset
&& offset
< mrp
->offset
+ mrp
->len
&&
176 (write
? (bool)mrp
->write
: (bool)mrp
->read
)) {
183 static uint64_t portio_read(void *opaque
, hwaddr addr
, unsigned size
)
185 MemoryRegionPortioList
*mrpio
= opaque
;
186 const MemoryRegionPortio
*mrp
= find_portio(mrpio
, addr
, size
, false);
189 data
= ((uint64_t)1 << (size
* 8)) - 1;
191 data
= mrp
->read(mrpio
->portio_opaque
, mrp
->base
+ addr
);
192 } else if (size
== 2) {
193 mrp
= find_portio(mrpio
, addr
, 1, false);
195 data
= mrp
->read(mrpio
->portio_opaque
, mrp
->base
+ addr
);
196 if (addr
+ 1 < mrp
->offset
+ mrp
->len
) {
197 data
|= mrp
->read(mrpio
->portio_opaque
, mrp
->base
+ addr
+ 1) << 8;
206 static void portio_write(void *opaque
, hwaddr addr
, uint64_t data
,
209 MemoryRegionPortioList
*mrpio
= opaque
;
210 const MemoryRegionPortio
*mrp
= find_portio(mrpio
, addr
, size
, true);
213 mrp
->write(mrpio
->portio_opaque
, mrp
->base
+ addr
, data
);
214 } else if (size
== 2) {
215 mrp
= find_portio(mrpio
, addr
, 1, true);
217 mrp
->write(mrpio
->portio_opaque
, mrp
->base
+ addr
, data
& 0xff);
218 if (addr
+ 1 < mrp
->offset
+ mrp
->len
) {
219 mrp
->write(mrpio
->portio_opaque
, mrp
->base
+ addr
+ 1, data
>> 8);
225 static const MemoryRegionOps portio_ops
= {
227 .write
= portio_write
,
228 .endianness
= DEVICE_LITTLE_ENDIAN
,
229 .valid
.unaligned
= true,
230 .impl
.unaligned
= true,
233 static void portio_list_add_1(PortioList
*piolist
,
234 const MemoryRegionPortio
*pio_init
,
235 unsigned count
, unsigned start
,
236 unsigned off_low
, unsigned off_high
)
238 MemoryRegionPortioList
*mrpio
;
241 /* Copy the sub-list and null-terminate it. */
242 mrpio
= g_malloc0(sizeof(MemoryRegionPortioList
) +
243 sizeof(MemoryRegionPortio
) * (count
+ 1));
244 mrpio
->portio_opaque
= piolist
->opaque
;
245 memcpy(mrpio
->ports
, pio_init
, sizeof(MemoryRegionPortio
) * count
);
246 memset(mrpio
->ports
+ count
, 0, sizeof(MemoryRegionPortio
));
248 /* Adjust the offsets to all be zero-based for the region. */
249 for (i
= 0; i
< count
; ++i
) {
250 mrpio
->ports
[i
].offset
-= off_low
;
251 mrpio
->ports
[i
].base
= start
+ off_low
;
254 memory_region_init_io(&mrpio
->mr
, piolist
->owner
, &portio_ops
, mrpio
,
255 piolist
->name
, off_high
- off_low
);
256 if (piolist
->flush_coalesced_mmio
) {
257 memory_region_set_flush_coalesced(&mrpio
->mr
);
259 memory_region_add_subregion(piolist
->address_space
,
260 start
+ off_low
, &mrpio
->mr
);
261 piolist
->regions
[piolist
->nr
] = &mrpio
->mr
;
265 void portio_list_add(PortioList
*piolist
,
266 MemoryRegion
*address_space
,
269 const MemoryRegionPortio
*pio
, *pio_start
= piolist
->ports
;
270 unsigned int off_low
, off_high
, off_last
, count
;
272 piolist
->address_space
= address_space
;
274 /* Handle the first entry specially. */
275 off_last
= off_low
= pio_start
->offset
;
276 off_high
= off_low
+ pio_start
->len
+ pio_start
->size
- 1;
279 for (pio
= pio_start
+ 1; pio
->size
!= 0; pio
++, count
++) {
280 /* All entries must be sorted by offset. */
281 assert(pio
->offset
>= off_last
);
282 off_last
= pio
->offset
;
284 /* If we see a hole, break the region. */
285 if (off_last
> off_high
) {
286 portio_list_add_1(piolist
, pio_start
, count
, start
, off_low
,
288 /* ... and start collecting anew. */
291 off_high
= off_low
+ pio
->len
+ pio_start
->size
- 1;
293 } else if (off_last
+ pio
->len
> off_high
) {
294 off_high
= off_last
+ pio
->len
+ pio_start
->size
- 1;
298 /* There will always be an open sub-list. */
299 portio_list_add_1(piolist
, pio_start
, count
, start
, off_low
, off_high
);
302 void portio_list_del(PortioList
*piolist
)
304 MemoryRegionPortioList
*mrpio
;
307 for (i
= 0; i
< piolist
->nr
; ++i
) {
308 mrpio
= container_of(piolist
->regions
[i
], MemoryRegionPortioList
, mr
);
309 memory_region_del_subregion(piolist
->address_space
, &mrpio
->mr
);