hw/timer/digic-timer.c

   1 /*
   2  * QEMU model of the Canon DIGIC timer block.
   3  *
   4  * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
   5  *
   6  * This model is based on reverse engineering efforts
   7  * made by CHDK (http://chdk.wikia.com) and
   8  * Magic Lantern (http://www.magiclantern.fm) projects
   9  * contributors.
  10  *
  11  * See "Timer/Clock Module" docs here:
  12  *   http://magiclantern.wikia.com/wiki/Register_Map
  13  *
  14  * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao
  15  * is used as a template.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25  * GNU General Public License for more details.
  26  *
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/ptimer.h"
  32 #include "qemu/main-loop.h"
  33
  34 #include "hw/timer/digic-timer.h"
  35
  36 static const VMStateDescription vmstate_digic_timer = {
  37     .name = "digic.timer",
  38     .version_id = 1,
  39     .minimum_version_id = 1,
  40     .fields = (VMStateField[]) {
  41         VMSTATE_PTIMER(ptimer, DigicTimerState),
  42         VMSTATE_UINT32(control, DigicTimerState),
  43         VMSTATE_UINT32(relvalue, DigicTimerState),
  44         VMSTATE_END_OF_LIST()
  45     }
  46 };
  47
  48 static void digic_timer_reset(DeviceState *dev)
  49 {
  50     DigicTimerState *s = DIGIC_TIMER(dev);
  51
  52     ptimer_stop(s->ptimer);
  53     s->control = 0;
  54     s->relvalue = 0;
  55 }
  56
  57 static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
  58 {
  59     DigicTimerState *s = opaque;
  60     uint64_t ret = 0;
  61
  62     switch (offset) {
  63     case DIGIC_TIMER_CONTROL:
  64         ret = s->control;
  65         break;
  66     case DIGIC_TIMER_RELVALUE:
  67         ret = s->relvalue;
  68         break;
  69     case DIGIC_TIMER_VALUE:
  70         ret = ptimer_get_count(s->ptimer) & 0xffff;
  71         break;
  72     default:
  73         qemu_log_mask(LOG_UNIMP,
  74                       "digic-timer: read access to unknown register 0x"
  75                       TARGET_FMT_plx, offset);
  76     }
  77
  78     return ret;
  79 }
  80
  81 static void digic_timer_write(void *opaque, hwaddr offset,
  82                               uint64_t value, unsigned size)
  83 {
  84     DigicTimerState *s = opaque;
  85
  86     switch (offset) {
  87     case DIGIC_TIMER_CONTROL:
  88         if (value & DIGIC_TIMER_CONTROL_RST) {
  89             digic_timer_reset((DeviceState *)s);
  90             break;
  91         }
  92
  93         if (value & DIGIC_TIMER_CONTROL_EN) {
  94             ptimer_run(s->ptimer, 0);
  95         }
  96
  97         s->control = (uint32_t)value;
  98         break;
  99
 100     case DIGIC_TIMER_RELVALUE:
 101         s->relvalue = extract32(value, 0, 16);
 102         ptimer_set_limit(s->ptimer, s->relvalue, 1);
 103         break;
 104
 105     case DIGIC_TIMER_VALUE:
 106         break;
 107
 108     default:
 109         qemu_log_mask(LOG_UNIMP,
 110                       "digic-timer: read access to unknown register 0x"
 111                       TARGET_FMT_plx, offset);
 112     }
 113 }
 114
 115 static const MemoryRegionOps digic_timer_ops = {
 116     .read = digic_timer_read,
 117     .write = digic_timer_write,
 118     .impl = {
 119         .min_access_size = 4,
 120         .max_access_size = 4,
 121     },
 122     .endianness = DEVICE_NATIVE_ENDIAN,
 123 };
 124
 125 static void digic_timer_init(Object *obj)
 126 {
 127     DigicTimerState *s = DIGIC_TIMER(obj);
 128
 129     s->ptimer = ptimer_init(NULL);
 130
 131     /*
 132      * FIXME: there is no documentation on Digic timer
 133      * frequency setup so let it always run at 1 MHz
 134      */
 135     ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
 136
 137     memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
 138                           TYPE_DIGIC_TIMER, 0x100);
 139     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 140 }
 141
 142 static void digic_timer_class_init(ObjectClass *klass, void *class_data)
 143 {
 144     DeviceClass *dc = DEVICE_CLASS(klass);
 145
 146     dc->reset = digic_timer_reset;
 147     dc->vmsd = &vmstate_digic_timer;
 148 }
 149
 150 static const TypeInfo digic_timer_info = {
 151     .name = TYPE_DIGIC_TIMER,
 152     .parent = TYPE_SYS_BUS_DEVICE,
 153     .instance_size = sizeof(DigicTimerState),
 154     .instance_init = digic_timer_init,
 155     .class_init = digic_timer_class_init,
 156 };
 157
 158 static void digic_timer_register_type(void)
 159 {
 160     type_register_static(&digic_timer_info);
 161 }
 162
 163 type_init(digic_timer_register_type)