4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef HW_ARM_GIC_COMMON_H
22 #define HW_ARM_GIC_COMMON_H
24 #include "hw/sysbus.h"
26 /* Maximum number of possible interrupts, determined by the GIC architecture */
27 #define GIC_MAXIRQ 1020
28 /* First 32 are private to each CPU (SGIs and PPIs). */
29 #define GIC_INTERNAL 32
30 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
33 typedef struct gic_irq_state
{
34 /* The enable bits are only banked for per-cpu interrupts. */
39 bool model
; /* 0 = N:N, 1 = 1:N */
40 bool edge_trigger
; /* true: edge-triggered, false: level-triggered */
43 typedef struct GICState
{
45 SysBusDevice parent_obj
;
48 qemu_irq parent_irq
[GIC_NCPU
];
50 bool cpu_enabled
[GIC_NCPU
];
52 gic_irq_state irq_state
[GIC_MAXIRQ
];
53 uint8_t irq_target
[GIC_MAXIRQ
];
54 uint8_t priority1
[GIC_INTERNAL
][GIC_NCPU
];
55 uint8_t priority2
[GIC_MAXIRQ
- GIC_INTERNAL
];
56 uint16_t last_active
[GIC_MAXIRQ
][GIC_NCPU
];
58 uint16_t priority_mask
[GIC_NCPU
];
59 uint16_t running_irq
[GIC_NCPU
];
60 uint16_t running_priority
[GIC_NCPU
];
61 uint16_t current_pending
[GIC_NCPU
];
65 MemoryRegion iomem
; /* Distributor */
66 /* This is just so we can have an opaque pointer which identifies
67 * both this GIC and which CPU interface we should be accessing.
69 struct GICState
*backref
[GIC_NCPU
];
70 MemoryRegion cpuiomem
[GIC_NCPU
+ 1]; /* CPU interfaces */
75 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
76 #define ARM_GIC_COMMON(obj) \
77 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
78 #define ARM_GIC_COMMON_CLASS(klass) \
79 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
80 #define ARM_GIC_COMMON_GET_CLASS(obj) \
81 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
83 typedef struct ARMGICCommonClass
{
85 SysBusDeviceClass parent_class
;
88 void (*pre_save
)(GICState
*s
);
89 void (*post_load
)(GICState
*s
);