2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "exec/tb-context.h"
30 #include "qemu/bitops.h"
31 #include "qemu/queue.h"
33 #include "tcg-target.h"
34 #include "qemu/int128.h"
36 /* XXX: make safe guess about sizes */
37 #define MAX_OP_PER_INSTR 266
39 #if HOST_LONG_BITS == 32
40 #define MAX_OPC_PARAM_PER_ARG 2
42 #define MAX_OPC_PARAM_PER_ARG 1
44 #define MAX_OPC_PARAM_IARGS 6
45 #define MAX_OPC_PARAM_OARGS 1
46 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
48 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
49 * and up to 4 + N parameters on 64-bit archs
50 * (N = number of input arguments + output arguments). */
51 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
53 #define CPU_TEMP_BUF_NLONGS 128
55 /* Default target word size to pointer size. */
56 #ifndef TCG_TARGET_REG_BITS
57 # if UINTPTR_MAX == UINT32_MAX
58 # define TCG_TARGET_REG_BITS 32
59 # elif UINTPTR_MAX == UINT64_MAX
60 # define TCG_TARGET_REG_BITS 64
62 # error Unknown pointer size for tcg target
66 #if TCG_TARGET_REG_BITS == 32
67 typedef int32_t tcg_target_long
;
68 typedef uint32_t tcg_target_ulong
;
69 #define TCG_PRIlx PRIx32
70 #define TCG_PRIld PRId32
71 #elif TCG_TARGET_REG_BITS == 64
72 typedef int64_t tcg_target_long
;
73 typedef uint64_t tcg_target_ulong
;
74 #define TCG_PRIlx PRIx64
75 #define TCG_PRIld PRId64
80 /* Oversized TCG guests make things like MTTCG hard
81 * as we can't use atomics for cputlb updates.
83 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
84 #define TCG_OVERSIZED_GUEST 1
86 #define TCG_OVERSIZED_GUEST 0
89 #if TCG_TARGET_NB_REGS <= 32
90 typedef uint32_t TCGRegSet
;
91 #elif TCG_TARGET_NB_REGS <= 64
92 typedef uint64_t TCGRegSet
;
97 #if TCG_TARGET_REG_BITS == 32
98 /* Turn some undef macros into false macros. */
99 #define TCG_TARGET_HAS_extrl_i64_i32 0
100 #define TCG_TARGET_HAS_extrh_i64_i32 0
101 #define TCG_TARGET_HAS_div_i64 0
102 #define TCG_TARGET_HAS_rem_i64 0
103 #define TCG_TARGET_HAS_div2_i64 0
104 #define TCG_TARGET_HAS_rot_i64 0
105 #define TCG_TARGET_HAS_ext8s_i64 0
106 #define TCG_TARGET_HAS_ext16s_i64 0
107 #define TCG_TARGET_HAS_ext32s_i64 0
108 #define TCG_TARGET_HAS_ext8u_i64 0
109 #define TCG_TARGET_HAS_ext16u_i64 0
110 #define TCG_TARGET_HAS_ext32u_i64 0
111 #define TCG_TARGET_HAS_bswap16_i64 0
112 #define TCG_TARGET_HAS_bswap32_i64 0
113 #define TCG_TARGET_HAS_bswap64_i64 0
114 #define TCG_TARGET_HAS_neg_i64 0
115 #define TCG_TARGET_HAS_not_i64 0
116 #define TCG_TARGET_HAS_andc_i64 0
117 #define TCG_TARGET_HAS_orc_i64 0
118 #define TCG_TARGET_HAS_eqv_i64 0
119 #define TCG_TARGET_HAS_nand_i64 0
120 #define TCG_TARGET_HAS_nor_i64 0
121 #define TCG_TARGET_HAS_clz_i64 0
122 #define TCG_TARGET_HAS_ctz_i64 0
123 #define TCG_TARGET_HAS_ctpop_i64 0
124 #define TCG_TARGET_HAS_deposit_i64 0
125 #define TCG_TARGET_HAS_extract_i64 0
126 #define TCG_TARGET_HAS_sextract_i64 0
127 #define TCG_TARGET_HAS_extract2_i64 0
128 #define TCG_TARGET_HAS_movcond_i64 0
129 #define TCG_TARGET_HAS_add2_i64 0
130 #define TCG_TARGET_HAS_sub2_i64 0
131 #define TCG_TARGET_HAS_mulu2_i64 0
132 #define TCG_TARGET_HAS_muls2_i64 0
133 #define TCG_TARGET_HAS_muluh_i64 0
134 #define TCG_TARGET_HAS_mulsh_i64 0
135 /* Turn some undef macros into true macros. */
136 #define TCG_TARGET_HAS_add2_i32 1
137 #define TCG_TARGET_HAS_sub2_i32 1
140 #ifndef TCG_TARGET_deposit_i32_valid
141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
143 #ifndef TCG_TARGET_deposit_i64_valid
144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
146 #ifndef TCG_TARGET_extract_i32_valid
147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
149 #ifndef TCG_TARGET_extract_i64_valid
150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
153 /* Only one of DIV or DIV2 should be defined. */
154 #if defined(TCG_TARGET_HAS_div_i32)
155 #define TCG_TARGET_HAS_div2_i32 0
156 #elif defined(TCG_TARGET_HAS_div2_i32)
157 #define TCG_TARGET_HAS_div_i32 0
158 #define TCG_TARGET_HAS_rem_i32 0
160 #if defined(TCG_TARGET_HAS_div_i64)
161 #define TCG_TARGET_HAS_div2_i64 0
162 #elif defined(TCG_TARGET_HAS_div2_i64)
163 #define TCG_TARGET_HAS_div_i64 0
164 #define TCG_TARGET_HAS_rem_i64 0
167 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
168 #if TCG_TARGET_REG_BITS == 32 \
169 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
170 || defined(TCG_TARGET_HAS_muluh_i32))
171 # error "Missing unsigned widening multiply"
174 #if !defined(TCG_TARGET_HAS_v64) \
175 && !defined(TCG_TARGET_HAS_v128) \
176 && !defined(TCG_TARGET_HAS_v256)
177 #define TCG_TARGET_MAYBE_vec 0
178 #define TCG_TARGET_HAS_abs_vec 0
179 #define TCG_TARGET_HAS_neg_vec 0
180 #define TCG_TARGET_HAS_not_vec 0
181 #define TCG_TARGET_HAS_andc_vec 0
182 #define TCG_TARGET_HAS_orc_vec 0
183 #define TCG_TARGET_HAS_shi_vec 0
184 #define TCG_TARGET_HAS_shs_vec 0
185 #define TCG_TARGET_HAS_shv_vec 0
186 #define TCG_TARGET_HAS_mul_vec 0
187 #define TCG_TARGET_HAS_sat_vec 0
188 #define TCG_TARGET_HAS_minmax_vec 0
189 #define TCG_TARGET_HAS_bitsel_vec 0
190 #define TCG_TARGET_HAS_cmpsel_vec 0
192 #define TCG_TARGET_MAYBE_vec 1
194 #ifndef TCG_TARGET_HAS_v64
195 #define TCG_TARGET_HAS_v64 0
197 #ifndef TCG_TARGET_HAS_v128
198 #define TCG_TARGET_HAS_v128 0
200 #ifndef TCG_TARGET_HAS_v256
201 #define TCG_TARGET_HAS_v256 0
204 #ifndef TARGET_INSN_START_EXTRA_WORDS
205 # define TARGET_INSN_START_WORDS 1
207 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
210 typedef enum TCGOpcode
{
211 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
217 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
218 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
219 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
221 #ifndef TCG_TARGET_INSN_UNIT_SIZE
222 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
223 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
224 typedef uint8_t tcg_insn_unit
;
225 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
226 typedef uint16_t tcg_insn_unit
;
227 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
228 typedef uint32_t tcg_insn_unit
;
229 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
230 typedef uint64_t tcg_insn_unit
;
232 /* The port better have done this. */
236 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
237 # define tcg_debug_assert(X) do { assert(X); } while (0)
239 # define tcg_debug_assert(X) \
240 do { if (!(X)) { __builtin_unreachable(); } } while (0)
243 typedef struct TCGRelocation TCGRelocation
;
244 struct TCGRelocation
{
245 QSIMPLEQ_ENTRY(TCGRelocation
) next
;
251 typedef struct TCGLabel TCGLabel
;
253 unsigned present
: 1;
254 unsigned has_value
: 1;
259 tcg_insn_unit
*value_ptr
;
261 QSIMPLEQ_HEAD(, TCGRelocation
) relocs
;
262 QSIMPLEQ_ENTRY(TCGLabel
) next
;
265 typedef struct TCGPool
{
266 struct TCGPool
*next
;
268 uint8_t data
[0] __attribute__ ((aligned
));
271 #define TCG_POOL_CHUNK_SIZE 32768
273 #define TCG_MAX_TEMPS 512
274 #define TCG_MAX_INSNS 512
276 /* when the size of the arguments of a called function is smaller than
277 this value, they are statically allocated in the TB stack frame */
278 #define TCG_STATIC_CALL_ARGS_SIZE 128
280 typedef enum TCGType
{
288 TCG_TYPE_COUNT
, /* number of different types */
290 /* An alias for the size of the host register. */
291 #if TCG_TARGET_REG_BITS == 32
292 TCG_TYPE_REG
= TCG_TYPE_I32
,
294 TCG_TYPE_REG
= TCG_TYPE_I64
,
297 /* An alias for the size of the native pointer. */
298 #if UINTPTR_MAX == UINT32_MAX
299 TCG_TYPE_PTR
= TCG_TYPE_I32
,
301 TCG_TYPE_PTR
= TCG_TYPE_I64
,
304 /* An alias for the size of the target "long", aka register. */
305 #if TARGET_LONG_BITS == 64
306 TCG_TYPE_TL
= TCG_TYPE_I64
,
308 TCG_TYPE_TL
= TCG_TYPE_I32
,
312 /* Constants for qemu_ld and qemu_st for the Memory Operation field. */
313 typedef enum TCGMemOp
{
318 MO_SIZE
= 3, /* Mask for the above. */
320 MO_SIGN
= 4, /* Sign-extended, otherwise zero-extended. */
322 MO_BSWAP
= 8, /* Host reverse endian. */
323 #ifdef HOST_WORDS_BIGENDIAN
330 #ifdef TARGET_WORDS_BIGENDIAN
337 * MO_UNALN accesses are never checked for alignment.
338 * MO_ALIGN accesses will result in a call to the CPU's
339 * do_unaligned_access hook if the guest address is not aligned.
340 * The default depends on whether the target CPU defines
341 * TARGET_ALIGNED_ONLY.
343 * Some architectures (e.g. ARMv8) need the address which is aligned
344 * to a size more than the size of the memory access.
345 * Some architectures (e.g. SPARCv9) need an address which is aligned,
346 * but less strictly than the natural alignment.
348 * MO_ALIGN supposes the alignment size is the size of a memory access.
350 * There are three options:
351 * - unaligned access permitted (MO_UNALN).
352 * - an alignment to the size of an access (MO_ALIGN);
353 * - an alignment to a specified size, which may be more or less than
354 * the access size (MO_ALIGN_x where 'x' is a size in bytes);
357 MO_AMASK
= 7 << MO_ASHIFT
,
358 #ifdef TARGET_ALIGNED_ONLY
365 MO_ALIGN_2
= 1 << MO_ASHIFT
,
366 MO_ALIGN_4
= 2 << MO_ASHIFT
,
367 MO_ALIGN_8
= 3 << MO_ASHIFT
,
368 MO_ALIGN_16
= 4 << MO_ASHIFT
,
369 MO_ALIGN_32
= 5 << MO_ASHIFT
,
370 MO_ALIGN_64
= 6 << MO_ASHIFT
,
372 /* Combinations of the above, for ease of use. */
376 MO_SB
= MO_SIGN
| MO_8
,
377 MO_SW
= MO_SIGN
| MO_16
,
378 MO_SL
= MO_SIGN
| MO_32
,
381 MO_LEUW
= MO_LE
| MO_UW
,
382 MO_LEUL
= MO_LE
| MO_UL
,
383 MO_LESW
= MO_LE
| MO_SW
,
384 MO_LESL
= MO_LE
| MO_SL
,
385 MO_LEQ
= MO_LE
| MO_Q
,
387 MO_BEUW
= MO_BE
| MO_UW
,
388 MO_BEUL
= MO_BE
| MO_UL
,
389 MO_BESW
= MO_BE
| MO_SW
,
390 MO_BESL
= MO_BE
| MO_SL
,
391 MO_BEQ
= MO_BE
| MO_Q
,
393 MO_TEUW
= MO_TE
| MO_UW
,
394 MO_TEUL
= MO_TE
| MO_UL
,
395 MO_TESW
= MO_TE
| MO_SW
,
396 MO_TESL
= MO_TE
| MO_SL
,
397 MO_TEQ
= MO_TE
| MO_Q
,
399 MO_SSIZE
= MO_SIZE
| MO_SIGN
,
404 * @memop: TCGMemOp value
406 * Extract the alignment size from the memop.
408 static inline unsigned get_alignment_bits(TCGMemOp memop
)
410 unsigned a
= memop
& MO_AMASK
;
413 /* No alignment required. */
415 } else if (a
== MO_ALIGN
) {
416 /* A natural alignment requirement. */
419 /* A specific alignment requirement. */
422 #if defined(CONFIG_SOFTMMU)
423 /* The requested alignment cannot overlap the TLB flags. */
424 tcg_debug_assert((TLB_FLAGS_MASK
& ((1 << a
) - 1)) == 0);
429 typedef tcg_target_ulong TCGArg
;
431 /* Define type and accessor macros for TCG variables.
433 TCG variables are the inputs and outputs of TCG ops, as described
434 in tcg/README. Target CPU front-end code uses these types to deal
435 with TCG variables as it emits TCG code via the tcg_gen_* functions.
436 They come in several flavours:
437 * TCGv_i32 : 32 bit integer type
438 * TCGv_i64 : 64 bit integer type
439 * TCGv_ptr : a host pointer type
440 * TCGv_vec : a host vector type; the exact size is not exposed
441 to the CPU front-end code.
442 * TCGv : an integer type the same size as target_ulong
443 (an alias for either TCGv_i32 or TCGv_i64)
444 The compiler's type checking will complain if you mix them
445 up and pass the wrong sized TCGv to a function.
447 Users of tcg_gen_* don't need to know about any of the internal
448 details of these, and should treat them as opaque types.
449 You won't be able to look inside them in a debugger either.
451 Internal implementation details follow:
453 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
454 This is deliberate, because the values we store in variables of type
455 TCGv_i32 are not really pointers-to-structures. They're just small
456 integers, but keeping them in pointer types like this means that the
457 compiler will complain if you accidentally pass a TCGv_i32 to a
458 function which takes a TCGv_i64, and so on. Only the internals of
459 TCG need to care about the actual contents of the types. */
461 typedef struct TCGv_i32_d
*TCGv_i32
;
462 typedef struct TCGv_i64_d
*TCGv_i64
;
463 typedef struct TCGv_ptr_d
*TCGv_ptr
;
464 typedef struct TCGv_vec_d
*TCGv_vec
;
465 typedef TCGv_ptr TCGv_env
;
466 #if TARGET_LONG_BITS == 32
467 #define TCGv TCGv_i32
468 #elif TARGET_LONG_BITS == 64
469 #define TCGv TCGv_i64
471 #error Unhandled TARGET_LONG_BITS value
475 /* Helper does not read globals (either directly or through an exception). It
476 implies TCG_CALL_NO_WRITE_GLOBALS. */
477 #define TCG_CALL_NO_READ_GLOBALS 0x0001
478 /* Helper does not write globals */
479 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002
480 /* Helper can be safely suppressed if the return value is not used. */
481 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004
482 /* Helper is QEMU_NORETURN. */
483 #define TCG_CALL_NO_RETURN 0x0008
485 /* convenience version of most used call flags */
486 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
487 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
488 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
489 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
490 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
492 /* Used to align parameters. See the comment before tcgv_i32_temp. */
493 #define TCG_CALL_DUMMY_ARG ((TCGArg)0)
495 /* Conditions. Note that these are laid out for easy manipulation by
497 bit 0 is used for inverting;
500 bit 3 is used with bit 0 for swapping signed/unsigned. */
503 TCG_COND_NEVER
= 0 | 0 | 0 | 0,
504 TCG_COND_ALWAYS
= 0 | 0 | 0 | 1,
505 TCG_COND_EQ
= 8 | 0 | 0 | 0,
506 TCG_COND_NE
= 8 | 0 | 0 | 1,
508 TCG_COND_LT
= 0 | 0 | 2 | 0,
509 TCG_COND_GE
= 0 | 0 | 2 | 1,
510 TCG_COND_LE
= 8 | 0 | 2 | 0,
511 TCG_COND_GT
= 8 | 0 | 2 | 1,
513 TCG_COND_LTU
= 0 | 4 | 0 | 0,
514 TCG_COND_GEU
= 0 | 4 | 0 | 1,
515 TCG_COND_LEU
= 8 | 4 | 0 | 0,
516 TCG_COND_GTU
= 8 | 4 | 0 | 1,
519 /* Invert the sense of the comparison. */
520 static inline TCGCond
tcg_invert_cond(TCGCond c
)
522 return (TCGCond
)(c
^ 1);
525 /* Swap the operands in a comparison. */
526 static inline TCGCond
tcg_swap_cond(TCGCond c
)
528 return c
& 6 ? (TCGCond
)(c
^ 9) : c
;
531 /* Create an "unsigned" version of a "signed" comparison. */
532 static inline TCGCond
tcg_unsigned_cond(TCGCond c
)
534 return c
& 2 ? (TCGCond
)(c
^ 6) : c
;
537 /* Create a "signed" version of an "unsigned" comparison. */
538 static inline TCGCond
tcg_signed_cond(TCGCond c
)
540 return c
& 4 ? (TCGCond
)(c
^ 6) : c
;
543 /* Must a comparison be considered unsigned? */
544 static inline bool is_unsigned_cond(TCGCond c
)
549 /* Create a "high" version of a double-word comparison.
550 This removes equality from a LTE or GTE comparison. */
551 static inline TCGCond
tcg_high_cond(TCGCond c
)
558 return (TCGCond
)(c
^ 8);
564 typedef enum TCGTempVal
{
571 typedef struct TCGTemp
{
573 TCGTempVal val_type
:8;
576 unsigned int fixed_reg
:1;
577 unsigned int indirect_reg
:1;
578 unsigned int indirect_base
:1;
579 unsigned int mem_coherent
:1;
580 unsigned int mem_allocated
:1;
581 /* If true, the temp is saved across both basic blocks and
582 translation blocks. */
583 unsigned int temp_global
:1;
584 /* If true, the temp is saved across basic blocks but dead
585 at the end of translation blocks. If false, the temp is
586 dead at the end of basic blocks. */
587 unsigned int temp_local
:1;
588 unsigned int temp_allocated
:1;
591 struct TCGTemp
*mem_base
;
595 /* Pass-specific information that can be stored for a temporary.
596 One word worth of integer data, and one pointer to data
597 allocated separately. */
602 typedef struct TCGContext TCGContext
;
604 typedef struct TCGTempSet
{
605 unsigned long l
[BITS_TO_LONGS(TCG_MAX_TEMPS
)];
608 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
609 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
610 There are never more than 2 outputs, which means that we can store all
611 dead + sync data within 16 bits. */
614 typedef uint16_t TCGLifeData
;
616 /* The layout here is designed to avoid a bitfield crossing of
617 a 32-bit boundary, which would cause GCC to add extra padding. */
618 typedef struct TCGOp
{
619 TCGOpcode opc
: 8; /* 8 */
621 /* Parameters for this opcode. See below. */
622 unsigned param1
: 4; /* 12 */
623 unsigned param2
: 4; /* 16 */
625 /* Lifetime data of the operands. */
626 unsigned life
: 16; /* 32 */
628 /* Next and previous opcodes. */
629 QTAILQ_ENTRY(TCGOp
) link
;
631 /* Arguments for the opcode. */
632 TCGArg args
[MAX_OPC_PARAM
];
634 /* Register preferences for the output(s). */
635 TCGRegSet output_pref
[2];
638 #define TCGOP_CALLI(X) (X)->param1
639 #define TCGOP_CALLO(X) (X)->param2
641 #define TCGOP_VECL(X) (X)->param1
642 #define TCGOP_VECE(X) (X)->param2
644 /* Make sure operands fit in the bitfields above. */
645 QEMU_BUILD_BUG_ON(NB_OPS
> (1 << 8));
647 typedef struct TCGProfile
{
648 int64_t cpu_exec_time
;
651 int64_t op_count
; /* total insn count */
652 int op_count_max
; /* max insn per TB */
655 int64_t del_op_count
;
657 int64_t code_out_len
;
658 int64_t search_out_len
;
663 int64_t restore_count
;
664 int64_t restore_time
;
665 int64_t table_op_count
[NB_OPS
];
669 uint8_t *pool_cur
, *pool_end
;
670 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
677 /* goto_tb support */
678 tcg_insn_unit
*code_buf
;
679 uint16_t *tb_jmp_reset_offset
; /* tb->jmp_reset_offset */
680 uintptr_t *tb_jmp_insn_offset
; /* tb->jmp_target_arg if direct_jump */
681 uintptr_t *tb_jmp_target_addr
; /* tb->jmp_target_arg if !direct_jump */
683 TCGRegSet reserved_regs
;
684 uint32_t tb_cflags
; /* cflags of the current TB */
685 intptr_t current_frame_offset
;
686 intptr_t frame_start
;
690 tcg_insn_unit
*code_ptr
;
692 #ifdef CONFIG_PROFILER
696 #ifdef CONFIG_DEBUG_TCG
698 int goto_tb_issue_mask
;
699 const TCGOpcode
*vecop_list
;
702 /* Code generation. Note that we specifically do not use tcg_insn_unit
703 here, because there's too much arithmetic throughout that relies
704 on addition and subtraction working on bytes. Rely on the GCC
705 extension that allows arithmetic on void*. */
706 void *code_gen_prologue
;
707 void *code_gen_epilogue
;
708 void *code_gen_buffer
;
709 size_t code_gen_buffer_size
;
713 /* Threshold to flush the translated code buffer. */
714 void *code_gen_highwater
;
716 size_t tb_phys_invalidate_count
;
718 /* Track which vCPU triggers events */
719 CPUState
*cpu
; /* *_trans */
721 /* These structures are private to tcg-target.inc.c. */
722 #ifdef TCG_TARGET_NEED_LDST_LABELS
723 QSIMPLEQ_HEAD(, TCGLabelQemuLdst
) ldst_labels
;
725 #ifdef TCG_TARGET_NEED_POOL_LABELS
726 struct TCGLabelPoolData
*pool_labels
;
729 TCGLabel
*exitreq_label
;
731 TCGTempSet free_temps
[TCG_TYPE_COUNT
* 2];
732 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
734 QTAILQ_HEAD(, TCGOp
) ops
, free_ops
;
735 QSIMPLEQ_HEAD(, TCGLabel
) labels
;
737 /* Tells which temporary holds a given register.
738 It does not take into account fixed registers */
739 TCGTemp
*reg_to_temp
[TCG_TARGET_NB_REGS
];
741 uint16_t gen_insn_end_off
[TCG_MAX_INSNS
];
742 target_ulong gen_insn_data
[TCG_MAX_INSNS
][TARGET_INSN_START_WORDS
];
745 extern TCGContext tcg_init_ctx
;
746 extern __thread TCGContext
*tcg_ctx
;
747 extern TCGv_env cpu_env
;
749 static inline size_t temp_idx(TCGTemp
*ts
)
751 ptrdiff_t n
= ts
- tcg_ctx
->temps
;
752 tcg_debug_assert(n
>= 0 && n
< tcg_ctx
->nb_temps
);
756 static inline TCGArg
temp_arg(TCGTemp
*ts
)
758 return (uintptr_t)ts
;
761 static inline TCGTemp
*arg_temp(TCGArg a
)
763 return (TCGTemp
*)(uintptr_t)a
;
766 /* Using the offset of a temporary, relative to TCGContext, rather than
767 its index means that we don't use 0. That leaves offset 0 free for
768 a NULL representation without having to leave index 0 unused. */
769 static inline TCGTemp
*tcgv_i32_temp(TCGv_i32 v
)
771 uintptr_t o
= (uintptr_t)v
;
772 TCGTemp
*t
= (void *)tcg_ctx
+ o
;
773 tcg_debug_assert(offsetof(TCGContext
, temps
[temp_idx(t
)]) == o
);
777 static inline TCGTemp
*tcgv_i64_temp(TCGv_i64 v
)
779 return tcgv_i32_temp((TCGv_i32
)v
);
782 static inline TCGTemp
*tcgv_ptr_temp(TCGv_ptr v
)
784 return tcgv_i32_temp((TCGv_i32
)v
);
787 static inline TCGTemp
*tcgv_vec_temp(TCGv_vec v
)
789 return tcgv_i32_temp((TCGv_i32
)v
);
792 static inline TCGArg
tcgv_i32_arg(TCGv_i32 v
)
794 return temp_arg(tcgv_i32_temp(v
));
797 static inline TCGArg
tcgv_i64_arg(TCGv_i64 v
)
799 return temp_arg(tcgv_i64_temp(v
));
802 static inline TCGArg
tcgv_ptr_arg(TCGv_ptr v
)
804 return temp_arg(tcgv_ptr_temp(v
));
807 static inline TCGArg
tcgv_vec_arg(TCGv_vec v
)
809 return temp_arg(tcgv_vec_temp(v
));
812 static inline TCGv_i32
temp_tcgv_i32(TCGTemp
*t
)
814 (void)temp_idx(t
); /* trigger embedded assert */
815 return (TCGv_i32
)((void *)t
- (void *)tcg_ctx
);
818 static inline TCGv_i64
temp_tcgv_i64(TCGTemp
*t
)
820 return (TCGv_i64
)temp_tcgv_i32(t
);
823 static inline TCGv_ptr
temp_tcgv_ptr(TCGTemp
*t
)
825 return (TCGv_ptr
)temp_tcgv_i32(t
);
828 static inline TCGv_vec
temp_tcgv_vec(TCGTemp
*t
)
830 return (TCGv_vec
)temp_tcgv_i32(t
);
833 #if TCG_TARGET_REG_BITS == 32
834 static inline TCGv_i32
TCGV_LOW(TCGv_i64 t
)
836 return temp_tcgv_i32(tcgv_i64_temp(t
));
839 static inline TCGv_i32
TCGV_HIGH(TCGv_i64 t
)
841 return temp_tcgv_i32(tcgv_i64_temp(t
) + 1);
845 static inline void tcg_set_insn_param(TCGOp
*op
, int arg
, TCGArg v
)
850 static inline void tcg_set_insn_start_param(TCGOp
*op
, int arg
, target_ulong v
)
852 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
853 tcg_set_insn_param(op
, arg
, v
);
855 tcg_set_insn_param(op
, arg
* 2, v
);
856 tcg_set_insn_param(op
, arg
* 2 + 1, v
>> 32);
860 /* The last op that was emitted. */
861 static inline TCGOp
*tcg_last_op(void)
863 return QTAILQ_LAST(&tcg_ctx
->ops
);
866 /* Test for whether to terminate the TB for using too many opcodes. */
867 static inline bool tcg_op_buf_full(void)
869 /* This is not a hard limit, it merely stops translation when
870 * we have produced "enough" opcodes. We want to limit TB size
871 * such that a RISC host can reasonably use a 16-bit signed
872 * branch within the TB. We also need to be mindful of the
873 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
874 * and TCGContext.gen_insn_end_off[].
876 return tcg_ctx
->nb_ops
>= 4000;
879 /* pool based memory allocation */
881 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
882 void *tcg_malloc_internal(TCGContext
*s
, int size
);
883 void tcg_pool_reset(TCGContext
*s
);
884 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
);
886 void tcg_region_init(void);
887 void tcg_region_reset_all(void);
889 size_t tcg_code_size(void);
890 size_t tcg_code_capacity(void);
892 void tcg_tb_insert(TranslationBlock
*tb
);
893 void tcg_tb_remove(TranslationBlock
*tb
);
894 size_t tcg_tb_phys_invalidate_count(void);
895 TranslationBlock
*tcg_tb_lookup(uintptr_t tc_ptr
);
896 void tcg_tb_foreach(GTraverseFunc func
, gpointer user_data
);
897 size_t tcg_nb_tbs(void);
899 /* user-mode: Called with mmap_lock held. */
900 static inline void *tcg_malloc(int size
)
902 TCGContext
*s
= tcg_ctx
;
903 uint8_t *ptr
, *ptr_end
;
905 /* ??? This is a weak placeholder for minimum malloc alignment. */
906 size
= QEMU_ALIGN_UP(size
, 8);
909 ptr_end
= ptr
+ size
;
910 if (unlikely(ptr_end
> s
->pool_end
)) {
911 return tcg_malloc_internal(tcg_ctx
, size
);
913 s
->pool_cur
= ptr_end
;
918 void tcg_context_init(TCGContext
*s
);
919 void tcg_register_thread(void);
920 void tcg_prologue_init(TCGContext
*s
);
921 void tcg_func_start(TCGContext
*s
);
923 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
);
925 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
);
927 TCGTemp
*tcg_global_mem_new_internal(TCGType
, TCGv_ptr
,
928 intptr_t, const char *);
929 TCGTemp
*tcg_temp_new_internal(TCGType
, bool);
930 void tcg_temp_free_internal(TCGTemp
*);
931 TCGv_vec
tcg_temp_new_vec(TCGType type
);
932 TCGv_vec
tcg_temp_new_vec_matching(TCGv_vec match
);
934 static inline void tcg_temp_free_i32(TCGv_i32 arg
)
936 tcg_temp_free_internal(tcgv_i32_temp(arg
));
939 static inline void tcg_temp_free_i64(TCGv_i64 arg
)
941 tcg_temp_free_internal(tcgv_i64_temp(arg
));
944 static inline void tcg_temp_free_ptr(TCGv_ptr arg
)
946 tcg_temp_free_internal(tcgv_ptr_temp(arg
));
949 static inline void tcg_temp_free_vec(TCGv_vec arg
)
951 tcg_temp_free_internal(tcgv_vec_temp(arg
));
954 static inline TCGv_i32
tcg_global_mem_new_i32(TCGv_ptr reg
, intptr_t offset
,
957 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I32
, reg
, offset
, name
);
958 return temp_tcgv_i32(t
);
961 static inline TCGv_i32
tcg_temp_new_i32(void)
963 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I32
, false);
964 return temp_tcgv_i32(t
);
967 static inline TCGv_i32
tcg_temp_local_new_i32(void)
969 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I32
, true);
970 return temp_tcgv_i32(t
);
973 static inline TCGv_i64
tcg_global_mem_new_i64(TCGv_ptr reg
, intptr_t offset
,
976 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_I64
, reg
, offset
, name
);
977 return temp_tcgv_i64(t
);
980 static inline TCGv_i64
tcg_temp_new_i64(void)
982 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I64
, false);
983 return temp_tcgv_i64(t
);
986 static inline TCGv_i64
tcg_temp_local_new_i64(void)
988 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_I64
, true);
989 return temp_tcgv_i64(t
);
992 static inline TCGv_ptr
tcg_global_mem_new_ptr(TCGv_ptr reg
, intptr_t offset
,
995 TCGTemp
*t
= tcg_global_mem_new_internal(TCG_TYPE_PTR
, reg
, offset
, name
);
996 return temp_tcgv_ptr(t
);
999 static inline TCGv_ptr
tcg_temp_new_ptr(void)
1001 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_PTR
, false);
1002 return temp_tcgv_ptr(t
);
1005 static inline TCGv_ptr
tcg_temp_local_new_ptr(void)
1007 TCGTemp
*t
= tcg_temp_new_internal(TCG_TYPE_PTR
, true);
1008 return temp_tcgv_ptr(t
);
1011 #if defined(CONFIG_DEBUG_TCG)
1012 /* If you call tcg_clear_temp_count() at the start of a section of
1013 * code which is not supposed to leak any TCG temporaries, then
1014 * calling tcg_check_temp_count() at the end of the section will
1015 * return 1 if the section did in fact leak a temporary.
1017 void tcg_clear_temp_count(void);
1018 int tcg_check_temp_count(void);
1020 #define tcg_clear_temp_count() do { } while (0)
1021 #define tcg_check_temp_count() 0
1024 int64_t tcg_cpu_exec_time(void);
1025 void tcg_dump_info(void);
1026 void tcg_dump_op_count(void);
1028 #define TCG_CT_ALIAS 0x80
1029 #define TCG_CT_IALIAS 0x40
1030 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1031 #define TCG_CT_REG 0x01
1032 #define TCG_CT_CONST 0x02 /* any constant of register size */
1034 typedef struct TCGArgConstraint
{
1036 uint8_t alias_index
;
1042 #define TCG_MAX_OP_ARGS 16
1044 /* Bits for TCGOpDef->flags, 8 bits available. */
1046 /* Instruction exits the translation block. */
1047 TCG_OPF_BB_EXIT
= 0x01,
1048 /* Instruction defines the end of a basic block. */
1049 TCG_OPF_BB_END
= 0x02,
1050 /* Instruction clobbers call registers and potentially update globals. */
1051 TCG_OPF_CALL_CLOBBER
= 0x04,
1052 /* Instruction has side effects: it cannot be removed if its outputs
1053 are not used, and might trigger exceptions. */
1054 TCG_OPF_SIDE_EFFECTS
= 0x08,
1055 /* Instruction operands are 64-bits (otherwise 32-bits). */
1056 TCG_OPF_64BIT
= 0x10,
1057 /* Instruction is optional and not implemented by the host, or insn
1058 is generic and should not be implemened by the host. */
1059 TCG_OPF_NOT_PRESENT
= 0x20,
1060 /* Instruction operands are vectors. */
1061 TCG_OPF_VECTOR
= 0x40,
1064 typedef struct TCGOpDef
{
1066 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
1068 TCGArgConstraint
*args_ct
;
1070 #if defined(CONFIG_DEBUG_TCG)
1075 extern TCGOpDef tcg_op_defs
[];
1076 extern const size_t tcg_op_defs_max
;
1078 typedef struct TCGTargetOpDef
{
1080 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
1083 #define tcg_abort() \
1085 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1089 bool tcg_op_supported(TCGOpcode op
);
1091 void tcg_gen_callN(void *func
, TCGTemp
*ret
, int nargs
, TCGTemp
**args
);
1093 TCGOp
*tcg_emit_op(TCGOpcode opc
);
1094 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
);
1095 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
);
1096 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*op
, TCGOpcode opc
);
1098 void tcg_optimize(TCGContext
*s
);
1100 TCGv_i32
tcg_const_i32(int32_t val
);
1101 TCGv_i64
tcg_const_i64(int64_t val
);
1102 TCGv_i32
tcg_const_local_i32(int32_t val
);
1103 TCGv_i64
tcg_const_local_i64(int64_t val
);
1104 TCGv_vec
tcg_const_zeros_vec(TCGType
);
1105 TCGv_vec
tcg_const_ones_vec(TCGType
);
1106 TCGv_vec
tcg_const_zeros_vec_matching(TCGv_vec
);
1107 TCGv_vec
tcg_const_ones_vec_matching(TCGv_vec
);
1109 #if UINTPTR_MAX == UINT32_MAX
1110 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1111 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1113 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1114 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1117 TCGLabel
*gen_new_label(void);
1123 * Encode a label for storage in the TCG opcode stream.
1126 static inline TCGArg
label_arg(TCGLabel
*l
)
1128 return (uintptr_t)l
;
1135 * The opposite of label_arg. Retrieve a label from the
1136 * encoding of the TCG opcode stream.
1139 static inline TCGLabel
*arg_label(TCGArg i
)
1141 return (TCGLabel
*)(uintptr_t)i
;
1146 * @a, @b: addresses to be differenced
1148 * There are many places within the TCG backends where we need a byte
1149 * difference between two pointers. While this can be accomplished
1150 * with local casting, it's easy to get wrong -- especially if one is
1151 * concerned with the signedness of the result.
1153 * This version relies on GCC's void pointer arithmetic to get the
1157 static inline ptrdiff_t tcg_ptr_byte_diff(void *a
, void *b
)
1164 * @s: the tcg context
1165 * @target: address of the target
1167 * Produce a pc-relative difference, from the current code_ptr
1168 * to the destination address.
1171 static inline ptrdiff_t tcg_pcrel_diff(TCGContext
*s
, void *target
)
1173 return tcg_ptr_byte_diff(target
, s
->code_ptr
);
1177 * tcg_current_code_size
1178 * @s: the tcg context
1180 * Compute the current code size within the translation block.
1181 * This is used to fill in qemu's data structures for goto_tb.
1184 static inline size_t tcg_current_code_size(TCGContext
*s
)
1186 return tcg_ptr_byte_diff(s
->code_ptr
, s
->code_buf
);
1189 /* Combine the TCGMemOp and mmu_idx parameters into a single value. */
1190 typedef uint32_t TCGMemOpIdx
;
1194 * @op: memory operation
1197 * Encode these values into a single parameter.
1199 static inline TCGMemOpIdx
make_memop_idx(TCGMemOp op
, unsigned idx
)
1201 tcg_debug_assert(idx
<= 15);
1202 return (op
<< 4) | idx
;
1207 * @oi: combined op/idx parameter
1209 * Extract the memory operation from the combined value.
1211 static inline TCGMemOp
get_memop(TCGMemOpIdx oi
)
1218 * @oi: combined op/idx parameter
1220 * Extract the mmu index from the combined value.
1222 static inline unsigned get_mmuidx(TCGMemOpIdx oi
)
1229 * @env: pointer to CPUArchState for the CPU
1230 * @tb_ptr: address of generated code for the TB to execute
1232 * Start executing code from a given translation block.
1233 * Where translation blocks have been linked, execution
1234 * may proceed from the given TB into successive ones.
1235 * Control eventually returns only when some action is needed
1236 * from the top-level loop: either control must pass to a TB
1237 * which has not yet been directly linked, or an asynchronous
1238 * event such as an interrupt needs handling.
1240 * Return: The return value is the value passed to the corresponding
1241 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1242 * The value is either zero or a 4-byte aligned pointer to that TB combined
1243 * with additional information in its two least significant bits. The
1244 * additional information is encoded as follows:
1245 * 0, 1: the link between this TB and the next is via the specified
1246 * TB index (0 or 1). That is, we left the TB via (the equivalent
1247 * of) "goto_tb <index>". The main loop uses this to determine
1248 * how to link the TB just executed to the next.
1249 * 2: we are using instruction counting code generation, and we
1250 * did not start executing this TB because the instruction counter
1251 * would hit zero midway through it. In this case the pointer
1252 * returned is the TB we were about to execute, and the caller must
1253 * arrange to execute the remaining count of instructions.
1254 * 3: we stopped because the CPU's exit_request flag was set
1255 * (usually meaning that there is an interrupt that needs to be
1256 * handled). The pointer returned is the TB we were about to execute
1257 * when we noticed the pending exit request.
1259 * If the bottom two bits indicate an exit-via-index then the CPU
1260 * state is correctly synchronised and ready for execution of the next
1261 * TB (and in particular the guest PC is the address to execute next).
1262 * Otherwise, we gave up on execution of this TB before it started, and
1263 * the caller must fix up the CPU state by calling the CPU's
1264 * synchronize_from_tb() method with the TB pointer we return (falling
1265 * back to calling the CPU's set_pc method with tb->pb if no
1266 * synchronize_from_tb() method exists).
1268 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1269 * to this default (which just calls the prologue.code emitted by
1270 * tcg_target_qemu_prologue()).
1272 #define TB_EXIT_MASK 3
1273 #define TB_EXIT_IDX0 0
1274 #define TB_EXIT_IDX1 1
1275 #define TB_EXIT_IDXMAX 1
1276 #define TB_EXIT_REQUESTED 3
1278 #ifdef HAVE_TCG_QEMU_TB_EXEC
1279 uintptr_t tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
);
1281 # define tcg_qemu_tb_exec(env, tb_ptr) \
1282 ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1285 void tcg_register_jit(void *buf
, size_t buf_size
);
1287 #if TCG_TARGET_MAYBE_vec
1288 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1289 return > 0 if it is directly supportable;
1290 return < 0 if we must call tcg_expand_vec_op. */
1291 int tcg_can_emit_vec_op(TCGOpcode
, TCGType
, unsigned);
1293 static inline int tcg_can_emit_vec_op(TCGOpcode o
, TCGType t
, unsigned ve
)
1299 /* Expand the tuple (opc, type, vece) on the given arguments. */
1300 void tcg_expand_vec_op(TCGOpcode
, TCGType
, unsigned, TCGArg
, ...);
1302 /* Replicate a constant C accoring to the log2 of the element size. */
1303 uint64_t dup_const(unsigned vece
, uint64_t c
);
1305 #define dup_const(VECE, C) \
1306 (__builtin_constant_p(VECE) \
1307 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1308 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1309 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1310 : dup_const(VECE, C)) \
1311 : dup_const(VECE, C))
1315 * Memory helpers that will be used by TCG generated code.
1317 #ifdef CONFIG_SOFTMMU
1318 /* Value zero-extended to tcg register size. */
1319 tcg_target_ulong
helper_ret_ldub_mmu(CPUArchState
*env
, target_ulong addr
,
1320 TCGMemOpIdx oi
, uintptr_t retaddr
);
1321 tcg_target_ulong
helper_le_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1322 TCGMemOpIdx oi
, uintptr_t retaddr
);
1323 tcg_target_ulong
helper_le_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1324 TCGMemOpIdx oi
, uintptr_t retaddr
);
1325 uint64_t helper_le_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1326 TCGMemOpIdx oi
, uintptr_t retaddr
);
1327 tcg_target_ulong
helper_be_lduw_mmu(CPUArchState
*env
, target_ulong addr
,
1328 TCGMemOpIdx oi
, uintptr_t retaddr
);
1329 tcg_target_ulong
helper_be_ldul_mmu(CPUArchState
*env
, target_ulong addr
,
1330 TCGMemOpIdx oi
, uintptr_t retaddr
);
1331 uint64_t helper_be_ldq_mmu(CPUArchState
*env
, target_ulong addr
,
1332 TCGMemOpIdx oi
, uintptr_t retaddr
);
1334 /* Value sign-extended to tcg register size. */
1335 tcg_target_ulong
helper_ret_ldsb_mmu(CPUArchState
*env
, target_ulong addr
,
1336 TCGMemOpIdx oi
, uintptr_t retaddr
);
1337 tcg_target_ulong
helper_le_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1338 TCGMemOpIdx oi
, uintptr_t retaddr
);
1339 tcg_target_ulong
helper_le_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1340 TCGMemOpIdx oi
, uintptr_t retaddr
);
1341 tcg_target_ulong
helper_be_ldsw_mmu(CPUArchState
*env
, target_ulong addr
,
1342 TCGMemOpIdx oi
, uintptr_t retaddr
);
1343 tcg_target_ulong
helper_be_ldsl_mmu(CPUArchState
*env
, target_ulong addr
,
1344 TCGMemOpIdx oi
, uintptr_t retaddr
);
1346 void helper_ret_stb_mmu(CPUArchState
*env
, target_ulong addr
, uint8_t val
,
1347 TCGMemOpIdx oi
, uintptr_t retaddr
);
1348 void helper_le_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1349 TCGMemOpIdx oi
, uintptr_t retaddr
);
1350 void helper_le_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1351 TCGMemOpIdx oi
, uintptr_t retaddr
);
1352 void helper_le_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1353 TCGMemOpIdx oi
, uintptr_t retaddr
);
1354 void helper_be_stw_mmu(CPUArchState
*env
, target_ulong addr
, uint16_t val
,
1355 TCGMemOpIdx oi
, uintptr_t retaddr
);
1356 void helper_be_stl_mmu(CPUArchState
*env
, target_ulong addr
, uint32_t val
,
1357 TCGMemOpIdx oi
, uintptr_t retaddr
);
1358 void helper_be_stq_mmu(CPUArchState
*env
, target_ulong addr
, uint64_t val
,
1359 TCGMemOpIdx oi
, uintptr_t retaddr
);
1361 uint8_t helper_ret_ldb_cmmu(CPUArchState
*env
, target_ulong addr
,
1362 TCGMemOpIdx oi
, uintptr_t retaddr
);
1363 uint16_t helper_le_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1364 TCGMemOpIdx oi
, uintptr_t retaddr
);
1365 uint32_t helper_le_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1366 TCGMemOpIdx oi
, uintptr_t retaddr
);
1367 uint64_t helper_le_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1368 TCGMemOpIdx oi
, uintptr_t retaddr
);
1369 uint16_t helper_be_ldw_cmmu(CPUArchState
*env
, target_ulong addr
,
1370 TCGMemOpIdx oi
, uintptr_t retaddr
);
1371 uint32_t helper_be_ldl_cmmu(CPUArchState
*env
, target_ulong addr
,
1372 TCGMemOpIdx oi
, uintptr_t retaddr
);
1373 uint64_t helper_be_ldq_cmmu(CPUArchState
*env
, target_ulong addr
,
1374 TCGMemOpIdx oi
, uintptr_t retaddr
);
1376 /* Temporary aliases until backends are converted. */
1377 #ifdef TARGET_WORDS_BIGENDIAN
1378 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1379 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1380 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1381 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1382 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1383 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1384 # define helper_ret_stw_mmu helper_be_stw_mmu
1385 # define helper_ret_stl_mmu helper_be_stl_mmu
1386 # define helper_ret_stq_mmu helper_be_stq_mmu
1387 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1388 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1389 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1391 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1392 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1393 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1394 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1395 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1396 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1397 # define helper_ret_stw_mmu helper_le_stw_mmu
1398 # define helper_ret_stl_mmu helper_le_stl_mmu
1399 # define helper_ret_stq_mmu helper_le_stq_mmu
1400 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1401 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1402 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1405 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState
*env
, target_ulong addr
,
1406 uint32_t cmpv
, uint32_t newv
,
1407 TCGMemOpIdx oi
, uintptr_t retaddr
);
1408 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState
*env
, target_ulong addr
,
1409 uint32_t cmpv
, uint32_t newv
,
1410 TCGMemOpIdx oi
, uintptr_t retaddr
);
1411 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState
*env
, target_ulong addr
,
1412 uint32_t cmpv
, uint32_t newv
,
1413 TCGMemOpIdx oi
, uintptr_t retaddr
);
1414 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState
*env
, target_ulong addr
,
1415 uint64_t cmpv
, uint64_t newv
,
1416 TCGMemOpIdx oi
, uintptr_t retaddr
);
1417 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState
*env
, target_ulong addr
,
1418 uint32_t cmpv
, uint32_t newv
,
1419 TCGMemOpIdx oi
, uintptr_t retaddr
);
1420 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState
*env
, target_ulong addr
,
1421 uint32_t cmpv
, uint32_t newv
,
1422 TCGMemOpIdx oi
, uintptr_t retaddr
);
1423 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState
*env
, target_ulong addr
,
1424 uint64_t cmpv
, uint64_t newv
,
1425 TCGMemOpIdx oi
, uintptr_t retaddr
);
1427 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1428 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1429 (CPUArchState *env, target_ulong addr, TYPE val, \
1430 TCGMemOpIdx oi, uintptr_t retaddr);
1432 #ifdef CONFIG_ATOMIC64
1433 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1434 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1435 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1436 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1437 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1438 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1439 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1440 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1442 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1443 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1444 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1445 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1446 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1447 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1450 GEN_ATOMIC_HELPER_ALL(fetch_add
)
1451 GEN_ATOMIC_HELPER_ALL(fetch_sub
)
1452 GEN_ATOMIC_HELPER_ALL(fetch_and
)
1453 GEN_ATOMIC_HELPER_ALL(fetch_or
)
1454 GEN_ATOMIC_HELPER_ALL(fetch_xor
)
1455 GEN_ATOMIC_HELPER_ALL(fetch_smin
)
1456 GEN_ATOMIC_HELPER_ALL(fetch_umin
)
1457 GEN_ATOMIC_HELPER_ALL(fetch_smax
)
1458 GEN_ATOMIC_HELPER_ALL(fetch_umax
)
1460 GEN_ATOMIC_HELPER_ALL(add_fetch
)
1461 GEN_ATOMIC_HELPER_ALL(sub_fetch
)
1462 GEN_ATOMIC_HELPER_ALL(and_fetch
)
1463 GEN_ATOMIC_HELPER_ALL(or_fetch
)
1464 GEN_ATOMIC_HELPER_ALL(xor_fetch
)
1465 GEN_ATOMIC_HELPER_ALL(smin_fetch
)
1466 GEN_ATOMIC_HELPER_ALL(umin_fetch
)
1467 GEN_ATOMIC_HELPER_ALL(smax_fetch
)
1468 GEN_ATOMIC_HELPER_ALL(umax_fetch
)
1470 GEN_ATOMIC_HELPER_ALL(xchg
)
1472 #undef GEN_ATOMIC_HELPER_ALL
1473 #undef GEN_ATOMIC_HELPER
1474 #endif /* CONFIG_SOFTMMU */
1477 * These aren't really a "proper" helpers because TCG cannot manage Int128.
1478 * However, use the same format as the others, for use by the backends.
1480 * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1481 * the ld/st functions are only defined if HAVE_ATOMIC128,
1482 * as defined by <qemu/atomic128.h>.
1484 Int128
helper_atomic_cmpxchgo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1485 Int128 cmpv
, Int128 newv
,
1486 TCGMemOpIdx oi
, uintptr_t retaddr
);
1487 Int128
helper_atomic_cmpxchgo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1488 Int128 cmpv
, Int128 newv
,
1489 TCGMemOpIdx oi
, uintptr_t retaddr
);
1491 Int128
helper_atomic_ldo_le_mmu(CPUArchState
*env
, target_ulong addr
,
1492 TCGMemOpIdx oi
, uintptr_t retaddr
);
1493 Int128
helper_atomic_ldo_be_mmu(CPUArchState
*env
, target_ulong addr
,
1494 TCGMemOpIdx oi
, uintptr_t retaddr
);
1495 void helper_atomic_sto_le_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1496 TCGMemOpIdx oi
, uintptr_t retaddr
);
1497 void helper_atomic_sto_be_mmu(CPUArchState
*env
, target_ulong addr
, Int128 val
,
1498 TCGMemOpIdx oi
, uintptr_t retaddr
);
1500 #ifdef CONFIG_DEBUG_TCG
1501 void tcg_assert_listed_vecop(TCGOpcode
);
1503 static inline void tcg_assert_listed_vecop(TCGOpcode op
) { }
1506 static inline const TCGOpcode
*tcg_swap_vecop_list(const TCGOpcode
*n
)
1508 #ifdef CONFIG_DEBUG_TCG
1509 const TCGOpcode
*o
= tcg_ctx
->vecop_list
;
1510 tcg_ctx
->vecop_list
= n
;
1517 bool tcg_can_emit_vecop_list(const TCGOpcode
*, TCGType
, unsigned);