4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
30 #include "hw/core/tcg-cpu-ops.h"
31 #endif /* CONFIG_TCG */
32 #include "internals.h"
33 #include "exec/exec-all.h"
34 #include "hw/qdev-properties.h"
35 #if !defined(CONFIG_USER_ONLY)
36 #include "hw/loader.h"
37 #include "hw/boards.h"
39 #include "sysemu/tcg.h"
40 #include "sysemu/hw_accel.h"
43 #include "disas/capstone.h"
44 #include "fpu/softfloat.h"
46 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
48 ARMCPU
*cpu
= ARM_CPU(cs
);
49 CPUARMState
*env
= &cpu
->env
;
55 env
->regs
[15] = value
& ~1;
56 env
->thumb
= value
& 1;
61 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
62 const TranslationBlock
*tb
)
64 ARMCPU
*cpu
= ARM_CPU(cs
);
65 CPUARMState
*env
= &cpu
->env
;
68 * It's OK to look at env for the current mode here, because it's
69 * never possible for an AArch64 TB to chain to an AArch32 TB.
74 env
->regs
[15] = tb
->pc
;
77 #endif /* CONFIG_TCG */
79 static bool arm_cpu_has_work(CPUState
*cs
)
81 ARMCPU
*cpu
= ARM_CPU(cs
);
83 return (cpu
->power_state
!= PSCI_OFF
)
84 && cs
->interrupt_request
&
85 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
86 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
87 | CPU_INTERRUPT_EXITTB
);
90 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
93 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
96 entry
->opaque
= opaque
;
98 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
101 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
104 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
107 entry
->opaque
= opaque
;
109 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
112 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
114 /* Reset a single ARMCPRegInfo register */
115 ARMCPRegInfo
*ri
= value
;
116 ARMCPU
*cpu
= opaque
;
118 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
123 ri
->resetfn(&cpu
->env
, ri
);
127 /* A zero offset is never possible as it would be regs[0]
128 * so we use it to indicate that reset is being handled elsewhere.
129 * This is basically only used for fields in non-core coprocessors
130 * (like the pxa2xx ones).
132 if (!ri
->fieldoffset
) {
136 if (cpreg_field_is_64bit(ri
)) {
137 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
139 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
143 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
145 /* Purely an assertion check: we've already done reset once,
146 * so now check that running the reset for the cpreg doesn't
147 * change its value. This traps bugs where two different cpregs
148 * both try to reset the same state field but to different values.
150 ARMCPRegInfo
*ri
= value
;
151 ARMCPU
*cpu
= opaque
;
152 uint64_t oldvalue
, newvalue
;
154 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
158 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
159 cp_reg_reset(key
, value
, opaque
);
160 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
161 assert(oldvalue
== newvalue
);
164 static void arm_cpu_reset(DeviceState
*dev
)
166 CPUState
*s
= CPU(dev
);
167 ARMCPU
*cpu
= ARM_CPU(s
);
168 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
169 CPUARMState
*env
= &cpu
->env
;
171 acc
->parent_reset(dev
);
173 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
175 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
176 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
178 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
179 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
180 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
181 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
183 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
185 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
186 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
189 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
190 /* 64 bit CPUs always start in 64 bit mode */
192 #if defined(CONFIG_USER_ONLY)
193 env
->pstate
= PSTATE_MODE_EL0t
;
194 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
195 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
196 /* Enable all PAC keys. */
197 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
198 SCTLR_EnDA
| SCTLR_EnDB
);
199 /* and to the FP/Neon instructions */
200 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
201 /* and to the SVE instructions */
202 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
203 /* with reasonable vector length */
204 if (cpu_isar_feature(aa64_sve
, cpu
)) {
206 aarch64_sve_zcr_get_valid_len(cpu
, cpu
->sve_default_vq
- 1);
209 * Enable TBI0 but not TBI1.
210 * Note that this must match useronly_clean_ptr.
212 env
->cp15
.tcr_el
[1].raw_tcr
= (1ULL << 37);
215 if (cpu_isar_feature(aa64_mte
, cpu
)) {
216 /* Enable tag access, but leave TCF0 as No Effect (0). */
217 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
219 * Exclude all tags, so that tag 0 is always used.
220 * This corresponds to Linux current->thread.gcr_incl = 0.
222 * Set RRND, so that helper_irg() will generate a seed later.
223 * Here in cpu_reset(), the crypto subsystem has not yet been
226 env
->cp15
.gcr_el1
= 0x1ffff;
229 /* Reset into the highest available EL */
230 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
231 env
->pstate
= PSTATE_MODE_EL3h
;
232 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
233 env
->pstate
= PSTATE_MODE_EL2h
;
235 env
->pstate
= PSTATE_MODE_EL1h
;
237 env
->pc
= cpu
->rvbar
;
240 #if defined(CONFIG_USER_ONLY)
241 /* Userspace expects access to cp10 and cp11 for FP/Neon */
242 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
246 #if defined(CONFIG_USER_ONLY)
247 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
248 /* For user mode we must enable access to coprocessors */
249 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
250 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
251 env
->cp15
.c15_cpar
= 3;
252 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
253 env
->cp15
.c15_cpar
= 1;
258 * If the highest available EL is EL2, AArch32 will start in Hyp
259 * mode; otherwise it starts in SVC. Note that if we start in
260 * AArch64 then these values in the uncached_cpsr will be ignored.
262 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
263 !arm_feature(env
, ARM_FEATURE_EL3
)) {
264 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
266 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
268 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
270 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
271 * executing as AArch32 then check if highvecs are enabled and
272 * adjust the PC accordingly.
274 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
275 env
->regs
[15] = 0xFFFF0000;
278 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
281 if (arm_feature(env
, ARM_FEATURE_M
)) {
282 #ifndef CONFIG_USER_ONLY
283 uint32_t initial_msp
; /* Loaded from 0x0 */
284 uint32_t initial_pc
; /* Loaded from 0x4 */
289 if (cpu_isar_feature(aa32_lob
, cpu
)) {
291 * LTPSIZE is constant 4 if MVE not implemented, and resets
292 * to an UNKNOWN value if MVE is implemented. We choose to
295 env
->v7m
.ltpsize
= 4;
296 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
297 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
298 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
301 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
302 env
->v7m
.secure
= true;
304 /* This bit resets to 0 if security is supported, but 1 if
305 * it is not. The bit is not present in v7M, but we set it
306 * here so we can avoid having to make checks on it conditional
307 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
309 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
311 * Set NSACR to indicate "NS access permitted to everything";
312 * this avoids having to have all the tests of it being
313 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
314 * v8.1M the guest-visible value of NSACR in a CPU without the
315 * Security Extension is 0xcff.
317 env
->v7m
.nsacr
= 0xcff;
320 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
321 * that it resets to 1, so QEMU always does that rather than making
322 * it dependent on CPU model. In v8M it is RES1.
324 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
325 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
326 if (arm_feature(env
, ARM_FEATURE_V8
)) {
327 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
328 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
329 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
331 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
332 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
333 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
336 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
337 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
338 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
339 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
342 #ifndef CONFIG_USER_ONLY
343 /* Unlike A/R profile, M profile defines the reset LR value */
344 env
->regs
[14] = 0xffffffff;
346 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
347 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
349 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
350 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
351 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
353 /* Address zero is covered by ROM which hasn't yet been
354 * copied into physical memory.
356 initial_msp
= ldl_p(rom
);
357 initial_pc
= ldl_p(rom
+ 4);
359 /* Address zero not covered by a ROM blob, or the ROM blob
360 * is in non-modifiable memory and this is a second reset after
361 * it got copied into memory. In the latter case, rom_ptr
362 * will return a NULL pointer and we should use ldl_phys instead.
364 initial_msp
= ldl_phys(s
->as
, vecbase
);
365 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
368 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
369 env
->regs
[15] = initial_pc
& ~1;
370 env
->thumb
= initial_pc
& 1;
373 * For user mode we run non-secure and with access to the FPU.
374 * The FPU context is active (ie does not need further setup)
375 * and is owned by non-secure.
377 env
->v7m
.secure
= false;
378 env
->v7m
.nsacr
= 0xcff;
379 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
380 env
->v7m
.fpccr
[M_REG_S
] &=
381 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
382 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
386 /* M profile requires that reset clears the exclusive monitor;
387 * A profile does not, but clearing it makes more sense than having it
388 * set with an exclusive access on address zero.
390 arm_clear_exclusive(env
);
392 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
393 if (cpu
->pmsav7_dregion
> 0) {
394 if (arm_feature(env
, ARM_FEATURE_V8
)) {
395 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
396 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
397 * cpu
->pmsav7_dregion
);
398 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
399 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
400 * cpu
->pmsav7_dregion
);
401 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
402 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
403 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
404 * cpu
->pmsav7_dregion
);
405 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
406 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
407 * cpu
->pmsav7_dregion
);
409 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
410 memset(env
->pmsav7
.drbar
, 0,
411 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
412 memset(env
->pmsav7
.drsr
, 0,
413 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
414 memset(env
->pmsav7
.dracr
, 0,
415 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
418 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
419 env
->pmsav7
.rnr
[M_REG_S
] = 0;
420 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
421 env
->pmsav8
.mair0
[M_REG_S
] = 0;
422 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
423 env
->pmsav8
.mair1
[M_REG_S
] = 0;
426 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
427 if (cpu
->sau_sregion
> 0) {
428 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
429 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
432 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
433 * the Cortex-M33 does.
438 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
439 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
440 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
441 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
442 set_float_detect_tininess(float_tininess_before_rounding
,
443 &env
->vfp
.fp_status
);
444 set_float_detect_tininess(float_tininess_before_rounding
,
445 &env
->vfp
.standard_fp_status
);
446 set_float_detect_tininess(float_tininess_before_rounding
,
447 &env
->vfp
.fp_status_f16
);
448 set_float_detect_tininess(float_tininess_before_rounding
,
449 &env
->vfp
.standard_fp_status_f16
);
450 #ifndef CONFIG_USER_ONLY
452 kvm_arm_reset_vcpu(cpu
);
456 hw_breakpoint_update_all(cpu
);
457 hw_watchpoint_update_all(cpu
);
458 arm_rebuild_hflags(env
);
461 #ifndef CONFIG_USER_ONLY
463 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
464 unsigned int target_el
,
465 unsigned int cur_el
, bool secure
,
468 CPUARMState
*env
= cs
->env_ptr
;
469 bool pstate_unmasked
;
470 bool unmasked
= false;
473 * Don't take exceptions if they target a lower EL.
474 * This check should catch any exceptions that would not be taken
477 if (cur_el
> target_el
) {
483 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
487 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
491 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
492 /* VFIQs are only taken when hypervized. */
495 return !(env
->daif
& PSTATE_F
);
497 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
498 /* VIRQs are only taken when hypervized. */
501 return !(env
->daif
& PSTATE_I
);
503 g_assert_not_reached();
507 * Use the target EL, current execution state and SCR/HCR settings to
508 * determine whether the corresponding CPSR bit is used to mask the
511 if ((target_el
> cur_el
) && (target_el
!= 1)) {
512 /* Exceptions targeting a higher EL may not be maskable */
513 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
515 * 64-bit masking rules are simple: exceptions to EL3
516 * can't be masked, and exceptions to EL2 can only be
517 * masked from Secure state. The HCR and SCR settings
518 * don't affect the masking logic, only the interrupt routing.
520 if (target_el
== 3 || !secure
|| (env
->cp15
.scr_el3
& SCR_EEL2
)) {
525 * The old 32-bit-only environment has a more complicated
526 * masking setup. HCR and SCR bits not only affect interrupt
527 * routing but also change the behaviour of masking.
534 * If FIQs are routed to EL3 or EL2 then there are cases where
535 * we override the CPSR.F in determining if the exception is
536 * masked or not. If neither of these are set then we fall back
537 * to the CPSR.F setting otherwise we further assess the state
540 hcr
= hcr_el2
& HCR_FMO
;
541 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
544 * When EL3 is 32-bit, the SCR.FW bit controls whether the
545 * CPSR.F bit masks FIQ interrupts when taken in non-secure
546 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
547 * when non-secure but only when FIQs are only routed to EL3.
549 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
553 * When EL3 execution state is 32-bit, if HCR.IMO is set then
554 * we may override the CPSR.I masking when in non-secure state.
555 * The SCR.IRQ setting has already been taken into consideration
556 * when setting the target EL, so it does not have a further
559 hcr
= hcr_el2
& HCR_IMO
;
563 g_assert_not_reached();
566 if ((scr
|| hcr
) && !secure
) {
573 * The PSTATE bits only mask the interrupt if we have not overriden the
576 return unmasked
|| pstate_unmasked
;
579 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
581 CPUClass
*cc
= CPU_GET_CLASS(cs
);
582 CPUARMState
*env
= cs
->env_ptr
;
583 uint32_t cur_el
= arm_current_el(env
);
584 bool secure
= arm_is_secure(env
);
585 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
589 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
591 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
593 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
594 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
595 cur_el
, secure
, hcr_el2
)) {
599 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
601 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
602 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
603 cur_el
, secure
, hcr_el2
)) {
607 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
608 excp_idx
= EXCP_VIRQ
;
610 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
611 cur_el
, secure
, hcr_el2
)) {
615 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
616 excp_idx
= EXCP_VFIQ
;
618 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
619 cur_el
, secure
, hcr_el2
)) {
626 cs
->exception_index
= excp_idx
;
627 env
->exception
.target_el
= target_el
;
628 cc
->tcg_ops
->do_interrupt(cs
);
631 #endif /* !CONFIG_USER_ONLY */
633 void arm_cpu_update_virq(ARMCPU
*cpu
)
636 * Update the interrupt level for VIRQ, which is the logical OR of
637 * the HCR_EL2.VI bit and the input line level from the GIC.
639 CPUARMState
*env
= &cpu
->env
;
640 CPUState
*cs
= CPU(cpu
);
642 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
643 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
645 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
647 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
649 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
654 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
657 * Update the interrupt level for VFIQ, which is the logical OR of
658 * the HCR_EL2.VF bit and the input line level from the GIC.
660 CPUARMState
*env
= &cpu
->env
;
661 CPUState
*cs
= CPU(cpu
);
663 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
664 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
666 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
668 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
670 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
675 #ifndef CONFIG_USER_ONLY
676 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
678 ARMCPU
*cpu
= opaque
;
679 CPUARMState
*env
= &cpu
->env
;
680 CPUState
*cs
= CPU(cpu
);
681 static const int mask
[] = {
682 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
683 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
684 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
685 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
689 env
->irq_line_state
|= mask
[irq
];
691 env
->irq_line_state
&= ~mask
[irq
];
696 assert(arm_feature(env
, ARM_FEATURE_EL2
));
697 arm_cpu_update_virq(cpu
);
700 assert(arm_feature(env
, ARM_FEATURE_EL2
));
701 arm_cpu_update_vfiq(cpu
);
706 cpu_interrupt(cs
, mask
[irq
]);
708 cpu_reset_interrupt(cs
, mask
[irq
]);
712 g_assert_not_reached();
716 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
719 ARMCPU
*cpu
= opaque
;
720 CPUARMState
*env
= &cpu
->env
;
721 CPUState
*cs
= CPU(cpu
);
722 uint32_t linestate_bit
;
727 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
728 linestate_bit
= CPU_INTERRUPT_HARD
;
731 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
732 linestate_bit
= CPU_INTERRUPT_FIQ
;
735 g_assert_not_reached();
739 env
->irq_line_state
|= linestate_bit
;
741 env
->irq_line_state
&= ~linestate_bit
;
743 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
747 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
749 ARMCPU
*cpu
= ARM_CPU(cs
);
750 CPUARMState
*env
= &cpu
->env
;
752 cpu_synchronize_state(cs
);
753 return arm_cpu_data_is_big_endian(env
);
759 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
761 return print_insn_arm(pc
| 1, info
);
764 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
766 ARMCPU
*ac
= ARM_CPU(cpu
);
767 CPUARMState
*env
= &ac
->env
;
771 /* We might not be compiled with the A64 disassembler
772 * because it needs a C++ compiler. Leave print_insn
773 * unset in this case to use the caller default behaviour.
775 #if defined(CONFIG_ARM_A64_DIS)
776 info
->print_insn
= print_insn_arm_a64
;
778 info
->cap_arch
= CS_ARCH_ARM64
;
779 info
->cap_insn_unit
= 4;
780 info
->cap_insn_split
= 4;
784 info
->print_insn
= print_insn_thumb1
;
785 info
->cap_insn_unit
= 2;
786 info
->cap_insn_split
= 4;
787 cap_mode
= CS_MODE_THUMB
;
789 info
->print_insn
= print_insn_arm
;
790 info
->cap_insn_unit
= 4;
791 info
->cap_insn_split
= 4;
792 cap_mode
= CS_MODE_ARM
;
794 if (arm_feature(env
, ARM_FEATURE_V8
)) {
795 cap_mode
|= CS_MODE_V8
;
797 if (arm_feature(env
, ARM_FEATURE_M
)) {
798 cap_mode
|= CS_MODE_MCLASS
;
800 info
->cap_arch
= CS_ARCH_ARM
;
801 info
->cap_mode
= cap_mode
;
804 sctlr_b
= arm_sctlr_b(env
);
805 if (bswap_code(sctlr_b
)) {
806 #ifdef TARGET_WORDS_BIGENDIAN
807 info
->endian
= BFD_ENDIAN_LITTLE
;
809 info
->endian
= BFD_ENDIAN_BIG
;
812 info
->flags
&= ~INSN_ARM_BE32
;
813 #ifndef CONFIG_USER_ONLY
815 info
->flags
|= INSN_ARM_BE32
;
820 #ifdef TARGET_AARCH64
822 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
824 ARMCPU
*cpu
= ARM_CPU(cs
);
825 CPUARMState
*env
= &cpu
->env
;
826 uint32_t psr
= pstate_read(env
);
828 int el
= arm_current_el(env
);
829 const char *ns_status
;
831 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
832 for (i
= 0; i
< 32; i
++) {
834 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
836 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
837 (i
+ 2) % 3 ? " " : "\n");
841 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
842 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
846 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
848 psr
& PSTATE_N
? 'N' : '-',
849 psr
& PSTATE_Z
? 'Z' : '-',
850 psr
& PSTATE_C
? 'C' : '-',
851 psr
& PSTATE_V
? 'V' : '-',
854 psr
& PSTATE_SP
? 'h' : 't');
856 if (cpu_isar_feature(aa64_bti
, cpu
)) {
857 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
859 if (!(flags
& CPU_DUMP_FPU
)) {
860 qemu_fprintf(f
, "\n");
863 if (fp_exception_el(env
, el
) != 0) {
864 qemu_fprintf(f
, " FPU disabled\n");
867 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
868 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
870 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
871 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
873 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
875 if (i
== FFR_PRED_NUM
) {
876 qemu_fprintf(f
, "FFR=");
877 /* It's last, so end the line. */
880 qemu_fprintf(f
, "P%02d=", i
);
893 /* More than one quadword per predicate. */
898 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
900 if (j
* 4 + 4 <= zcr_len
+ 1) {
903 digits
= (zcr_len
% 4 + 1) * 4;
905 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
906 env
->vfp
.pregs
[i
].p
[j
],
907 j
? ":" : eol
? "\n" : " ");
911 for (i
= 0; i
< 32; i
++) {
913 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
914 i
, env
->vfp
.zregs
[i
].d
[1],
915 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
916 } else if (zcr_len
== 1) {
917 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
918 ":%016" PRIx64
":%016" PRIx64
"\n",
919 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
920 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
922 for (j
= zcr_len
; j
>= 0; j
--) {
923 bool odd
= (zcr_len
- j
) % 2 != 0;
925 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
928 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
930 qemu_fprintf(f
, " [%x]=", j
);
933 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
934 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
935 env
->vfp
.zregs
[i
].d
[j
* 2],
936 odd
|| j
== 0 ? "\n" : ":");
941 for (i
= 0; i
< 32; i
++) {
942 uint64_t *q
= aa64_vfp_qreg(env
, i
);
943 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
944 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
951 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
953 g_assert_not_reached();
958 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
960 ARMCPU
*cpu
= ARM_CPU(cs
);
961 CPUARMState
*env
= &cpu
->env
;
965 aarch64_cpu_dump_state(cs
, f
, flags
);
969 for (i
= 0; i
< 16; i
++) {
970 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
972 qemu_fprintf(f
, "\n");
974 qemu_fprintf(f
, " ");
978 if (arm_feature(env
, ARM_FEATURE_M
)) {
979 uint32_t xpsr
= xpsr_read(env
);
981 const char *ns_status
= "";
983 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
984 ns_status
= env
->v7m
.secure
? "S " : "NS ";
987 if (xpsr
& XPSR_EXCP
) {
990 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
991 mode
= "unpriv-thread";
993 mode
= "priv-thread";
997 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
999 xpsr
& XPSR_N
? 'N' : '-',
1000 xpsr
& XPSR_Z
? 'Z' : '-',
1001 xpsr
& XPSR_C
? 'C' : '-',
1002 xpsr
& XPSR_V
? 'V' : '-',
1003 xpsr
& XPSR_T
? 'T' : 'A',
1007 uint32_t psr
= cpsr_read(env
);
1008 const char *ns_status
= "";
1010 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1011 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1012 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1015 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1017 psr
& CPSR_N
? 'N' : '-',
1018 psr
& CPSR_Z
? 'Z' : '-',
1019 psr
& CPSR_C
? 'C' : '-',
1020 psr
& CPSR_V
? 'V' : '-',
1021 psr
& CPSR_T
? 'T' : 'A',
1023 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1026 if (flags
& CPU_DUMP_FPU
) {
1028 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1030 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1033 for (i
= 0; i
< numvfpregs
; i
++) {
1034 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1035 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1037 i
* 2 + 1, (uint32_t)(v
>> 32),
1040 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1041 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1042 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1047 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1049 uint32_t Aff1
= idx
/ clustersz
;
1050 uint32_t Aff0
= idx
% clustersz
;
1051 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1054 static void cpreg_hashtable_data_destroy(gpointer data
)
1057 * Destroy function for cpu->cp_regs hashtable data entries.
1058 * We must free the name string because it was g_strdup()ed in
1059 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1060 * from r->name because we know we definitely allocated it.
1062 ARMCPRegInfo
*r
= data
;
1064 g_free((void *)r
->name
);
1068 static void arm_cpu_initfn(Object
*obj
)
1070 ARMCPU
*cpu
= ARM_CPU(obj
);
1072 cpu_set_cpustate_pointers(cpu
);
1073 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1074 g_free
, cpreg_hashtable_data_destroy
);
1076 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1077 QLIST_INIT(&cpu
->el_change_hooks
);
1079 #ifdef CONFIG_USER_ONLY
1080 # ifdef TARGET_AARCH64
1082 * The linux kernel defaults to 512-bit vectors, when sve is supported.
1083 * See documentation for /proc/sys/abi/sve_default_vector_length, and
1084 * our corresponding sve-default-vector-length cpu property.
1086 cpu
->sve_default_vq
= 4;
1089 /* Our inbound IRQ and FIQ lines */
1090 if (kvm_enabled()) {
1091 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1092 * the same interface as non-KVM CPUs.
1094 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1096 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1099 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1100 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1102 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1103 "gicv3-maintenance-interrupt", 1);
1104 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1105 "pmu-interrupt", 1);
1108 /* DTB consumers generally don't in fact care what the 'compatible'
1109 * string is, so always provide some string and trust that a hypothetical
1110 * picky DTB consumer will also provide a helpful error message.
1112 cpu
->dtb_compatible
= "qemu,unknown";
1113 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1114 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1116 if (tcg_enabled() || hvf_enabled()) {
1117 cpu
->psci_version
= 2; /* TCG and HVF implement PSCI 0.2 */
1121 static Property arm_cpu_gt_cntfrq_property
=
1122 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1123 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1125 static Property arm_cpu_reset_cbar_property
=
1126 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1128 static Property arm_cpu_reset_hivecs_property
=
1129 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1131 static Property arm_cpu_rvbar_property
=
1132 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1134 #ifndef CONFIG_USER_ONLY
1135 static Property arm_cpu_has_el2_property
=
1136 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1138 static Property arm_cpu_has_el3_property
=
1139 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1142 static Property arm_cpu_cfgend_property
=
1143 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1145 static Property arm_cpu_has_vfp_property
=
1146 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1148 static Property arm_cpu_has_neon_property
=
1149 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1151 static Property arm_cpu_has_dsp_property
=
1152 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1154 static Property arm_cpu_has_mpu_property
=
1155 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1157 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1158 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1159 * the right value for that particular CPU type, and we don't want
1160 * to override that with an incorrect constant value.
1162 static Property arm_cpu_pmsav7_dregion_property
=
1163 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1165 qdev_prop_uint32
, uint32_t);
1167 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1169 ARMCPU
*cpu
= ARM_CPU(obj
);
1171 return cpu
->has_pmu
;
1174 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1176 ARMCPU
*cpu
= ARM_CPU(obj
);
1179 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1180 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1183 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1185 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1187 cpu
->has_pmu
= value
;
1190 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1193 * The exact approach to calculating guest ticks is:
1195 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1196 * NANOSECONDS_PER_SECOND);
1198 * We don't do that. Rather we intentionally use integer division
1199 * truncation below and in the caller for the conversion of host monotonic
1200 * time to guest ticks to provide the exact inverse for the semantics of
1201 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1202 * it loses precision when representing frequencies where
1203 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1204 * provide an exact inverse leads to scheduling timers with negative
1205 * periods, which in turn leads to sticky behaviour in the guest.
1207 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1208 * cannot become zero.
1210 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1211 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1214 void arm_cpu_post_init(Object
*obj
)
1216 ARMCPU
*cpu
= ARM_CPU(obj
);
1218 /* M profile implies PMSA. We have to do this here rather than
1219 * in realize with the other feature-implication checks because
1220 * we look at the PMSA bit to see if we should add some properties.
1222 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1223 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1226 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1227 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1228 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1231 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1232 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1235 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1236 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1239 #ifndef CONFIG_USER_ONLY
1240 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1241 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1242 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1244 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1246 object_property_add_link(obj
, "secure-memory",
1248 (Object
**)&cpu
->secure_memory
,
1249 qdev_prop_allow_set_link_before_realize
,
1250 OBJ_PROP_LINK_STRONG
);
1253 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1254 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1258 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1259 cpu
->has_pmu
= true;
1260 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1264 * Allow user to turn off VFP and Neon support, but only for TCG --
1265 * KVM does not currently allow us to lie to the guest about its
1266 * ID/feature registers, so the guest always sees what the host has.
1268 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1269 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1270 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1271 cpu
->has_vfp
= true;
1272 if (!kvm_enabled()) {
1273 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1277 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1278 cpu
->has_neon
= true;
1279 if (!kvm_enabled()) {
1280 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1284 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1285 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1286 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1289 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1290 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1291 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1292 qdev_property_add_static(DEVICE(obj
),
1293 &arm_cpu_pmsav7_dregion_property
);
1297 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1298 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1299 qdev_prop_allow_set_link_before_realize
,
1300 OBJ_PROP_LINK_STRONG
);
1302 * M profile: initial value of the Secure VTOR. We can't just use
1303 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1304 * the property to be set after realize.
1306 object_property_add_uint32_ptr(obj
, "init-svtor",
1308 OBJ_PROP_FLAG_READWRITE
);
1310 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1312 * Initial value of the NS VTOR (for cores without the Security
1313 * extension, this is the only VTOR)
1315 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1317 OBJ_PROP_FLAG_READWRITE
);
1320 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1322 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1323 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1326 if (kvm_enabled()) {
1327 kvm_arm_add_vcpu_properties(obj
);
1330 #ifndef CONFIG_USER_ONLY
1331 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1332 cpu_isar_feature(aa64_mte
, cpu
)) {
1333 object_property_add_link(obj
, "tag-memory",
1335 (Object
**)&cpu
->tag_memory
,
1336 qdev_prop_allow_set_link_before_realize
,
1337 OBJ_PROP_LINK_STRONG
);
1339 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1340 object_property_add_link(obj
, "secure-tag-memory",
1342 (Object
**)&cpu
->secure_tag_memory
,
1343 qdev_prop_allow_set_link_before_realize
,
1344 OBJ_PROP_LINK_STRONG
);
1350 static void arm_cpu_finalizefn(Object
*obj
)
1352 ARMCPU
*cpu
= ARM_CPU(obj
);
1353 ARMELChangeHook
*hook
, *next
;
1355 g_hash_table_destroy(cpu
->cp_regs
);
1357 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1358 QLIST_REMOVE(hook
, node
);
1361 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1362 QLIST_REMOVE(hook
, node
);
1365 #ifndef CONFIG_USER_ONLY
1366 if (cpu
->pmu_timer
) {
1367 timer_free(cpu
->pmu_timer
);
1372 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1374 Error
*local_err
= NULL
;
1376 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1377 arm_cpu_sve_finalize(cpu
, &local_err
);
1378 if (local_err
!= NULL
) {
1379 error_propagate(errp
, local_err
);
1384 * KVM does not support modifications to this feature.
1385 * We have not registered the cpu properties when KVM
1386 * is in use, so the user will not be able to set them.
1388 if (!kvm_enabled()) {
1389 arm_cpu_pauth_finalize(cpu
, &local_err
);
1390 if (local_err
!= NULL
) {
1391 error_propagate(errp
, local_err
);
1397 if (kvm_enabled()) {
1398 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1399 if (local_err
!= NULL
) {
1400 error_propagate(errp
, local_err
);
1406 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1408 CPUState
*cs
= CPU(dev
);
1409 ARMCPU
*cpu
= ARM_CPU(dev
);
1410 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1411 CPUARMState
*env
= &cpu
->env
;
1413 Error
*local_err
= NULL
;
1414 bool no_aa32
= false;
1416 /* If we needed to query the host kernel for the CPU features
1417 * then it's possible that might have failed in the initfn, but
1418 * this is the first point where we can report it.
1420 if (cpu
->host_cpu_probe_failed
) {
1421 if (!kvm_enabled() && !hvf_enabled()) {
1422 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1424 error_setg(errp
, "Failed to retrieve host CPU features");
1429 #ifndef CONFIG_USER_ONLY
1430 /* The NVIC and M-profile CPU are two halves of a single piece of
1431 * hardware; trying to use one without the other is a command line
1432 * error and will result in segfaults if not caught here.
1434 if (arm_feature(env
, ARM_FEATURE_M
)) {
1436 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1441 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1446 if (kvm_enabled()) {
1448 * Catch all the cases which might cause us to create more than one
1449 * address space for the CPU (otherwise we will assert() later in
1450 * cpu_address_space_init()).
1452 if (arm_feature(env
, ARM_FEATURE_M
)) {
1454 "Cannot enable KVM when using an M-profile guest CPU");
1459 "Cannot enable KVM when guest CPU has EL3 enabled");
1462 if (cpu
->tag_memory
) {
1464 "Cannot enable KVM when guest CPUs has MTE enabled");
1472 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1473 if (!cpu
->gt_cntfrq_hz
) {
1474 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1478 scale
= gt_cntfrq_period_ns(cpu
);
1480 scale
= GTIMER_SCALE
;
1483 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1484 arm_gt_ptimer_cb
, cpu
);
1485 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1486 arm_gt_vtimer_cb
, cpu
);
1487 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1488 arm_gt_htimer_cb
, cpu
);
1489 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1490 arm_gt_stimer_cb
, cpu
);
1491 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1492 arm_gt_hvtimer_cb
, cpu
);
1496 cpu_exec_realizefn(cs
, &local_err
);
1497 if (local_err
!= NULL
) {
1498 error_propagate(errp
, local_err
);
1502 arm_cpu_finalize_features(cpu
, &local_err
);
1503 if (local_err
!= NULL
) {
1504 error_propagate(errp
, local_err
);
1508 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1509 cpu
->has_vfp
!= cpu
->has_neon
) {
1511 * This is an architectural requirement for AArch64; AArch32 is
1512 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1515 "AArch64 CPUs must have both VFP and Neon or neither");
1519 if (!cpu
->has_vfp
) {
1523 t
= cpu
->isar
.id_aa64isar1
;
1524 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1525 cpu
->isar
.id_aa64isar1
= t
;
1527 t
= cpu
->isar
.id_aa64pfr0
;
1528 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1529 cpu
->isar
.id_aa64pfr0
= t
;
1531 u
= cpu
->isar
.id_isar6
;
1532 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1533 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1534 cpu
->isar
.id_isar6
= u
;
1536 u
= cpu
->isar
.mvfr0
;
1537 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1538 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1539 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1540 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1541 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1542 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1543 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1544 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1546 cpu
->isar
.mvfr0
= u
;
1548 u
= cpu
->isar
.mvfr1
;
1549 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1550 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1551 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1552 if (arm_feature(env
, ARM_FEATURE_M
)) {
1553 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1555 cpu
->isar
.mvfr1
= u
;
1557 u
= cpu
->isar
.mvfr2
;
1558 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1559 cpu
->isar
.mvfr2
= u
;
1562 if (!cpu
->has_neon
) {
1566 unset_feature(env
, ARM_FEATURE_NEON
);
1568 t
= cpu
->isar
.id_aa64isar0
;
1569 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1570 cpu
->isar
.id_aa64isar0
= t
;
1572 t
= cpu
->isar
.id_aa64isar1
;
1573 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1574 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
1575 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
1576 cpu
->isar
.id_aa64isar1
= t
;
1578 t
= cpu
->isar
.id_aa64pfr0
;
1579 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1580 cpu
->isar
.id_aa64pfr0
= t
;
1582 u
= cpu
->isar
.id_isar5
;
1583 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1584 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1585 cpu
->isar
.id_isar5
= u
;
1587 u
= cpu
->isar
.id_isar6
;
1588 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1589 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1590 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1591 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
1592 cpu
->isar
.id_isar6
= u
;
1594 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1595 u
= cpu
->isar
.mvfr1
;
1596 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1597 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1598 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1599 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1600 cpu
->isar
.mvfr1
= u
;
1602 u
= cpu
->isar
.mvfr2
;
1603 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1604 cpu
->isar
.mvfr2
= u
;
1608 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1612 t
= cpu
->isar
.id_aa64isar0
;
1613 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1614 cpu
->isar
.id_aa64isar0
= t
;
1616 t
= cpu
->isar
.id_aa64isar1
;
1617 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1618 cpu
->isar
.id_aa64isar1
= t
;
1620 u
= cpu
->isar
.mvfr0
;
1621 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1622 cpu
->isar
.mvfr0
= u
;
1624 /* Despite the name, this field covers both VFP and Neon */
1625 u
= cpu
->isar
.mvfr1
;
1626 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1627 cpu
->isar
.mvfr1
= u
;
1630 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1633 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1635 u
= cpu
->isar
.id_isar1
;
1636 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1637 cpu
->isar
.id_isar1
= u
;
1639 u
= cpu
->isar
.id_isar2
;
1640 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1641 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1642 cpu
->isar
.id_isar2
= u
;
1644 u
= cpu
->isar
.id_isar3
;
1645 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1646 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1647 cpu
->isar
.id_isar3
= u
;
1650 /* Some features automatically imply others: */
1651 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1652 if (arm_feature(env
, ARM_FEATURE_M
)) {
1653 set_feature(env
, ARM_FEATURE_V7
);
1655 set_feature(env
, ARM_FEATURE_V7VE
);
1660 * There exist AArch64 cpus without AArch32 support. When KVM
1661 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1662 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1663 * As a general principle, we also do not make ID register
1664 * consistency checks anywhere unless using TCG, because only
1665 * for TCG would a consistency-check failure be a QEMU bug.
1667 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1668 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1671 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1672 /* v7 Virtualization Extensions. In real hardware this implies
1673 * EL2 and also the presence of the Security Extensions.
1674 * For QEMU, for backwards-compatibility we implement some
1675 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1676 * include the various other features that V7VE implies.
1677 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1678 * Security Extensions is ARM_FEATURE_EL3.
1680 assert(!tcg_enabled() || no_aa32
||
1681 cpu_isar_feature(aa32_arm_div
, cpu
));
1682 set_feature(env
, ARM_FEATURE_LPAE
);
1683 set_feature(env
, ARM_FEATURE_V7
);
1685 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1686 set_feature(env
, ARM_FEATURE_VAPA
);
1687 set_feature(env
, ARM_FEATURE_THUMB2
);
1688 set_feature(env
, ARM_FEATURE_MPIDR
);
1689 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1690 set_feature(env
, ARM_FEATURE_V6K
);
1692 set_feature(env
, ARM_FEATURE_V6
);
1695 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1696 * non-EL3 configs. This is needed by some legacy boards.
1698 set_feature(env
, ARM_FEATURE_VBAR
);
1700 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1701 set_feature(env
, ARM_FEATURE_V6
);
1702 set_feature(env
, ARM_FEATURE_MVFR
);
1704 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1705 set_feature(env
, ARM_FEATURE_V5
);
1706 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1707 assert(!tcg_enabled() || no_aa32
||
1708 cpu_isar_feature(aa32_jazelle
, cpu
));
1709 set_feature(env
, ARM_FEATURE_AUXCR
);
1712 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1713 set_feature(env
, ARM_FEATURE_V4T
);
1715 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1716 set_feature(env
, ARM_FEATURE_V7MP
);
1718 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1719 set_feature(env
, ARM_FEATURE_CBAR
);
1721 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1722 !arm_feature(env
, ARM_FEATURE_M
)) {
1723 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1727 * We rely on no XScale CPU having VFP so we can use the same bits in the
1728 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1730 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1731 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1732 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1734 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1735 !arm_feature(env
, ARM_FEATURE_M
) &&
1736 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1737 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1742 /* For CPUs which might have tiny 1K pages, or which have an
1743 * MPU and might have small region sizes, stick with 1K pages.
1747 if (!set_preferred_target_page_bits(pagebits
)) {
1748 /* This can only ever happen for hotplugging a CPU, or if
1749 * the board code incorrectly creates a CPU which it has
1750 * promised via minimum_page_size that it will not.
1752 error_setg(errp
, "This CPU requires a smaller page size than the "
1757 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1758 * We don't support setting cluster ID ([16..23]) (known as Aff2
1759 * in later ARM ARM versions), or any of the higher affinity level fields,
1760 * so these bits always RAZ.
1762 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1763 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1764 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1767 if (cpu
->reset_hivecs
) {
1768 cpu
->reset_sctlr
|= (1 << 13);
1772 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1773 cpu
->reset_sctlr
|= SCTLR_EE
;
1775 cpu
->reset_sctlr
|= SCTLR_B
;
1779 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
1780 /* If the has_el3 CPU property is disabled then we need to disable the
1783 unset_feature(env
, ARM_FEATURE_EL3
);
1785 /* Disable the security extension feature bits in the processor feature
1786 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1788 cpu
->isar
.id_pfr1
&= ~0xf0;
1789 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1792 if (!cpu
->has_el2
) {
1793 unset_feature(env
, ARM_FEATURE_EL2
);
1796 if (!cpu
->has_pmu
) {
1797 unset_feature(env
, ARM_FEATURE_PMU
);
1799 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1802 if (!kvm_enabled()) {
1803 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1804 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1807 #ifndef CONFIG_USER_ONLY
1808 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1812 cpu
->isar
.id_aa64dfr0
=
1813 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1814 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1819 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1820 /* Disable the hypervisor feature bits in the processor feature
1821 * registers if we don't have EL2. These are id_pfr1[15:12] and
1822 * id_aa64pfr0_el1[11:8].
1824 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1825 cpu
->isar
.id_pfr1
&= ~0xf000;
1828 #ifndef CONFIG_USER_ONLY
1829 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1831 * Disable the MTE feature bits if we do not have tag-memory
1832 * provided by the machine.
1834 cpu
->isar
.id_aa64pfr1
=
1835 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1839 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1840 * to false or by setting pmsav7-dregion to 0.
1842 if (!cpu
->has_mpu
) {
1843 cpu
->pmsav7_dregion
= 0;
1845 if (cpu
->pmsav7_dregion
== 0) {
1846 cpu
->has_mpu
= false;
1849 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1850 arm_feature(env
, ARM_FEATURE_V7
)) {
1851 uint32_t nr
= cpu
->pmsav7_dregion
;
1854 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1859 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1861 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1862 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1863 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1864 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1865 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1868 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1869 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1870 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1875 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1876 uint32_t nr
= cpu
->sau_sregion
;
1879 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1884 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1885 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1889 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1890 set_feature(env
, ARM_FEATURE_VBAR
);
1893 register_cp_regs_for_features(cpu
);
1894 arm_cpu_register_gdb_regs_for_features(cpu
);
1896 init_cpreg_list(cpu
);
1898 #ifndef CONFIG_USER_ONLY
1899 MachineState
*ms
= MACHINE(qdev_get_machine());
1900 unsigned int smp_cpus
= ms
->smp
.cpus
;
1901 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1904 * We must set cs->num_ases to the final value before
1905 * the first call to cpu_address_space_init.
1907 if (cpu
->tag_memory
!= NULL
) {
1908 cs
->num_ases
= 3 + has_secure
;
1910 cs
->num_ases
= 1 + has_secure
;
1914 if (!cpu
->secure_memory
) {
1915 cpu
->secure_memory
= cs
->memory
;
1917 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1918 cpu
->secure_memory
);
1921 if (cpu
->tag_memory
!= NULL
) {
1922 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1925 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1926 cpu
->secure_tag_memory
);
1930 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1932 /* No core_count specified, default to smp_cpus. */
1933 if (cpu
->core_count
== -1) {
1934 cpu
->core_count
= smp_cpus
;
1938 if (tcg_enabled()) {
1939 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
1942 * We only support DCZ blocklen that fits on one page.
1944 * Architectually this is always true. However TARGET_PAGE_SIZE
1945 * is variable and, for compatibility with -machine virt-2.7,
1946 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1947 * But even then, while the largest architectural DCZ blocklen
1948 * is 2KiB, no cpu actually uses such a large blocklen.
1950 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
1953 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1954 * both nibbles of each byte storing tag data may be written at once.
1955 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1957 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1958 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
1965 acc
->parent_realize(dev
, errp
);
1968 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1973 const char *cpunamestr
;
1975 cpuname
= g_strsplit(cpu_model
, ",", 1);
1976 cpunamestr
= cpuname
[0];
1977 #ifdef CONFIG_USER_ONLY
1978 /* For backwards compatibility usermode emulation allows "-cpu any",
1979 * which has the same semantics as "-cpu max".
1981 if (!strcmp(cpunamestr
, "any")) {
1985 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1986 oc
= object_class_by_name(typename
);
1987 g_strfreev(cpuname
);
1989 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1990 object_class_is_abstract(oc
)) {
1996 static Property arm_cpu_properties
[] = {
1997 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1998 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
1999 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2000 mp_affinity
, ARM64_AFFINITY_INVALID
),
2001 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2002 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2003 DEFINE_PROP_END_OF_LIST()
2006 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2008 ARMCPU
*cpu
= ARM_CPU(cs
);
2009 CPUARMState
*env
= &cpu
->env
;
2011 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2012 return g_strdup("iwmmxt");
2014 return g_strdup("arm");
2017 #ifndef CONFIG_USER_ONLY
2018 #include "hw/core/sysemu-cpu-ops.h"
2020 static const struct SysemuCPUOps arm_sysemu_ops
= {
2021 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2022 .asidx_from_attrs
= arm_asidx_from_attrs
,
2023 .write_elf32_note
= arm_cpu_write_elf32_note
,
2024 .write_elf64_note
= arm_cpu_write_elf64_note
,
2025 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2026 .legacy_vmsd
= &vmstate_arm_cpu
,
2031 static const struct TCGCPUOps arm_tcg_ops
= {
2032 .initialize
= arm_translate_init
,
2033 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2034 .debug_excp_handler
= arm_debug_excp_handler
,
2036 #ifdef CONFIG_USER_ONLY
2037 .record_sigsegv
= arm_cpu_record_sigsegv
,
2038 .record_sigbus
= arm_cpu_record_sigbus
,
2040 .tlb_fill
= arm_cpu_tlb_fill
,
2041 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2042 .do_interrupt
= arm_cpu_do_interrupt
,
2043 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2044 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2045 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2046 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2047 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2048 #endif /* !CONFIG_USER_ONLY */
2050 #endif /* CONFIG_TCG */
2052 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2054 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2055 CPUClass
*cc
= CPU_CLASS(acc
);
2056 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2058 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2059 &acc
->parent_realize
);
2061 device_class_set_props(dc
, arm_cpu_properties
);
2062 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2064 cc
->class_by_name
= arm_cpu_class_by_name
;
2065 cc
->has_work
= arm_cpu_has_work
;
2066 cc
->dump_state
= arm_cpu_dump_state
;
2067 cc
->set_pc
= arm_cpu_set_pc
;
2068 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2069 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2070 #ifndef CONFIG_USER_ONLY
2071 cc
->sysemu_ops
= &arm_sysemu_ops
;
2073 cc
->gdb_num_core_regs
= 26;
2074 cc
->gdb_core_xml_file
= "arm-core.xml";
2075 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2076 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2077 cc
->gdb_stop_before_watchpoint
= true;
2078 cc
->disas_set_info
= arm_disas_set_info
;
2081 cc
->tcg_ops
= &arm_tcg_ops
;
2082 #endif /* CONFIG_TCG */
2085 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2086 static void arm_host_initfn(Object
*obj
)
2088 ARMCPU
*cpu
= ARM_CPU(obj
);
2091 kvm_arm_set_cpu_features_from_host(cpu
);
2092 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2093 aarch64_add_sve_properties(obj
);
2096 hvf_arm_set_cpu_features_from_host(cpu
);
2098 arm_cpu_post_init(obj
);
2101 static const TypeInfo host_arm_cpu_type_info
= {
2102 .name
= TYPE_ARM_HOST_CPU
,
2103 .parent
= TYPE_AARCH64_CPU
,
2104 .instance_init
= arm_host_initfn
,
2109 static void arm_cpu_instance_init(Object
*obj
)
2111 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2113 acc
->info
->initfn(obj
);
2114 arm_cpu_post_init(obj
);
2117 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2119 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2124 void arm_cpu_register(const ARMCPUInfo
*info
)
2126 TypeInfo type_info
= {
2127 .parent
= TYPE_ARM_CPU
,
2128 .instance_size
= sizeof(ARMCPU
),
2129 .instance_align
= __alignof__(ARMCPU
),
2130 .instance_init
= arm_cpu_instance_init
,
2131 .class_size
= sizeof(ARMCPUClass
),
2132 .class_init
= info
->class_init
?: cpu_register_class_init
,
2133 .class_data
= (void *)info
,
2136 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2137 type_register(&type_info
);
2138 g_free((void *)type_info
.name
);
2141 static const TypeInfo arm_cpu_type_info
= {
2142 .name
= TYPE_ARM_CPU
,
2144 .instance_size
= sizeof(ARMCPU
),
2145 .instance_align
= __alignof__(ARMCPU
),
2146 .instance_init
= arm_cpu_initfn
,
2147 .instance_finalize
= arm_cpu_finalizefn
,
2149 .class_size
= sizeof(ARMCPUClass
),
2150 .class_init
= arm_cpu_class_init
,
2153 static void arm_cpu_register_types(void)
2155 type_register_static(&arm_cpu_type_info
);
2157 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2158 type_register_static(&host_arm_cpu_type_info
);
2162 type_init(arm_cpu_register_types
)