2 * OpenRISC virtual CPU header.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef OPENRISC_CPU_H
21 #define OPENRISC_CPU_H
23 #define TARGET_LONG_BITS 32
25 #define CPUArchState struct CPUOpenRISCState
27 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
30 #include "qemu-common.h"
31 #include "exec/cpu-defs.h"
32 #include "fpu/softfloat.h"
35 #define TYPE_OPENRISC_CPU "or1k-cpu"
37 #define OPENRISC_CPU_CLASS(klass) \
38 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
39 #define OPENRISC_CPU(obj) \
40 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
41 #define OPENRISC_CPU_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
46 * @parent_realize: The parent class' realize handler.
47 * @parent_reset: The parent class' reset handler.
49 * A OpenRISC CPU model.
51 typedef struct OpenRISCCPUClass
{
53 CPUClass parent_class
;
56 DeviceRealize parent_realize
;
57 void (*parent_reset
)(CPUState
*cpu
);
60 #define NB_MMU_MODES 3
61 #define TARGET_INSN_START_EXTRA_WORDS 1
65 MMU_SUPERVISOR_IDX
= 1,
69 #define TARGET_PAGE_BITS 13
71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74 #define SET_FP_CAUSE(reg, v) do {\
75 (reg) = ((reg) & ~(0x3f << 12)) | \
78 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
79 #define UPDATE_FP_FLAGS(reg, v) do {\
80 (reg) |= ((v & 0x1f) << 2);\
83 /* Version Register */
84 #define SPR_VR 0xFFFF003F
89 /* Unit presece register */
102 UPR_CUP
= (255 << 24),
105 /* CPU configure register */
107 CPUCFGR_NSGF
= (15 << 0),
108 CPUCFGR_CGF
= (1 << 4),
109 CPUCFGR_OB32S
= (1 << 5),
110 CPUCFGR_OB64S
= (1 << 6),
111 CPUCFGR_OF32S
= (1 << 7),
112 CPUCFGR_OF64S
= (1 << 8),
113 CPUCFGR_OV64S
= (1 << 9),
114 /* CPUCFGR_ND = (1 << 10), */
115 /* CPUCFGR_AVRP = (1 << 11), */
116 CPUCFGR_EVBARP
= (1 << 12),
117 /* CPUCFGR_ISRP = (1 << 13), */
118 /* CPUCFGR_AECSRP = (1 << 14), */
121 /* DMMU configure register */
123 DMMUCFGR_NTW
= (3 << 0),
124 DMMUCFGR_NTS
= (7 << 2),
125 DMMUCFGR_NAE
= (7 << 5),
126 DMMUCFGR_CRI
= (1 << 8),
127 DMMUCFGR_PRI
= (1 << 9),
128 DMMUCFGR_TEIRI
= (1 << 10),
129 DMMUCFGR_HTR
= (1 << 11),
132 /* IMMU configure register */
134 IMMUCFGR_NTW
= (3 << 0),
135 IMMUCFGR_NTS
= (7 << 2),
136 IMMUCFGR_NAE
= (7 << 5),
137 IMMUCFGR_CRI
= (1 << 8),
138 IMMUCFGR_PRI
= (1 << 9),
139 IMMUCFGR_TEIRI
= (1 << 10),
140 IMMUCFGR_HTR
= (1 << 11),
143 /* Power management register */
152 /* Float point control status register */
156 FPCSR_OVF
= (1 << 3),
157 FPCSR_UNF
= (1 << 4),
158 FPCSR_SNF
= (1 << 5),
159 FPCSR_QNF
= (1 << 6),
161 FPCSR_IXF
= (1 << 8),
162 FPCSR_IVF
= (1 << 9),
163 FPCSR_INF
= (1 << 10),
164 FPCSR_DZF
= (1 << 11),
167 /* Exceptions indices */
186 /* Supervisor register */
204 SR_SUMRA
= (1 << 16),
208 /* Tick Timer Mode Register */
210 TTMR_TP
= (0xfffffff),
218 TIMER_NONE
= (0 << 30),
219 TIMER_INTR
= (1 << 30),
220 TIMER_SHOT
= (2 << 30),
221 TIMER_CONT
= (3 << 30),
228 DTLB_MASK
= (DTLB_SIZE
-1),
231 ITLB_MASK
= (ITLB_SIZE
-1),
245 /* check if tlb available */
253 typedef struct OpenRISCTLBEntry
{
258 #ifndef CONFIG_USER_ONLY
259 typedef struct CPUOpenRISCTLBContext
{
260 OpenRISCTLBEntry itlb
[ITLB_WAYS
][ITLB_SIZE
];
261 OpenRISCTLBEntry dtlb
[DTLB_WAYS
][DTLB_SIZE
];
263 int (*cpu_openrisc_map_address_code
)(struct OpenRISCCPU
*cpu
,
266 target_ulong address
, int rw
);
267 int (*cpu_openrisc_map_address_data
)(struct OpenRISCCPU
*cpu
,
270 target_ulong address
, int rw
);
271 } CPUOpenRISCTLBContext
;
274 typedef struct CPUOpenRISCState
{
275 target_ulong shadow_gpr
[16][32]; /* Shadow registers */
277 target_ulong pc
; /* Program counter */
278 target_ulong ppc
; /* Prev PC */
279 target_ulong jmp_pc
; /* Jump PC */
281 uint64_t mac
; /* Multiply registers MACHI:MACLO */
283 target_ulong epcr
; /* Exception PC register */
284 target_ulong eear
; /* Exception EA register */
286 target_ulong sr_f
; /* the SR_F bit, values 0, 1. */
287 target_ulong sr_cy
; /* the SR_CY bit, values 0, 1. */
288 target_long sr_ov
; /* the SR_OV bit (in the sign bit only) */
289 uint32_t sr
; /* Supervisor register, without SR_{F,CY,OV} */
290 uint32_t vr
; /* Version register */
291 uint32_t upr
; /* Unit presence register */
292 uint32_t dmmucfgr
; /* DMMU configure register */
293 uint32_t immucfgr
; /* IMMU configure register */
294 uint32_t esr
; /* Exception supervisor register */
295 uint32_t evbar
; /* Exception vector base address register */
296 uint32_t pmr
; /* Power Management Register */
297 uint32_t fpcsr
; /* Float register */
298 float_status fp_status
;
300 target_ulong lock_addr
;
301 target_ulong lock_value
;
303 uint32_t dflag
; /* In delay slot (boolean) */
305 /* Fields up to this point are cleared by a CPU reset */
306 struct {} end_reset_fields
;
310 /* Fields from here on are preserved across CPU reset. */
311 uint32_t cpucfgr
; /* CPU configure register */
313 #ifndef CONFIG_USER_ONLY
314 CPUOpenRISCTLBContext
* tlb
;
317 uint32_t ttmr
; /* Timer tick mode register */
320 uint32_t picmr
; /* Interrupt mask register */
321 uint32_t picsr
; /* Interrupt contrl register*/
323 void *irq
[32]; /* Interrupt irq input */
328 * @env: #CPUOpenRISCState
332 typedef struct OpenRISCCPU
{
337 CPUOpenRISCState env
;
341 static inline OpenRISCCPU
*openrisc_env_get_cpu(CPUOpenRISCState
*env
)
343 return container_of(env
, OpenRISCCPU
, env
);
346 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
348 #define ENV_OFFSET offsetof(OpenRISCCPU, env)
350 void cpu_openrisc_list(FILE *f
, fprintf_function cpu_fprintf
);
351 void openrisc_cpu_do_interrupt(CPUState
*cpu
);
352 bool openrisc_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
353 void openrisc_cpu_dump_state(CPUState
*cpu
, FILE *f
,
354 fprintf_function cpu_fprintf
, int flags
);
355 hwaddr
openrisc_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
356 int openrisc_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
357 int openrisc_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
358 void openrisc_translate_init(void);
359 int openrisc_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
,
360 int rw
, int mmu_idx
);
361 int cpu_openrisc_signal_handler(int host_signum
, void *pinfo
, void *puc
);
363 #define cpu_list cpu_openrisc_list
364 #define cpu_signal_handler cpu_openrisc_signal_handler
366 #ifndef CONFIG_USER_ONLY
367 extern const struct VMStateDescription vmstate_openrisc_cpu
;
369 /* hw/openrisc_pic.c */
370 void cpu_openrisc_pic_init(OpenRISCCPU
*cpu
);
372 /* hw/openrisc_timer.c */
373 void cpu_openrisc_clock_init(OpenRISCCPU
*cpu
);
374 uint32_t cpu_openrisc_count_get(OpenRISCCPU
*cpu
);
375 void cpu_openrisc_count_set(OpenRISCCPU
*cpu
, uint32_t val
);
376 void cpu_openrisc_count_update(OpenRISCCPU
*cpu
);
377 void cpu_openrisc_timer_update(OpenRISCCPU
*cpu
);
378 void cpu_openrisc_count_start(OpenRISCCPU
*cpu
);
379 void cpu_openrisc_count_stop(OpenRISCCPU
*cpu
);
381 void cpu_openrisc_mmu_init(OpenRISCCPU
*cpu
);
382 int cpu_openrisc_get_phys_nommu(OpenRISCCPU
*cpu
,
384 int *prot
, target_ulong address
, int rw
);
385 int cpu_openrisc_get_phys_code(OpenRISCCPU
*cpu
,
387 int *prot
, target_ulong address
, int rw
);
388 int cpu_openrisc_get_phys_data(OpenRISCCPU
*cpu
,
390 int *prot
, target_ulong address
, int rw
);
393 #define cpu_init(cpu_model) cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)
395 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
396 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
398 #include "exec/cpu-all.h"
400 #define TB_FLAGS_DFLAG 1
401 #define TB_FLAGS_R0_0 2
402 #define TB_FLAGS_OVE SR_OVE
404 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState
*env
, int i
)
406 return env
->shadow_gpr
[0][i
];
409 static inline void cpu_set_gpr(CPUOpenRISCState
*env
, int i
, uint32_t val
)
411 env
->shadow_gpr
[0][i
] = val
;
414 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env
,
416 target_ulong
*cs_base
, uint32_t *flags
)
421 | (cpu_get_gpr(env
, 0) == 0 ? TB_FLAGS_R0_0
: 0)
422 | (env
->sr
& SR_OVE
));
425 static inline int cpu_mmu_index(CPUOpenRISCState
*env
, bool ifetch
)
427 if (!(env
->sr
& SR_IME
)) {
428 return MMU_NOMMU_IDX
;
430 return (env
->sr
& SR_SM
) == 0 ? MMU_USER_IDX
: MMU_SUPERVISOR_IDX
;
433 static inline uint32_t cpu_get_sr(const CPUOpenRISCState
*env
)
438 + (env
->sr_ov
< 0) * SR_OV
);
441 static inline void cpu_set_sr(CPUOpenRISCState
*env
, uint32_t val
)
443 env
->sr_f
= (val
& SR_F
) != 0;
444 env
->sr_cy
= (val
& SR_CY
) != 0;
445 env
->sr_ov
= (val
& SR_OV
? -1 : 0);
446 env
->sr
= (val
& ~(SR_F
| SR_CY
| SR_OV
)) | SR_FO
;
449 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
451 #endif /* OPENRISC_CPU_H */