4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline int get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
111 switch (s
->mmu_idx
) {
112 case ARMMMUIdx_S12NSE1
:
113 useridx
= ARMMMUIdx_S12NSE0
;
115 case ARMMMUIdx_S1SE1
:
116 useridx
= ARMMMUIdx_S1SE0
;
119 g_assert_not_reached();
121 useridx
= s
->mmu_idx
;
124 return arm_to_core_mmu_idx(useridx
);
127 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
128 fprintf_function cpu_fprintf
, int flags
)
130 ARMCPU
*cpu
= ARM_CPU(cs
);
131 CPUARMState
*env
= &cpu
->env
;
132 uint32_t psr
= pstate_read(env
);
134 int el
= arm_current_el(env
);
135 const char *ns_status
;
137 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
138 env
->pc
, env
->xregs
[31]);
139 for (i
= 0; i
< 31; i
++) {
140 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
142 cpu_fprintf(f
, "\n");
148 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
149 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
154 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
156 psr
& PSTATE_N
? 'N' : '-',
157 psr
& PSTATE_Z
? 'Z' : '-',
158 psr
& PSTATE_C
? 'C' : '-',
159 psr
& PSTATE_V
? 'V' : '-',
162 psr
& PSTATE_SP
? 'h' : 't');
164 if (flags
& CPU_DUMP_FPU
) {
166 for (i
= 0; i
< numvfpregs
; i
+= 2) {
167 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
168 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
169 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
171 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
172 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
173 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
176 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
181 void gen_a64_set_pc_im(uint64_t val
)
183 tcg_gen_movi_i64(cpu_pc
, val
);
186 /* Load the PC from a generic TCG variable.
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
202 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
205 if (s
->current_el
<= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
210 if (s
->tbi0
&& s
->tbi1
) {
211 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
215 tcg_gen_shli_i64(tmp_reg
, src
, 8);
216 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
217 tcg_temp_free_i64(tmp_reg
);
218 } else if (!s
->tbi0
&& !s
->tbi1
) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc
, src
);
222 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
224 TCGv_i64 tcg_zero
= tcg_const_i64(0);
226 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval
, src
,
231 0x00FFFFFFFFFFFFFFull
);
232 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval
, src
,
237 0xFF00000000000000ull
);
238 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
241 tcg_temp_free_i64(tcg_zero
);
242 tcg_temp_free_i64(tcg_bit55
);
243 tcg_temp_free_i64(tcg_tmpval
);
245 } else { /* EL > 1 */
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc
, src
);
256 typedef struct DisasCompare64
{
261 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
265 arm_test_cc(&c32
, cc
);
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64
->cond
= c32
.cond
;
270 c64
->value
= tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
276 static void a64_free_cc(DisasCompare64
*c64
)
278 tcg_temp_free_i64(c64
->value
);
281 static void gen_exception_internal(int excp
)
283 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
285 assert(excp_is_internal(excp
));
286 gen_helper_exception_internal(cpu_env
, tcg_excp
);
287 tcg_temp_free_i32(tcg_excp
);
290 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
292 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
293 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
294 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
296 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
298 tcg_temp_free_i32(tcg_el
);
299 tcg_temp_free_i32(tcg_syn
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
305 gen_a64_set_pc_im(s
->pc
- offset
);
306 gen_exception_internal(excp
);
307 s
->base
.is_jmp
= DISAS_NORETURN
;
310 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
311 uint32_t syndrome
, uint32_t target_el
)
313 gen_a64_set_pc_im(s
->pc
- offset
);
314 gen_exception(excp
, syndrome
, target_el
);
315 s
->base
.is_jmp
= DISAS_NORETURN
;
318 static void gen_ss_advance(DisasContext
*s
)
320 /* If the singlestep state is Active-not-pending, advance to
325 gen_helper_clear_pstate_ss(cpu_env
);
329 static void gen_step_complete_exception(DisasContext
*s
)
331 /* We just completed step of an insn. Move from Active-not-pending
332 * to Active-pending, and then also take the swstep exception.
333 * This corresponds to making the (IMPDEF) choice to prioritize
334 * swstep exceptions over asynchronous exceptions taken to an exception
335 * level where debug is disabled. This choice has the advantage that
336 * we do not need to maintain internal state corresponding to the
337 * ISV/EX syndrome bits between completion of the step and generation
338 * of the exception, and our syndrome information is always correct.
341 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
342 default_exception_el(s
));
343 s
->base
.is_jmp
= DISAS_NORETURN
;
346 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
348 /* No direct tb linking with singlestep (either QEMU's or the ARM
349 * debug architecture kind) or deterministic io
351 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
352 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
356 #ifndef CONFIG_USER_ONLY
357 /* Only link tbs from inside the same guest page */
358 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
366 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
368 TranslationBlock
*tb
;
371 if (use_goto_tb(s
, n
, dest
)) {
373 gen_a64_set_pc_im(dest
);
374 tcg_gen_exit_tb((intptr_t)tb
+ n
);
375 s
->base
.is_jmp
= DISAS_NORETURN
;
377 gen_a64_set_pc_im(dest
);
379 gen_step_complete_exception(s
);
380 } else if (s
->base
.singlestep_enabled
) {
381 gen_exception_internal(EXCP_DEBUG
);
383 tcg_gen_lookup_and_goto_ptr();
384 s
->base
.is_jmp
= DISAS_NORETURN
;
389 static void unallocated_encoding(DisasContext
*s
)
391 /* Unallocated and reserved encodings are uncategorized */
392 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
393 default_exception_el(s
));
396 #define unsupported_encoding(s, insn) \
398 qemu_log_mask(LOG_UNIMP, \
399 "%s:%d: unsupported instruction encoding 0x%08x " \
400 "at pc=%016" PRIx64 "\n", \
401 __FILE__, __LINE__, insn, s->pc - 4); \
402 unallocated_encoding(s); \
405 static void init_tmp_a64_array(DisasContext
*s
)
407 #ifdef CONFIG_DEBUG_TCG
408 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
410 s
->tmp_a64_count
= 0;
413 static void free_tmp_a64(DisasContext
*s
)
416 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
417 tcg_temp_free_i64(s
->tmp_a64
[i
]);
419 init_tmp_a64_array(s
);
422 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
424 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
425 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
428 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
430 TCGv_i64 t
= new_tmp_a64(s
);
431 tcg_gen_movi_i64(t
, 0);
436 * Register access functions
438 * These functions are used for directly accessing a register in where
439 * changes to the final register value are likely to be made. If you
440 * need to use a register for temporary calculation (e.g. index type
441 * operations) use the read_* form.
443 * B1.2.1 Register mappings
445 * In instruction register encoding 31 can refer to ZR (zero register) or
446 * the SP (stack pointer) depending on context. In QEMU's case we map SP
447 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
448 * This is the point of the _sp forms.
450 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
453 return new_tmp_a64_zero(s
);
459 /* register access for when 31 == SP */
460 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
465 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
466 * representing the register contents. This TCGv is an auto-freed
467 * temporary so it need not be explicitly freed, and may be modified.
469 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
471 TCGv_i64 v
= new_tmp_a64(s
);
474 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
476 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
479 tcg_gen_movi_i64(v
, 0);
484 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
486 TCGv_i64 v
= new_tmp_a64(s
);
488 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
490 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
495 /* We should have at some point before trying to access an FP register
496 * done the necessary access check, so assert that
497 * (a) we did the check and
498 * (b) we didn't then just plough ahead anyway if it failed.
499 * Print the instruction pattern in the abort message so we can figure
500 * out what we need to fix if a user encounters this problem in the wild.
502 static inline void assert_fp_access_checked(DisasContext
*s
)
504 #ifdef CONFIG_DEBUG_TCG
505 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
506 fprintf(stderr
, "target-arm: FP access check missing for "
507 "instruction 0x%08x\n", s
->insn
);
513 /* Return the offset into CPUARMState of an element of specified
514 * size, 'element' places in from the least significant end of
515 * the FP/vector register Qn.
517 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
518 int element
, TCGMemOp size
)
521 #ifdef HOST_WORDS_BIGENDIAN
522 /* This is complicated slightly because vfp.regs[2n] is
523 * still the low half and vfp.regs[2n+1] the high half
524 * of the 128 bit vector, even on big endian systems.
525 * Calculate the offset assuming a fully bigendian 128 bits,
526 * then XOR to account for the order of the two 64 bit halves.
528 offs
+= (16 - ((element
+ 1) * (1 << size
)));
531 offs
+= element
* (1 << size
);
533 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
534 assert_fp_access_checked(s
);
538 /* Return the offset into CPUARMState of a slice (from
539 * the least significant end) of FP register Qn (ie
541 * (Note that this is not the same mapping as for A32; see cpu.h)
543 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
545 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
546 #ifdef HOST_WORDS_BIGENDIAN
547 offs
+= (8 - (1 << size
));
549 assert_fp_access_checked(s
);
553 /* Offset of the high half of the 128 bit vector Qn */
554 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
556 assert_fp_access_checked(s
);
557 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
560 /* Convenience accessors for reading and writing single and double
561 * FP registers. Writing clears the upper parts of the associated
562 * 128 bit vector register, as required by the architecture.
563 * Note that unlike the GP register accessors, the values returned
564 * by the read functions must be manually freed.
566 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
568 TCGv_i64 v
= tcg_temp_new_i64();
570 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
574 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
576 TCGv_i32 v
= tcg_temp_new_i32();
578 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
582 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
584 TCGv_i64 tcg_zero
= tcg_const_i64(0);
586 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
587 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
588 tcg_temp_free_i64(tcg_zero
);
591 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
593 TCGv_i64 tmp
= tcg_temp_new_i64();
595 tcg_gen_extu_i32_i64(tmp
, v
);
596 write_fp_dreg(s
, reg
, tmp
);
597 tcg_temp_free_i64(tmp
);
600 static TCGv_ptr
get_fpstatus_ptr(void)
602 TCGv_ptr statusptr
= tcg_temp_new_ptr();
605 /* In A64 all instructions (both FP and Neon) use the FPCR;
606 * there is no equivalent of the A32 Neon "standard FPSCR value"
607 * and all operations use vfp.fp_status.
609 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
610 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
614 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
615 * than the 32 bit equivalent.
617 static inline void gen_set_NZ64(TCGv_i64 result
)
619 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
620 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
623 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
624 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
627 gen_set_NZ64(result
);
629 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
630 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
632 tcg_gen_movi_i32(cpu_CF
, 0);
633 tcg_gen_movi_i32(cpu_VF
, 0);
636 /* dest = T0 + T1; compute C, N, V and Z flags */
637 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
640 TCGv_i64 result
, flag
, tmp
;
641 result
= tcg_temp_new_i64();
642 flag
= tcg_temp_new_i64();
643 tmp
= tcg_temp_new_i64();
645 tcg_gen_movi_i64(tmp
, 0);
646 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
648 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
650 gen_set_NZ64(result
);
652 tcg_gen_xor_i64(flag
, result
, t0
);
653 tcg_gen_xor_i64(tmp
, t0
, t1
);
654 tcg_gen_andc_i64(flag
, flag
, tmp
);
655 tcg_temp_free_i64(tmp
);
656 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
658 tcg_gen_mov_i64(dest
, result
);
659 tcg_temp_free_i64(result
);
660 tcg_temp_free_i64(flag
);
662 /* 32 bit arithmetic */
663 TCGv_i32 t0_32
= tcg_temp_new_i32();
664 TCGv_i32 t1_32
= tcg_temp_new_i32();
665 TCGv_i32 tmp
= tcg_temp_new_i32();
667 tcg_gen_movi_i32(tmp
, 0);
668 tcg_gen_extrl_i64_i32(t0_32
, t0
);
669 tcg_gen_extrl_i64_i32(t1_32
, t1
);
670 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
671 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
672 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
673 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
674 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
675 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
677 tcg_temp_free_i32(tmp
);
678 tcg_temp_free_i32(t0_32
);
679 tcg_temp_free_i32(t1_32
);
683 /* dest = T0 - T1; compute C, N, V and Z flags */
684 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
687 /* 64 bit arithmetic */
688 TCGv_i64 result
, flag
, tmp
;
690 result
= tcg_temp_new_i64();
691 flag
= tcg_temp_new_i64();
692 tcg_gen_sub_i64(result
, t0
, t1
);
694 gen_set_NZ64(result
);
696 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
697 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
699 tcg_gen_xor_i64(flag
, result
, t0
);
700 tmp
= tcg_temp_new_i64();
701 tcg_gen_xor_i64(tmp
, t0
, t1
);
702 tcg_gen_and_i64(flag
, flag
, tmp
);
703 tcg_temp_free_i64(tmp
);
704 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
705 tcg_gen_mov_i64(dest
, result
);
706 tcg_temp_free_i64(flag
);
707 tcg_temp_free_i64(result
);
709 /* 32 bit arithmetic */
710 TCGv_i32 t0_32
= tcg_temp_new_i32();
711 TCGv_i32 t1_32
= tcg_temp_new_i32();
714 tcg_gen_extrl_i64_i32(t0_32
, t0
);
715 tcg_gen_extrl_i64_i32(t1_32
, t1
);
716 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
717 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
718 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
719 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
720 tmp
= tcg_temp_new_i32();
721 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
722 tcg_temp_free_i32(t0_32
);
723 tcg_temp_free_i32(t1_32
);
724 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
725 tcg_temp_free_i32(tmp
);
726 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
730 /* dest = T0 + T1 + CF; do not compute flags. */
731 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
733 TCGv_i64 flag
= tcg_temp_new_i64();
734 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
735 tcg_gen_add_i64(dest
, t0
, t1
);
736 tcg_gen_add_i64(dest
, dest
, flag
);
737 tcg_temp_free_i64(flag
);
740 tcg_gen_ext32u_i64(dest
, dest
);
744 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
745 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
749 result
= tcg_temp_new_i64();
750 cf_64
= tcg_temp_new_i64();
751 vf_64
= tcg_temp_new_i64();
752 tmp
= tcg_const_i64(0);
754 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
755 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
756 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
757 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
758 gen_set_NZ64(result
);
760 tcg_gen_xor_i64(vf_64
, result
, t0
);
761 tcg_gen_xor_i64(tmp
, t0
, t1
);
762 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
763 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
765 tcg_gen_mov_i64(dest
, result
);
767 tcg_temp_free_i64(tmp
);
768 tcg_temp_free_i64(vf_64
);
769 tcg_temp_free_i64(cf_64
);
770 tcg_temp_free_i64(result
);
772 TCGv_i32 t0_32
, t1_32
, tmp
;
773 t0_32
= tcg_temp_new_i32();
774 t1_32
= tcg_temp_new_i32();
775 tmp
= tcg_const_i32(0);
777 tcg_gen_extrl_i64_i32(t0_32
, t0
);
778 tcg_gen_extrl_i64_i32(t1_32
, t1
);
779 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
780 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
782 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
783 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
784 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
785 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
786 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
788 tcg_temp_free_i32(tmp
);
789 tcg_temp_free_i32(t1_32
);
790 tcg_temp_free_i32(t0_32
);
795 * Load/Store generators
799 * Store from GPR register to memory.
801 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
802 TCGv_i64 tcg_addr
, int size
, int memidx
,
804 unsigned int iss_srt
,
805 bool iss_sf
, bool iss_ar
)
808 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
813 syn
= syn_data_abort_with_iss(0,
819 0, 0, 0, 0, 0, false);
820 disas_set_insn_syndrome(s
, syn
);
824 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
825 TCGv_i64 tcg_addr
, int size
,
827 unsigned int iss_srt
,
828 bool iss_sf
, bool iss_ar
)
830 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
831 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
835 * Load from memory to GPR register
837 static void do_gpr_ld_memidx(DisasContext
*s
,
838 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
839 int size
, bool is_signed
,
840 bool extend
, int memidx
,
841 bool iss_valid
, unsigned int iss_srt
,
842 bool iss_sf
, bool iss_ar
)
844 TCGMemOp memop
= s
->be_data
+ size
;
852 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
854 if (extend
&& is_signed
) {
856 tcg_gen_ext32u_i64(dest
, dest
);
862 syn
= syn_data_abort_with_iss(0,
868 0, 0, 0, 0, 0, false);
869 disas_set_insn_syndrome(s
, syn
);
873 static void do_gpr_ld(DisasContext
*s
,
874 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
875 int size
, bool is_signed
, bool extend
,
876 bool iss_valid
, unsigned int iss_srt
,
877 bool iss_sf
, bool iss_ar
)
879 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
881 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
885 * Store from FP register to memory
887 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
889 /* This writes the bottom N bits of a 128 bit wide vector to memory */
890 TCGv_i64 tmp
= tcg_temp_new_i64();
891 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
893 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
896 bool be
= s
->be_data
== MO_BE
;
897 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
899 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
900 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
902 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
903 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
905 tcg_temp_free_i64(tcg_hiaddr
);
908 tcg_temp_free_i64(tmp
);
912 * Load from memory to FP register
914 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
916 /* This always zero-extends and writes to a full 128 bit wide vector */
917 TCGv_i64 tmplo
= tcg_temp_new_i64();
921 TCGMemOp memop
= s
->be_data
+ size
;
922 tmphi
= tcg_const_i64(0);
923 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
925 bool be
= s
->be_data
== MO_BE
;
928 tmphi
= tcg_temp_new_i64();
929 tcg_hiaddr
= tcg_temp_new_i64();
931 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
932 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
934 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
936 tcg_temp_free_i64(tcg_hiaddr
);
939 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
940 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
942 tcg_temp_free_i64(tmplo
);
943 tcg_temp_free_i64(tmphi
);
947 * Vector load/store helpers.
949 * The principal difference between this and a FP load is that we don't
950 * zero extend as we are filling a partial chunk of the vector register.
951 * These functions don't support 128 bit loads/stores, which would be
952 * normal load/store operations.
954 * The _i32 versions are useful when operating on 32 bit quantities
955 * (eg for floating point single or using Neon helper functions).
958 /* Get value of an element within a vector register */
959 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
960 int element
, TCGMemOp memop
)
962 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
965 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
968 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
971 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
974 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
977 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
984 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
987 g_assert_not_reached();
991 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
992 int element
, TCGMemOp memop
)
994 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
997 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1000 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1003 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1010 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1013 g_assert_not_reached();
1017 /* Set value of an element within a vector register */
1018 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1019 int element
, TCGMemOp memop
)
1021 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1024 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1027 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1030 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1033 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1036 g_assert_not_reached();
1040 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1041 int destidx
, int element
, TCGMemOp memop
)
1043 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1046 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1049 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1052 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1055 g_assert_not_reached();
1059 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1060 * vector ops all need to do this).
1062 static void clear_vec_high(DisasContext
*s
, int rd
)
1064 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1066 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1067 tcg_temp_free_i64(tcg_zero
);
1070 /* Store from vector register to memory */
1071 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1072 TCGv_i64 tcg_addr
, int size
)
1074 TCGMemOp memop
= s
->be_data
+ size
;
1075 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1077 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1078 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1080 tcg_temp_free_i64(tcg_tmp
);
1083 /* Load from memory to vector register */
1084 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1085 TCGv_i64 tcg_addr
, int size
)
1087 TCGMemOp memop
= s
->be_data
+ size
;
1088 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1090 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1091 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1093 tcg_temp_free_i64(tcg_tmp
);
1096 /* Check that FP/Neon access is enabled. If it is, return
1097 * true. If not, emit code to generate an appropriate exception,
1098 * and return false; the caller should not emit any code for
1099 * the instruction. Note that this check must happen after all
1100 * unallocated-encoding checks (otherwise the syndrome information
1101 * for the resulting exception will be incorrect).
1103 static inline bool fp_access_check(DisasContext
*s
)
1105 assert(!s
->fp_access_checked
);
1106 s
->fp_access_checked
= true;
1108 if (!s
->fp_excp_el
) {
1112 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1118 * This utility function is for doing register extension with an
1119 * optional shift. You will likely want to pass a temporary for the
1120 * destination register. See DecodeRegExtend() in the ARM ARM.
1122 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1123 int option
, unsigned int shift
)
1125 int extsize
= extract32(option
, 0, 2);
1126 bool is_signed
= extract32(option
, 2, 1);
1131 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1134 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1137 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1140 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1146 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1149 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1152 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1155 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1161 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1165 static inline void gen_check_sp_alignment(DisasContext
*s
)
1167 /* The AArch64 architecture mandates that (if enabled via PSTATE
1168 * or SCTLR bits) there is a check that SP is 16-aligned on every
1169 * SP-relative load or store (with an exception generated if it is not).
1170 * In line with general QEMU practice regarding misaligned accesses,
1171 * we omit these checks for the sake of guest program performance.
1172 * This function is provided as a hook so we can more easily add these
1173 * checks in future (possibly as a "favour catching guest program bugs
1174 * over speed" user selectable option).
1179 * This provides a simple table based table lookup decoder. It is
1180 * intended to be used when the relevant bits for decode are too
1181 * awkwardly placed and switch/if based logic would be confusing and
1182 * deeply nested. Since it's a linear search through the table, tables
1183 * should be kept small.
1185 * It returns the first handler where insn & mask == pattern, or
1186 * NULL if there is no match.
1187 * The table is terminated by an empty mask (i.e. 0)
1189 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1192 const AArch64DecodeTable
*tptr
= table
;
1194 while (tptr
->mask
) {
1195 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1196 return tptr
->disas_fn
;
1204 * The instruction disassembly implemented here matches
1205 * the instruction encoding classifications in chapter C4
1206 * of the ARM Architecture Reference Manual (DDI0487B_a);
1207 * classification names and decode diagrams here should generally
1208 * match up with those in the manual.
1211 /* Unconditional branch (immediate)
1213 * +----+-----------+-------------------------------------+
1214 * | op | 0 0 1 0 1 | imm26 |
1215 * +----+-----------+-------------------------------------+
1217 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1219 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1221 if (insn
& (1U << 31)) {
1222 /* BL Branch with link */
1223 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1226 /* B Branch / BL Branch with link */
1227 gen_goto_tb(s
, 0, addr
);
1230 /* Compare and branch (immediate)
1231 * 31 30 25 24 23 5 4 0
1232 * +----+-------------+----+---------------------+--------+
1233 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1234 * +----+-------------+----+---------------------+--------+
1236 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1238 unsigned int sf
, op
, rt
;
1240 TCGLabel
*label_match
;
1243 sf
= extract32(insn
, 31, 1);
1244 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1245 rt
= extract32(insn
, 0, 5);
1246 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1248 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1249 label_match
= gen_new_label();
1251 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1252 tcg_cmp
, 0, label_match
);
1254 gen_goto_tb(s
, 0, s
->pc
);
1255 gen_set_label(label_match
);
1256 gen_goto_tb(s
, 1, addr
);
1259 /* Test and branch (immediate)
1260 * 31 30 25 24 23 19 18 5 4 0
1261 * +----+-------------+----+-------+-------------+------+
1262 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1263 * +----+-------------+----+-------+-------------+------+
1265 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1267 unsigned int bit_pos
, op
, rt
;
1269 TCGLabel
*label_match
;
1272 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1273 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1274 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1275 rt
= extract32(insn
, 0, 5);
1277 tcg_cmp
= tcg_temp_new_i64();
1278 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1279 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->pc
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1304 cond
= extract32(insn
, 0, 4);
1307 /* genuinely conditional branches */
1308 TCGLabel
*label_match
= gen_new_label();
1309 arm_gen_test_cc(cond
, label_match
);
1310 gen_goto_tb(s
, 0, s
->pc
);
1311 gen_set_label(label_match
);
1312 gen_goto_tb(s
, 1, addr
);
1314 /* 0xe and 0xf are both "always" conditions */
1315 gen_goto_tb(s
, 0, addr
);
1319 /* HINT instruction group, including various allocated HINTs */
1320 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1321 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1323 unsigned int selector
= crm
<< 3 | op2
;
1326 unallocated_encoding(s
);
1334 s
->base
.is_jmp
= DISAS_WFI
;
1336 /* When running in MTTCG we don't generate jumps to the yield and
1337 * WFE helpers as it won't affect the scheduling of other vCPUs.
1338 * If we wanted to more completely model WFE/SEV so we don't busy
1339 * spin unnecessarily we would need to do something more involved.
1342 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1343 s
->base
.is_jmp
= DISAS_YIELD
;
1347 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1348 s
->base
.is_jmp
= DISAS_WFE
;
1353 /* we treat all as NOP at least for now */
1356 /* default specified as NOP equivalent */
1361 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1363 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1366 /* CLREX, DSB, DMB, ISB */
1367 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1368 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1373 unallocated_encoding(s
);
1384 case 1: /* MBReqTypes_Reads */
1385 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1387 case 2: /* MBReqTypes_Writes */
1388 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1390 default: /* MBReqTypes_All */
1391 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1397 /* We need to break the TB after this insn to execute
1398 * a self-modified code correctly and also to take
1399 * any pending interrupts immediately.
1401 gen_goto_tb(s
, 0, s
->pc
);
1404 unallocated_encoding(s
);
1409 /* MSR (immediate) - move immediate to processor state field */
1410 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1411 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1413 int op
= op1
<< 3 | op2
;
1415 case 0x05: /* SPSel */
1416 if (s
->current_el
== 0) {
1417 unallocated_encoding(s
);
1421 case 0x1e: /* DAIFSet */
1422 case 0x1f: /* DAIFClear */
1424 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1425 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1426 gen_a64_set_pc_im(s
->pc
- 4);
1427 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1428 tcg_temp_free_i32(tcg_imm
);
1429 tcg_temp_free_i32(tcg_op
);
1430 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1431 gen_a64_set_pc_im(s
->pc
);
1432 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1436 unallocated_encoding(s
);
1441 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1443 TCGv_i32 tmp
= tcg_temp_new_i32();
1444 TCGv_i32 nzcv
= tcg_temp_new_i32();
1446 /* build bit 31, N */
1447 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1448 /* build bit 30, Z */
1449 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1450 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1451 /* build bit 29, C */
1452 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1453 /* build bit 28, V */
1454 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1455 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1456 /* generate result */
1457 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1459 tcg_temp_free_i32(nzcv
);
1460 tcg_temp_free_i32(tmp
);
1463 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1466 TCGv_i32 nzcv
= tcg_temp_new_i32();
1468 /* take NZCV from R[t] */
1469 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1472 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1474 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1475 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1477 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1478 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1480 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1481 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1482 tcg_temp_free_i32(nzcv
);
1485 /* MRS - move from system register
1486 * MSR (register) - move to system register
1489 * These are all essentially the same insn in 'read' and 'write'
1490 * versions, with varying op0 fields.
1492 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1493 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1494 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1496 const ARMCPRegInfo
*ri
;
1499 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1500 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1501 crn
, crm
, op0
, op1
, op2
));
1504 /* Unknown register; this might be a guest error or a QEMU
1505 * unimplemented feature.
1507 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1508 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1509 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1510 unallocated_encoding(s
);
1514 /* Check access permissions */
1515 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1516 unallocated_encoding(s
);
1521 /* Emit code to perform further access permissions checks at
1522 * runtime; this may result in an exception.
1525 TCGv_i32 tcg_syn
, tcg_isread
;
1528 gen_a64_set_pc_im(s
->pc
- 4);
1529 tmpptr
= tcg_const_ptr(ri
);
1530 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1531 tcg_syn
= tcg_const_i32(syndrome
);
1532 tcg_isread
= tcg_const_i32(isread
);
1533 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1534 tcg_temp_free_ptr(tmpptr
);
1535 tcg_temp_free_i32(tcg_syn
);
1536 tcg_temp_free_i32(tcg_isread
);
1539 /* Handle special cases first */
1540 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1544 tcg_rt
= cpu_reg(s
, rt
);
1546 gen_get_nzcv(tcg_rt
);
1548 gen_set_nzcv(tcg_rt
);
1551 case ARM_CP_CURRENTEL
:
1552 /* Reads as current EL value from pstate, which is
1553 * guaranteed to be constant by the tb flags.
1555 tcg_rt
= cpu_reg(s
, rt
);
1556 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1559 /* Writes clear the aligned block of memory which rt points into. */
1560 tcg_rt
= cpu_reg(s
, rt
);
1561 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1567 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1571 tcg_rt
= cpu_reg(s
, rt
);
1574 if (ri
->type
& ARM_CP_CONST
) {
1575 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1576 } else if (ri
->readfn
) {
1578 tmpptr
= tcg_const_ptr(ri
);
1579 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1580 tcg_temp_free_ptr(tmpptr
);
1582 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1585 if (ri
->type
& ARM_CP_CONST
) {
1586 /* If not forbidden by access permissions, treat as WI */
1588 } else if (ri
->writefn
) {
1590 tmpptr
= tcg_const_ptr(ri
);
1591 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1592 tcg_temp_free_ptr(tmpptr
);
1594 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1598 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1599 /* I/O operations must end the TB here (whether read or write) */
1601 s
->base
.is_jmp
= DISAS_UPDATE
;
1602 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1603 /* We default to ending the TB on a coprocessor register write,
1604 * but allow this to be suppressed by the register definition
1605 * (usually only necessary to work around guest bugs).
1607 s
->base
.is_jmp
= DISAS_UPDATE
;
1612 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1613 * +---------------------+---+-----+-----+-------+-------+-----+------+
1614 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1615 * +---------------------+---+-----+-----+-------+-------+-----+------+
1617 static void disas_system(DisasContext
*s
, uint32_t insn
)
1619 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1620 l
= extract32(insn
, 21, 1);
1621 op0
= extract32(insn
, 19, 2);
1622 op1
= extract32(insn
, 16, 3);
1623 crn
= extract32(insn
, 12, 4);
1624 crm
= extract32(insn
, 8, 4);
1625 op2
= extract32(insn
, 5, 3);
1626 rt
= extract32(insn
, 0, 5);
1629 if (l
|| rt
!= 31) {
1630 unallocated_encoding(s
);
1634 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1635 handle_hint(s
, insn
, op1
, op2
, crm
);
1637 case 3: /* CLREX, DSB, DMB, ISB */
1638 handle_sync(s
, insn
, op1
, op2
, crm
);
1640 case 4: /* MSR (immediate) */
1641 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1644 unallocated_encoding(s
);
1649 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1652 /* Exception generation
1654 * 31 24 23 21 20 5 4 2 1 0
1655 * +-----------------+-----+------------------------+-----+----+
1656 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1657 * +-----------------------+------------------------+----------+
1659 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1661 int opc
= extract32(insn
, 21, 3);
1662 int op2_ll
= extract32(insn
, 0, 5);
1663 int imm16
= extract32(insn
, 5, 16);
1668 /* For SVC, HVC and SMC we advance the single-step state
1669 * machine before taking the exception. This is architecturally
1670 * mandated, to ensure that single-stepping a system call
1671 * instruction works properly.
1676 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1677 default_exception_el(s
));
1680 if (s
->current_el
== 0) {
1681 unallocated_encoding(s
);
1684 /* The pre HVC helper handles cases when HVC gets trapped
1685 * as an undefined insn by runtime configuration.
1687 gen_a64_set_pc_im(s
->pc
- 4);
1688 gen_helper_pre_hvc(cpu_env
);
1690 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1693 if (s
->current_el
== 0) {
1694 unallocated_encoding(s
);
1697 gen_a64_set_pc_im(s
->pc
- 4);
1698 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1699 gen_helper_pre_smc(cpu_env
, tmp
);
1700 tcg_temp_free_i32(tmp
);
1702 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1705 unallocated_encoding(s
);
1711 unallocated_encoding(s
);
1715 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1716 default_exception_el(s
));
1720 unallocated_encoding(s
);
1723 /* HLT. This has two purposes.
1724 * Architecturally, it is an external halting debug instruction.
1725 * Since QEMU doesn't implement external debug, we treat this as
1726 * it is required for halting debug disabled: it will UNDEF.
1727 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1729 if (semihosting_enabled() && imm16
== 0xf000) {
1730 #ifndef CONFIG_USER_ONLY
1731 /* In system mode, don't allow userspace access to semihosting,
1732 * to provide some semblance of security (and for consistency
1733 * with our 32-bit semihosting).
1735 if (s
->current_el
== 0) {
1736 unsupported_encoding(s
, insn
);
1740 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1742 unsupported_encoding(s
, insn
);
1746 if (op2_ll
< 1 || op2_ll
> 3) {
1747 unallocated_encoding(s
);
1750 /* DCPS1, DCPS2, DCPS3 */
1751 unsupported_encoding(s
, insn
);
1754 unallocated_encoding(s
);
1759 /* Unconditional branch (register)
1760 * 31 25 24 21 20 16 15 10 9 5 4 0
1761 * +---------------+-------+-------+-------+------+-------+
1762 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1763 * +---------------+-------+-------+-------+------+-------+
1765 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1767 unsigned int opc
, op2
, op3
, rn
, op4
;
1769 opc
= extract32(insn
, 21, 4);
1770 op2
= extract32(insn
, 16, 5);
1771 op3
= extract32(insn
, 10, 6);
1772 rn
= extract32(insn
, 5, 5);
1773 op4
= extract32(insn
, 0, 5);
1775 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1776 unallocated_encoding(s
);
1784 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1785 /* BLR also needs to load return address */
1787 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1791 if (s
->current_el
== 0) {
1792 unallocated_encoding(s
);
1795 gen_helper_exception_return(cpu_env
);
1796 /* Must exit loop to check un-masked IRQs */
1797 s
->base
.is_jmp
= DISAS_EXIT
;
1801 unallocated_encoding(s
);
1803 unsupported_encoding(s
, insn
);
1807 unallocated_encoding(s
);
1811 s
->base
.is_jmp
= DISAS_JUMP
;
1814 /* Branches, exception generating and system instructions */
1815 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1817 switch (extract32(insn
, 25, 7)) {
1818 case 0x0a: case 0x0b:
1819 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1820 disas_uncond_b_imm(s
, insn
);
1822 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1823 disas_comp_b_imm(s
, insn
);
1825 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1826 disas_test_b_imm(s
, insn
);
1828 case 0x2a: /* Conditional branch (immediate) */
1829 disas_cond_b_imm(s
, insn
);
1831 case 0x6a: /* Exception generation / System */
1832 if (insn
& (1 << 24)) {
1833 disas_system(s
, insn
);
1838 case 0x6b: /* Unconditional branch (register) */
1839 disas_uncond_b_reg(s
, insn
);
1842 unallocated_encoding(s
);
1848 * Load/Store exclusive instructions are implemented by remembering
1849 * the value/address loaded, and seeing if these are the same
1850 * when the store is performed. This is not actually the architecturally
1851 * mandated semantics, but it works for typical guest code sequences
1852 * and avoids having to monitor regular stores.
1854 * The store exclusive uses the atomic cmpxchg primitives to avoid
1855 * races in multi-threaded linux-user and when MTTCG softmmu is
1858 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1859 TCGv_i64 addr
, int size
, bool is_pair
)
1861 int idx
= get_mem_index(s
);
1862 TCGMemOp memop
= s
->be_data
;
1864 g_assert(size
<= 3);
1866 g_assert(size
>= 2);
1868 /* The pair must be single-copy atomic for the doubleword. */
1869 memop
|= MO_64
| MO_ALIGN
;
1870 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1871 if (s
->be_data
== MO_LE
) {
1872 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
1873 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
1875 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
1876 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
1879 /* The pair must be single-copy atomic for *each* doubleword, not
1880 the entire quadword, however it must be quadword aligned. */
1882 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
1883 memop
| MO_ALIGN_16
);
1885 TCGv_i64 addr2
= tcg_temp_new_i64();
1886 tcg_gen_addi_i64(addr2
, addr
, 8);
1887 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
1888 tcg_temp_free_i64(addr2
);
1890 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1891 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
1894 memop
|= size
| MO_ALIGN
;
1895 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
1896 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
1898 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1901 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1902 TCGv_i64 addr
, int size
, int is_pair
)
1904 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1905 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1908 * [addr + datasize] = {Rt2};
1914 * env->exclusive_addr = -1;
1916 TCGLabel
*fail_label
= gen_new_label();
1917 TCGLabel
*done_label
= gen_new_label();
1920 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1922 tmp
= tcg_temp_new_i64();
1925 if (s
->be_data
== MO_LE
) {
1926 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1928 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
1930 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
1931 cpu_exclusive_val
, tmp
,
1933 MO_64
| MO_ALIGN
| s
->be_data
);
1934 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1935 } else if (s
->be_data
== MO_LE
) {
1936 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1937 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
1942 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
1943 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1946 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
1947 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
1952 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
1953 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1957 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
1958 cpu_reg(s
, rt
), get_mem_index(s
),
1959 size
| MO_ALIGN
| s
->be_data
);
1960 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1962 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1963 tcg_temp_free_i64(tmp
);
1964 tcg_gen_br(done_label
);
1966 gen_set_label(fail_label
);
1967 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1968 gen_set_label(done_label
);
1969 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1972 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1973 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1975 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1977 int opc0
= extract32(opc
, 0, 1);
1981 regsize
= opc0
? 32 : 64;
1983 regsize
= size
== 3 ? 64 : 32;
1985 return regsize
== 64;
1988 /* Load/store exclusive
1990 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1991 * +-----+-------------+----+---+----+------+----+-------+------+------+
1992 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1993 * +-----+-------------+----+---+----+------+----+-------+------+------+
1995 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1996 * L: 0 -> store, 1 -> load
1997 * o2: 0 -> exclusive, 1 -> not
1998 * o1: 0 -> single register, 1 -> register pair
1999 * o0: 1 -> load-acquire/store-release, 0 -> not
2001 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2003 int rt
= extract32(insn
, 0, 5);
2004 int rn
= extract32(insn
, 5, 5);
2005 int rt2
= extract32(insn
, 10, 5);
2006 int is_lasr
= extract32(insn
, 15, 1);
2007 int rs
= extract32(insn
, 16, 5);
2008 int is_pair
= extract32(insn
, 21, 1);
2009 int is_store
= !extract32(insn
, 22, 1);
2010 int is_excl
= !extract32(insn
, 23, 1);
2011 int size
= extract32(insn
, 30, 2);
2014 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
2015 (!is_excl
&& is_pair
) ||
2016 (is_pair
&& size
< 2)) {
2017 unallocated_encoding(s
);
2022 gen_check_sp_alignment(s
);
2024 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2026 /* Note that since TCG is single threaded load-acquire/store-release
2027 * semantics require no extra if (is_lasr) { ... } handling.
2033 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2035 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2039 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2041 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2044 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2045 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2047 /* Generate ISS for non-exclusive accesses including LASR. */
2050 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2052 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2053 true, rt
, iss_sf
, is_lasr
);
2055 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2056 true, rt
, iss_sf
, is_lasr
);
2058 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2065 * Load register (literal)
2067 * 31 30 29 27 26 25 24 23 5 4 0
2068 * +-----+-------+---+-----+-------------------+-------+
2069 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2070 * +-----+-------+---+-----+-------------------+-------+
2072 * V: 1 -> vector (simd/fp)
2073 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2074 * 10-> 32 bit signed, 11 -> prefetch
2075 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2077 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2079 int rt
= extract32(insn
, 0, 5);
2080 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2081 bool is_vector
= extract32(insn
, 26, 1);
2082 int opc
= extract32(insn
, 30, 2);
2083 bool is_signed
= false;
2085 TCGv_i64 tcg_rt
, tcg_addr
;
2089 unallocated_encoding(s
);
2093 if (!fp_access_check(s
)) {
2098 /* PRFM (literal) : prefetch */
2101 size
= 2 + extract32(opc
, 0, 1);
2102 is_signed
= extract32(opc
, 1, 1);
2105 tcg_rt
= cpu_reg(s
, rt
);
2107 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2109 do_fp_ld(s
, rt
, tcg_addr
, size
);
2111 /* Only unsigned 32bit loads target 32bit registers. */
2112 bool iss_sf
= opc
!= 0;
2114 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2115 true, rt
, iss_sf
, false);
2117 tcg_temp_free_i64(tcg_addr
);
2121 * LDNP (Load Pair - non-temporal hint)
2122 * LDP (Load Pair - non vector)
2123 * LDPSW (Load Pair Signed Word - non vector)
2124 * STNP (Store Pair - non-temporal hint)
2125 * STP (Store Pair - non vector)
2126 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2127 * LDP (Load Pair of SIMD&FP)
2128 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2129 * STP (Store Pair of SIMD&FP)
2131 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2132 * +-----+-------+---+---+-------+---+-----------------------------+
2133 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2134 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2136 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2138 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2139 * V: 0 -> GPR, 1 -> Vector
2140 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2141 * 10 -> signed offset, 11 -> pre-index
2142 * L: 0 -> Store 1 -> Load
2144 * Rt, Rt2 = GPR or SIMD registers to be stored
2145 * Rn = general purpose register containing address
2146 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2148 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2150 int rt
= extract32(insn
, 0, 5);
2151 int rn
= extract32(insn
, 5, 5);
2152 int rt2
= extract32(insn
, 10, 5);
2153 uint64_t offset
= sextract64(insn
, 15, 7);
2154 int index
= extract32(insn
, 23, 2);
2155 bool is_vector
= extract32(insn
, 26, 1);
2156 bool is_load
= extract32(insn
, 22, 1);
2157 int opc
= extract32(insn
, 30, 2);
2159 bool is_signed
= false;
2160 bool postindex
= false;
2163 TCGv_i64 tcg_addr
; /* calculated address */
2167 unallocated_encoding(s
);
2174 size
= 2 + extract32(opc
, 1, 1);
2175 is_signed
= extract32(opc
, 0, 1);
2176 if (!is_load
&& is_signed
) {
2177 unallocated_encoding(s
);
2183 case 1: /* post-index */
2188 /* signed offset with "non-temporal" hint. Since we don't emulate
2189 * caches we don't care about hints to the cache system about
2190 * data access patterns, and handle this identically to plain
2194 /* There is no non-temporal-hint version of LDPSW */
2195 unallocated_encoding(s
);
2200 case 2: /* signed offset, rn not updated */
2203 case 3: /* pre-index */
2209 if (is_vector
&& !fp_access_check(s
)) {
2216 gen_check_sp_alignment(s
);
2219 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2222 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2227 do_fp_ld(s
, rt
, tcg_addr
, size
);
2229 do_fp_st(s
, rt
, tcg_addr
, size
);
2231 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2233 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2235 do_fp_st(s
, rt2
, tcg_addr
, size
);
2238 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2239 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2242 TCGv_i64 tmp
= tcg_temp_new_i64();
2244 /* Do not modify tcg_rt before recognizing any exception
2245 * from the second load.
2247 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2248 false, 0, false, false);
2249 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2250 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2251 false, 0, false, false);
2253 tcg_gen_mov_i64(tcg_rt
, tmp
);
2254 tcg_temp_free_i64(tmp
);
2256 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2257 false, 0, false, false);
2258 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2259 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2260 false, 0, false, false);
2266 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2268 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2270 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2275 * Load/store (immediate post-indexed)
2276 * Load/store (immediate pre-indexed)
2277 * Load/store (unscaled immediate)
2279 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2280 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2281 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2282 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2284 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2286 * V = 0 -> non-vector
2287 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2288 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2290 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2296 int rn
= extract32(insn
, 5, 5);
2297 int imm9
= sextract32(insn
, 12, 9);
2298 int idx
= extract32(insn
, 10, 2);
2299 bool is_signed
= false;
2300 bool is_store
= false;
2301 bool is_extended
= false;
2302 bool is_unpriv
= (idx
== 2);
2303 bool iss_valid
= !is_vector
;
2310 size
|= (opc
& 2) << 1;
2311 if (size
> 4 || is_unpriv
) {
2312 unallocated_encoding(s
);
2315 is_store
= ((opc
& 1) == 0);
2316 if (!fp_access_check(s
)) {
2320 if (size
== 3 && opc
== 2) {
2321 /* PRFM - prefetch */
2323 unallocated_encoding(s
);
2328 if (opc
== 3 && size
> 1) {
2329 unallocated_encoding(s
);
2332 is_store
= (opc
== 0);
2333 is_signed
= extract32(opc
, 1, 1);
2334 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2352 g_assert_not_reached();
2356 gen_check_sp_alignment(s
);
2358 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2361 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2366 do_fp_st(s
, rt
, tcg_addr
, size
);
2368 do_fp_ld(s
, rt
, tcg_addr
, size
);
2371 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2372 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2373 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2376 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2377 iss_valid
, rt
, iss_sf
, false);
2379 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2380 is_signed
, is_extended
, memidx
,
2381 iss_valid
, rt
, iss_sf
, false);
2386 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2388 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2390 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2395 * Load/store (register offset)
2397 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2398 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2399 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2400 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2403 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2404 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2406 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2407 * opc<0>: 0 -> store, 1 -> load
2408 * V: 1 -> vector/simd
2409 * opt: extend encoding (see DecodeRegExtend)
2410 * S: if S=1 then scale (essentially index by sizeof(size))
2411 * Rt: register to transfer into/out of
2412 * Rn: address register or SP for base
2413 * Rm: offset register or ZR for offset
2415 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2421 int rn
= extract32(insn
, 5, 5);
2422 int shift
= extract32(insn
, 12, 1);
2423 int rm
= extract32(insn
, 16, 5);
2424 int opt
= extract32(insn
, 13, 3);
2425 bool is_signed
= false;
2426 bool is_store
= false;
2427 bool is_extended
= false;
2432 if (extract32(opt
, 1, 1) == 0) {
2433 unallocated_encoding(s
);
2438 size
|= (opc
& 2) << 1;
2440 unallocated_encoding(s
);
2443 is_store
= !extract32(opc
, 0, 1);
2444 if (!fp_access_check(s
)) {
2448 if (size
== 3 && opc
== 2) {
2449 /* PRFM - prefetch */
2452 if (opc
== 3 && size
> 1) {
2453 unallocated_encoding(s
);
2456 is_store
= (opc
== 0);
2457 is_signed
= extract32(opc
, 1, 1);
2458 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2462 gen_check_sp_alignment(s
);
2464 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2466 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2467 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2469 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2473 do_fp_st(s
, rt
, tcg_addr
, size
);
2475 do_fp_ld(s
, rt
, tcg_addr
, size
);
2478 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2479 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2481 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2482 true, rt
, iss_sf
, false);
2484 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2485 is_signed
, is_extended
,
2486 true, rt
, iss_sf
, false);
2492 * Load/store (unsigned immediate)
2494 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2495 * +----+-------+---+-----+-----+------------+-------+------+
2496 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2497 * +----+-------+---+-----+-----+------------+-------+------+
2500 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2501 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2503 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2504 * opc<0>: 0 -> store, 1 -> load
2505 * Rn: base address register (inc SP)
2506 * Rt: target register
2508 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2514 int rn
= extract32(insn
, 5, 5);
2515 unsigned int imm12
= extract32(insn
, 10, 12);
2516 unsigned int offset
;
2521 bool is_signed
= false;
2522 bool is_extended
= false;
2525 size
|= (opc
& 2) << 1;
2527 unallocated_encoding(s
);
2530 is_store
= !extract32(opc
, 0, 1);
2531 if (!fp_access_check(s
)) {
2535 if (size
== 3 && opc
== 2) {
2536 /* PRFM - prefetch */
2539 if (opc
== 3 && size
> 1) {
2540 unallocated_encoding(s
);
2543 is_store
= (opc
== 0);
2544 is_signed
= extract32(opc
, 1, 1);
2545 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2549 gen_check_sp_alignment(s
);
2551 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2552 offset
= imm12
<< size
;
2553 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2557 do_fp_st(s
, rt
, tcg_addr
, size
);
2559 do_fp_ld(s
, rt
, tcg_addr
, size
);
2562 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2563 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2565 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2566 true, rt
, iss_sf
, false);
2568 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2569 true, rt
, iss_sf
, false);
2574 /* Load/store register (all forms) */
2575 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2577 int rt
= extract32(insn
, 0, 5);
2578 int opc
= extract32(insn
, 22, 2);
2579 bool is_vector
= extract32(insn
, 26, 1);
2580 int size
= extract32(insn
, 30, 2);
2582 switch (extract32(insn
, 24, 2)) {
2584 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2585 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2587 /* Load/store register (unscaled immediate)
2588 * Load/store immediate pre/post-indexed
2589 * Load/store register unprivileged
2591 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2595 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2598 unallocated_encoding(s
);
2603 /* AdvSIMD load/store multiple structures
2605 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2606 * +---+---+---------------+---+-------------+--------+------+------+------+
2607 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2608 * +---+---+---------------+---+-------------+--------+------+------+------+
2610 * AdvSIMD load/store multiple structures (post-indexed)
2612 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2613 * +---+---+---------------+---+---+---------+--------+------+------+------+
2614 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2615 * +---+---+---------------+---+---+---------+--------+------+------+------+
2617 * Rt: first (or only) SIMD&FP register to be transferred
2618 * Rn: base address or SP
2619 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2621 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2623 int rt
= extract32(insn
, 0, 5);
2624 int rn
= extract32(insn
, 5, 5);
2625 int size
= extract32(insn
, 10, 2);
2626 int opcode
= extract32(insn
, 12, 4);
2627 bool is_store
= !extract32(insn
, 22, 1);
2628 bool is_postidx
= extract32(insn
, 23, 1);
2629 bool is_q
= extract32(insn
, 30, 1);
2630 TCGv_i64 tcg_addr
, tcg_rn
;
2632 int ebytes
= 1 << size
;
2633 int elements
= (is_q
? 128 : 64) / (8 << size
);
2634 int rpt
; /* num iterations */
2635 int selem
; /* structure elements */
2638 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2639 unallocated_encoding(s
);
2643 /* From the shared decode logic */
2674 unallocated_encoding(s
);
2678 if (size
== 3 && !is_q
&& selem
!= 1) {
2680 unallocated_encoding(s
);
2684 if (!fp_access_check(s
)) {
2689 gen_check_sp_alignment(s
);
2692 tcg_rn
= cpu_reg_sp(s
, rn
);
2693 tcg_addr
= tcg_temp_new_i64();
2694 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2696 for (r
= 0; r
< rpt
; r
++) {
2698 for (e
= 0; e
< elements
; e
++) {
2699 int tt
= (rt
+ r
) % 32;
2701 for (xs
= 0; xs
< selem
; xs
++) {
2703 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2705 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2707 /* For non-quad operations, setting a slice of the low
2708 * 64 bits of the register clears the high 64 bits (in
2709 * the ARM ARM pseudocode this is implicit in the fact
2710 * that 'rval' is a 64 bit wide variable). We optimize
2711 * by noticing that we only need to do this the first
2712 * time we touch a register.
2714 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2715 clear_vec_high(s
, tt
);
2718 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2725 int rm
= extract32(insn
, 16, 5);
2727 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2729 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2732 tcg_temp_free_i64(tcg_addr
);
2735 /* AdvSIMD load/store single structure
2737 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2738 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2739 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2740 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2742 * AdvSIMD load/store single structure (post-indexed)
2744 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2745 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2746 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2747 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2749 * Rt: first (or only) SIMD&FP register to be transferred
2750 * Rn: base address or SP
2751 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2752 * index = encoded in Q:S:size dependent on size
2754 * lane_size = encoded in R, opc
2755 * transfer width = encoded in opc, S, size
2757 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2759 int rt
= extract32(insn
, 0, 5);
2760 int rn
= extract32(insn
, 5, 5);
2761 int size
= extract32(insn
, 10, 2);
2762 int S
= extract32(insn
, 12, 1);
2763 int opc
= extract32(insn
, 13, 3);
2764 int R
= extract32(insn
, 21, 1);
2765 int is_load
= extract32(insn
, 22, 1);
2766 int is_postidx
= extract32(insn
, 23, 1);
2767 int is_q
= extract32(insn
, 30, 1);
2769 int scale
= extract32(opc
, 1, 2);
2770 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2771 bool replicate
= false;
2772 int index
= is_q
<< 3 | S
<< 2 | size
;
2774 TCGv_i64 tcg_addr
, tcg_rn
;
2778 if (!is_load
|| S
) {
2779 unallocated_encoding(s
);
2788 if (extract32(size
, 0, 1)) {
2789 unallocated_encoding(s
);
2795 if (extract32(size
, 1, 1)) {
2796 unallocated_encoding(s
);
2799 if (!extract32(size
, 0, 1)) {
2803 unallocated_encoding(s
);
2811 g_assert_not_reached();
2814 if (!fp_access_check(s
)) {
2818 ebytes
= 1 << scale
;
2821 gen_check_sp_alignment(s
);
2824 tcg_rn
= cpu_reg_sp(s
, rn
);
2825 tcg_addr
= tcg_temp_new_i64();
2826 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2828 for (xs
= 0; xs
< selem
; xs
++) {
2830 /* Load and replicate to all elements */
2832 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2834 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2835 get_mem_index(s
), s
->be_data
+ scale
);
2838 mulconst
= 0x0101010101010101ULL
;
2841 mulconst
= 0x0001000100010001ULL
;
2844 mulconst
= 0x0000000100000001ULL
;
2850 g_assert_not_reached();
2853 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2855 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2857 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2859 clear_vec_high(s
, rt
);
2861 tcg_temp_free_i64(tcg_tmp
);
2863 /* Load/store one element per register */
2865 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2867 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2870 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2875 int rm
= extract32(insn
, 16, 5);
2877 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2879 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2882 tcg_temp_free_i64(tcg_addr
);
2885 /* Loads and stores */
2886 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2888 switch (extract32(insn
, 24, 6)) {
2889 case 0x08: /* Load/store exclusive */
2890 disas_ldst_excl(s
, insn
);
2892 case 0x18: case 0x1c: /* Load register (literal) */
2893 disas_ld_lit(s
, insn
);
2895 case 0x28: case 0x29:
2896 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2897 disas_ldst_pair(s
, insn
);
2899 case 0x38: case 0x39:
2900 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2901 disas_ldst_reg(s
, insn
);
2903 case 0x0c: /* AdvSIMD load/store multiple structures */
2904 disas_ldst_multiple_struct(s
, insn
);
2906 case 0x0d: /* AdvSIMD load/store single structure */
2907 disas_ldst_single_struct(s
, insn
);
2910 unallocated_encoding(s
);
2915 /* PC-rel. addressing
2916 * 31 30 29 28 24 23 5 4 0
2917 * +----+-------+-----------+-------------------+------+
2918 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2919 * +----+-------+-----------+-------------------+------+
2921 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2923 unsigned int page
, rd
;
2927 page
= extract32(insn
, 31, 1);
2928 /* SignExtend(immhi:immlo) -> offset */
2929 offset
= sextract64(insn
, 5, 19);
2930 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2931 rd
= extract32(insn
, 0, 5);
2935 /* ADRP (page based) */
2940 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2944 * Add/subtract (immediate)
2946 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2947 * +--+--+--+-----------+-----+-------------+-----+-----+
2948 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2949 * +--+--+--+-----------+-----+-------------+-----+-----+
2951 * sf: 0 -> 32bit, 1 -> 64bit
2952 * op: 0 -> add , 1 -> sub
2954 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2956 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2958 int rd
= extract32(insn
, 0, 5);
2959 int rn
= extract32(insn
, 5, 5);
2960 uint64_t imm
= extract32(insn
, 10, 12);
2961 int shift
= extract32(insn
, 22, 2);
2962 bool setflags
= extract32(insn
, 29, 1);
2963 bool sub_op
= extract32(insn
, 30, 1);
2964 bool is_64bit
= extract32(insn
, 31, 1);
2966 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2967 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2968 TCGv_i64 tcg_result
;
2977 unallocated_encoding(s
);
2981 tcg_result
= tcg_temp_new_i64();
2984 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2986 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2989 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2991 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2993 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2995 tcg_temp_free_i64(tcg_imm
);
2999 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3001 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3004 tcg_temp_free_i64(tcg_result
);
3007 /* The input should be a value in the bottom e bits (with higher
3008 * bits zero); returns that value replicated into every element
3009 * of size e in a 64 bit integer.
3011 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3021 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3022 static inline uint64_t bitmask64(unsigned int length
)
3024 assert(length
> 0 && length
<= 64);
3025 return ~0ULL >> (64 - length
);
3028 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3029 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3030 * value (ie should cause a guest UNDEF exception), and true if they are
3031 * valid, in which case the decoded bit pattern is written to result.
3033 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3034 unsigned int imms
, unsigned int immr
)
3037 unsigned e
, levels
, s
, r
;
3040 assert(immn
< 2 && imms
< 64 && immr
< 64);
3042 /* The bit patterns we create here are 64 bit patterns which
3043 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3044 * 64 bits each. Each element contains the same value: a run
3045 * of between 1 and e-1 non-zero bits, rotated within the
3046 * element by between 0 and e-1 bits.
3048 * The element size and run length are encoded into immn (1 bit)
3049 * and imms (6 bits) as follows:
3050 * 64 bit elements: immn = 1, imms = <length of run - 1>
3051 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3052 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3053 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3054 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3055 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3056 * Notice that immn = 0, imms = 11111x is the only combination
3057 * not covered by one of the above options; this is reserved.
3058 * Further, <length of run - 1> all-ones is a reserved pattern.
3060 * In all cases the rotation is by immr % e (and immr is 6 bits).
3063 /* First determine the element size */
3064 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3066 /* This is the immn == 0, imms == 0x11111x case */
3076 /* <length of run - 1> mustn't be all-ones. */
3080 /* Create the value of one element: s+1 set bits rotated
3081 * by r within the element (which is e bits wide)...
3083 mask
= bitmask64(s
+ 1);
3085 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3086 mask
&= bitmask64(e
);
3088 /* ...then replicate the element over the whole 64 bit value */
3089 mask
= bitfield_replicate(mask
, e
);
3094 /* Logical (immediate)
3095 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3096 * +----+-----+-------------+---+------+------+------+------+
3097 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3098 * +----+-----+-------------+---+------+------+------+------+
3100 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3102 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3103 TCGv_i64 tcg_rd
, tcg_rn
;
3105 bool is_and
= false;
3107 sf
= extract32(insn
, 31, 1);
3108 opc
= extract32(insn
, 29, 2);
3109 is_n
= extract32(insn
, 22, 1);
3110 immr
= extract32(insn
, 16, 6);
3111 imms
= extract32(insn
, 10, 6);
3112 rn
= extract32(insn
, 5, 5);
3113 rd
= extract32(insn
, 0, 5);
3116 unallocated_encoding(s
);
3120 if (opc
== 0x3) { /* ANDS */
3121 tcg_rd
= cpu_reg(s
, rd
);
3123 tcg_rd
= cpu_reg_sp(s
, rd
);
3125 tcg_rn
= cpu_reg(s
, rn
);
3127 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3128 /* some immediate field values are reserved */
3129 unallocated_encoding(s
);
3134 wmask
&= 0xffffffff;
3138 case 0x3: /* ANDS */
3140 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3144 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3147 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3150 assert(FALSE
); /* must handle all above */
3154 if (!sf
&& !is_and
) {
3155 /* zero extend final result; we know we can skip this for AND
3156 * since the immediate had the high 32 bits clear.
3158 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3161 if (opc
== 3) { /* ANDS */
3162 gen_logic_CC(sf
, tcg_rd
);
3167 * Move wide (immediate)
3169 * 31 30 29 28 23 22 21 20 5 4 0
3170 * +--+-----+-------------+-----+----------------+------+
3171 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3172 * +--+-----+-------------+-----+----------------+------+
3174 * sf: 0 -> 32 bit, 1 -> 64 bit
3175 * opc: 00 -> N, 10 -> Z, 11 -> K
3176 * hw: shift/16 (0,16, and sf only 32, 48)
3178 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3180 int rd
= extract32(insn
, 0, 5);
3181 uint64_t imm
= extract32(insn
, 5, 16);
3182 int sf
= extract32(insn
, 31, 1);
3183 int opc
= extract32(insn
, 29, 2);
3184 int pos
= extract32(insn
, 21, 2) << 4;
3185 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3188 if (!sf
&& (pos
>= 32)) {
3189 unallocated_encoding(s
);
3203 tcg_gen_movi_i64(tcg_rd
, imm
);
3206 tcg_imm
= tcg_const_i64(imm
);
3207 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3208 tcg_temp_free_i64(tcg_imm
);
3210 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3214 unallocated_encoding(s
);
3220 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3221 * +----+-----+-------------+---+------+------+------+------+
3222 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3223 * +----+-----+-------------+---+------+------+------+------+
3225 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3227 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3228 TCGv_i64 tcg_rd
, tcg_tmp
;
3230 sf
= extract32(insn
, 31, 1);
3231 opc
= extract32(insn
, 29, 2);
3232 n
= extract32(insn
, 22, 1);
3233 ri
= extract32(insn
, 16, 6);
3234 si
= extract32(insn
, 10, 6);
3235 rn
= extract32(insn
, 5, 5);
3236 rd
= extract32(insn
, 0, 5);
3237 bitsize
= sf
? 64 : 32;
3239 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3240 unallocated_encoding(s
);
3244 tcg_rd
= cpu_reg(s
, rd
);
3246 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3247 to be smaller than bitsize, we'll never reference data outside the
3248 low 32-bits anyway. */
3249 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3251 /* Recognize simple(r) extractions. */
3253 /* Wd<s-r:0> = Wn<s:r> */
3254 len
= (si
- ri
) + 1;
3255 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3256 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3258 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3259 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3262 /* opc == 1, BXFIL fall through to deposit */
3263 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3266 /* Handle the ri > si case with a deposit
3267 * Wd<32+s-r,32-r> = Wn<s:0>
3270 pos
= (bitsize
- ri
) & (bitsize
- 1);
3273 if (opc
== 0 && len
< ri
) {
3274 /* SBFM: sign extend the destination field from len to fill
3275 the balance of the word. Let the deposit below insert all
3276 of those sign bits. */
3277 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3281 if (opc
== 1) { /* BFM, BXFIL */
3282 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3284 /* SBFM or UBFM: We start with zero, and we haven't modified
3285 any bits outside bitsize, therefore the zero-extension
3286 below is unneeded. */
3287 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3292 if (!sf
) { /* zero extend final result */
3293 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3298 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3299 * +----+------+-------------+---+----+------+--------+------+------+
3300 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3301 * +----+------+-------------+---+----+------+--------+------+------+
3303 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3305 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3307 sf
= extract32(insn
, 31, 1);
3308 n
= extract32(insn
, 22, 1);
3309 rm
= extract32(insn
, 16, 5);
3310 imm
= extract32(insn
, 10, 6);
3311 rn
= extract32(insn
, 5, 5);
3312 rd
= extract32(insn
, 0, 5);
3313 op21
= extract32(insn
, 29, 2);
3314 op0
= extract32(insn
, 21, 1);
3315 bitsize
= sf
? 64 : 32;
3317 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3318 unallocated_encoding(s
);
3320 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3322 tcg_rd
= cpu_reg(s
, rd
);
3324 if (unlikely(imm
== 0)) {
3325 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3326 * so an extract from bit 0 is a special case.
3329 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3331 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3333 } else if (rm
== rn
) { /* ROR */
3334 tcg_rm
= cpu_reg(s
, rm
);
3336 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3338 TCGv_i32 tmp
= tcg_temp_new_i32();
3339 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3340 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3341 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3342 tcg_temp_free_i32(tmp
);
3345 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3346 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3347 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3348 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3349 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3351 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3357 /* Data processing - immediate */
3358 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3360 switch (extract32(insn
, 23, 6)) {
3361 case 0x20: case 0x21: /* PC-rel. addressing */
3362 disas_pc_rel_adr(s
, insn
);
3364 case 0x22: case 0x23: /* Add/subtract (immediate) */
3365 disas_add_sub_imm(s
, insn
);
3367 case 0x24: /* Logical (immediate) */
3368 disas_logic_imm(s
, insn
);
3370 case 0x25: /* Move wide (immediate) */
3371 disas_movw_imm(s
, insn
);
3373 case 0x26: /* Bitfield */
3374 disas_bitfield(s
, insn
);
3376 case 0x27: /* Extract */
3377 disas_extract(s
, insn
);
3380 unallocated_encoding(s
);
3385 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3386 * Note that it is the caller's responsibility to ensure that the
3387 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3388 * mandated semantics for out of range shifts.
3390 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3391 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3393 switch (shift_type
) {
3394 case A64_SHIFT_TYPE_LSL
:
3395 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3397 case A64_SHIFT_TYPE_LSR
:
3398 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3400 case A64_SHIFT_TYPE_ASR
:
3402 tcg_gen_ext32s_i64(dst
, src
);
3404 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3406 case A64_SHIFT_TYPE_ROR
:
3408 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3411 t0
= tcg_temp_new_i32();
3412 t1
= tcg_temp_new_i32();
3413 tcg_gen_extrl_i64_i32(t0
, src
);
3414 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3415 tcg_gen_rotr_i32(t0
, t0
, t1
);
3416 tcg_gen_extu_i32_i64(dst
, t0
);
3417 tcg_temp_free_i32(t0
);
3418 tcg_temp_free_i32(t1
);
3422 assert(FALSE
); /* all shift types should be handled */
3426 if (!sf
) { /* zero extend final result */
3427 tcg_gen_ext32u_i64(dst
, dst
);
3431 /* Shift a TCGv src by immediate, put result in dst.
3432 * The shift amount must be in range (this should always be true as the
3433 * relevant instructions will UNDEF on bad shift immediates).
3435 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3436 enum a64_shift_type shift_type
, unsigned int shift_i
)
3438 assert(shift_i
< (sf
? 64 : 32));
3441 tcg_gen_mov_i64(dst
, src
);
3443 TCGv_i64 shift_const
;
3445 shift_const
= tcg_const_i64(shift_i
);
3446 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3447 tcg_temp_free_i64(shift_const
);
3451 /* Logical (shifted register)
3452 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3453 * +----+-----+-----------+-------+---+------+--------+------+------+
3454 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3455 * +----+-----+-----------+-------+---+------+--------+------+------+
3457 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3459 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3460 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3462 sf
= extract32(insn
, 31, 1);
3463 opc
= extract32(insn
, 29, 2);
3464 shift_type
= extract32(insn
, 22, 2);
3465 invert
= extract32(insn
, 21, 1);
3466 rm
= extract32(insn
, 16, 5);
3467 shift_amount
= extract32(insn
, 10, 6);
3468 rn
= extract32(insn
, 5, 5);
3469 rd
= extract32(insn
, 0, 5);
3471 if (!sf
&& (shift_amount
& (1 << 5))) {
3472 unallocated_encoding(s
);
3476 tcg_rd
= cpu_reg(s
, rd
);
3478 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3479 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3480 * register-register MOV and MVN, so it is worth special casing.
3482 tcg_rm
= cpu_reg(s
, rm
);
3484 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3486 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3490 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3492 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3498 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3501 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3504 tcg_rn
= cpu_reg(s
, rn
);
3506 switch (opc
| (invert
<< 2)) {
3509 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3512 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3515 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3519 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3522 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3525 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3533 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3537 gen_logic_CC(sf
, tcg_rd
);
3542 * Add/subtract (extended register)
3544 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3545 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3546 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3547 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3549 * sf: 0 -> 32bit, 1 -> 64bit
3550 * op: 0 -> add , 1 -> sub
3553 * option: extension type (see DecodeRegExtend)
3554 * imm3: optional shift to Rm
3556 * Rd = Rn + LSL(extend(Rm), amount)
3558 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3560 int rd
= extract32(insn
, 0, 5);
3561 int rn
= extract32(insn
, 5, 5);
3562 int imm3
= extract32(insn
, 10, 3);
3563 int option
= extract32(insn
, 13, 3);
3564 int rm
= extract32(insn
, 16, 5);
3565 bool setflags
= extract32(insn
, 29, 1);
3566 bool sub_op
= extract32(insn
, 30, 1);
3567 bool sf
= extract32(insn
, 31, 1);
3569 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3571 TCGv_i64 tcg_result
;
3574 unallocated_encoding(s
);
3578 /* non-flag setting ops may use SP */
3580 tcg_rd
= cpu_reg_sp(s
, rd
);
3582 tcg_rd
= cpu_reg(s
, rd
);
3584 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3586 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3587 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3589 tcg_result
= tcg_temp_new_i64();
3593 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3595 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3599 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3601 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3606 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3608 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3611 tcg_temp_free_i64(tcg_result
);
3615 * Add/subtract (shifted register)
3617 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3618 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3619 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3620 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3622 * sf: 0 -> 32bit, 1 -> 64bit
3623 * op: 0 -> add , 1 -> sub
3625 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3626 * imm6: Shift amount to apply to Rm before the add/sub
3628 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3630 int rd
= extract32(insn
, 0, 5);
3631 int rn
= extract32(insn
, 5, 5);
3632 int imm6
= extract32(insn
, 10, 6);
3633 int rm
= extract32(insn
, 16, 5);
3634 int shift_type
= extract32(insn
, 22, 2);
3635 bool setflags
= extract32(insn
, 29, 1);
3636 bool sub_op
= extract32(insn
, 30, 1);
3637 bool sf
= extract32(insn
, 31, 1);
3639 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3640 TCGv_i64 tcg_rn
, tcg_rm
;
3641 TCGv_i64 tcg_result
;
3643 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3644 unallocated_encoding(s
);
3648 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3649 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3651 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3653 tcg_result
= tcg_temp_new_i64();
3657 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3659 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3663 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3665 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3670 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3672 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3675 tcg_temp_free_i64(tcg_result
);
3678 /* Data-processing (3 source)
3680 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3681 * +--+------+-----------+------+------+----+------+------+------+
3682 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3683 * +--+------+-----------+------+------+----+------+------+------+
3685 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3687 int rd
= extract32(insn
, 0, 5);
3688 int rn
= extract32(insn
, 5, 5);
3689 int ra
= extract32(insn
, 10, 5);
3690 int rm
= extract32(insn
, 16, 5);
3691 int op_id
= (extract32(insn
, 29, 3) << 4) |
3692 (extract32(insn
, 21, 3) << 1) |
3693 extract32(insn
, 15, 1);
3694 bool sf
= extract32(insn
, 31, 1);
3695 bool is_sub
= extract32(op_id
, 0, 1);
3696 bool is_high
= extract32(op_id
, 2, 1);
3697 bool is_signed
= false;
3702 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3704 case 0x42: /* SMADDL */
3705 case 0x43: /* SMSUBL */
3706 case 0x44: /* SMULH */
3709 case 0x0: /* MADD (32bit) */
3710 case 0x1: /* MSUB (32bit) */
3711 case 0x40: /* MADD (64bit) */
3712 case 0x41: /* MSUB (64bit) */
3713 case 0x4a: /* UMADDL */
3714 case 0x4b: /* UMSUBL */
3715 case 0x4c: /* UMULH */
3718 unallocated_encoding(s
);
3723 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3724 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3725 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3726 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3729 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3731 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3734 tcg_temp_free_i64(low_bits
);
3738 tcg_op1
= tcg_temp_new_i64();
3739 tcg_op2
= tcg_temp_new_i64();
3740 tcg_tmp
= tcg_temp_new_i64();
3743 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3744 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3747 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3748 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3750 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3751 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3755 if (ra
== 31 && !is_sub
) {
3756 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3757 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3759 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3761 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3763 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3768 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3771 tcg_temp_free_i64(tcg_op1
);
3772 tcg_temp_free_i64(tcg_op2
);
3773 tcg_temp_free_i64(tcg_tmp
);
3776 /* Add/subtract (with carry)
3777 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3778 * +--+--+--+------------------------+------+---------+------+-----+
3779 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3780 * +--+--+--+------------------------+------+---------+------+-----+
3784 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3786 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3787 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3789 if (extract32(insn
, 10, 6) != 0) {
3790 unallocated_encoding(s
);
3794 sf
= extract32(insn
, 31, 1);
3795 op
= extract32(insn
, 30, 1);
3796 setflags
= extract32(insn
, 29, 1);
3797 rm
= extract32(insn
, 16, 5);
3798 rn
= extract32(insn
, 5, 5);
3799 rd
= extract32(insn
, 0, 5);
3801 tcg_rd
= cpu_reg(s
, rd
);
3802 tcg_rn
= cpu_reg(s
, rn
);
3805 tcg_y
= new_tmp_a64(s
);
3806 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3808 tcg_y
= cpu_reg(s
, rm
);
3812 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3814 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3818 /* Conditional compare (immediate / register)
3819 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3820 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3821 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3822 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3825 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3827 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3828 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3829 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3832 if (!extract32(insn
, 29, 1)) {
3833 unallocated_encoding(s
);
3836 if (insn
& (1 << 10 | 1 << 4)) {
3837 unallocated_encoding(s
);
3840 sf
= extract32(insn
, 31, 1);
3841 op
= extract32(insn
, 30, 1);
3842 is_imm
= extract32(insn
, 11, 1);
3843 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3844 cond
= extract32(insn
, 12, 4);
3845 rn
= extract32(insn
, 5, 5);
3846 nzcv
= extract32(insn
, 0, 4);
3848 /* Set T0 = !COND. */
3849 tcg_t0
= tcg_temp_new_i32();
3850 arm_test_cc(&c
, cond
);
3851 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3854 /* Load the arguments for the new comparison. */
3856 tcg_y
= new_tmp_a64(s
);
3857 tcg_gen_movi_i64(tcg_y
, y
);
3859 tcg_y
= cpu_reg(s
, y
);
3861 tcg_rn
= cpu_reg(s
, rn
);
3863 /* Set the flags for the new comparison. */
3864 tcg_tmp
= tcg_temp_new_i64();
3866 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3868 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3870 tcg_temp_free_i64(tcg_tmp
);
3872 /* If COND was false, force the flags to #nzcv. Compute two masks
3873 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3874 * For tcg hosts that support ANDC, we can make do with just T1.
3875 * In either case, allow the tcg optimizer to delete any unused mask.
3877 tcg_t1
= tcg_temp_new_i32();
3878 tcg_t2
= tcg_temp_new_i32();
3879 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3880 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3882 if (nzcv
& 8) { /* N */
3883 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3885 if (TCG_TARGET_HAS_andc_i32
) {
3886 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3888 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3891 if (nzcv
& 4) { /* Z */
3892 if (TCG_TARGET_HAS_andc_i32
) {
3893 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3895 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3898 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3900 if (nzcv
& 2) { /* C */
3901 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3903 if (TCG_TARGET_HAS_andc_i32
) {
3904 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3906 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3909 if (nzcv
& 1) { /* V */
3910 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3912 if (TCG_TARGET_HAS_andc_i32
) {
3913 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3915 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3918 tcg_temp_free_i32(tcg_t0
);
3919 tcg_temp_free_i32(tcg_t1
);
3920 tcg_temp_free_i32(tcg_t2
);
3923 /* Conditional select
3924 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3925 * +----+----+---+-----------------+------+------+-----+------+------+
3926 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3927 * +----+----+---+-----------------+------+------+-----+------+------+
3929 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3931 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3932 TCGv_i64 tcg_rd
, zero
;
3935 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3936 /* S == 1 or op2<1> == 1 */
3937 unallocated_encoding(s
);
3940 sf
= extract32(insn
, 31, 1);
3941 else_inv
= extract32(insn
, 30, 1);
3942 rm
= extract32(insn
, 16, 5);
3943 cond
= extract32(insn
, 12, 4);
3944 else_inc
= extract32(insn
, 10, 1);
3945 rn
= extract32(insn
, 5, 5);
3946 rd
= extract32(insn
, 0, 5);
3948 tcg_rd
= cpu_reg(s
, rd
);
3950 a64_test_cc(&c
, cond
);
3951 zero
= tcg_const_i64(0);
3953 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3955 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3957 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3960 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3961 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3962 if (else_inv
&& else_inc
) {
3963 tcg_gen_neg_i64(t_false
, t_false
);
3964 } else if (else_inv
) {
3965 tcg_gen_not_i64(t_false
, t_false
);
3966 } else if (else_inc
) {
3967 tcg_gen_addi_i64(t_false
, t_false
, 1);
3969 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3972 tcg_temp_free_i64(zero
);
3976 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3980 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3981 unsigned int rn
, unsigned int rd
)
3983 TCGv_i64 tcg_rd
, tcg_rn
;
3984 tcg_rd
= cpu_reg(s
, rd
);
3985 tcg_rn
= cpu_reg(s
, rn
);
3988 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3990 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3991 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3992 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3993 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3994 tcg_temp_free_i32(tcg_tmp32
);
3998 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3999 unsigned int rn
, unsigned int rd
)
4001 TCGv_i64 tcg_rd
, tcg_rn
;
4002 tcg_rd
= cpu_reg(s
, rd
);
4003 tcg_rn
= cpu_reg(s
, rn
);
4006 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4008 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4009 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4010 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4011 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4012 tcg_temp_free_i32(tcg_tmp32
);
4016 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4017 unsigned int rn
, unsigned int rd
)
4019 TCGv_i64 tcg_rd
, tcg_rn
;
4020 tcg_rd
= cpu_reg(s
, rd
);
4021 tcg_rn
= cpu_reg(s
, rn
);
4024 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4026 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4027 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4028 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4029 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4030 tcg_temp_free_i32(tcg_tmp32
);
4034 /* REV with sf==1, opcode==3 ("REV64") */
4035 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4036 unsigned int rn
, unsigned int rd
)
4039 unallocated_encoding(s
);
4042 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4045 /* REV with sf==0, opcode==2
4046 * REV32 (sf==1, opcode==2)
4048 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4049 unsigned int rn
, unsigned int rd
)
4051 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4054 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4055 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4057 /* bswap32_i64 requires zero high word */
4058 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4059 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4060 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4061 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4062 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4064 tcg_temp_free_i64(tcg_tmp
);
4066 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4067 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4071 /* REV16 (opcode==1) */
4072 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4073 unsigned int rn
, unsigned int rd
)
4075 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4076 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4077 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4078 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4080 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4081 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4082 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4083 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4084 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4086 tcg_temp_free_i64(mask
);
4087 tcg_temp_free_i64(tcg_tmp
);
4090 /* Data-processing (1 source)
4091 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4092 * +----+---+---+-----------------+---------+--------+------+------+
4093 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4094 * +----+---+---+-----------------+---------+--------+------+------+
4096 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4098 unsigned int sf
, opcode
, rn
, rd
;
4100 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4101 unallocated_encoding(s
);
4105 sf
= extract32(insn
, 31, 1);
4106 opcode
= extract32(insn
, 10, 6);
4107 rn
= extract32(insn
, 5, 5);
4108 rd
= extract32(insn
, 0, 5);
4112 handle_rbit(s
, sf
, rn
, rd
);
4115 handle_rev16(s
, sf
, rn
, rd
);
4118 handle_rev32(s
, sf
, rn
, rd
);
4121 handle_rev64(s
, sf
, rn
, rd
);
4124 handle_clz(s
, sf
, rn
, rd
);
4127 handle_cls(s
, sf
, rn
, rd
);
4132 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4133 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4135 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4136 tcg_rd
= cpu_reg(s
, rd
);
4138 if (!sf
&& is_signed
) {
4139 tcg_n
= new_tmp_a64(s
);
4140 tcg_m
= new_tmp_a64(s
);
4141 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4142 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4144 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4145 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4149 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4151 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4154 if (!sf
) { /* zero extend final result */
4155 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4159 /* LSLV, LSRV, ASRV, RORV */
4160 static void handle_shift_reg(DisasContext
*s
,
4161 enum a64_shift_type shift_type
, unsigned int sf
,
4162 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4164 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4165 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4166 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4168 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4169 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4170 tcg_temp_free_i64(tcg_shift
);
4173 /* CRC32[BHWX], CRC32C[BHWX] */
4174 static void handle_crc32(DisasContext
*s
,
4175 unsigned int sf
, unsigned int sz
, bool crc32c
,
4176 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4178 TCGv_i64 tcg_acc
, tcg_val
;
4181 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4182 || (sf
== 1 && sz
!= 3)
4183 || (sf
== 0 && sz
== 3)) {
4184 unallocated_encoding(s
);
4189 tcg_val
= cpu_reg(s
, rm
);
4203 g_assert_not_reached();
4205 tcg_val
= new_tmp_a64(s
);
4206 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4209 tcg_acc
= cpu_reg(s
, rn
);
4210 tcg_bytes
= tcg_const_i32(1 << sz
);
4213 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4215 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4218 tcg_temp_free_i32(tcg_bytes
);
4221 /* Data-processing (2 source)
4222 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4223 * +----+---+---+-----------------+------+--------+------+------+
4224 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4225 * +----+---+---+-----------------+------+--------+------+------+
4227 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4229 unsigned int sf
, rm
, opcode
, rn
, rd
;
4230 sf
= extract32(insn
, 31, 1);
4231 rm
= extract32(insn
, 16, 5);
4232 opcode
= extract32(insn
, 10, 6);
4233 rn
= extract32(insn
, 5, 5);
4234 rd
= extract32(insn
, 0, 5);
4236 if (extract32(insn
, 29, 1)) {
4237 unallocated_encoding(s
);
4243 handle_div(s
, false, sf
, rm
, rn
, rd
);
4246 handle_div(s
, true, sf
, rm
, rn
, rd
);
4249 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4252 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4255 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4258 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4267 case 23: /* CRC32 */
4269 int sz
= extract32(opcode
, 0, 2);
4270 bool crc32c
= extract32(opcode
, 2, 1);
4271 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4275 unallocated_encoding(s
);
4280 /* Data processing - register */
4281 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4283 switch (extract32(insn
, 24, 5)) {
4284 case 0x0a: /* Logical (shifted register) */
4285 disas_logic_reg(s
, insn
);
4287 case 0x0b: /* Add/subtract */
4288 if (insn
& (1 << 21)) { /* (extended register) */
4289 disas_add_sub_ext_reg(s
, insn
);
4291 disas_add_sub_reg(s
, insn
);
4294 case 0x1b: /* Data-processing (3 source) */
4295 disas_data_proc_3src(s
, insn
);
4298 switch (extract32(insn
, 21, 3)) {
4299 case 0x0: /* Add/subtract (with carry) */
4300 disas_adc_sbc(s
, insn
);
4302 case 0x2: /* Conditional compare */
4303 disas_cc(s
, insn
); /* both imm and reg forms */
4305 case 0x4: /* Conditional select */
4306 disas_cond_select(s
, insn
);
4308 case 0x6: /* Data-processing */
4309 if (insn
& (1 << 30)) { /* (1 source) */
4310 disas_data_proc_1src(s
, insn
);
4311 } else { /* (2 source) */
4312 disas_data_proc_2src(s
, insn
);
4316 unallocated_encoding(s
);
4321 unallocated_encoding(s
);
4326 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4327 unsigned int rn
, unsigned int rm
,
4328 bool cmp_with_zero
, bool signal_all_nans
)
4330 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4331 TCGv_ptr fpst
= get_fpstatus_ptr();
4334 TCGv_i64 tcg_vn
, tcg_vm
;
4336 tcg_vn
= read_fp_dreg(s
, rn
);
4337 if (cmp_with_zero
) {
4338 tcg_vm
= tcg_const_i64(0);
4340 tcg_vm
= read_fp_dreg(s
, rm
);
4342 if (signal_all_nans
) {
4343 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4345 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4347 tcg_temp_free_i64(tcg_vn
);
4348 tcg_temp_free_i64(tcg_vm
);
4350 TCGv_i32 tcg_vn
, tcg_vm
;
4352 tcg_vn
= read_fp_sreg(s
, rn
);
4353 if (cmp_with_zero
) {
4354 tcg_vm
= tcg_const_i32(0);
4356 tcg_vm
= read_fp_sreg(s
, rm
);
4358 if (signal_all_nans
) {
4359 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4361 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4363 tcg_temp_free_i32(tcg_vn
);
4364 tcg_temp_free_i32(tcg_vm
);
4367 tcg_temp_free_ptr(fpst
);
4369 gen_set_nzcv(tcg_flags
);
4371 tcg_temp_free_i64(tcg_flags
);
4374 /* Floating point compare
4375 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4376 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4377 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4378 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4380 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4382 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4384 mos
= extract32(insn
, 29, 3);
4385 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4386 rm
= extract32(insn
, 16, 5);
4387 op
= extract32(insn
, 14, 2);
4388 rn
= extract32(insn
, 5, 5);
4389 opc
= extract32(insn
, 3, 2);
4390 op2r
= extract32(insn
, 0, 3);
4392 if (mos
|| op
|| op2r
|| type
> 1) {
4393 unallocated_encoding(s
);
4397 if (!fp_access_check(s
)) {
4401 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4404 /* Floating point conditional compare
4405 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4406 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4407 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4408 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4410 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4412 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4414 TCGLabel
*label_continue
= NULL
;
4416 mos
= extract32(insn
, 29, 3);
4417 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4418 rm
= extract32(insn
, 16, 5);
4419 cond
= extract32(insn
, 12, 4);
4420 rn
= extract32(insn
, 5, 5);
4421 op
= extract32(insn
, 4, 1);
4422 nzcv
= extract32(insn
, 0, 4);
4424 if (mos
|| type
> 1) {
4425 unallocated_encoding(s
);
4429 if (!fp_access_check(s
)) {
4433 if (cond
< 0x0e) { /* not always */
4434 TCGLabel
*label_match
= gen_new_label();
4435 label_continue
= gen_new_label();
4436 arm_gen_test_cc(cond
, label_match
);
4438 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4439 gen_set_nzcv(tcg_flags
);
4440 tcg_temp_free_i64(tcg_flags
);
4441 tcg_gen_br(label_continue
);
4442 gen_set_label(label_match
);
4445 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4448 gen_set_label(label_continue
);
4452 /* Floating point conditional select
4453 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4454 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4455 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4456 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4458 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4460 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4461 TCGv_i64 t_true
, t_false
, t_zero
;
4464 mos
= extract32(insn
, 29, 3);
4465 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4466 rm
= extract32(insn
, 16, 5);
4467 cond
= extract32(insn
, 12, 4);
4468 rn
= extract32(insn
, 5, 5);
4469 rd
= extract32(insn
, 0, 5);
4471 if (mos
|| type
> 1) {
4472 unallocated_encoding(s
);
4476 if (!fp_access_check(s
)) {
4480 /* Zero extend sreg inputs to 64 bits now. */
4481 t_true
= tcg_temp_new_i64();
4482 t_false
= tcg_temp_new_i64();
4483 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4484 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4486 a64_test_cc(&c
, cond
);
4487 t_zero
= tcg_const_i64(0);
4488 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4489 tcg_temp_free_i64(t_zero
);
4490 tcg_temp_free_i64(t_false
);
4493 /* Note that sregs write back zeros to the high bits,
4494 and we've already done the zero-extension. */
4495 write_fp_dreg(s
, rd
, t_true
);
4496 tcg_temp_free_i64(t_true
);
4499 /* Floating-point data-processing (1 source) - single precision */
4500 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4506 fpst
= get_fpstatus_ptr();
4507 tcg_op
= read_fp_sreg(s
, rn
);
4508 tcg_res
= tcg_temp_new_i32();
4511 case 0x0: /* FMOV */
4512 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4514 case 0x1: /* FABS */
4515 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4517 case 0x2: /* FNEG */
4518 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4520 case 0x3: /* FSQRT */
4521 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4523 case 0x8: /* FRINTN */
4524 case 0x9: /* FRINTP */
4525 case 0xa: /* FRINTM */
4526 case 0xb: /* FRINTZ */
4527 case 0xc: /* FRINTA */
4529 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4531 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4532 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4534 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4535 tcg_temp_free_i32(tcg_rmode
);
4538 case 0xe: /* FRINTX */
4539 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4541 case 0xf: /* FRINTI */
4542 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4548 write_fp_sreg(s
, rd
, tcg_res
);
4550 tcg_temp_free_ptr(fpst
);
4551 tcg_temp_free_i32(tcg_op
);
4552 tcg_temp_free_i32(tcg_res
);
4555 /* Floating-point data-processing (1 source) - double precision */
4556 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4562 fpst
= get_fpstatus_ptr();
4563 tcg_op
= read_fp_dreg(s
, rn
);
4564 tcg_res
= tcg_temp_new_i64();
4567 case 0x0: /* FMOV */
4568 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4570 case 0x1: /* FABS */
4571 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4573 case 0x2: /* FNEG */
4574 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4576 case 0x3: /* FSQRT */
4577 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4579 case 0x8: /* FRINTN */
4580 case 0x9: /* FRINTP */
4581 case 0xa: /* FRINTM */
4582 case 0xb: /* FRINTZ */
4583 case 0xc: /* FRINTA */
4585 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4587 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4588 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4590 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4591 tcg_temp_free_i32(tcg_rmode
);
4594 case 0xe: /* FRINTX */
4595 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4597 case 0xf: /* FRINTI */
4598 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4604 write_fp_dreg(s
, rd
, tcg_res
);
4606 tcg_temp_free_ptr(fpst
);
4607 tcg_temp_free_i64(tcg_op
);
4608 tcg_temp_free_i64(tcg_res
);
4611 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4612 int rd
, int rn
, int dtype
, int ntype
)
4617 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4619 /* Single to double */
4620 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4621 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4622 write_fp_dreg(s
, rd
, tcg_rd
);
4623 tcg_temp_free_i64(tcg_rd
);
4625 /* Single to half */
4626 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4627 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4628 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4629 write_fp_sreg(s
, rd
, tcg_rd
);
4630 tcg_temp_free_i32(tcg_rd
);
4632 tcg_temp_free_i32(tcg_rn
);
4637 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4638 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4640 /* Double to single */
4641 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4643 /* Double to half */
4644 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4645 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4647 write_fp_sreg(s
, rd
, tcg_rd
);
4648 tcg_temp_free_i32(tcg_rd
);
4649 tcg_temp_free_i64(tcg_rn
);
4654 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4655 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4657 /* Half to single */
4658 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4659 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4660 write_fp_sreg(s
, rd
, tcg_rd
);
4661 tcg_temp_free_i32(tcg_rd
);
4663 /* Half to double */
4664 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4665 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4666 write_fp_dreg(s
, rd
, tcg_rd
);
4667 tcg_temp_free_i64(tcg_rd
);
4669 tcg_temp_free_i32(tcg_rn
);
4677 /* Floating point data-processing (1 source)
4678 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4679 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4680 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4681 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4683 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4685 int type
= extract32(insn
, 22, 2);
4686 int opcode
= extract32(insn
, 15, 6);
4687 int rn
= extract32(insn
, 5, 5);
4688 int rd
= extract32(insn
, 0, 5);
4691 case 0x4: case 0x5: case 0x7:
4693 /* FCVT between half, single and double precision */
4694 int dtype
= extract32(opcode
, 0, 2);
4695 if (type
== 2 || dtype
== type
) {
4696 unallocated_encoding(s
);
4699 if (!fp_access_check(s
)) {
4703 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4709 /* 32-to-32 and 64-to-64 ops */
4712 if (!fp_access_check(s
)) {
4716 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4719 if (!fp_access_check(s
)) {
4723 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4726 unallocated_encoding(s
);
4730 unallocated_encoding(s
);
4735 /* Floating-point data-processing (2 source) - single precision */
4736 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4737 int rd
, int rn
, int rm
)
4744 tcg_res
= tcg_temp_new_i32();
4745 fpst
= get_fpstatus_ptr();
4746 tcg_op1
= read_fp_sreg(s
, rn
);
4747 tcg_op2
= read_fp_sreg(s
, rm
);
4750 case 0x0: /* FMUL */
4751 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4753 case 0x1: /* FDIV */
4754 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4756 case 0x2: /* FADD */
4757 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4759 case 0x3: /* FSUB */
4760 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4762 case 0x4: /* FMAX */
4763 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4765 case 0x5: /* FMIN */
4766 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4768 case 0x6: /* FMAXNM */
4769 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4771 case 0x7: /* FMINNM */
4772 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4774 case 0x8: /* FNMUL */
4775 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4776 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4780 write_fp_sreg(s
, rd
, tcg_res
);
4782 tcg_temp_free_ptr(fpst
);
4783 tcg_temp_free_i32(tcg_op1
);
4784 tcg_temp_free_i32(tcg_op2
);
4785 tcg_temp_free_i32(tcg_res
);
4788 /* Floating-point data-processing (2 source) - double precision */
4789 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4790 int rd
, int rn
, int rm
)
4797 tcg_res
= tcg_temp_new_i64();
4798 fpst
= get_fpstatus_ptr();
4799 tcg_op1
= read_fp_dreg(s
, rn
);
4800 tcg_op2
= read_fp_dreg(s
, rm
);
4803 case 0x0: /* FMUL */
4804 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4806 case 0x1: /* FDIV */
4807 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4809 case 0x2: /* FADD */
4810 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4812 case 0x3: /* FSUB */
4813 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4815 case 0x4: /* FMAX */
4816 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4818 case 0x5: /* FMIN */
4819 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4821 case 0x6: /* FMAXNM */
4822 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4824 case 0x7: /* FMINNM */
4825 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4827 case 0x8: /* FNMUL */
4828 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4829 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4833 write_fp_dreg(s
, rd
, tcg_res
);
4835 tcg_temp_free_ptr(fpst
);
4836 tcg_temp_free_i64(tcg_op1
);
4837 tcg_temp_free_i64(tcg_op2
);
4838 tcg_temp_free_i64(tcg_res
);
4841 /* Floating point data-processing (2 source)
4842 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4843 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4844 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4845 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4847 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4849 int type
= extract32(insn
, 22, 2);
4850 int rd
= extract32(insn
, 0, 5);
4851 int rn
= extract32(insn
, 5, 5);
4852 int rm
= extract32(insn
, 16, 5);
4853 int opcode
= extract32(insn
, 12, 4);
4856 unallocated_encoding(s
);
4862 if (!fp_access_check(s
)) {
4865 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4868 if (!fp_access_check(s
)) {
4871 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4874 unallocated_encoding(s
);
4878 /* Floating-point data-processing (3 source) - single precision */
4879 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4880 int rd
, int rn
, int rm
, int ra
)
4882 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4883 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4884 TCGv_ptr fpst
= get_fpstatus_ptr();
4886 tcg_op1
= read_fp_sreg(s
, rn
);
4887 tcg_op2
= read_fp_sreg(s
, rm
);
4888 tcg_op3
= read_fp_sreg(s
, ra
);
4890 /* These are fused multiply-add, and must be done as one
4891 * floating point operation with no rounding between the
4892 * multiplication and addition steps.
4893 * NB that doing the negations here as separate steps is
4894 * correct : an input NaN should come out with its sign bit
4895 * flipped if it is a negated-input.
4898 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4902 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4905 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4907 write_fp_sreg(s
, rd
, tcg_res
);
4909 tcg_temp_free_ptr(fpst
);
4910 tcg_temp_free_i32(tcg_op1
);
4911 tcg_temp_free_i32(tcg_op2
);
4912 tcg_temp_free_i32(tcg_op3
);
4913 tcg_temp_free_i32(tcg_res
);
4916 /* Floating-point data-processing (3 source) - double precision */
4917 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4918 int rd
, int rn
, int rm
, int ra
)
4920 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4921 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4922 TCGv_ptr fpst
= get_fpstatus_ptr();
4924 tcg_op1
= read_fp_dreg(s
, rn
);
4925 tcg_op2
= read_fp_dreg(s
, rm
);
4926 tcg_op3
= read_fp_dreg(s
, ra
);
4928 /* These are fused multiply-add, and must be done as one
4929 * floating point operation with no rounding between the
4930 * multiplication and addition steps.
4931 * NB that doing the negations here as separate steps is
4932 * correct : an input NaN should come out with its sign bit
4933 * flipped if it is a negated-input.
4936 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4940 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4943 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4945 write_fp_dreg(s
, rd
, tcg_res
);
4947 tcg_temp_free_ptr(fpst
);
4948 tcg_temp_free_i64(tcg_op1
);
4949 tcg_temp_free_i64(tcg_op2
);
4950 tcg_temp_free_i64(tcg_op3
);
4951 tcg_temp_free_i64(tcg_res
);
4954 /* Floating point data-processing (3 source)
4955 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4956 * +---+---+---+-----------+------+----+------+----+------+------+------+
4957 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4958 * +---+---+---+-----------+------+----+------+----+------+------+------+
4960 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4962 int type
= extract32(insn
, 22, 2);
4963 int rd
= extract32(insn
, 0, 5);
4964 int rn
= extract32(insn
, 5, 5);
4965 int ra
= extract32(insn
, 10, 5);
4966 int rm
= extract32(insn
, 16, 5);
4967 bool o0
= extract32(insn
, 15, 1);
4968 bool o1
= extract32(insn
, 21, 1);
4972 if (!fp_access_check(s
)) {
4975 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4978 if (!fp_access_check(s
)) {
4981 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4984 unallocated_encoding(s
);
4988 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
4989 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
4990 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
4992 static uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
4998 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4999 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5000 extract32(imm8
, 0, 6);
5004 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5005 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5006 (extract32(imm8
, 0, 6) << 3);
5010 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5011 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5012 (extract32(imm8
, 0, 6) << 6);
5015 g_assert_not_reached();
5020 /* Floating point immediate
5021 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5022 * +---+---+---+-----------+------+---+------------+-------+------+------+
5023 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5024 * +---+---+---+-----------+------+---+------------+-------+------+------+
5026 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5028 int rd
= extract32(insn
, 0, 5);
5029 int imm8
= extract32(insn
, 13, 8);
5030 int is_double
= extract32(insn
, 22, 2);
5034 if (is_double
> 1) {
5035 unallocated_encoding(s
);
5039 if (!fp_access_check(s
)) {
5043 imm
= vfp_expand_imm(MO_32
+ is_double
, imm8
);
5045 tcg_res
= tcg_const_i64(imm
);
5046 write_fp_dreg(s
, rd
, tcg_res
);
5047 tcg_temp_free_i64(tcg_res
);
5050 /* Handle floating point <=> fixed point conversions. Note that we can
5051 * also deal with fp <=> integer conversions as a special case (scale == 64)
5052 * OPTME: consider handling that special case specially or at least skipping
5053 * the call to scalbn in the helpers for zero shifts.
5055 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5056 bool itof
, int rmode
, int scale
, int sf
, int type
)
5058 bool is_signed
= !(opcode
& 1);
5059 bool is_double
= type
;
5060 TCGv_ptr tcg_fpstatus
;
5063 tcg_fpstatus
= get_fpstatus_ptr();
5065 tcg_shift
= tcg_const_i32(64 - scale
);
5068 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5070 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5073 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5075 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5078 tcg_int
= tcg_extend
;
5082 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5084 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5085 tcg_shift
, tcg_fpstatus
);
5087 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5088 tcg_shift
, tcg_fpstatus
);
5090 write_fp_dreg(s
, rd
, tcg_double
);
5091 tcg_temp_free_i64(tcg_double
);
5093 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5095 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5096 tcg_shift
, tcg_fpstatus
);
5098 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5099 tcg_shift
, tcg_fpstatus
);
5101 write_fp_sreg(s
, rd
, tcg_single
);
5102 tcg_temp_free_i32(tcg_single
);
5105 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5108 if (extract32(opcode
, 2, 1)) {
5109 /* There are too many rounding modes to all fit into rmode,
5110 * so FCVTA[US] is a special case.
5112 rmode
= FPROUNDING_TIEAWAY
;
5115 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5117 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5120 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5123 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5124 tcg_shift
, tcg_fpstatus
);
5126 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5127 tcg_shift
, tcg_fpstatus
);
5131 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5132 tcg_shift
, tcg_fpstatus
);
5134 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5135 tcg_shift
, tcg_fpstatus
);
5138 tcg_temp_free_i64(tcg_double
);
5140 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5143 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5144 tcg_shift
, tcg_fpstatus
);
5146 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5147 tcg_shift
, tcg_fpstatus
);
5150 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5152 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5153 tcg_shift
, tcg_fpstatus
);
5155 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5156 tcg_shift
, tcg_fpstatus
);
5158 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5159 tcg_temp_free_i32(tcg_dest
);
5161 tcg_temp_free_i32(tcg_single
);
5164 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5165 tcg_temp_free_i32(tcg_rmode
);
5168 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5172 tcg_temp_free_ptr(tcg_fpstatus
);
5173 tcg_temp_free_i32(tcg_shift
);
5176 /* Floating point <-> fixed point conversions
5177 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5178 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5179 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5180 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5182 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5184 int rd
= extract32(insn
, 0, 5);
5185 int rn
= extract32(insn
, 5, 5);
5186 int scale
= extract32(insn
, 10, 6);
5187 int opcode
= extract32(insn
, 16, 3);
5188 int rmode
= extract32(insn
, 19, 2);
5189 int type
= extract32(insn
, 22, 2);
5190 bool sbit
= extract32(insn
, 29, 1);
5191 bool sf
= extract32(insn
, 31, 1);
5194 if (sbit
|| (type
> 1)
5195 || (!sf
&& scale
< 32)) {
5196 unallocated_encoding(s
);
5200 switch ((rmode
<< 3) | opcode
) {
5201 case 0x2: /* SCVTF */
5202 case 0x3: /* UCVTF */
5205 case 0x18: /* FCVTZS */
5206 case 0x19: /* FCVTZU */
5210 unallocated_encoding(s
);
5214 if (!fp_access_check(s
)) {
5218 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5221 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5223 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5224 * without conversion.
5228 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5234 TCGv_i64 tmp
= tcg_temp_new_i64();
5235 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5236 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5237 tcg_gen_movi_i64(tmp
, 0);
5238 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5239 tcg_temp_free_i64(tmp
);
5245 TCGv_i64 tmp
= tcg_const_i64(0);
5246 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5247 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5248 tcg_temp_free_i64(tmp
);
5252 /* 64 bit to top half. */
5253 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5257 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5262 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5266 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5269 /* 64 bits from top half */
5270 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5276 /* Floating point <-> integer conversions
5277 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5278 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5279 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5280 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5282 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5284 int rd
= extract32(insn
, 0, 5);
5285 int rn
= extract32(insn
, 5, 5);
5286 int opcode
= extract32(insn
, 16, 3);
5287 int rmode
= extract32(insn
, 19, 2);
5288 int type
= extract32(insn
, 22, 2);
5289 bool sbit
= extract32(insn
, 29, 1);
5290 bool sf
= extract32(insn
, 31, 1);
5293 unallocated_encoding(s
);
5299 bool itof
= opcode
& 1;
5302 unallocated_encoding(s
);
5306 switch (sf
<< 3 | type
<< 1 | rmode
) {
5307 case 0x0: /* 32 bit */
5308 case 0xa: /* 64 bit */
5309 case 0xd: /* 64 bit to top half of quad */
5312 /* all other sf/type/rmode combinations are invalid */
5313 unallocated_encoding(s
);
5317 if (!fp_access_check(s
)) {
5320 handle_fmov(s
, rd
, rn
, type
, itof
);
5322 /* actual FP conversions */
5323 bool itof
= extract32(opcode
, 1, 1);
5325 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5326 unallocated_encoding(s
);
5330 if (!fp_access_check(s
)) {
5333 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5337 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5338 * 31 30 29 28 25 24 0
5339 * +---+---+---+---------+-----------------------------+
5340 * | | 0 | | 1 1 1 1 | |
5341 * +---+---+---+---------+-----------------------------+
5343 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5345 if (extract32(insn
, 24, 1)) {
5346 /* Floating point data-processing (3 source) */
5347 disas_fp_3src(s
, insn
);
5348 } else if (extract32(insn
, 21, 1) == 0) {
5349 /* Floating point to fixed point conversions */
5350 disas_fp_fixed_conv(s
, insn
);
5352 switch (extract32(insn
, 10, 2)) {
5354 /* Floating point conditional compare */
5355 disas_fp_ccomp(s
, insn
);
5358 /* Floating point data-processing (2 source) */
5359 disas_fp_2src(s
, insn
);
5362 /* Floating point conditional select */
5363 disas_fp_csel(s
, insn
);
5366 switch (ctz32(extract32(insn
, 12, 4))) {
5367 case 0: /* [15:12] == xxx1 */
5368 /* Floating point immediate */
5369 disas_fp_imm(s
, insn
);
5371 case 1: /* [15:12] == xx10 */
5372 /* Floating point compare */
5373 disas_fp_compare(s
, insn
);
5375 case 2: /* [15:12] == x100 */
5376 /* Floating point data-processing (1 source) */
5377 disas_fp_1src(s
, insn
);
5379 case 3: /* [15:12] == 1000 */
5380 unallocated_encoding(s
);
5382 default: /* [15:12] == 0000 */
5383 /* Floating point <-> integer conversions */
5384 disas_fp_int_conv(s
, insn
);
5392 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5395 /* Extract 64 bits from the middle of two concatenated 64 bit
5396 * vector register slices left:right. The extracted bits start
5397 * at 'pos' bits into the right (least significant) side.
5398 * We return the result in tcg_right, and guarantee not to
5401 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5402 assert(pos
> 0 && pos
< 64);
5404 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5405 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5406 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5408 tcg_temp_free_i64(tcg_tmp
);
5412 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5413 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5414 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5415 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5417 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5419 int is_q
= extract32(insn
, 30, 1);
5420 int op2
= extract32(insn
, 22, 2);
5421 int imm4
= extract32(insn
, 11, 4);
5422 int rm
= extract32(insn
, 16, 5);
5423 int rn
= extract32(insn
, 5, 5);
5424 int rd
= extract32(insn
, 0, 5);
5425 int pos
= imm4
<< 3;
5426 TCGv_i64 tcg_resl
, tcg_resh
;
5428 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5429 unallocated_encoding(s
);
5433 if (!fp_access_check(s
)) {
5437 tcg_resh
= tcg_temp_new_i64();
5438 tcg_resl
= tcg_temp_new_i64();
5440 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5441 * either extracting 128 bits from a 128:128 concatenation, or
5442 * extracting 64 bits from a 64:64 concatenation.
5445 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5447 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5448 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5450 tcg_gen_movi_i64(tcg_resh
, 0);
5457 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5458 EltPosns
*elt
= eltposns
;
5465 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5467 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5470 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5471 tcg_hh
= tcg_temp_new_i64();
5472 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5473 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5474 tcg_temp_free_i64(tcg_hh
);
5478 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5479 tcg_temp_free_i64(tcg_resl
);
5480 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5481 tcg_temp_free_i64(tcg_resh
);
5485 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5486 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5487 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5488 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5490 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5492 int op2
= extract32(insn
, 22, 2);
5493 int is_q
= extract32(insn
, 30, 1);
5494 int rm
= extract32(insn
, 16, 5);
5495 int rn
= extract32(insn
, 5, 5);
5496 int rd
= extract32(insn
, 0, 5);
5497 int is_tblx
= extract32(insn
, 12, 1);
5498 int len
= extract32(insn
, 13, 2);
5499 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5500 TCGv_i32 tcg_regno
, tcg_numregs
;
5503 unallocated_encoding(s
);
5507 if (!fp_access_check(s
)) {
5511 /* This does a table lookup: for every byte element in the input
5512 * we index into a table formed from up to four vector registers,
5513 * and then the output is the result of the lookups. Our helper
5514 * function does the lookup operation for a single 64 bit part of
5517 tcg_resl
= tcg_temp_new_i64();
5518 tcg_resh
= tcg_temp_new_i64();
5521 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5523 tcg_gen_movi_i64(tcg_resl
, 0);
5525 if (is_tblx
&& is_q
) {
5526 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5528 tcg_gen_movi_i64(tcg_resh
, 0);
5531 tcg_idx
= tcg_temp_new_i64();
5532 tcg_regno
= tcg_const_i32(rn
);
5533 tcg_numregs
= tcg_const_i32(len
+ 1);
5534 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5535 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5536 tcg_regno
, tcg_numregs
);
5538 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5539 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5540 tcg_regno
, tcg_numregs
);
5542 tcg_temp_free_i64(tcg_idx
);
5543 tcg_temp_free_i32(tcg_regno
);
5544 tcg_temp_free_i32(tcg_numregs
);
5546 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5547 tcg_temp_free_i64(tcg_resl
);
5548 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5549 tcg_temp_free_i64(tcg_resh
);
5553 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5554 * +---+---+-------------+------+---+------+---+------------------+------+
5555 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5556 * +---+---+-------------+------+---+------+---+------------------+------+
5558 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5560 int rd
= extract32(insn
, 0, 5);
5561 int rn
= extract32(insn
, 5, 5);
5562 int rm
= extract32(insn
, 16, 5);
5563 int size
= extract32(insn
, 22, 2);
5564 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5565 * bit 2 indicates 1 vs 2 variant of the insn.
5567 int opcode
= extract32(insn
, 12, 2);
5568 bool part
= extract32(insn
, 14, 1);
5569 bool is_q
= extract32(insn
, 30, 1);
5570 int esize
= 8 << size
;
5572 int datasize
= is_q
? 128 : 64;
5573 int elements
= datasize
/ esize
;
5574 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5576 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5577 unallocated_encoding(s
);
5581 if (!fp_access_check(s
)) {
5585 tcg_resl
= tcg_const_i64(0);
5586 tcg_resh
= tcg_const_i64(0);
5587 tcg_res
= tcg_temp_new_i64();
5589 for (i
= 0; i
< elements
; i
++) {
5591 case 1: /* UZP1/2 */
5593 int midpoint
= elements
/ 2;
5595 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5597 read_vec_element(s
, tcg_res
, rm
,
5598 2 * (i
- midpoint
) + part
, size
);
5602 case 2: /* TRN1/2 */
5604 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5606 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5609 case 3: /* ZIP1/2 */
5611 int base
= part
* elements
/ 2;
5613 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5615 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5620 g_assert_not_reached();
5625 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5626 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5628 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5629 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5633 tcg_temp_free_i64(tcg_res
);
5635 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5636 tcg_temp_free_i64(tcg_resl
);
5637 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5638 tcg_temp_free_i64(tcg_resh
);
5641 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5642 int opc
, bool is_min
, TCGv_ptr fpst
)
5644 /* Helper function for disas_simd_across_lanes: do a single precision
5645 * min/max operation on the specified two inputs,
5646 * and return the result in tcg_elt1.
5650 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5652 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5657 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5659 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5664 /* AdvSIMD across lanes
5665 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5666 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5667 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5668 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5670 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5672 int rd
= extract32(insn
, 0, 5);
5673 int rn
= extract32(insn
, 5, 5);
5674 int size
= extract32(insn
, 22, 2);
5675 int opcode
= extract32(insn
, 12, 5);
5676 bool is_q
= extract32(insn
, 30, 1);
5677 bool is_u
= extract32(insn
, 29, 1);
5679 bool is_min
= false;
5683 TCGv_i64 tcg_res
, tcg_elt
;
5686 case 0x1b: /* ADDV */
5688 unallocated_encoding(s
);
5692 case 0x3: /* SADDLV, UADDLV */
5693 case 0xa: /* SMAXV, UMAXV */
5694 case 0x1a: /* SMINV, UMINV */
5695 if (size
== 3 || (size
== 2 && !is_q
)) {
5696 unallocated_encoding(s
);
5700 case 0xc: /* FMAXNMV, FMINNMV */
5701 case 0xf: /* FMAXV, FMINV */
5702 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5703 unallocated_encoding(s
);
5706 /* Bit 1 of size field encodes min vs max, and actual size is always
5707 * 32 bits: adjust the size variable so following code can rely on it
5709 is_min
= extract32(size
, 1, 1);
5714 unallocated_encoding(s
);
5718 if (!fp_access_check(s
)) {
5723 elements
= (is_q
? 128 : 64) / esize
;
5725 tcg_res
= tcg_temp_new_i64();
5726 tcg_elt
= tcg_temp_new_i64();
5728 /* These instructions operate across all lanes of a vector
5729 * to produce a single result. We can guarantee that a 64
5730 * bit intermediate is sufficient:
5731 * + for [US]ADDLV the maximum element size is 32 bits, and
5732 * the result type is 64 bits
5733 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5734 * same as the element size, which is 32 bits at most
5735 * For the integer operations we can choose to work at 64
5736 * or 32 bits and truncate at the end; for simplicity
5737 * we use 64 bits always. The floating point
5738 * ops do require 32 bit intermediates, though.
5741 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5743 for (i
= 1; i
< elements
; i
++) {
5744 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5747 case 0x03: /* SADDLV / UADDLV */
5748 case 0x1b: /* ADDV */
5749 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5751 case 0x0a: /* SMAXV / UMAXV */
5752 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5754 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5756 case 0x1a: /* SMINV / UMINV */
5757 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5759 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5763 g_assert_not_reached();
5768 /* Floating point ops which work on 32 bit (single) intermediates.
5769 * Note that correct NaN propagation requires that we do these
5770 * operations in exactly the order specified by the pseudocode.
5772 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5773 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5774 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5775 TCGv_ptr fpst
= get_fpstatus_ptr();
5777 assert(esize
== 32);
5778 assert(elements
== 4);
5780 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5781 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5782 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5783 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5785 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5787 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5788 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5789 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5790 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5792 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5794 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5796 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5797 tcg_temp_free_i32(tcg_elt1
);
5798 tcg_temp_free_i32(tcg_elt2
);
5799 tcg_temp_free_i32(tcg_elt3
);
5800 tcg_temp_free_ptr(fpst
);
5803 tcg_temp_free_i64(tcg_elt
);
5805 /* Now truncate the result to the width required for the final output */
5806 if (opcode
== 0x03) {
5807 /* SADDLV, UADDLV: result is 2*esize */
5813 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5816 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5819 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5824 g_assert_not_reached();
5827 write_fp_dreg(s
, rd
, tcg_res
);
5828 tcg_temp_free_i64(tcg_res
);
5831 /* DUP (Element, Vector)
5833 * 31 30 29 21 20 16 15 10 9 5 4 0
5834 * +---+---+-------------------+--------+-------------+------+------+
5835 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5836 * +---+---+-------------------+--------+-------------+------+------+
5838 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5840 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5843 int size
= ctz32(imm5
);
5844 int esize
= 8 << size
;
5845 int elements
= (is_q
? 128 : 64) / esize
;
5849 if (size
> 3 || (size
== 3 && !is_q
)) {
5850 unallocated_encoding(s
);
5854 if (!fp_access_check(s
)) {
5858 index
= imm5
>> (size
+ 1);
5860 tmp
= tcg_temp_new_i64();
5861 read_vec_element(s
, tmp
, rn
, index
, size
);
5863 for (i
= 0; i
< elements
; i
++) {
5864 write_vec_element(s
, tmp
, rd
, i
, size
);
5868 clear_vec_high(s
, rd
);
5871 tcg_temp_free_i64(tmp
);
5874 /* DUP (element, scalar)
5875 * 31 21 20 16 15 10 9 5 4 0
5876 * +-----------------------+--------+-------------+------+------+
5877 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5878 * +-----------------------+--------+-------------+------+------+
5880 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5883 int size
= ctz32(imm5
);
5888 unallocated_encoding(s
);
5892 if (!fp_access_check(s
)) {
5896 index
= imm5
>> (size
+ 1);
5898 /* This instruction just extracts the specified element and
5899 * zero-extends it into the bottom of the destination register.
5901 tmp
= tcg_temp_new_i64();
5902 read_vec_element(s
, tmp
, rn
, index
, size
);
5903 write_fp_dreg(s
, rd
, tmp
);
5904 tcg_temp_free_i64(tmp
);
5909 * 31 30 29 21 20 16 15 10 9 5 4 0
5910 * +---+---+-------------------+--------+-------------+------+------+
5911 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5912 * +---+---+-------------------+--------+-------------+------+------+
5914 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5916 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5919 int size
= ctz32(imm5
);
5920 int esize
= 8 << size
;
5921 int elements
= (is_q
? 128 : 64)/esize
;
5924 if (size
> 3 || ((size
== 3) && !is_q
)) {
5925 unallocated_encoding(s
);
5929 if (!fp_access_check(s
)) {
5933 for (i
= 0; i
< elements
; i
++) {
5934 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5937 clear_vec_high(s
, rd
);
5943 * 31 21 20 16 15 14 11 10 9 5 4 0
5944 * +-----------------------+--------+------------+---+------+------+
5945 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5946 * +-----------------------+--------+------------+---+------+------+
5948 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5949 * index: encoded in imm5<4:size+1>
5951 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5954 int size
= ctz32(imm5
);
5955 int src_index
, dst_index
;
5959 unallocated_encoding(s
);
5963 if (!fp_access_check(s
)) {
5967 dst_index
= extract32(imm5
, 1+size
, 5);
5968 src_index
= extract32(imm4
, size
, 4);
5970 tmp
= tcg_temp_new_i64();
5972 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5973 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5975 tcg_temp_free_i64(tmp
);
5981 * 31 21 20 16 15 10 9 5 4 0
5982 * +-----------------------+--------+-------------+------+------+
5983 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5984 * +-----------------------+--------+-------------+------+------+
5986 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5987 * index: encoded in imm5<4:size+1>
5989 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5991 int size
= ctz32(imm5
);
5995 unallocated_encoding(s
);
5999 if (!fp_access_check(s
)) {
6003 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6004 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6011 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6012 * +---+---+-------------------+--------+-------------+------+------+
6013 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6014 * +---+---+-------------------+--------+-------------+------+------+
6016 * U: unsigned when set
6017 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6019 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6020 int rn
, int rd
, int imm5
)
6022 int size
= ctz32(imm5
);
6026 /* Check for UnallocatedEncodings */
6028 if (size
> 2 || (size
== 2 && !is_q
)) {
6029 unallocated_encoding(s
);
6034 || (size
< 3 && is_q
)
6035 || (size
== 3 && !is_q
)) {
6036 unallocated_encoding(s
);
6041 if (!fp_access_check(s
)) {
6045 element
= extract32(imm5
, 1+size
, 4);
6047 tcg_rd
= cpu_reg(s
, rd
);
6048 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6049 if (is_signed
&& !is_q
) {
6050 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6055 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6056 * +---+---+----+-----------------+------+---+------+---+------+------+
6057 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6058 * +---+---+----+-----------------+------+---+------+---+------+------+
6060 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6062 int rd
= extract32(insn
, 0, 5);
6063 int rn
= extract32(insn
, 5, 5);
6064 int imm4
= extract32(insn
, 11, 4);
6065 int op
= extract32(insn
, 29, 1);
6066 int is_q
= extract32(insn
, 30, 1);
6067 int imm5
= extract32(insn
, 16, 5);
6072 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6074 unallocated_encoding(s
);
6079 /* DUP (element - vector) */
6080 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6084 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6089 handle_simd_insg(s
, rd
, rn
, imm5
);
6091 unallocated_encoding(s
);
6096 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6097 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6100 unallocated_encoding(s
);
6106 /* AdvSIMD modified immediate
6107 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6108 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6109 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6110 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6112 * There are a number of operations that can be carried out here:
6113 * MOVI - move (shifted) imm into register
6114 * MVNI - move inverted (shifted) imm into register
6115 * ORR - bitwise OR of (shifted) imm with register
6116 * BIC - bitwise clear of (shifted) imm with register
6118 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6120 int rd
= extract32(insn
, 0, 5);
6121 int cmode
= extract32(insn
, 12, 4);
6122 int cmode_3_1
= extract32(cmode
, 1, 3);
6123 int cmode_0
= extract32(cmode
, 0, 1);
6124 int o2
= extract32(insn
, 11, 1);
6125 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6126 bool is_neg
= extract32(insn
, 29, 1);
6127 bool is_q
= extract32(insn
, 30, 1);
6129 TCGv_i64 tcg_rd
, tcg_imm
;
6132 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6133 unallocated_encoding(s
);
6137 if (!fp_access_check(s
)) {
6141 /* See AdvSIMDExpandImm() in ARM ARM */
6142 switch (cmode_3_1
) {
6143 case 0: /* Replicate(Zeros(24):imm8, 2) */
6144 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6145 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6146 case 3: /* Replicate(imm8:Zeros(24), 2) */
6148 int shift
= cmode_3_1
* 8;
6149 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6152 case 4: /* Replicate(Zeros(8):imm8, 4) */
6153 case 5: /* Replicate(imm8:Zeros(8), 4) */
6155 int shift
= (cmode_3_1
& 0x1) * 8;
6156 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6161 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6162 imm
= (abcdefgh
<< 16) | 0xffff;
6164 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6165 imm
= (abcdefgh
<< 8) | 0xff;
6167 imm
= bitfield_replicate(imm
, 32);
6170 if (!cmode_0
&& !is_neg
) {
6171 imm
= bitfield_replicate(abcdefgh
, 8);
6172 } else if (!cmode_0
&& is_neg
) {
6175 for (i
= 0; i
< 8; i
++) {
6176 if ((abcdefgh
) & (1 << i
)) {
6177 imm
|= 0xffULL
<< (i
* 8);
6180 } else if (cmode_0
) {
6182 imm
= (abcdefgh
& 0x3f) << 48;
6183 if (abcdefgh
& 0x80) {
6184 imm
|= 0x8000000000000000ULL
;
6186 if (abcdefgh
& 0x40) {
6187 imm
|= 0x3fc0000000000000ULL
;
6189 imm
|= 0x4000000000000000ULL
;
6192 imm
= (abcdefgh
& 0x3f) << 19;
6193 if (abcdefgh
& 0x80) {
6196 if (abcdefgh
& 0x40) {
6207 if (cmode_3_1
!= 7 && is_neg
) {
6211 tcg_imm
= tcg_const_i64(imm
);
6212 tcg_rd
= new_tmp_a64(s
);
6214 for (i
= 0; i
< 2; i
++) {
6215 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6217 if (i
== 1 && !is_q
) {
6218 /* non-quad ops clear high half of vector */
6219 tcg_gen_movi_i64(tcg_rd
, 0);
6220 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6221 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6224 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6227 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6231 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6233 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6236 tcg_temp_free_i64(tcg_imm
);
6239 /* AdvSIMD scalar copy
6240 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6241 * +-----+----+-----------------+------+---+------+---+------+------+
6242 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6243 * +-----+----+-----------------+------+---+------+---+------+------+
6245 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6247 int rd
= extract32(insn
, 0, 5);
6248 int rn
= extract32(insn
, 5, 5);
6249 int imm4
= extract32(insn
, 11, 4);
6250 int imm5
= extract32(insn
, 16, 5);
6251 int op
= extract32(insn
, 29, 1);
6253 if (op
!= 0 || imm4
!= 0) {
6254 unallocated_encoding(s
);
6258 /* DUP (element, scalar) */
6259 handle_simd_dupes(s
, rd
, rn
, imm5
);
6262 /* AdvSIMD scalar pairwise
6263 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6264 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6265 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6266 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6268 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6270 int u
= extract32(insn
, 29, 1);
6271 int size
= extract32(insn
, 22, 2);
6272 int opcode
= extract32(insn
, 12, 5);
6273 int rn
= extract32(insn
, 5, 5);
6274 int rd
= extract32(insn
, 0, 5);
6277 /* For some ops (the FP ones), size[1] is part of the encoding.
6278 * For ADDP strictly it is not but size[1] is always 1 for valid
6281 opcode
|= (extract32(size
, 1, 1) << 5);
6284 case 0x3b: /* ADDP */
6285 if (u
|| size
!= 3) {
6286 unallocated_encoding(s
);
6289 if (!fp_access_check(s
)) {
6295 case 0xc: /* FMAXNMP */
6296 case 0xd: /* FADDP */
6297 case 0xf: /* FMAXP */
6298 case 0x2c: /* FMINNMP */
6299 case 0x2f: /* FMINP */
6300 /* FP op, size[0] is 32 or 64 bit */
6302 unallocated_encoding(s
);
6305 if (!fp_access_check(s
)) {
6309 size
= extract32(size
, 0, 1) ? 3 : 2;
6310 fpst
= get_fpstatus_ptr();
6313 unallocated_encoding(s
);
6318 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6319 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6320 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6322 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6323 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6326 case 0x3b: /* ADDP */
6327 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6329 case 0xc: /* FMAXNMP */
6330 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6332 case 0xd: /* FADDP */
6333 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6335 case 0xf: /* FMAXP */
6336 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6338 case 0x2c: /* FMINNMP */
6339 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6341 case 0x2f: /* FMINP */
6342 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6345 g_assert_not_reached();
6348 write_fp_dreg(s
, rd
, tcg_res
);
6350 tcg_temp_free_i64(tcg_op1
);
6351 tcg_temp_free_i64(tcg_op2
);
6352 tcg_temp_free_i64(tcg_res
);
6354 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6355 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6356 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6358 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6359 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6362 case 0xc: /* FMAXNMP */
6363 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6365 case 0xd: /* FADDP */
6366 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6368 case 0xf: /* FMAXP */
6369 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6371 case 0x2c: /* FMINNMP */
6372 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6374 case 0x2f: /* FMINP */
6375 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6378 g_assert_not_reached();
6381 write_fp_sreg(s
, rd
, tcg_res
);
6383 tcg_temp_free_i32(tcg_op1
);
6384 tcg_temp_free_i32(tcg_op2
);
6385 tcg_temp_free_i32(tcg_res
);
6389 tcg_temp_free_ptr(fpst
);
6394 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6396 * This code is handles the common shifting code and is used by both
6397 * the vector and scalar code.
6399 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6400 TCGv_i64 tcg_rnd
, bool accumulate
,
6401 bool is_u
, int size
, int shift
)
6403 bool extended_result
= false;
6404 bool round
= tcg_rnd
!= NULL
;
6406 TCGv_i64 tcg_src_hi
;
6408 if (round
&& size
== 3) {
6409 extended_result
= true;
6410 ext_lshift
= 64 - shift
;
6411 tcg_src_hi
= tcg_temp_new_i64();
6412 } else if (shift
== 64) {
6413 if (!accumulate
&& is_u
) {
6414 /* result is zero */
6415 tcg_gen_movi_i64(tcg_res
, 0);
6420 /* Deal with the rounding step */
6422 if (extended_result
) {
6423 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6425 /* take care of sign extending tcg_res */
6426 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6427 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6428 tcg_src
, tcg_src_hi
,
6431 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6435 tcg_temp_free_i64(tcg_zero
);
6437 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6441 /* Now do the shift right */
6442 if (round
&& extended_result
) {
6443 /* extended case, >64 bit precision required */
6444 if (ext_lshift
== 0) {
6445 /* special case, only high bits matter */
6446 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6448 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6449 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6450 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6455 /* essentially shifting in 64 zeros */
6456 tcg_gen_movi_i64(tcg_src
, 0);
6458 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6462 /* effectively extending the sign-bit */
6463 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6465 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6471 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6473 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6476 if (extended_result
) {
6477 tcg_temp_free_i64(tcg_src_hi
);
6481 /* Common SHL/SLI - Shift left with an optional insert */
6482 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6483 bool insert
, int shift
)
6485 if (insert
) { /* SLI */
6486 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6488 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6492 /* SRI: shift right with insert */
6493 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6494 int size
, int shift
)
6496 int esize
= 8 << size
;
6498 /* shift count same as element size is valid but does nothing;
6499 * special case to avoid potential shift by 64.
6501 if (shift
!= esize
) {
6502 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6503 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6507 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6508 static void handle_scalar_simd_shri(DisasContext
*s
,
6509 bool is_u
, int immh
, int immb
,
6510 int opcode
, int rn
, int rd
)
6513 int immhb
= immh
<< 3 | immb
;
6514 int shift
= 2 * (8 << size
) - immhb
;
6515 bool accumulate
= false;
6517 bool insert
= false;
6522 if (!extract32(immh
, 3, 1)) {
6523 unallocated_encoding(s
);
6527 if (!fp_access_check(s
)) {
6532 case 0x02: /* SSRA / USRA (accumulate) */
6535 case 0x04: /* SRSHR / URSHR (rounding) */
6538 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6539 accumulate
= round
= true;
6541 case 0x08: /* SRI */
6547 uint64_t round_const
= 1ULL << (shift
- 1);
6548 tcg_round
= tcg_const_i64(round_const
);
6553 tcg_rn
= read_fp_dreg(s
, rn
);
6554 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6557 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6559 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6560 accumulate
, is_u
, size
, shift
);
6563 write_fp_dreg(s
, rd
, tcg_rd
);
6565 tcg_temp_free_i64(tcg_rn
);
6566 tcg_temp_free_i64(tcg_rd
);
6568 tcg_temp_free_i64(tcg_round
);
6572 /* SHL/SLI - Scalar shift left */
6573 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6574 int immh
, int immb
, int opcode
,
6577 int size
= 32 - clz32(immh
) - 1;
6578 int immhb
= immh
<< 3 | immb
;
6579 int shift
= immhb
- (8 << size
);
6580 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6581 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6583 if (!extract32(immh
, 3, 1)) {
6584 unallocated_encoding(s
);
6588 if (!fp_access_check(s
)) {
6592 tcg_rn
= read_fp_dreg(s
, rn
);
6593 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6595 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6597 write_fp_dreg(s
, rd
, tcg_rd
);
6599 tcg_temp_free_i64(tcg_rn
);
6600 tcg_temp_free_i64(tcg_rd
);
6603 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6604 * (signed/unsigned) narrowing */
6605 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6606 bool is_u_shift
, bool is_u_narrow
,
6607 int immh
, int immb
, int opcode
,
6610 int immhb
= immh
<< 3 | immb
;
6611 int size
= 32 - clz32(immh
) - 1;
6612 int esize
= 8 << size
;
6613 int shift
= (2 * esize
) - immhb
;
6614 int elements
= is_scalar
? 1 : (64 / esize
);
6615 bool round
= extract32(opcode
, 0, 1);
6616 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6617 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6618 TCGv_i32 tcg_rd_narrowed
;
6621 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6622 { gen_helper_neon_narrow_sat_s8
,
6623 gen_helper_neon_unarrow_sat8
},
6624 { gen_helper_neon_narrow_sat_s16
,
6625 gen_helper_neon_unarrow_sat16
},
6626 { gen_helper_neon_narrow_sat_s32
,
6627 gen_helper_neon_unarrow_sat32
},
6630 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6631 gen_helper_neon_narrow_sat_u8
,
6632 gen_helper_neon_narrow_sat_u16
,
6633 gen_helper_neon_narrow_sat_u32
,
6636 NeonGenNarrowEnvFn
*narrowfn
;
6642 if (extract32(immh
, 3, 1)) {
6643 unallocated_encoding(s
);
6647 if (!fp_access_check(s
)) {
6652 narrowfn
= unsigned_narrow_fns
[size
];
6654 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6657 tcg_rn
= tcg_temp_new_i64();
6658 tcg_rd
= tcg_temp_new_i64();
6659 tcg_rd_narrowed
= tcg_temp_new_i32();
6660 tcg_final
= tcg_const_i64(0);
6663 uint64_t round_const
= 1ULL << (shift
- 1);
6664 tcg_round
= tcg_const_i64(round_const
);
6669 for (i
= 0; i
< elements
; i
++) {
6670 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6671 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6672 false, is_u_shift
, size
+1, shift
);
6673 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6674 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6675 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6679 clear_vec_high(s
, rd
);
6680 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6682 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6686 tcg_temp_free_i64(tcg_round
);
6688 tcg_temp_free_i64(tcg_rn
);
6689 tcg_temp_free_i64(tcg_rd
);
6690 tcg_temp_free_i32(tcg_rd_narrowed
);
6691 tcg_temp_free_i64(tcg_final
);
6695 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6696 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6697 bool src_unsigned
, bool dst_unsigned
,
6698 int immh
, int immb
, int rn
, int rd
)
6700 int immhb
= immh
<< 3 | immb
;
6701 int size
= 32 - clz32(immh
) - 1;
6702 int shift
= immhb
- (8 << size
);
6706 assert(!(scalar
&& is_q
));
6709 if (!is_q
&& extract32(immh
, 3, 1)) {
6710 unallocated_encoding(s
);
6714 /* Since we use the variable-shift helpers we must
6715 * replicate the shift count into each element of
6716 * the tcg_shift value.
6720 shift
|= shift
<< 8;
6723 shift
|= shift
<< 16;
6729 g_assert_not_reached();
6733 if (!fp_access_check(s
)) {
6738 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6739 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6740 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6741 { NULL
, gen_helper_neon_qshl_u64
},
6743 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6744 int maxpass
= is_q
? 2 : 1;
6746 for (pass
= 0; pass
< maxpass
; pass
++) {
6747 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6749 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6750 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6751 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6753 tcg_temp_free_i64(tcg_op
);
6755 tcg_temp_free_i64(tcg_shift
);
6758 clear_vec_high(s
, rd
);
6761 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6762 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6764 { gen_helper_neon_qshl_s8
,
6765 gen_helper_neon_qshl_s16
,
6766 gen_helper_neon_qshl_s32
},
6767 { gen_helper_neon_qshlu_s8
,
6768 gen_helper_neon_qshlu_s16
,
6769 gen_helper_neon_qshlu_s32
}
6771 { NULL
, NULL
, NULL
},
6772 { gen_helper_neon_qshl_u8
,
6773 gen_helper_neon_qshl_u16
,
6774 gen_helper_neon_qshl_u32
}
6777 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6778 TCGMemOp memop
= scalar
? size
: MO_32
;
6779 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6781 for (pass
= 0; pass
< maxpass
; pass
++) {
6782 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6784 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6785 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6789 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6792 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6797 g_assert_not_reached();
6799 write_fp_sreg(s
, rd
, tcg_op
);
6801 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6804 tcg_temp_free_i32(tcg_op
);
6806 tcg_temp_free_i32(tcg_shift
);
6808 if (!is_q
&& !scalar
) {
6809 clear_vec_high(s
, rd
);
6814 /* Common vector code for handling integer to FP conversion */
6815 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6816 int elements
, int is_signed
,
6817 int fracbits
, int size
)
6819 bool is_double
= size
== 3 ? true : false;
6820 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6821 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6822 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6823 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6826 for (pass
= 0; pass
< elements
; pass
++) {
6827 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6830 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6832 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6833 tcg_shift
, tcg_fpst
);
6835 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6836 tcg_shift
, tcg_fpst
);
6838 if (elements
== 1) {
6839 write_fp_dreg(s
, rd
, tcg_double
);
6841 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6843 tcg_temp_free_i64(tcg_double
);
6845 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6847 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6848 tcg_shift
, tcg_fpst
);
6850 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6851 tcg_shift
, tcg_fpst
);
6853 if (elements
== 1) {
6854 write_fp_sreg(s
, rd
, tcg_single
);
6856 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6858 tcg_temp_free_i32(tcg_single
);
6862 if (!is_double
&& elements
== 2) {
6863 clear_vec_high(s
, rd
);
6866 tcg_temp_free_i64(tcg_int
);
6867 tcg_temp_free_ptr(tcg_fpst
);
6868 tcg_temp_free_i32(tcg_shift
);
6871 /* UCVTF/SCVTF - Integer to FP conversion */
6872 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6873 bool is_q
, bool is_u
,
6874 int immh
, int immb
, int opcode
,
6877 bool is_double
= extract32(immh
, 3, 1);
6878 int size
= is_double
? MO_64
: MO_32
;
6880 int immhb
= immh
<< 3 | immb
;
6881 int fracbits
= (is_double
? 128 : 64) - immhb
;
6883 if (!extract32(immh
, 2, 2)) {
6884 unallocated_encoding(s
);
6891 elements
= is_double
? 2 : is_q
? 4 : 2;
6892 if (is_double
&& !is_q
) {
6893 unallocated_encoding(s
);
6898 if (!fp_access_check(s
)) {
6902 /* immh == 0 would be a failure of the decode logic */
6905 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6908 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6909 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6910 bool is_q
, bool is_u
,
6911 int immh
, int immb
, int rn
, int rd
)
6913 bool is_double
= extract32(immh
, 3, 1);
6914 int immhb
= immh
<< 3 | immb
;
6915 int fracbits
= (is_double
? 128 : 64) - immhb
;
6917 TCGv_ptr tcg_fpstatus
;
6918 TCGv_i32 tcg_rmode
, tcg_shift
;
6920 if (!extract32(immh
, 2, 2)) {
6921 unallocated_encoding(s
);
6925 if (!is_scalar
&& !is_q
&& is_double
) {
6926 unallocated_encoding(s
);
6930 if (!fp_access_check(s
)) {
6934 assert(!(is_scalar
&& is_q
));
6936 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6937 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6938 tcg_fpstatus
= get_fpstatus_ptr();
6939 tcg_shift
= tcg_const_i32(fracbits
);
6942 int maxpass
= is_scalar
? 1 : 2;
6944 for (pass
= 0; pass
< maxpass
; pass
++) {
6945 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6947 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6949 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6951 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6953 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6954 tcg_temp_free_i64(tcg_op
);
6957 clear_vec_high(s
, rd
);
6960 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6961 for (pass
= 0; pass
< maxpass
; pass
++) {
6962 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6964 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6966 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6968 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6971 write_fp_sreg(s
, rd
, tcg_op
);
6973 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6975 tcg_temp_free_i32(tcg_op
);
6977 if (!is_q
&& !is_scalar
) {
6978 clear_vec_high(s
, rd
);
6982 tcg_temp_free_ptr(tcg_fpstatus
);
6983 tcg_temp_free_i32(tcg_shift
);
6984 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6985 tcg_temp_free_i32(tcg_rmode
);
6988 /* AdvSIMD scalar shift by immediate
6989 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6990 * +-----+---+-------------+------+------+--------+---+------+------+
6991 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6992 * +-----+---+-------------+------+------+--------+---+------+------+
6994 * This is the scalar version so it works on a fixed sized registers
6996 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6998 int rd
= extract32(insn
, 0, 5);
6999 int rn
= extract32(insn
, 5, 5);
7000 int opcode
= extract32(insn
, 11, 5);
7001 int immb
= extract32(insn
, 16, 3);
7002 int immh
= extract32(insn
, 19, 4);
7003 bool is_u
= extract32(insn
, 29, 1);
7006 unallocated_encoding(s
);
7011 case 0x08: /* SRI */
7013 unallocated_encoding(s
);
7017 case 0x00: /* SSHR / USHR */
7018 case 0x02: /* SSRA / USRA */
7019 case 0x04: /* SRSHR / URSHR */
7020 case 0x06: /* SRSRA / URSRA */
7021 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7023 case 0x0a: /* SHL / SLI */
7024 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7026 case 0x1c: /* SCVTF, UCVTF */
7027 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7030 case 0x10: /* SQSHRUN, SQSHRUN2 */
7031 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7033 unallocated_encoding(s
);
7036 handle_vec_simd_sqshrn(s
, true, false, false, true,
7037 immh
, immb
, opcode
, rn
, rd
);
7039 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7040 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7041 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7042 immh
, immb
, opcode
, rn
, rd
);
7044 case 0xc: /* SQSHLU */
7046 unallocated_encoding(s
);
7049 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7051 case 0xe: /* SQSHL, UQSHL */
7052 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7054 case 0x1f: /* FCVTZS, FCVTZU */
7055 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7058 unallocated_encoding(s
);
7063 /* AdvSIMD scalar three different
7064 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7065 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7066 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7067 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7069 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7071 bool is_u
= extract32(insn
, 29, 1);
7072 int size
= extract32(insn
, 22, 2);
7073 int opcode
= extract32(insn
, 12, 4);
7074 int rm
= extract32(insn
, 16, 5);
7075 int rn
= extract32(insn
, 5, 5);
7076 int rd
= extract32(insn
, 0, 5);
7079 unallocated_encoding(s
);
7084 case 0x9: /* SQDMLAL, SQDMLAL2 */
7085 case 0xb: /* SQDMLSL, SQDMLSL2 */
7086 case 0xd: /* SQDMULL, SQDMULL2 */
7087 if (size
== 0 || size
== 3) {
7088 unallocated_encoding(s
);
7093 unallocated_encoding(s
);
7097 if (!fp_access_check(s
)) {
7102 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7103 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7104 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7106 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7107 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7109 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7110 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7113 case 0xd: /* SQDMULL, SQDMULL2 */
7115 case 0xb: /* SQDMLSL, SQDMLSL2 */
7116 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7118 case 0x9: /* SQDMLAL, SQDMLAL2 */
7119 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7120 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7124 g_assert_not_reached();
7127 write_fp_dreg(s
, rd
, tcg_res
);
7129 tcg_temp_free_i64(tcg_op1
);
7130 tcg_temp_free_i64(tcg_op2
);
7131 tcg_temp_free_i64(tcg_res
);
7133 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7134 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7135 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7137 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7138 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7140 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7141 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7144 case 0xd: /* SQDMULL, SQDMULL2 */
7146 case 0xb: /* SQDMLSL, SQDMLSL2 */
7147 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7149 case 0x9: /* SQDMLAL, SQDMLAL2 */
7151 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7152 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7153 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7155 tcg_temp_free_i64(tcg_op3
);
7159 g_assert_not_reached();
7162 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7163 write_fp_dreg(s
, rd
, tcg_res
);
7165 tcg_temp_free_i32(tcg_op1
);
7166 tcg_temp_free_i32(tcg_op2
);
7167 tcg_temp_free_i64(tcg_res
);
7171 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7172 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7174 /* Handle 64x64->64 opcodes which are shared between the scalar
7175 * and vector 3-same groups. We cover every opcode where size == 3
7176 * is valid in either the three-reg-same (integer, not pairwise)
7177 * or scalar-three-reg-same groups. (Some opcodes are not yet
7183 case 0x1: /* SQADD */
7185 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7187 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7190 case 0x5: /* SQSUB */
7192 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7194 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7197 case 0x6: /* CMGT, CMHI */
7198 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7199 * We implement this using setcond (test) and then negating.
7201 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7203 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7204 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7206 case 0x7: /* CMGE, CMHS */
7207 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7209 case 0x11: /* CMTST, CMEQ */
7214 /* CMTST : test is "if (X & Y != 0)". */
7215 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7216 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7217 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7219 case 0x8: /* SSHL, USHL */
7221 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7223 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7226 case 0x9: /* SQSHL, UQSHL */
7228 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7230 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7233 case 0xa: /* SRSHL, URSHL */
7235 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7237 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7240 case 0xb: /* SQRSHL, UQRSHL */
7242 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7244 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7247 case 0x10: /* ADD, SUB */
7249 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7251 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7255 g_assert_not_reached();
7259 /* Handle the 3-same-operands float operations; shared by the scalar
7260 * and vector encodings. The caller must filter out any encodings
7261 * not allocated for the encoding it is dealing with.
7263 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7264 int fpopcode
, int rd
, int rn
, int rm
)
7267 TCGv_ptr fpst
= get_fpstatus_ptr();
7269 for (pass
= 0; pass
< elements
; pass
++) {
7272 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7273 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7274 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7276 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7277 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7280 case 0x39: /* FMLS */
7281 /* As usual for ARM, separate negation for fused multiply-add */
7282 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7284 case 0x19: /* FMLA */
7285 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7286 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7289 case 0x18: /* FMAXNM */
7290 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7292 case 0x1a: /* FADD */
7293 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7295 case 0x1b: /* FMULX */
7296 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7298 case 0x1c: /* FCMEQ */
7299 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7301 case 0x1e: /* FMAX */
7302 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7304 case 0x1f: /* FRECPS */
7305 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7307 case 0x38: /* FMINNM */
7308 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7310 case 0x3a: /* FSUB */
7311 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7313 case 0x3e: /* FMIN */
7314 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7316 case 0x3f: /* FRSQRTS */
7317 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7319 case 0x5b: /* FMUL */
7320 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7322 case 0x5c: /* FCMGE */
7323 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7325 case 0x5d: /* FACGE */
7326 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7328 case 0x5f: /* FDIV */
7329 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7331 case 0x7a: /* FABD */
7332 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7333 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7335 case 0x7c: /* FCMGT */
7336 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7338 case 0x7d: /* FACGT */
7339 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7342 g_assert_not_reached();
7345 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7347 tcg_temp_free_i64(tcg_res
);
7348 tcg_temp_free_i64(tcg_op1
);
7349 tcg_temp_free_i64(tcg_op2
);
7352 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7353 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7354 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7356 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7357 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7360 case 0x39: /* FMLS */
7361 /* As usual for ARM, separate negation for fused multiply-add */
7362 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7364 case 0x19: /* FMLA */
7365 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7366 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7369 case 0x1a: /* FADD */
7370 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7372 case 0x1b: /* FMULX */
7373 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7375 case 0x1c: /* FCMEQ */
7376 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7378 case 0x1e: /* FMAX */
7379 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7381 case 0x1f: /* FRECPS */
7382 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7384 case 0x18: /* FMAXNM */
7385 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7387 case 0x38: /* FMINNM */
7388 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7390 case 0x3a: /* FSUB */
7391 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7393 case 0x3e: /* FMIN */
7394 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7396 case 0x3f: /* FRSQRTS */
7397 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7399 case 0x5b: /* FMUL */
7400 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7402 case 0x5c: /* FCMGE */
7403 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7405 case 0x5d: /* FACGE */
7406 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7408 case 0x5f: /* FDIV */
7409 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7411 case 0x7a: /* FABD */
7412 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7413 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7415 case 0x7c: /* FCMGT */
7416 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7418 case 0x7d: /* FACGT */
7419 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7422 g_assert_not_reached();
7425 if (elements
== 1) {
7426 /* scalar single so clear high part */
7427 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7429 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7430 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7431 tcg_temp_free_i64(tcg_tmp
);
7433 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7436 tcg_temp_free_i32(tcg_res
);
7437 tcg_temp_free_i32(tcg_op1
);
7438 tcg_temp_free_i32(tcg_op2
);
7442 tcg_temp_free_ptr(fpst
);
7444 if ((elements
<< size
) < 4) {
7445 /* scalar, or non-quad vector op */
7446 clear_vec_high(s
, rd
);
7450 /* AdvSIMD scalar three same
7451 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7452 * +-----+---+-----------+------+---+------+--------+---+------+------+
7453 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7454 * +-----+---+-----------+------+---+------+--------+---+------+------+
7456 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7458 int rd
= extract32(insn
, 0, 5);
7459 int rn
= extract32(insn
, 5, 5);
7460 int opcode
= extract32(insn
, 11, 5);
7461 int rm
= extract32(insn
, 16, 5);
7462 int size
= extract32(insn
, 22, 2);
7463 bool u
= extract32(insn
, 29, 1);
7466 if (opcode
>= 0x18) {
7467 /* Floating point: U, size[1] and opcode indicate operation */
7468 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7470 case 0x1b: /* FMULX */
7471 case 0x1f: /* FRECPS */
7472 case 0x3f: /* FRSQRTS */
7473 case 0x5d: /* FACGE */
7474 case 0x7d: /* FACGT */
7475 case 0x1c: /* FCMEQ */
7476 case 0x5c: /* FCMGE */
7477 case 0x7c: /* FCMGT */
7478 case 0x7a: /* FABD */
7481 unallocated_encoding(s
);
7485 if (!fp_access_check(s
)) {
7489 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7494 case 0x1: /* SQADD, UQADD */
7495 case 0x5: /* SQSUB, UQSUB */
7496 case 0x9: /* SQSHL, UQSHL */
7497 case 0xb: /* SQRSHL, UQRSHL */
7499 case 0x8: /* SSHL, USHL */
7500 case 0xa: /* SRSHL, URSHL */
7501 case 0x6: /* CMGT, CMHI */
7502 case 0x7: /* CMGE, CMHS */
7503 case 0x11: /* CMTST, CMEQ */
7504 case 0x10: /* ADD, SUB (vector) */
7506 unallocated_encoding(s
);
7510 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7511 if (size
!= 1 && size
!= 2) {
7512 unallocated_encoding(s
);
7517 unallocated_encoding(s
);
7521 if (!fp_access_check(s
)) {
7525 tcg_rd
= tcg_temp_new_i64();
7528 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7529 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7531 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7532 tcg_temp_free_i64(tcg_rn
);
7533 tcg_temp_free_i64(tcg_rm
);
7535 /* Do a single operation on the lowest element in the vector.
7536 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7537 * no side effects for all these operations.
7538 * OPTME: special-purpose helpers would avoid doing some
7539 * unnecessary work in the helper for the 8 and 16 bit cases.
7541 NeonGenTwoOpEnvFn
*genenvfn
;
7542 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7543 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7544 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7546 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7547 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7550 case 0x1: /* SQADD, UQADD */
7552 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7553 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7554 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7555 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7557 genenvfn
= fns
[size
][u
];
7560 case 0x5: /* SQSUB, UQSUB */
7562 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7563 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7564 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7565 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7567 genenvfn
= fns
[size
][u
];
7570 case 0x9: /* SQSHL, UQSHL */
7572 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7573 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7574 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7575 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7577 genenvfn
= fns
[size
][u
];
7580 case 0xb: /* SQRSHL, UQRSHL */
7582 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7583 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7584 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7585 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7587 genenvfn
= fns
[size
][u
];
7590 case 0x16: /* SQDMULH, SQRDMULH */
7592 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7593 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7594 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7596 assert(size
== 1 || size
== 2);
7597 genenvfn
= fns
[size
- 1][u
];
7601 g_assert_not_reached();
7604 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7605 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7606 tcg_temp_free_i32(tcg_rd32
);
7607 tcg_temp_free_i32(tcg_rn
);
7608 tcg_temp_free_i32(tcg_rm
);
7611 write_fp_dreg(s
, rd
, tcg_rd
);
7613 tcg_temp_free_i64(tcg_rd
);
7616 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7617 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7618 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7620 /* Handle 64->64 opcodes which are shared between the scalar and
7621 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7622 * is valid in either group and also the double-precision fp ops.
7623 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7629 case 0x4: /* CLS, CLZ */
7631 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7633 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7637 /* This opcode is shared with CNT and RBIT but we have earlier
7638 * enforced that size == 3 if and only if this is the NOT insn.
7640 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7642 case 0x7: /* SQABS, SQNEG */
7644 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7646 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7649 case 0xa: /* CMLT */
7650 /* 64 bit integer comparison against zero, result is
7651 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7656 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7657 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7659 case 0x8: /* CMGT, CMGE */
7660 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7662 case 0x9: /* CMEQ, CMLE */
7663 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7665 case 0xb: /* ABS, NEG */
7667 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7669 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7670 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7671 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7673 tcg_temp_free_i64(tcg_zero
);
7676 case 0x2f: /* FABS */
7677 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7679 case 0x6f: /* FNEG */
7680 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7682 case 0x7f: /* FSQRT */
7683 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7685 case 0x1a: /* FCVTNS */
7686 case 0x1b: /* FCVTMS */
7687 case 0x1c: /* FCVTAS */
7688 case 0x3a: /* FCVTPS */
7689 case 0x3b: /* FCVTZS */
7691 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7692 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7693 tcg_temp_free_i32(tcg_shift
);
7696 case 0x5a: /* FCVTNU */
7697 case 0x5b: /* FCVTMU */
7698 case 0x5c: /* FCVTAU */
7699 case 0x7a: /* FCVTPU */
7700 case 0x7b: /* FCVTZU */
7702 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7703 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7704 tcg_temp_free_i32(tcg_shift
);
7707 case 0x18: /* FRINTN */
7708 case 0x19: /* FRINTM */
7709 case 0x38: /* FRINTP */
7710 case 0x39: /* FRINTZ */
7711 case 0x58: /* FRINTA */
7712 case 0x79: /* FRINTI */
7713 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7715 case 0x59: /* FRINTX */
7716 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7719 g_assert_not_reached();
7723 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7724 bool is_scalar
, bool is_u
, bool is_q
,
7725 int size
, int rn
, int rd
)
7727 bool is_double
= (size
== 3);
7730 if (!fp_access_check(s
)) {
7734 fpst
= get_fpstatus_ptr();
7737 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7738 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7739 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7740 NeonGenTwoDoubleOPFn
*genfn
;
7745 case 0x2e: /* FCMLT (zero) */
7748 case 0x2c: /* FCMGT (zero) */
7749 genfn
= gen_helper_neon_cgt_f64
;
7751 case 0x2d: /* FCMEQ (zero) */
7752 genfn
= gen_helper_neon_ceq_f64
;
7754 case 0x6d: /* FCMLE (zero) */
7757 case 0x6c: /* FCMGE (zero) */
7758 genfn
= gen_helper_neon_cge_f64
;
7761 g_assert_not_reached();
7764 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7765 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7767 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7769 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7771 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7774 clear_vec_high(s
, rd
);
7777 tcg_temp_free_i64(tcg_res
);
7778 tcg_temp_free_i64(tcg_zero
);
7779 tcg_temp_free_i64(tcg_op
);
7781 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7782 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7783 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7784 NeonGenTwoSingleOPFn
*genfn
;
7786 int pass
, maxpasses
;
7789 case 0x2e: /* FCMLT (zero) */
7792 case 0x2c: /* FCMGT (zero) */
7793 genfn
= gen_helper_neon_cgt_f32
;
7795 case 0x2d: /* FCMEQ (zero) */
7796 genfn
= gen_helper_neon_ceq_f32
;
7798 case 0x6d: /* FCMLE (zero) */
7801 case 0x6c: /* FCMGE (zero) */
7802 genfn
= gen_helper_neon_cge_f32
;
7805 g_assert_not_reached();
7811 maxpasses
= is_q
? 4 : 2;
7814 for (pass
= 0; pass
< maxpasses
; pass
++) {
7815 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7817 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7819 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7822 write_fp_sreg(s
, rd
, tcg_res
);
7824 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7827 tcg_temp_free_i32(tcg_res
);
7828 tcg_temp_free_i32(tcg_zero
);
7829 tcg_temp_free_i32(tcg_op
);
7830 if (!is_q
&& !is_scalar
) {
7831 clear_vec_high(s
, rd
);
7835 tcg_temp_free_ptr(fpst
);
7838 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7839 bool is_scalar
, bool is_u
, bool is_q
,
7840 int size
, int rn
, int rd
)
7842 bool is_double
= (size
== 3);
7843 TCGv_ptr fpst
= get_fpstatus_ptr();
7846 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7847 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7850 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7851 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7853 case 0x3d: /* FRECPE */
7854 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7856 case 0x3f: /* FRECPX */
7857 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7859 case 0x7d: /* FRSQRTE */
7860 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7863 g_assert_not_reached();
7865 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7868 clear_vec_high(s
, rd
);
7871 tcg_temp_free_i64(tcg_res
);
7872 tcg_temp_free_i64(tcg_op
);
7874 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7875 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7876 int pass
, maxpasses
;
7881 maxpasses
= is_q
? 4 : 2;
7884 for (pass
= 0; pass
< maxpasses
; pass
++) {
7885 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7888 case 0x3c: /* URECPE */
7889 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7891 case 0x3d: /* FRECPE */
7892 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7894 case 0x3f: /* FRECPX */
7895 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7897 case 0x7d: /* FRSQRTE */
7898 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7901 g_assert_not_reached();
7905 write_fp_sreg(s
, rd
, tcg_res
);
7907 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7910 tcg_temp_free_i32(tcg_res
);
7911 tcg_temp_free_i32(tcg_op
);
7912 if (!is_q
&& !is_scalar
) {
7913 clear_vec_high(s
, rd
);
7916 tcg_temp_free_ptr(fpst
);
7919 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7920 int opcode
, bool u
, bool is_q
,
7921 int size
, int rn
, int rd
)
7923 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7924 * in the source becomes a size element in the destination).
7927 TCGv_i32 tcg_res
[2];
7928 int destelt
= is_q
? 2 : 0;
7929 int passes
= scalar
? 1 : 2;
7932 tcg_res
[1] = tcg_const_i32(0);
7935 for (pass
= 0; pass
< passes
; pass
++) {
7936 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7937 NeonGenNarrowFn
*genfn
= NULL
;
7938 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7941 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7943 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7945 tcg_res
[pass
] = tcg_temp_new_i32();
7948 case 0x12: /* XTN, SQXTUN */
7950 static NeonGenNarrowFn
* const xtnfns
[3] = {
7951 gen_helper_neon_narrow_u8
,
7952 gen_helper_neon_narrow_u16
,
7953 tcg_gen_extrl_i64_i32
,
7955 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7956 gen_helper_neon_unarrow_sat8
,
7957 gen_helper_neon_unarrow_sat16
,
7958 gen_helper_neon_unarrow_sat32
,
7961 genenvfn
= sqxtunfns
[size
];
7963 genfn
= xtnfns
[size
];
7967 case 0x14: /* SQXTN, UQXTN */
7969 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7970 { gen_helper_neon_narrow_sat_s8
,
7971 gen_helper_neon_narrow_sat_u8
},
7972 { gen_helper_neon_narrow_sat_s16
,
7973 gen_helper_neon_narrow_sat_u16
},
7974 { gen_helper_neon_narrow_sat_s32
,
7975 gen_helper_neon_narrow_sat_u32
},
7977 genenvfn
= fns
[size
][u
];
7980 case 0x16: /* FCVTN, FCVTN2 */
7981 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7983 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7985 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7986 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7987 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7988 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7989 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7990 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7991 tcg_temp_free_i32(tcg_lo
);
7992 tcg_temp_free_i32(tcg_hi
);
7995 case 0x56: /* FCVTXN, FCVTXN2 */
7996 /* 64 bit to 32 bit float conversion
7997 * with von Neumann rounding (round to odd)
8000 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
8003 g_assert_not_reached();
8007 genfn(tcg_res
[pass
], tcg_op
);
8008 } else if (genenvfn
) {
8009 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
8012 tcg_temp_free_i64(tcg_op
);
8015 for (pass
= 0; pass
< 2; pass
++) {
8016 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
8017 tcg_temp_free_i32(tcg_res
[pass
]);
8020 clear_vec_high(s
, rd
);
8024 /* Remaining saturating accumulating ops */
8025 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
8026 bool is_q
, int size
, int rn
, int rd
)
8028 bool is_double
= (size
== 3);
8031 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
8032 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8035 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8036 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8037 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8039 if (is_u
) { /* USQADD */
8040 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8041 } else { /* SUQADD */
8042 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8044 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8047 clear_vec_high(s
, rd
);
8050 tcg_temp_free_i64(tcg_rd
);
8051 tcg_temp_free_i64(tcg_rn
);
8053 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8054 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8055 int pass
, maxpasses
;
8060 maxpasses
= is_q
? 4 : 2;
8063 for (pass
= 0; pass
< maxpasses
; pass
++) {
8065 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8066 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8068 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8069 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8072 if (is_u
) { /* USQADD */
8075 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8078 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8081 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8084 g_assert_not_reached();
8086 } else { /* SUQADD */
8089 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8092 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8095 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8098 g_assert_not_reached();
8103 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8104 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8105 tcg_temp_free_i64(tcg_zero
);
8107 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8111 clear_vec_high(s
, rd
);
8114 tcg_temp_free_i32(tcg_rd
);
8115 tcg_temp_free_i32(tcg_rn
);
8119 /* AdvSIMD scalar two reg misc
8120 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8121 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8122 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8123 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8125 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8127 int rd
= extract32(insn
, 0, 5);
8128 int rn
= extract32(insn
, 5, 5);
8129 int opcode
= extract32(insn
, 12, 5);
8130 int size
= extract32(insn
, 22, 2);
8131 bool u
= extract32(insn
, 29, 1);
8132 bool is_fcvt
= false;
8135 TCGv_ptr tcg_fpstatus
;
8138 case 0x3: /* USQADD / SUQADD*/
8139 if (!fp_access_check(s
)) {
8142 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8144 case 0x7: /* SQABS / SQNEG */
8146 case 0xa: /* CMLT */
8148 unallocated_encoding(s
);
8152 case 0x8: /* CMGT, CMGE */
8153 case 0x9: /* CMEQ, CMLE */
8154 case 0xb: /* ABS, NEG */
8156 unallocated_encoding(s
);
8160 case 0x12: /* SQXTUN */
8162 unallocated_encoding(s
);
8166 case 0x14: /* SQXTN, UQXTN */
8168 unallocated_encoding(s
);
8171 if (!fp_access_check(s
)) {
8174 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8179 /* Floating point: U, size[1] and opcode indicate operation;
8180 * size[0] indicates single or double precision.
8182 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8183 size
= extract32(size
, 0, 1) ? 3 : 2;
8185 case 0x2c: /* FCMGT (zero) */
8186 case 0x2d: /* FCMEQ (zero) */
8187 case 0x2e: /* FCMLT (zero) */
8188 case 0x6c: /* FCMGE (zero) */
8189 case 0x6d: /* FCMLE (zero) */
8190 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8192 case 0x1d: /* SCVTF */
8193 case 0x5d: /* UCVTF */
8195 bool is_signed
= (opcode
== 0x1d);
8196 if (!fp_access_check(s
)) {
8199 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8202 case 0x3d: /* FRECPE */
8203 case 0x3f: /* FRECPX */
8204 case 0x7d: /* FRSQRTE */
8205 if (!fp_access_check(s
)) {
8208 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8210 case 0x1a: /* FCVTNS */
8211 case 0x1b: /* FCVTMS */
8212 case 0x3a: /* FCVTPS */
8213 case 0x3b: /* FCVTZS */
8214 case 0x5a: /* FCVTNU */
8215 case 0x5b: /* FCVTMU */
8216 case 0x7a: /* FCVTPU */
8217 case 0x7b: /* FCVTZU */
8219 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8221 case 0x1c: /* FCVTAS */
8222 case 0x5c: /* FCVTAU */
8223 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8225 rmode
= FPROUNDING_TIEAWAY
;
8227 case 0x56: /* FCVTXN, FCVTXN2 */
8229 unallocated_encoding(s
);
8232 if (!fp_access_check(s
)) {
8235 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8238 unallocated_encoding(s
);
8243 unallocated_encoding(s
);
8247 if (!fp_access_check(s
)) {
8252 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8253 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8254 tcg_fpstatus
= get_fpstatus_ptr();
8257 tcg_fpstatus
= NULL
;
8261 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8262 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8264 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8265 write_fp_dreg(s
, rd
, tcg_rd
);
8266 tcg_temp_free_i64(tcg_rd
);
8267 tcg_temp_free_i64(tcg_rn
);
8269 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8270 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8272 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8275 case 0x7: /* SQABS, SQNEG */
8277 NeonGenOneOpEnvFn
*genfn
;
8278 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8279 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8280 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8281 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8283 genfn
= fns
[size
][u
];
8284 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8287 case 0x1a: /* FCVTNS */
8288 case 0x1b: /* FCVTMS */
8289 case 0x1c: /* FCVTAS */
8290 case 0x3a: /* FCVTPS */
8291 case 0x3b: /* FCVTZS */
8293 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8294 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8295 tcg_temp_free_i32(tcg_shift
);
8298 case 0x5a: /* FCVTNU */
8299 case 0x5b: /* FCVTMU */
8300 case 0x5c: /* FCVTAU */
8301 case 0x7a: /* FCVTPU */
8302 case 0x7b: /* FCVTZU */
8304 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8305 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8306 tcg_temp_free_i32(tcg_shift
);
8310 g_assert_not_reached();
8313 write_fp_sreg(s
, rd
, tcg_rd
);
8314 tcg_temp_free_i32(tcg_rd
);
8315 tcg_temp_free_i32(tcg_rn
);
8319 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8320 tcg_temp_free_i32(tcg_rmode
);
8321 tcg_temp_free_ptr(tcg_fpstatus
);
8325 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8326 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8327 int immh
, int immb
, int opcode
, int rn
, int rd
)
8329 int size
= 32 - clz32(immh
) - 1;
8330 int immhb
= immh
<< 3 | immb
;
8331 int shift
= 2 * (8 << size
) - immhb
;
8332 bool accumulate
= false;
8334 bool insert
= false;
8335 int dsize
= is_q
? 128 : 64;
8336 int esize
= 8 << size
;
8337 int elements
= dsize
/esize
;
8338 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8339 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8340 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8344 if (extract32(immh
, 3, 1) && !is_q
) {
8345 unallocated_encoding(s
);
8349 if (size
> 3 && !is_q
) {
8350 unallocated_encoding(s
);
8354 if (!fp_access_check(s
)) {
8359 case 0x02: /* SSRA / USRA (accumulate) */
8362 case 0x04: /* SRSHR / URSHR (rounding) */
8365 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8366 accumulate
= round
= true;
8368 case 0x08: /* SRI */
8374 uint64_t round_const
= 1ULL << (shift
- 1);
8375 tcg_round
= tcg_const_i64(round_const
);
8380 for (i
= 0; i
< elements
; i
++) {
8381 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8382 if (accumulate
|| insert
) {
8383 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8387 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8389 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8390 accumulate
, is_u
, size
, shift
);
8393 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8397 clear_vec_high(s
, rd
);
8401 tcg_temp_free_i64(tcg_round
);
8405 /* SHL/SLI - Vector shift left */
8406 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8407 int immh
, int immb
, int opcode
, int rn
, int rd
)
8409 int size
= 32 - clz32(immh
) - 1;
8410 int immhb
= immh
<< 3 | immb
;
8411 int shift
= immhb
- (8 << size
);
8412 int dsize
= is_q
? 128 : 64;
8413 int esize
= 8 << size
;
8414 int elements
= dsize
/esize
;
8415 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8416 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8419 if (extract32(immh
, 3, 1) && !is_q
) {
8420 unallocated_encoding(s
);
8424 if (size
> 3 && !is_q
) {
8425 unallocated_encoding(s
);
8429 if (!fp_access_check(s
)) {
8433 for (i
= 0; i
< elements
; i
++) {
8434 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8436 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8439 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8441 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8445 clear_vec_high(s
, rd
);
8449 /* USHLL/SHLL - Vector shift left with widening */
8450 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8451 int immh
, int immb
, int opcode
, int rn
, int rd
)
8453 int size
= 32 - clz32(immh
) - 1;
8454 int immhb
= immh
<< 3 | immb
;
8455 int shift
= immhb
- (8 << size
);
8457 int esize
= 8 << size
;
8458 int elements
= dsize
/esize
;
8459 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8460 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8464 unallocated_encoding(s
);
8468 if (!fp_access_check(s
)) {
8472 /* For the LL variants the store is larger than the load,
8473 * so if rd == rn we would overwrite parts of our input.
8474 * So load everything right now and use shifts in the main loop.
8476 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8478 for (i
= 0; i
< elements
; i
++) {
8479 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8480 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8481 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8482 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8486 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8487 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8488 int immh
, int immb
, int opcode
, int rn
, int rd
)
8490 int immhb
= immh
<< 3 | immb
;
8491 int size
= 32 - clz32(immh
) - 1;
8493 int esize
= 8 << size
;
8494 int elements
= dsize
/esize
;
8495 int shift
= (2 * esize
) - immhb
;
8496 bool round
= extract32(opcode
, 0, 1);
8497 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8501 if (extract32(immh
, 3, 1)) {
8502 unallocated_encoding(s
);
8506 if (!fp_access_check(s
)) {
8510 tcg_rn
= tcg_temp_new_i64();
8511 tcg_rd
= tcg_temp_new_i64();
8512 tcg_final
= tcg_temp_new_i64();
8513 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8516 uint64_t round_const
= 1ULL << (shift
- 1);
8517 tcg_round
= tcg_const_i64(round_const
);
8522 for (i
= 0; i
< elements
; i
++) {
8523 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8524 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8525 false, true, size
+1, shift
);
8527 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8531 clear_vec_high(s
, rd
);
8532 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8534 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8538 tcg_temp_free_i64(tcg_round
);
8540 tcg_temp_free_i64(tcg_rn
);
8541 tcg_temp_free_i64(tcg_rd
);
8542 tcg_temp_free_i64(tcg_final
);
8547 /* AdvSIMD shift by immediate
8548 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8549 * +---+---+---+-------------+------+------+--------+---+------+------+
8550 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8551 * +---+---+---+-------------+------+------+--------+---+------+------+
8553 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8555 int rd
= extract32(insn
, 0, 5);
8556 int rn
= extract32(insn
, 5, 5);
8557 int opcode
= extract32(insn
, 11, 5);
8558 int immb
= extract32(insn
, 16, 3);
8559 int immh
= extract32(insn
, 19, 4);
8560 bool is_u
= extract32(insn
, 29, 1);
8561 bool is_q
= extract32(insn
, 30, 1);
8564 case 0x08: /* SRI */
8566 unallocated_encoding(s
);
8570 case 0x00: /* SSHR / USHR */
8571 case 0x02: /* SSRA / USRA (accumulate) */
8572 case 0x04: /* SRSHR / URSHR (rounding) */
8573 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8574 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8576 case 0x0a: /* SHL / SLI */
8577 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8579 case 0x10: /* SHRN */
8580 case 0x11: /* RSHRN / SQRSHRUN */
8582 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8585 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8588 case 0x12: /* SQSHRN / UQSHRN */
8589 case 0x13: /* SQRSHRN / UQRSHRN */
8590 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8593 case 0x14: /* SSHLL / USHLL */
8594 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8596 case 0x1c: /* SCVTF / UCVTF */
8597 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8600 case 0xc: /* SQSHLU */
8602 unallocated_encoding(s
);
8605 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8607 case 0xe: /* SQSHL, UQSHL */
8608 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8610 case 0x1f: /* FCVTZS/ FCVTZU */
8611 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8614 unallocated_encoding(s
);
8619 /* Generate code to do a "long" addition or subtraction, ie one done in
8620 * TCGv_i64 on vector lanes twice the width specified by size.
8622 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8623 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8625 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8626 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8627 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8628 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8630 NeonGenTwo64OpFn
*genfn
;
8633 genfn
= fns
[size
][is_sub
];
8634 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8637 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8638 int opcode
, int rd
, int rn
, int rm
)
8640 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8641 TCGv_i64 tcg_res
[2];
8644 tcg_res
[0] = tcg_temp_new_i64();
8645 tcg_res
[1] = tcg_temp_new_i64();
8647 /* Does this op do an adding accumulate, a subtracting accumulate,
8648 * or no accumulate at all?
8666 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8667 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8670 /* size == 2 means two 32x32->64 operations; this is worth special
8671 * casing because we can generally handle it inline.
8674 for (pass
= 0; pass
< 2; pass
++) {
8675 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8676 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8677 TCGv_i64 tcg_passres
;
8678 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8680 int elt
= pass
+ is_q
* 2;
8682 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8683 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8686 tcg_passres
= tcg_res
[pass
];
8688 tcg_passres
= tcg_temp_new_i64();
8692 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8693 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8695 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8696 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8698 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8699 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8701 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8702 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8704 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8705 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8706 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8708 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8709 tcg_temp_free_i64(tcg_tmp1
);
8710 tcg_temp_free_i64(tcg_tmp2
);
8713 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8714 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8715 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8716 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8718 case 9: /* SQDMLAL, SQDMLAL2 */
8719 case 11: /* SQDMLSL, SQDMLSL2 */
8720 case 13: /* SQDMULL, SQDMULL2 */
8721 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8722 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8723 tcg_passres
, tcg_passres
);
8726 g_assert_not_reached();
8729 if (opcode
== 9 || opcode
== 11) {
8730 /* saturating accumulate ops */
8732 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8734 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8735 tcg_res
[pass
], tcg_passres
);
8736 } else if (accop
> 0) {
8737 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8738 } else if (accop
< 0) {
8739 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8743 tcg_temp_free_i64(tcg_passres
);
8746 tcg_temp_free_i64(tcg_op1
);
8747 tcg_temp_free_i64(tcg_op2
);
8750 /* size 0 or 1, generally helper functions */
8751 for (pass
= 0; pass
< 2; pass
++) {
8752 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8753 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8754 TCGv_i64 tcg_passres
;
8755 int elt
= pass
+ is_q
* 2;
8757 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8758 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8761 tcg_passres
= tcg_res
[pass
];
8763 tcg_passres
= tcg_temp_new_i64();
8767 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8768 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8770 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8771 static NeonGenWidenFn
* const widenfns
[2][2] = {
8772 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8773 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8775 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8777 widenfn(tcg_op2_64
, tcg_op2
);
8778 widenfn(tcg_passres
, tcg_op1
);
8779 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8780 tcg_passres
, tcg_op2_64
);
8781 tcg_temp_free_i64(tcg_op2_64
);
8784 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8785 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8788 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8790 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8794 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8796 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8800 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8801 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8802 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8805 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8807 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8811 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8813 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8817 case 9: /* SQDMLAL, SQDMLAL2 */
8818 case 11: /* SQDMLSL, SQDMLSL2 */
8819 case 13: /* SQDMULL, SQDMULL2 */
8821 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8822 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8823 tcg_passres
, tcg_passres
);
8825 case 14: /* PMULL */
8827 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8830 g_assert_not_reached();
8832 tcg_temp_free_i32(tcg_op1
);
8833 tcg_temp_free_i32(tcg_op2
);
8836 if (opcode
== 9 || opcode
== 11) {
8837 /* saturating accumulate ops */
8839 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8841 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8845 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8846 tcg_res
[pass
], tcg_passres
);
8848 tcg_temp_free_i64(tcg_passres
);
8853 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8854 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8855 tcg_temp_free_i64(tcg_res
[0]);
8856 tcg_temp_free_i64(tcg_res
[1]);
8859 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8860 int opcode
, int rd
, int rn
, int rm
)
8862 TCGv_i64 tcg_res
[2];
8863 int part
= is_q
? 2 : 0;
8866 for (pass
= 0; pass
< 2; pass
++) {
8867 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8868 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8869 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8870 static NeonGenWidenFn
* const widenfns
[3][2] = {
8871 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8872 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8873 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8875 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8877 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8878 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8879 widenfn(tcg_op2_wide
, tcg_op2
);
8880 tcg_temp_free_i32(tcg_op2
);
8881 tcg_res
[pass
] = tcg_temp_new_i64();
8882 gen_neon_addl(size
, (opcode
== 3),
8883 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8884 tcg_temp_free_i64(tcg_op1
);
8885 tcg_temp_free_i64(tcg_op2_wide
);
8888 for (pass
= 0; pass
< 2; pass
++) {
8889 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8890 tcg_temp_free_i64(tcg_res
[pass
]);
8894 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8896 tcg_gen_addi_i64(in
, in
, 1U << 31);
8897 tcg_gen_extrh_i64_i32(res
, in
);
8900 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8901 int opcode
, int rd
, int rn
, int rm
)
8903 TCGv_i32 tcg_res
[2];
8904 int part
= is_q
? 2 : 0;
8907 for (pass
= 0; pass
< 2; pass
++) {
8908 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8909 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8910 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8911 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8912 { gen_helper_neon_narrow_high_u8
,
8913 gen_helper_neon_narrow_round_high_u8
},
8914 { gen_helper_neon_narrow_high_u16
,
8915 gen_helper_neon_narrow_round_high_u16
},
8916 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8918 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8920 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8921 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8923 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8925 tcg_temp_free_i64(tcg_op1
);
8926 tcg_temp_free_i64(tcg_op2
);
8928 tcg_res
[pass
] = tcg_temp_new_i32();
8929 gennarrow(tcg_res
[pass
], tcg_wideres
);
8930 tcg_temp_free_i64(tcg_wideres
);
8933 for (pass
= 0; pass
< 2; pass
++) {
8934 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8935 tcg_temp_free_i32(tcg_res
[pass
]);
8938 clear_vec_high(s
, rd
);
8942 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8944 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8945 * is the only three-reg-diff instruction which produces a
8946 * 128-bit wide result from a single operation. However since
8947 * it's possible to calculate the two halves more or less
8948 * separately we just use two helper calls.
8950 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8951 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8952 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8954 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8955 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8956 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8957 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8958 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8959 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8961 tcg_temp_free_i64(tcg_op1
);
8962 tcg_temp_free_i64(tcg_op2
);
8963 tcg_temp_free_i64(tcg_res
);
8966 /* AdvSIMD three different
8967 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8968 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8969 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8970 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8972 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8974 /* Instructions in this group fall into three basic classes
8975 * (in each case with the operation working on each element in
8976 * the input vectors):
8977 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8979 * (2) wide 64 x 128 -> 128
8980 * (3) narrowing 128 x 128 -> 64
8981 * Here we do initial decode, catch unallocated cases and
8982 * dispatch to separate functions for each class.
8984 int is_q
= extract32(insn
, 30, 1);
8985 int is_u
= extract32(insn
, 29, 1);
8986 int size
= extract32(insn
, 22, 2);
8987 int opcode
= extract32(insn
, 12, 4);
8988 int rm
= extract32(insn
, 16, 5);
8989 int rn
= extract32(insn
, 5, 5);
8990 int rd
= extract32(insn
, 0, 5);
8993 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8994 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8995 /* 64 x 128 -> 128 */
8997 unallocated_encoding(s
);
9000 if (!fp_access_check(s
)) {
9003 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9005 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
9006 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
9007 /* 128 x 128 -> 64 */
9009 unallocated_encoding(s
);
9012 if (!fp_access_check(s
)) {
9015 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9017 case 14: /* PMULL, PMULL2 */
9018 if (is_u
|| size
== 1 || size
== 2) {
9019 unallocated_encoding(s
);
9023 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
9024 unallocated_encoding(s
);
9027 if (!fp_access_check(s
)) {
9030 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
9034 case 9: /* SQDMLAL, SQDMLAL2 */
9035 case 11: /* SQDMLSL, SQDMLSL2 */
9036 case 13: /* SQDMULL, SQDMULL2 */
9037 if (is_u
|| size
== 0) {
9038 unallocated_encoding(s
);
9042 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9043 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9044 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9045 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9046 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9047 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9048 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9049 /* 64 x 64 -> 128 */
9051 unallocated_encoding(s
);
9055 if (!fp_access_check(s
)) {
9059 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9062 /* opcode 15 not allocated */
9063 unallocated_encoding(s
);
9068 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9069 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9071 int rd
= extract32(insn
, 0, 5);
9072 int rn
= extract32(insn
, 5, 5);
9073 int rm
= extract32(insn
, 16, 5);
9074 int size
= extract32(insn
, 22, 2);
9075 bool is_u
= extract32(insn
, 29, 1);
9076 bool is_q
= extract32(insn
, 30, 1);
9077 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9080 if (!fp_access_check(s
)) {
9084 tcg_op1
= tcg_temp_new_i64();
9085 tcg_op2
= tcg_temp_new_i64();
9086 tcg_res
[0] = tcg_temp_new_i64();
9087 tcg_res
[1] = tcg_temp_new_i64();
9089 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9090 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9091 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9096 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9099 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9102 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9105 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9110 /* B* ops need res loaded to operate on */
9111 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9116 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9118 case 1: /* BSL bitwise select */
9119 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9120 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9121 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9123 case 2: /* BIT, bitwise insert if true */
9124 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9125 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9126 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9128 case 3: /* BIF, bitwise insert if false */
9129 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9130 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9131 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9137 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9139 tcg_gen_movi_i64(tcg_res
[1], 0);
9141 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9143 tcg_temp_free_i64(tcg_op1
);
9144 tcg_temp_free_i64(tcg_op2
);
9145 tcg_temp_free_i64(tcg_res
[0]);
9146 tcg_temp_free_i64(tcg_res
[1]);
9149 /* Helper functions for 32 bit comparisons */
9150 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9152 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9155 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9157 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9160 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9162 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9165 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9167 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9170 /* Pairwise op subgroup of C3.6.16.
9172 * This is called directly or via the handle_3same_float for float pairwise
9173 * operations where the opcode and size are calculated differently.
9175 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9176 int size
, int rn
, int rm
, int rd
)
9181 /* Floating point operations need fpst */
9182 if (opcode
>= 0x58) {
9183 fpst
= get_fpstatus_ptr();
9188 if (!fp_access_check(s
)) {
9192 /* These operations work on the concatenated rm:rn, with each pair of
9193 * adjacent elements being operated on to produce an element in the result.
9196 TCGv_i64 tcg_res
[2];
9198 for (pass
= 0; pass
< 2; pass
++) {
9199 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9200 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9201 int passreg
= (pass
== 0) ? rn
: rm
;
9203 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9204 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9205 tcg_res
[pass
] = tcg_temp_new_i64();
9208 case 0x17: /* ADDP */
9209 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9211 case 0x58: /* FMAXNMP */
9212 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9214 case 0x5a: /* FADDP */
9215 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9217 case 0x5e: /* FMAXP */
9218 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9220 case 0x78: /* FMINNMP */
9221 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9223 case 0x7e: /* FMINP */
9224 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9227 g_assert_not_reached();
9230 tcg_temp_free_i64(tcg_op1
);
9231 tcg_temp_free_i64(tcg_op2
);
9234 for (pass
= 0; pass
< 2; pass
++) {
9235 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9236 tcg_temp_free_i64(tcg_res
[pass
]);
9239 int maxpass
= is_q
? 4 : 2;
9240 TCGv_i32 tcg_res
[4];
9242 for (pass
= 0; pass
< maxpass
; pass
++) {
9243 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9244 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9245 NeonGenTwoOpFn
*genfn
= NULL
;
9246 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9247 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9249 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9250 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9251 tcg_res
[pass
] = tcg_temp_new_i32();
9254 case 0x17: /* ADDP */
9256 static NeonGenTwoOpFn
* const fns
[3] = {
9257 gen_helper_neon_padd_u8
,
9258 gen_helper_neon_padd_u16
,
9264 case 0x14: /* SMAXP, UMAXP */
9266 static NeonGenTwoOpFn
* const fns
[3][2] = {
9267 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9268 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9269 { gen_max_s32
, gen_max_u32
},
9271 genfn
= fns
[size
][u
];
9274 case 0x15: /* SMINP, UMINP */
9276 static NeonGenTwoOpFn
* const fns
[3][2] = {
9277 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9278 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9279 { gen_min_s32
, gen_min_u32
},
9281 genfn
= fns
[size
][u
];
9284 /* The FP operations are all on single floats (32 bit) */
9285 case 0x58: /* FMAXNMP */
9286 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9288 case 0x5a: /* FADDP */
9289 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9291 case 0x5e: /* FMAXP */
9292 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9294 case 0x78: /* FMINNMP */
9295 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9297 case 0x7e: /* FMINP */
9298 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9301 g_assert_not_reached();
9304 /* FP ops called directly, otherwise call now */
9306 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9309 tcg_temp_free_i32(tcg_op1
);
9310 tcg_temp_free_i32(tcg_op2
);
9313 for (pass
= 0; pass
< maxpass
; pass
++) {
9314 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9315 tcg_temp_free_i32(tcg_res
[pass
]);
9318 clear_vec_high(s
, rd
);
9323 tcg_temp_free_ptr(fpst
);
9327 /* Floating point op subgroup of C3.6.16. */
9328 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9330 /* For floating point ops, the U, size[1] and opcode bits
9331 * together indicate the operation. size[0] indicates single
9334 int fpopcode
= extract32(insn
, 11, 5)
9335 | (extract32(insn
, 23, 1) << 5)
9336 | (extract32(insn
, 29, 1) << 6);
9337 int is_q
= extract32(insn
, 30, 1);
9338 int size
= extract32(insn
, 22, 1);
9339 int rm
= extract32(insn
, 16, 5);
9340 int rn
= extract32(insn
, 5, 5);
9341 int rd
= extract32(insn
, 0, 5);
9343 int datasize
= is_q
? 128 : 64;
9344 int esize
= 32 << size
;
9345 int elements
= datasize
/ esize
;
9347 if (size
== 1 && !is_q
) {
9348 unallocated_encoding(s
);
9353 case 0x58: /* FMAXNMP */
9354 case 0x5a: /* FADDP */
9355 case 0x5e: /* FMAXP */
9356 case 0x78: /* FMINNMP */
9357 case 0x7e: /* FMINP */
9358 if (size
&& !is_q
) {
9359 unallocated_encoding(s
);
9362 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9365 case 0x1b: /* FMULX */
9366 case 0x1f: /* FRECPS */
9367 case 0x3f: /* FRSQRTS */
9368 case 0x5d: /* FACGE */
9369 case 0x7d: /* FACGT */
9370 case 0x19: /* FMLA */
9371 case 0x39: /* FMLS */
9372 case 0x18: /* FMAXNM */
9373 case 0x1a: /* FADD */
9374 case 0x1c: /* FCMEQ */
9375 case 0x1e: /* FMAX */
9376 case 0x38: /* FMINNM */
9377 case 0x3a: /* FSUB */
9378 case 0x3e: /* FMIN */
9379 case 0x5b: /* FMUL */
9380 case 0x5c: /* FCMGE */
9381 case 0x5f: /* FDIV */
9382 case 0x7a: /* FABD */
9383 case 0x7c: /* FCMGT */
9384 if (!fp_access_check(s
)) {
9388 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9391 unallocated_encoding(s
);
9396 /* Integer op subgroup of C3.6.16. */
9397 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9399 int is_q
= extract32(insn
, 30, 1);
9400 int u
= extract32(insn
, 29, 1);
9401 int size
= extract32(insn
, 22, 2);
9402 int opcode
= extract32(insn
, 11, 5);
9403 int rm
= extract32(insn
, 16, 5);
9404 int rn
= extract32(insn
, 5, 5);
9405 int rd
= extract32(insn
, 0, 5);
9409 case 0x13: /* MUL, PMUL */
9410 if (u
&& size
!= 0) {
9411 unallocated_encoding(s
);
9415 case 0x0: /* SHADD, UHADD */
9416 case 0x2: /* SRHADD, URHADD */
9417 case 0x4: /* SHSUB, UHSUB */
9418 case 0xc: /* SMAX, UMAX */
9419 case 0xd: /* SMIN, UMIN */
9420 case 0xe: /* SABD, UABD */
9421 case 0xf: /* SABA, UABA */
9422 case 0x12: /* MLA, MLS */
9424 unallocated_encoding(s
);
9428 case 0x16: /* SQDMULH, SQRDMULH */
9429 if (size
== 0 || size
== 3) {
9430 unallocated_encoding(s
);
9435 if (size
== 3 && !is_q
) {
9436 unallocated_encoding(s
);
9442 if (!fp_access_check(s
)) {
9448 for (pass
= 0; pass
< 2; pass
++) {
9449 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9450 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9451 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9453 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9454 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9456 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9458 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9460 tcg_temp_free_i64(tcg_res
);
9461 tcg_temp_free_i64(tcg_op1
);
9462 tcg_temp_free_i64(tcg_op2
);
9465 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9466 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9467 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9468 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9469 NeonGenTwoOpFn
*genfn
= NULL
;
9470 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9472 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9473 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9476 case 0x0: /* SHADD, UHADD */
9478 static NeonGenTwoOpFn
* const fns
[3][2] = {
9479 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9480 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9481 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9483 genfn
= fns
[size
][u
];
9486 case 0x1: /* SQADD, UQADD */
9488 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9489 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9490 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9491 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9493 genenvfn
= fns
[size
][u
];
9496 case 0x2: /* SRHADD, URHADD */
9498 static NeonGenTwoOpFn
* const fns
[3][2] = {
9499 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9500 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9501 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9503 genfn
= fns
[size
][u
];
9506 case 0x4: /* SHSUB, UHSUB */
9508 static NeonGenTwoOpFn
* const fns
[3][2] = {
9509 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9510 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9511 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9513 genfn
= fns
[size
][u
];
9516 case 0x5: /* SQSUB, UQSUB */
9518 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9519 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9520 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9521 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9523 genenvfn
= fns
[size
][u
];
9526 case 0x6: /* CMGT, CMHI */
9528 static NeonGenTwoOpFn
* const fns
[3][2] = {
9529 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9530 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9531 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9533 genfn
= fns
[size
][u
];
9536 case 0x7: /* CMGE, CMHS */
9538 static NeonGenTwoOpFn
* const fns
[3][2] = {
9539 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9540 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9541 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9543 genfn
= fns
[size
][u
];
9546 case 0x8: /* SSHL, USHL */
9548 static NeonGenTwoOpFn
* const fns
[3][2] = {
9549 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9550 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9551 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9553 genfn
= fns
[size
][u
];
9556 case 0x9: /* SQSHL, UQSHL */
9558 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9559 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9560 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9561 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9563 genenvfn
= fns
[size
][u
];
9566 case 0xa: /* SRSHL, URSHL */
9568 static NeonGenTwoOpFn
* const fns
[3][2] = {
9569 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9570 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9571 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9573 genfn
= fns
[size
][u
];
9576 case 0xb: /* SQRSHL, UQRSHL */
9578 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9579 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9580 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9581 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9583 genenvfn
= fns
[size
][u
];
9586 case 0xc: /* SMAX, UMAX */
9588 static NeonGenTwoOpFn
* const fns
[3][2] = {
9589 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9590 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9591 { gen_max_s32
, gen_max_u32
},
9593 genfn
= fns
[size
][u
];
9597 case 0xd: /* SMIN, UMIN */
9599 static NeonGenTwoOpFn
* const fns
[3][2] = {
9600 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9601 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9602 { gen_min_s32
, gen_min_u32
},
9604 genfn
= fns
[size
][u
];
9607 case 0xe: /* SABD, UABD */
9608 case 0xf: /* SABA, UABA */
9610 static NeonGenTwoOpFn
* const fns
[3][2] = {
9611 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9612 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9613 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9615 genfn
= fns
[size
][u
];
9618 case 0x10: /* ADD, SUB */
9620 static NeonGenTwoOpFn
* const fns
[3][2] = {
9621 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9622 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9623 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9625 genfn
= fns
[size
][u
];
9628 case 0x11: /* CMTST, CMEQ */
9630 static NeonGenTwoOpFn
* const fns
[3][2] = {
9631 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9632 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9633 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9635 genfn
= fns
[size
][u
];
9638 case 0x13: /* MUL, PMUL */
9642 genfn
= gen_helper_neon_mul_p8
;
9645 /* fall through : MUL */
9646 case 0x12: /* MLA, MLS */
9648 static NeonGenTwoOpFn
* const fns
[3] = {
9649 gen_helper_neon_mul_u8
,
9650 gen_helper_neon_mul_u16
,
9656 case 0x16: /* SQDMULH, SQRDMULH */
9658 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9659 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9660 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9662 assert(size
== 1 || size
== 2);
9663 genenvfn
= fns
[size
- 1][u
];
9667 g_assert_not_reached();
9671 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9673 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9676 if (opcode
== 0xf || opcode
== 0x12) {
9677 /* SABA, UABA, MLA, MLS: accumulating ops */
9678 static NeonGenTwoOpFn
* const fns
[3][2] = {
9679 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9680 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9681 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9683 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9685 genfn
= fns
[size
][is_sub
];
9686 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9687 genfn(tcg_res
, tcg_op1
, tcg_res
);
9690 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9692 tcg_temp_free_i32(tcg_res
);
9693 tcg_temp_free_i32(tcg_op1
);
9694 tcg_temp_free_i32(tcg_op2
);
9699 clear_vec_high(s
, rd
);
9703 /* AdvSIMD three same
9704 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9705 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9706 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9707 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9709 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9711 int opcode
= extract32(insn
, 11, 5);
9714 case 0x3: /* logic ops */
9715 disas_simd_3same_logic(s
, insn
);
9717 case 0x17: /* ADDP */
9718 case 0x14: /* SMAXP, UMAXP */
9719 case 0x15: /* SMINP, UMINP */
9721 /* Pairwise operations */
9722 int is_q
= extract32(insn
, 30, 1);
9723 int u
= extract32(insn
, 29, 1);
9724 int size
= extract32(insn
, 22, 2);
9725 int rm
= extract32(insn
, 16, 5);
9726 int rn
= extract32(insn
, 5, 5);
9727 int rd
= extract32(insn
, 0, 5);
9728 if (opcode
== 0x17) {
9729 if (u
|| (size
== 3 && !is_q
)) {
9730 unallocated_encoding(s
);
9735 unallocated_encoding(s
);
9739 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9743 /* floating point ops, sz[1] and U are part of opcode */
9744 disas_simd_3same_float(s
, insn
);
9747 disas_simd_3same_int(s
, insn
);
9752 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9753 int size
, int rn
, int rd
)
9755 /* Handle 2-reg-misc ops which are widening (so each size element
9756 * in the source becomes a 2*size element in the destination.
9757 * The only instruction like this is FCVTL.
9762 /* 32 -> 64 bit fp conversion */
9763 TCGv_i64 tcg_res
[2];
9764 int srcelt
= is_q
? 2 : 0;
9766 for (pass
= 0; pass
< 2; pass
++) {
9767 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9768 tcg_res
[pass
] = tcg_temp_new_i64();
9770 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9771 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9772 tcg_temp_free_i32(tcg_op
);
9774 for (pass
= 0; pass
< 2; pass
++) {
9775 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9776 tcg_temp_free_i64(tcg_res
[pass
]);
9779 /* 16 -> 32 bit fp conversion */
9780 int srcelt
= is_q
? 4 : 0;
9781 TCGv_i32 tcg_res
[4];
9783 for (pass
= 0; pass
< 4; pass
++) {
9784 tcg_res
[pass
] = tcg_temp_new_i32();
9786 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9787 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9790 for (pass
= 0; pass
< 4; pass
++) {
9791 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9792 tcg_temp_free_i32(tcg_res
[pass
]);
9797 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9798 bool is_q
, int size
, int rn
, int rd
)
9800 int op
= (opcode
<< 1) | u
;
9801 int opsz
= op
+ size
;
9802 int grp_size
= 3 - opsz
;
9803 int dsize
= is_q
? 128 : 64;
9807 unallocated_encoding(s
);
9811 if (!fp_access_check(s
)) {
9816 /* Special case bytes, use bswap op on each group of elements */
9817 int groups
= dsize
/ (8 << grp_size
);
9819 for (i
= 0; i
< groups
; i
++) {
9820 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9822 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9825 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9828 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9831 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9834 g_assert_not_reached();
9836 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9837 tcg_temp_free_i64(tcg_tmp
);
9840 clear_vec_high(s
, rd
);
9843 int revmask
= (1 << grp_size
) - 1;
9844 int esize
= 8 << size
;
9845 int elements
= dsize
/ esize
;
9846 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9847 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9848 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9850 for (i
= 0; i
< elements
; i
++) {
9851 int e_rev
= (i
& 0xf) ^ revmask
;
9852 int off
= e_rev
* esize
;
9853 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9855 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9856 tcg_rn
, off
- 64, esize
);
9858 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9861 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9862 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9864 tcg_temp_free_i64(tcg_rd_hi
);
9865 tcg_temp_free_i64(tcg_rd
);
9866 tcg_temp_free_i64(tcg_rn
);
9870 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9871 bool is_q
, int size
, int rn
, int rd
)
9873 /* Implement the pairwise operations from 2-misc:
9874 * SADDLP, UADDLP, SADALP, UADALP.
9875 * These all add pairs of elements in the input to produce a
9876 * double-width result element in the output (possibly accumulating).
9878 bool accum
= (opcode
== 0x6);
9879 int maxpass
= is_q
? 2 : 1;
9881 TCGv_i64 tcg_res
[2];
9884 /* 32 + 32 -> 64 op */
9885 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9887 for (pass
= 0; pass
< maxpass
; pass
++) {
9888 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9889 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9891 tcg_res
[pass
] = tcg_temp_new_i64();
9893 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9894 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9895 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9897 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9898 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9901 tcg_temp_free_i64(tcg_op1
);
9902 tcg_temp_free_i64(tcg_op2
);
9905 for (pass
= 0; pass
< maxpass
; pass
++) {
9906 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9907 NeonGenOneOpFn
*genfn
;
9908 static NeonGenOneOpFn
* const fns
[2][2] = {
9909 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9910 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9913 genfn
= fns
[size
][u
];
9915 tcg_res
[pass
] = tcg_temp_new_i64();
9917 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9918 genfn(tcg_res
[pass
], tcg_op
);
9921 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9923 gen_helper_neon_addl_u16(tcg_res
[pass
],
9924 tcg_res
[pass
], tcg_op
);
9926 gen_helper_neon_addl_u32(tcg_res
[pass
],
9927 tcg_res
[pass
], tcg_op
);
9930 tcg_temp_free_i64(tcg_op
);
9934 tcg_res
[1] = tcg_const_i64(0);
9936 for (pass
= 0; pass
< 2; pass
++) {
9937 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9938 tcg_temp_free_i64(tcg_res
[pass
]);
9942 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9944 /* Implement SHLL and SHLL2 */
9946 int part
= is_q
? 2 : 0;
9947 TCGv_i64 tcg_res
[2];
9949 for (pass
= 0; pass
< 2; pass
++) {
9950 static NeonGenWidenFn
* const widenfns
[3] = {
9951 gen_helper_neon_widen_u8
,
9952 gen_helper_neon_widen_u16
,
9953 tcg_gen_extu_i32_i64
,
9955 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9956 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9958 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9959 tcg_res
[pass
] = tcg_temp_new_i64();
9960 widenfn(tcg_res
[pass
], tcg_op
);
9961 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9963 tcg_temp_free_i32(tcg_op
);
9966 for (pass
= 0; pass
< 2; pass
++) {
9967 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9968 tcg_temp_free_i64(tcg_res
[pass
]);
9972 /* AdvSIMD two reg misc
9973 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9974 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9975 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9976 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9978 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9980 int size
= extract32(insn
, 22, 2);
9981 int opcode
= extract32(insn
, 12, 5);
9982 bool u
= extract32(insn
, 29, 1);
9983 bool is_q
= extract32(insn
, 30, 1);
9984 int rn
= extract32(insn
, 5, 5);
9985 int rd
= extract32(insn
, 0, 5);
9986 bool need_fpstatus
= false;
9987 bool need_rmode
= false;
9990 TCGv_ptr tcg_fpstatus
;
9993 case 0x0: /* REV64, REV32 */
9994 case 0x1: /* REV16 */
9995 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9997 case 0x5: /* CNT, NOT, RBIT */
9998 if (u
&& size
== 0) {
9999 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
10002 } else if (u
&& size
== 1) {
10005 } else if (!u
&& size
== 0) {
10009 unallocated_encoding(s
);
10011 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
10012 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
10014 unallocated_encoding(s
);
10017 if (!fp_access_check(s
)) {
10021 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
10023 case 0x4: /* CLS, CLZ */
10025 unallocated_encoding(s
);
10029 case 0x2: /* SADDLP, UADDLP */
10030 case 0x6: /* SADALP, UADALP */
10032 unallocated_encoding(s
);
10035 if (!fp_access_check(s
)) {
10038 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10040 case 0x13: /* SHLL, SHLL2 */
10041 if (u
== 0 || size
== 3) {
10042 unallocated_encoding(s
);
10045 if (!fp_access_check(s
)) {
10048 handle_shll(s
, is_q
, size
, rn
, rd
);
10050 case 0xa: /* CMLT */
10052 unallocated_encoding(s
);
10056 case 0x8: /* CMGT, CMGE */
10057 case 0x9: /* CMEQ, CMLE */
10058 case 0xb: /* ABS, NEG */
10059 if (size
== 3 && !is_q
) {
10060 unallocated_encoding(s
);
10064 case 0x3: /* SUQADD, USQADD */
10065 if (size
== 3 && !is_q
) {
10066 unallocated_encoding(s
);
10069 if (!fp_access_check(s
)) {
10072 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10074 case 0x7: /* SQABS, SQNEG */
10075 if (size
== 3 && !is_q
) {
10076 unallocated_encoding(s
);
10081 case 0x16 ... 0x1d:
10084 /* Floating point: U, size[1] and opcode indicate operation;
10085 * size[0] indicates single or double precision.
10087 int is_double
= extract32(size
, 0, 1);
10088 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10089 size
= is_double
? 3 : 2;
10091 case 0x2f: /* FABS */
10092 case 0x6f: /* FNEG */
10093 if (size
== 3 && !is_q
) {
10094 unallocated_encoding(s
);
10098 case 0x1d: /* SCVTF */
10099 case 0x5d: /* UCVTF */
10101 bool is_signed
= (opcode
== 0x1d) ? true : false;
10102 int elements
= is_double
? 2 : is_q
? 4 : 2;
10103 if (is_double
&& !is_q
) {
10104 unallocated_encoding(s
);
10107 if (!fp_access_check(s
)) {
10110 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10113 case 0x2c: /* FCMGT (zero) */
10114 case 0x2d: /* FCMEQ (zero) */
10115 case 0x2e: /* FCMLT (zero) */
10116 case 0x6c: /* FCMGE (zero) */
10117 case 0x6d: /* FCMLE (zero) */
10118 if (size
== 3 && !is_q
) {
10119 unallocated_encoding(s
);
10122 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10124 case 0x7f: /* FSQRT */
10125 if (size
== 3 && !is_q
) {
10126 unallocated_encoding(s
);
10130 case 0x1a: /* FCVTNS */
10131 case 0x1b: /* FCVTMS */
10132 case 0x3a: /* FCVTPS */
10133 case 0x3b: /* FCVTZS */
10134 case 0x5a: /* FCVTNU */
10135 case 0x5b: /* FCVTMU */
10136 case 0x7a: /* FCVTPU */
10137 case 0x7b: /* FCVTZU */
10138 need_fpstatus
= true;
10140 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10141 if (size
== 3 && !is_q
) {
10142 unallocated_encoding(s
);
10146 case 0x5c: /* FCVTAU */
10147 case 0x1c: /* FCVTAS */
10148 need_fpstatus
= true;
10150 rmode
= FPROUNDING_TIEAWAY
;
10151 if (size
== 3 && !is_q
) {
10152 unallocated_encoding(s
);
10156 case 0x3c: /* URECPE */
10158 unallocated_encoding(s
);
10162 case 0x3d: /* FRECPE */
10163 case 0x7d: /* FRSQRTE */
10164 if (size
== 3 && !is_q
) {
10165 unallocated_encoding(s
);
10168 if (!fp_access_check(s
)) {
10171 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10173 case 0x56: /* FCVTXN, FCVTXN2 */
10175 unallocated_encoding(s
);
10179 case 0x16: /* FCVTN, FCVTN2 */
10180 /* handle_2misc_narrow does a 2*size -> size operation, but these
10181 * instructions encode the source size rather than dest size.
10183 if (!fp_access_check(s
)) {
10186 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10188 case 0x17: /* FCVTL, FCVTL2 */
10189 if (!fp_access_check(s
)) {
10192 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10194 case 0x18: /* FRINTN */
10195 case 0x19: /* FRINTM */
10196 case 0x38: /* FRINTP */
10197 case 0x39: /* FRINTZ */
10199 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10201 case 0x59: /* FRINTX */
10202 case 0x79: /* FRINTI */
10203 need_fpstatus
= true;
10204 if (size
== 3 && !is_q
) {
10205 unallocated_encoding(s
);
10209 case 0x58: /* FRINTA */
10211 rmode
= FPROUNDING_TIEAWAY
;
10212 need_fpstatus
= true;
10213 if (size
== 3 && !is_q
) {
10214 unallocated_encoding(s
);
10218 case 0x7c: /* URSQRTE */
10220 unallocated_encoding(s
);
10223 need_fpstatus
= true;
10226 unallocated_encoding(s
);
10232 unallocated_encoding(s
);
10236 if (!fp_access_check(s
)) {
10240 if (need_fpstatus
) {
10241 tcg_fpstatus
= get_fpstatus_ptr();
10243 tcg_fpstatus
= NULL
;
10246 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10247 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10253 /* All 64-bit element operations can be shared with scalar 2misc */
10256 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10257 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10258 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10260 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10262 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10263 tcg_rmode
, tcg_fpstatus
);
10265 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10267 tcg_temp_free_i64(tcg_res
);
10268 tcg_temp_free_i64(tcg_op
);
10273 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10274 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10275 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10278 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10281 /* Special cases for 32 bit elements */
10283 case 0xa: /* CMLT */
10284 /* 32 bit integer comparison against zero, result is
10285 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10288 cond
= TCG_COND_LT
;
10290 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10291 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10293 case 0x8: /* CMGT, CMGE */
10294 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10296 case 0x9: /* CMEQ, CMLE */
10297 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10299 case 0x4: /* CLS */
10301 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10303 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10306 case 0x7: /* SQABS, SQNEG */
10308 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10310 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10313 case 0xb: /* ABS, NEG */
10315 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10317 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10318 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10319 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10320 tcg_zero
, tcg_op
, tcg_res
);
10321 tcg_temp_free_i32(tcg_zero
);
10324 case 0x2f: /* FABS */
10325 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10327 case 0x6f: /* FNEG */
10328 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10330 case 0x7f: /* FSQRT */
10331 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10333 case 0x1a: /* FCVTNS */
10334 case 0x1b: /* FCVTMS */
10335 case 0x1c: /* FCVTAS */
10336 case 0x3a: /* FCVTPS */
10337 case 0x3b: /* FCVTZS */
10339 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10340 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10341 tcg_shift
, tcg_fpstatus
);
10342 tcg_temp_free_i32(tcg_shift
);
10345 case 0x5a: /* FCVTNU */
10346 case 0x5b: /* FCVTMU */
10347 case 0x5c: /* FCVTAU */
10348 case 0x7a: /* FCVTPU */
10349 case 0x7b: /* FCVTZU */
10351 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10352 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10353 tcg_shift
, tcg_fpstatus
);
10354 tcg_temp_free_i32(tcg_shift
);
10357 case 0x18: /* FRINTN */
10358 case 0x19: /* FRINTM */
10359 case 0x38: /* FRINTP */
10360 case 0x39: /* FRINTZ */
10361 case 0x58: /* FRINTA */
10362 case 0x79: /* FRINTI */
10363 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10365 case 0x59: /* FRINTX */
10366 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10368 case 0x7c: /* URSQRTE */
10369 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10372 g_assert_not_reached();
10375 /* Use helpers for 8 and 16 bit elements */
10377 case 0x5: /* CNT, RBIT */
10378 /* For these two insns size is part of the opcode specifier
10379 * (handled earlier); they always operate on byte elements.
10382 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10384 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10387 case 0x7: /* SQABS, SQNEG */
10389 NeonGenOneOpEnvFn
*genfn
;
10390 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10391 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10392 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10394 genfn
= fns
[size
][u
];
10395 genfn(tcg_res
, cpu_env
, tcg_op
);
10398 case 0x8: /* CMGT, CMGE */
10399 case 0x9: /* CMEQ, CMLE */
10400 case 0xa: /* CMLT */
10402 static NeonGenTwoOpFn
* const fns
[3][2] = {
10403 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10404 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10405 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10407 NeonGenTwoOpFn
*genfn
;
10410 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10412 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10413 comp
= (opcode
- 0x8) * 2 + u
;
10414 /* ...but LE, LT are implemented as reverse GE, GT */
10415 reverse
= (comp
> 2);
10419 genfn
= fns
[comp
][size
];
10421 genfn(tcg_res
, tcg_zero
, tcg_op
);
10423 genfn(tcg_res
, tcg_op
, tcg_zero
);
10425 tcg_temp_free_i32(tcg_zero
);
10428 case 0xb: /* ABS, NEG */
10430 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10432 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10434 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10436 tcg_temp_free_i32(tcg_zero
);
10439 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10441 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10445 case 0x4: /* CLS, CLZ */
10448 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10450 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10454 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10456 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10461 g_assert_not_reached();
10465 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10467 tcg_temp_free_i32(tcg_res
);
10468 tcg_temp_free_i32(tcg_op
);
10472 clear_vec_high(s
, rd
);
10476 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10477 tcg_temp_free_i32(tcg_rmode
);
10479 if (need_fpstatus
) {
10480 tcg_temp_free_ptr(tcg_fpstatus
);
10484 /* AdvSIMD scalar x indexed element
10485 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10486 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10487 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10488 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10489 * AdvSIMD vector x indexed element
10490 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10491 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10492 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10493 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10495 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10497 /* This encoding has two kinds of instruction:
10498 * normal, where we perform elt x idxelt => elt for each
10499 * element in the vector
10500 * long, where we perform elt x idxelt and generate a result of
10501 * double the width of the input element
10502 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10504 bool is_scalar
= extract32(insn
, 28, 1);
10505 bool is_q
= extract32(insn
, 30, 1);
10506 bool u
= extract32(insn
, 29, 1);
10507 int size
= extract32(insn
, 22, 2);
10508 int l
= extract32(insn
, 21, 1);
10509 int m
= extract32(insn
, 20, 1);
10510 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10511 int rm
= extract32(insn
, 16, 4);
10512 int opcode
= extract32(insn
, 12, 4);
10513 int h
= extract32(insn
, 11, 1);
10514 int rn
= extract32(insn
, 5, 5);
10515 int rd
= extract32(insn
, 0, 5);
10516 bool is_long
= false;
10517 bool is_fp
= false;
10522 case 0x0: /* MLA */
10523 case 0x4: /* MLS */
10524 if (!u
|| is_scalar
) {
10525 unallocated_encoding(s
);
10529 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10530 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10531 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10533 unallocated_encoding(s
);
10538 case 0x3: /* SQDMLAL, SQDMLAL2 */
10539 case 0x7: /* SQDMLSL, SQDMLSL2 */
10540 case 0xb: /* SQDMULL, SQDMULL2 */
10543 case 0xc: /* SQDMULH */
10544 case 0xd: /* SQRDMULH */
10546 unallocated_encoding(s
);
10550 case 0x8: /* MUL */
10551 if (u
|| is_scalar
) {
10552 unallocated_encoding(s
);
10556 case 0x1: /* FMLA */
10557 case 0x5: /* FMLS */
10559 unallocated_encoding(s
);
10563 case 0x9: /* FMUL, FMULX */
10564 if (!extract32(size
, 1, 1)) {
10565 unallocated_encoding(s
);
10571 unallocated_encoding(s
);
10576 /* low bit of size indicates single/double */
10577 size
= extract32(size
, 0, 1) ? 3 : 2;
10579 index
= h
<< 1 | l
;
10582 unallocated_encoding(s
);
10591 index
= h
<< 2 | l
<< 1 | m
;
10594 index
= h
<< 1 | l
;
10598 unallocated_encoding(s
);
10603 if (!fp_access_check(s
)) {
10608 fpst
= get_fpstatus_ptr();
10614 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10617 assert(is_fp
&& is_q
&& !is_long
);
10619 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10621 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10622 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10623 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10625 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10628 case 0x5: /* FMLS */
10629 /* As usual for ARM, separate negation for fused multiply-add */
10630 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10632 case 0x1: /* FMLA */
10633 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10634 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10636 case 0x9: /* FMUL, FMULX */
10638 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10640 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10644 g_assert_not_reached();
10647 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10648 tcg_temp_free_i64(tcg_op
);
10649 tcg_temp_free_i64(tcg_res
);
10653 clear_vec_high(s
, rd
);
10656 tcg_temp_free_i64(tcg_idx
);
10657 } else if (!is_long
) {
10658 /* 32 bit floating point, or 16 or 32 bit integer.
10659 * For the 16 bit scalar case we use the usual Neon helpers and
10660 * rely on the fact that 0 op 0 == 0 with no side effects.
10662 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10663 int pass
, maxpasses
;
10668 maxpasses
= is_q
? 4 : 2;
10671 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10673 if (size
== 1 && !is_scalar
) {
10674 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10675 * the index into both halves of the 32 bit tcg_idx and then use
10676 * the usual Neon helpers.
10678 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10681 for (pass
= 0; pass
< maxpasses
; pass
++) {
10682 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10683 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10685 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10688 case 0x0: /* MLA */
10689 case 0x4: /* MLS */
10690 case 0x8: /* MUL */
10692 static NeonGenTwoOpFn
* const fns
[2][2] = {
10693 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10694 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10696 NeonGenTwoOpFn
*genfn
;
10697 bool is_sub
= opcode
== 0x4;
10700 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10702 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10704 if (opcode
== 0x8) {
10707 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10708 genfn
= fns
[size
- 1][is_sub
];
10709 genfn(tcg_res
, tcg_op
, tcg_res
);
10712 case 0x5: /* FMLS */
10713 /* As usual for ARM, separate negation for fused multiply-add */
10714 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10716 case 0x1: /* FMLA */
10717 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10718 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10720 case 0x9: /* FMUL, FMULX */
10722 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10724 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10727 case 0xc: /* SQDMULH */
10729 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10732 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10736 case 0xd: /* SQRDMULH */
10738 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10741 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10746 g_assert_not_reached();
10750 write_fp_sreg(s
, rd
, tcg_res
);
10752 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10755 tcg_temp_free_i32(tcg_op
);
10756 tcg_temp_free_i32(tcg_res
);
10759 tcg_temp_free_i32(tcg_idx
);
10762 clear_vec_high(s
, rd
);
10765 /* long ops: 16x16->32 or 32x32->64 */
10766 TCGv_i64 tcg_res
[2];
10768 bool satop
= extract32(opcode
, 0, 1);
10769 TCGMemOp memop
= MO_32
;
10776 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10778 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10780 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10781 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10782 TCGv_i64 tcg_passres
;
10788 passelt
= pass
+ (is_q
* 2);
10791 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10793 tcg_res
[pass
] = tcg_temp_new_i64();
10795 if (opcode
== 0xa || opcode
== 0xb) {
10796 /* Non-accumulating ops */
10797 tcg_passres
= tcg_res
[pass
];
10799 tcg_passres
= tcg_temp_new_i64();
10802 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10803 tcg_temp_free_i64(tcg_op
);
10806 /* saturating, doubling */
10807 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10808 tcg_passres
, tcg_passres
);
10811 if (opcode
== 0xa || opcode
== 0xb) {
10815 /* Accumulating op: handle accumulate step */
10816 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10819 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10820 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10822 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10823 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10825 case 0x7: /* SQDMLSL, SQDMLSL2 */
10826 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10828 case 0x3: /* SQDMLAL, SQDMLAL2 */
10829 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10834 g_assert_not_reached();
10836 tcg_temp_free_i64(tcg_passres
);
10838 tcg_temp_free_i64(tcg_idx
);
10841 clear_vec_high(s
, rd
);
10844 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10847 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10850 /* The simplest way to handle the 16x16 indexed ops is to
10851 * duplicate the index into both halves of the 32 bit tcg_idx
10852 * and then use the usual Neon helpers.
10854 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10857 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10858 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10859 TCGv_i64 tcg_passres
;
10862 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10864 read_vec_element_i32(s
, tcg_op
, rn
,
10865 pass
+ (is_q
* 2), MO_32
);
10868 tcg_res
[pass
] = tcg_temp_new_i64();
10870 if (opcode
== 0xa || opcode
== 0xb) {
10871 /* Non-accumulating ops */
10872 tcg_passres
= tcg_res
[pass
];
10874 tcg_passres
= tcg_temp_new_i64();
10877 if (memop
& MO_SIGN
) {
10878 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10880 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10883 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10884 tcg_passres
, tcg_passres
);
10886 tcg_temp_free_i32(tcg_op
);
10888 if (opcode
== 0xa || opcode
== 0xb) {
10892 /* Accumulating op: handle accumulate step */
10893 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10896 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10897 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10900 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10901 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10904 case 0x7: /* SQDMLSL, SQDMLSL2 */
10905 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10907 case 0x3: /* SQDMLAL, SQDMLAL2 */
10908 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10913 g_assert_not_reached();
10915 tcg_temp_free_i64(tcg_passres
);
10917 tcg_temp_free_i32(tcg_idx
);
10920 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10925 tcg_res
[1] = tcg_const_i64(0);
10928 for (pass
= 0; pass
< 2; pass
++) {
10929 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10930 tcg_temp_free_i64(tcg_res
[pass
]);
10935 tcg_temp_free_ptr(fpst
);
10940 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10941 * +-----------------+------+-----------+--------+-----+------+------+
10942 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10943 * +-----------------+------+-----------+--------+-----+------+------+
10945 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10947 int size
= extract32(insn
, 22, 2);
10948 int opcode
= extract32(insn
, 12, 5);
10949 int rn
= extract32(insn
, 5, 5);
10950 int rd
= extract32(insn
, 0, 5);
10952 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10953 CryptoThreeOpEnvFn
*genfn
;
10955 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10957 unallocated_encoding(s
);
10962 case 0x4: /* AESE */
10964 genfn
= gen_helper_crypto_aese
;
10966 case 0x6: /* AESMC */
10968 genfn
= gen_helper_crypto_aesmc
;
10970 case 0x5: /* AESD */
10972 genfn
= gen_helper_crypto_aese
;
10974 case 0x7: /* AESIMC */
10976 genfn
= gen_helper_crypto_aesmc
;
10979 unallocated_encoding(s
);
10983 if (!fp_access_check(s
)) {
10987 /* Note that we convert the Vx register indexes into the
10988 * index within the vfp.regs[] array, so we can share the
10989 * helper with the AArch32 instructions.
10991 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10992 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10993 tcg_decrypt
= tcg_const_i32(decrypt
);
10995 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10997 tcg_temp_free_i32(tcg_rd_regno
);
10998 tcg_temp_free_i32(tcg_rn_regno
);
10999 tcg_temp_free_i32(tcg_decrypt
);
11002 /* Crypto three-reg SHA
11003 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
11004 * +-----------------+------+---+------+---+--------+-----+------+------+
11005 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
11006 * +-----------------+------+---+------+---+--------+-----+------+------+
11008 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
11010 int size
= extract32(insn
, 22, 2);
11011 int opcode
= extract32(insn
, 12, 3);
11012 int rm
= extract32(insn
, 16, 5);
11013 int rn
= extract32(insn
, 5, 5);
11014 int rd
= extract32(insn
, 0, 5);
11015 CryptoThreeOpEnvFn
*genfn
;
11016 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
11017 int feature
= ARM_FEATURE_V8_SHA256
;
11020 unallocated_encoding(s
);
11025 case 0: /* SHA1C */
11026 case 1: /* SHA1P */
11027 case 2: /* SHA1M */
11028 case 3: /* SHA1SU0 */
11030 feature
= ARM_FEATURE_V8_SHA1
;
11032 case 4: /* SHA256H */
11033 genfn
= gen_helper_crypto_sha256h
;
11035 case 5: /* SHA256H2 */
11036 genfn
= gen_helper_crypto_sha256h2
;
11038 case 6: /* SHA256SU1 */
11039 genfn
= gen_helper_crypto_sha256su1
;
11042 unallocated_encoding(s
);
11046 if (!arm_dc_feature(s
, feature
)) {
11047 unallocated_encoding(s
);
11051 if (!fp_access_check(s
)) {
11055 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11056 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11057 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11060 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11062 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11064 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11065 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11066 tcg_temp_free_i32(tcg_opcode
);
11069 tcg_temp_free_i32(tcg_rd_regno
);
11070 tcg_temp_free_i32(tcg_rn_regno
);
11071 tcg_temp_free_i32(tcg_rm_regno
);
11074 /* Crypto two-reg SHA
11075 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11076 * +-----------------+------+-----------+--------+-----+------+------+
11077 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11078 * +-----------------+------+-----------+--------+-----+------+------+
11080 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11082 int size
= extract32(insn
, 22, 2);
11083 int opcode
= extract32(insn
, 12, 5);
11084 int rn
= extract32(insn
, 5, 5);
11085 int rd
= extract32(insn
, 0, 5);
11086 CryptoTwoOpEnvFn
*genfn
;
11088 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11091 unallocated_encoding(s
);
11096 case 0: /* SHA1H */
11097 feature
= ARM_FEATURE_V8_SHA1
;
11098 genfn
= gen_helper_crypto_sha1h
;
11100 case 1: /* SHA1SU1 */
11101 feature
= ARM_FEATURE_V8_SHA1
;
11102 genfn
= gen_helper_crypto_sha1su1
;
11104 case 2: /* SHA256SU0 */
11105 feature
= ARM_FEATURE_V8_SHA256
;
11106 genfn
= gen_helper_crypto_sha256su0
;
11109 unallocated_encoding(s
);
11113 if (!arm_dc_feature(s
, feature
)) {
11114 unallocated_encoding(s
);
11118 if (!fp_access_check(s
)) {
11122 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11123 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11125 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11127 tcg_temp_free_i32(tcg_rd_regno
);
11128 tcg_temp_free_i32(tcg_rn_regno
);
11131 /* C3.6 Data processing - SIMD, inc Crypto
11133 * As the decode gets a little complex we are using a table based
11134 * approach for this part of the decode.
11136 static const AArch64DecodeTable data_proc_simd
[] = {
11137 /* pattern , mask , fn */
11138 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11139 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11140 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11141 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11142 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11143 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11144 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11145 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11146 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11147 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11148 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11149 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11150 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11151 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11152 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11153 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11154 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11155 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11156 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11157 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11158 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11159 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11160 { 0x00000000, 0x00000000, NULL
}
11163 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11165 /* Note that this is called with all non-FP cases from
11166 * table C3-6 so it must UNDEF for entries not specifically
11167 * allocated to instructions in that table.
11169 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11173 unallocated_encoding(s
);
11177 /* C3.6 Data processing - SIMD and floating point */
11178 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11180 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11181 disas_data_proc_fp(s
, insn
);
11183 /* SIMD, including crypto */
11184 disas_data_proc_simd(s
, insn
);
11188 /* C3.1 A64 instruction index by encoding */
11189 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11193 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11197 s
->fp_access_checked
= false;
11199 switch (extract32(insn
, 25, 4)) {
11200 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11201 unallocated_encoding(s
);
11203 case 0x8: case 0x9: /* Data processing - immediate */
11204 disas_data_proc_imm(s
, insn
);
11206 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11207 disas_b_exc_sys(s
, insn
);
11212 case 0xe: /* Loads and stores */
11213 disas_ldst(s
, insn
);
11216 case 0xd: /* Data processing - register */
11217 disas_data_proc_reg(s
, insn
);
11220 case 0xf: /* Data processing - SIMD and floating point */
11221 disas_data_proc_simd_fp(s
, insn
);
11224 assert(FALSE
); /* all 15 cases should be handled above */
11228 /* if we allocated any temporaries, free them here */
11232 static int aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
11233 CPUState
*cpu
, int max_insns
)
11235 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11236 CPUARMState
*env
= cpu
->env_ptr
;
11237 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
11240 dc
->pc
= dc
->base
.pc_first
;
11244 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11245 * there is no secure EL1, so we route exceptions to EL3.
11247 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11248 !arm_el_is_aa64(env
, 3);
11251 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
11252 dc
->condexec_mask
= 0;
11253 dc
->condexec_cond
= 0;
11254 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
11255 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
11256 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
11257 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11258 #if !defined(CONFIG_USER_ONLY)
11259 dc
->user
= (dc
->current_el
== 0);
11261 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
11263 dc
->vec_stride
= 0;
11264 dc
->cp_regs
= arm_cpu
->cp_regs
;
11265 dc
->features
= env
->features
;
11267 /* Single step state. The code-generation logic here is:
11269 * generate code with no special handling for single-stepping (except
11270 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11271 * this happens anyway because those changes are all system register or
11273 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11274 * emit code for one insn
11275 * emit code to clear PSTATE.SS
11276 * emit code to generate software step exception for completed step
11277 * end TB (as usual for having generated an exception)
11278 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11279 * emit code to generate a software step exception
11282 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
11283 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
11284 dc
->is_ldex
= false;
11285 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11287 /* Bound the number of insns to execute to those left on the page. */
11288 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11290 /* If architectural single step active, limit to 1. */
11291 if (dc
->ss_active
) {
11294 max_insns
= MIN(max_insns
, bound
);
11296 init_tmp_a64_array(dc
);
11301 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
11303 tcg_clear_temp_count();
11306 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11308 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11310 tcg_gen_insn_start(dc
->pc
, 0, 0);
11311 dc
->insn_start
= tcg_last_op();
11314 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11315 const CPUBreakpoint
*bp
)
11317 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11319 if (bp
->flags
& BP_CPU
) {
11320 gen_a64_set_pc_im(dc
->pc
);
11321 gen_helper_check_breakpoints(cpu_env
);
11322 /* End the TB early; it likely won't be executed */
11323 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11325 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11326 /* The address covered by the breakpoint must be
11327 included in [tb->pc, tb->pc + tb->size) in order
11328 to for it to be properly cleared -- thus we
11329 increment the PC here so that the logic setting
11330 tb->size below does the right thing. */
11332 dc
->base
.is_jmp
= DISAS_NORETURN
;
11338 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11340 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11341 CPUARMState
*env
= cpu
->env_ptr
;
11343 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11344 /* Singlestep state is Active-pending.
11345 * If we're in this state at the start of a TB then either
11346 * a) we just took an exception to an EL which is being debugged
11347 * and this is the first insn in the exception handler
11348 * b) debug exceptions were masked and we just unmasked them
11349 * without changing EL (eg by clearing PSTATE.D)
11350 * In either case we're going to take a swstep exception in the
11351 * "did not step an insn" case, and so the syndrome ISV and EX
11352 * bits should be zero.
11354 assert(dc
->base
.num_insns
== 1);
11355 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11356 default_exception_el(dc
));
11357 dc
->base
.is_jmp
= DISAS_NORETURN
;
11359 disas_a64_insn(env
, dc
);
11362 dc
->base
.pc_next
= dc
->pc
;
11363 translator_loop_temp_check(&dc
->base
);
11366 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
11368 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11370 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
11371 /* Note that this means single stepping WFI doesn't halt the CPU.
11372 * For conditional branch insns this is harmless unreachable code as
11373 * gen_goto_tb() has already handled emitting the debug exception
11374 * (and thus a tb-jump is not possible when singlestepping).
11376 switch (dc
->base
.is_jmp
) {
11378 gen_a64_set_pc_im(dc
->pc
);
11382 if (dc
->base
.singlestep_enabled
) {
11383 gen_exception_internal(EXCP_DEBUG
);
11385 gen_step_complete_exception(dc
);
11388 case DISAS_NORETURN
:
11392 switch (dc
->base
.is_jmp
) {
11394 case DISAS_TOO_MANY
:
11395 gen_goto_tb(dc
, 1, dc
->pc
);
11399 gen_a64_set_pc_im(dc
->pc
);
11402 tcg_gen_lookup_and_goto_ptr();
11405 tcg_gen_exit_tb(0);
11407 case DISAS_NORETURN
:
11411 gen_a64_set_pc_im(dc
->pc
);
11412 gen_helper_wfe(cpu_env
);
11415 gen_a64_set_pc_im(dc
->pc
);
11416 gen_helper_yield(cpu_env
);
11420 /* This is a special case because we don't want to just halt the CPU
11421 * if trying to debug across a WFI.
11423 TCGv_i32 tmp
= tcg_const_i32(4);
11425 gen_a64_set_pc_im(dc
->pc
);
11426 gen_helper_wfi(cpu_env
, tmp
);
11427 tcg_temp_free_i32(tmp
);
11428 /* The helper doesn't necessarily throw an exception, but we
11429 * must go back to the main loop to check for interrupts anyway.
11431 tcg_gen_exit_tb(0);
11437 /* Functions above can change dc->pc, so re-align db->pc_next */
11438 dc
->base
.pc_next
= dc
->pc
;
11441 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
11444 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11446 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
11447 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
11450 const TranslatorOps aarch64_translator_ops
= {
11451 .init_disas_context
= aarch64_tr_init_disas_context
,
11452 .tb_start
= aarch64_tr_tb_start
,
11453 .insn_start
= aarch64_tr_insn_start
,
11454 .breakpoint_check
= aarch64_tr_breakpoint_check
,
11455 .translate_insn
= aarch64_tr_translate_insn
,
11456 .tb_stop
= aarch64_tr_tb_stop
,
11457 .disas_log
= aarch64_tr_disas_log
,