4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu/qemu-print.h"
31 static void cris_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 CRISCPU
*cpu
= CRIS_CPU(cs
);
38 static vaddr
cris_cpu_get_pc(CPUState
*cs
)
40 CRISCPU
*cpu
= CRIS_CPU(cs
);
45 static void cris_restore_state_to_opc(CPUState
*cs
,
46 const TranslationBlock
*tb
,
49 CRISCPU
*cpu
= CRIS_CPU(cs
);
51 cpu
->env
.pc
= data
[0];
54 static bool cris_cpu_has_work(CPUState
*cs
)
56 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
59 static void cris_cpu_reset_hold(Object
*obj
)
61 CPUState
*s
= CPU(obj
);
62 CRISCPU
*cpu
= CRIS_CPU(s
);
63 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(cpu
);
64 CPUCRISState
*env
= &cpu
->env
;
67 if (ccc
->parent_phases
.hold
) {
68 ccc
->parent_phases
.hold(obj
);
71 vr
= env
->pregs
[PR_VR
];
72 memset(env
, 0, offsetof(CPUCRISState
, end_reset_fields
));
73 env
->pregs
[PR_VR
] = vr
;
75 #if defined(CONFIG_USER_ONLY)
76 /* start in user mode with interrupts enabled. */
77 env
->pregs
[PR_CCS
] |= U_FLAG
| I_FLAG
| P_FLAG
;
80 env
->pregs
[PR_CCS
] = 0;
84 static ObjectClass
*cris_cpu_class_by_name(const char *cpu_model
)
89 #if defined(CONFIG_USER_ONLY)
90 if (strcasecmp(cpu_model
, "any") == 0) {
91 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32"));
95 typename
= g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model
);
96 oc
= object_class_by_name(typename
);
98 if (oc
!= NULL
&& (!object_class_dynamic_cast(oc
, TYPE_CRIS_CPU
) ||
99 object_class_is_abstract(oc
))) {
105 /* Sort alphabetically by VR. */
106 static gint
cris_cpu_list_compare(gconstpointer a
, gconstpointer b
)
108 CRISCPUClass
*ccc_a
= CRIS_CPU_CLASS(a
);
109 CRISCPUClass
*ccc_b
= CRIS_CPU_CLASS(b
);
112 if (ccc_a
->vr
> ccc_b
->vr
) {
114 } else if (ccc_a
->vr
< ccc_b
->vr
) {
121 static void cris_cpu_list_entry(gpointer data
, gpointer user_data
)
123 ObjectClass
*oc
= data
;
124 const char *typename
= object_class_get_name(oc
);
127 name
= g_strndup(typename
, strlen(typename
) - strlen(CRIS_CPU_TYPE_SUFFIX
));
128 qemu_printf(" %s\n", name
);
132 void cris_cpu_list(void)
136 list
= object_class_get_list(TYPE_CRIS_CPU
, false);
137 list
= g_slist_sort(list
, cris_cpu_list_compare
);
138 qemu_printf("Available CPUs:\n");
139 g_slist_foreach(list
, cris_cpu_list_entry
, NULL
);
143 static void cris_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
145 CPUState
*cs
= CPU(dev
);
146 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(dev
);
147 Error
*local_err
= NULL
;
149 cpu_exec_realizefn(cs
, &local_err
);
150 if (local_err
!= NULL
) {
151 error_propagate(errp
, local_err
);
158 ccc
->parent_realize(dev
, errp
);
161 #ifndef CONFIG_USER_ONLY
162 static void cris_cpu_set_irq(void *opaque
, int irq
, int level
)
164 CRISCPU
*cpu
= opaque
;
165 CPUState
*cs
= CPU(cpu
);
166 int type
= irq
== CRIS_CPU_IRQ
? CPU_INTERRUPT_HARD
: CPU_INTERRUPT_NMI
;
168 if (irq
== CRIS_CPU_IRQ
) {
170 * The PIC passes us the vector for the IRQ as the value it sends
171 * over the qemu_irq line
173 cpu
->env
.interrupt_vector
= level
;
177 cpu_interrupt(cs
, type
);
179 cpu_reset_interrupt(cs
, type
);
184 static void cris_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
186 CRISCPU
*cc
= CRIS_CPU(cpu
);
187 CPUCRISState
*env
= &cc
->env
;
189 if (env
->pregs
[PR_VR
] != 32) {
190 info
->mach
= bfd_mach_cris_v0_v10
;
191 info
->print_insn
= print_insn_crisv10
;
193 info
->mach
= bfd_mach_cris_v32
;
194 info
->print_insn
= print_insn_crisv32
;
198 static void cris_cpu_initfn(Object
*obj
)
200 CRISCPU
*cpu
= CRIS_CPU(obj
);
201 CRISCPUClass
*ccc
= CRIS_CPU_GET_CLASS(obj
);
202 CPUCRISState
*env
= &cpu
->env
;
204 env
->pregs
[PR_VR
] = ccc
->vr
;
206 #ifndef CONFIG_USER_ONLY
207 /* IRQ and NMI lines. */
208 qdev_init_gpio_in(DEVICE(cpu
), cris_cpu_set_irq
, 2);
212 #ifndef CONFIG_USER_ONLY
213 #include "hw/core/sysemu-cpu-ops.h"
215 static const struct SysemuCPUOps cris_sysemu_ops
= {
216 .get_phys_page_debug
= cris_cpu_get_phys_page_debug
,
220 #include "hw/core/tcg-cpu-ops.h"
222 static const struct TCGCPUOps crisv10_tcg_ops
= {
223 .initialize
= cris_initialize_crisv10_tcg
,
224 .restore_state_to_opc
= cris_restore_state_to_opc
,
226 #ifndef CONFIG_USER_ONLY
227 .tlb_fill
= cris_cpu_tlb_fill
,
228 .cpu_exec_interrupt
= cris_cpu_exec_interrupt
,
229 .do_interrupt
= crisv10_cpu_do_interrupt
,
230 #endif /* !CONFIG_USER_ONLY */
233 static const struct TCGCPUOps crisv32_tcg_ops
= {
234 .initialize
= cris_initialize_tcg
,
235 .restore_state_to_opc
= cris_restore_state_to_opc
,
237 #ifndef CONFIG_USER_ONLY
238 .tlb_fill
= cris_cpu_tlb_fill
,
239 .cpu_exec_interrupt
= cris_cpu_exec_interrupt
,
240 .do_interrupt
= cris_cpu_do_interrupt
,
241 #endif /* !CONFIG_USER_ONLY */
244 static void crisv8_cpu_class_init(ObjectClass
*oc
, void *data
)
246 CPUClass
*cc
= CPU_CLASS(oc
);
247 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
250 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
251 cc
->tcg_ops
= &crisv10_tcg_ops
;
254 static void crisv9_cpu_class_init(ObjectClass
*oc
, void *data
)
256 CPUClass
*cc
= CPU_CLASS(oc
);
257 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
260 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
261 cc
->tcg_ops
= &crisv10_tcg_ops
;
264 static void crisv10_cpu_class_init(ObjectClass
*oc
, void *data
)
266 CPUClass
*cc
= CPU_CLASS(oc
);
267 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
270 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
271 cc
->tcg_ops
= &crisv10_tcg_ops
;
274 static void crisv11_cpu_class_init(ObjectClass
*oc
, void *data
)
276 CPUClass
*cc
= CPU_CLASS(oc
);
277 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
280 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
281 cc
->tcg_ops
= &crisv10_tcg_ops
;
284 static void crisv17_cpu_class_init(ObjectClass
*oc
, void *data
)
286 CPUClass
*cc
= CPU_CLASS(oc
);
287 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
290 cc
->gdb_read_register
= crisv10_cpu_gdb_read_register
;
291 cc
->tcg_ops
= &crisv10_tcg_ops
;
294 static void crisv32_cpu_class_init(ObjectClass
*oc
, void *data
)
296 CPUClass
*cc
= CPU_CLASS(oc
);
297 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
300 cc
->tcg_ops
= &crisv32_tcg_ops
;
303 static void cris_cpu_class_init(ObjectClass
*oc
, void *data
)
305 DeviceClass
*dc
= DEVICE_CLASS(oc
);
306 CPUClass
*cc
= CPU_CLASS(oc
);
307 CRISCPUClass
*ccc
= CRIS_CPU_CLASS(oc
);
308 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
310 device_class_set_parent_realize(dc
, cris_cpu_realizefn
,
311 &ccc
->parent_realize
);
313 resettable_class_set_parent_phases(rc
, NULL
, cris_cpu_reset_hold
, NULL
,
314 &ccc
->parent_phases
);
316 cc
->class_by_name
= cris_cpu_class_by_name
;
317 cc
->has_work
= cris_cpu_has_work
;
318 cc
->dump_state
= cris_cpu_dump_state
;
319 cc
->set_pc
= cris_cpu_set_pc
;
320 cc
->get_pc
= cris_cpu_get_pc
;
321 cc
->gdb_read_register
= cris_cpu_gdb_read_register
;
322 cc
->gdb_write_register
= cris_cpu_gdb_write_register
;
323 #ifndef CONFIG_USER_ONLY
324 dc
->vmsd
= &vmstate_cris_cpu
;
325 cc
->sysemu_ops
= &cris_sysemu_ops
;
328 cc
->gdb_num_core_regs
= 49;
329 cc
->gdb_stop_before_watchpoint
= true;
331 cc
->disas_set_info
= cris_disas_set_info
;
334 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
336 .parent = TYPE_CRIS_CPU, \
337 .class_init = initfn, \
338 .name = CRIS_CPU_TYPE_NAME(cpu_model), \
341 static const TypeInfo cris_cpu_model_type_infos
[] = {
343 .name
= TYPE_CRIS_CPU
,
345 .instance_size
= sizeof(CRISCPU
),
346 .instance_align
= __alignof(CRISCPU
),
347 .instance_init
= cris_cpu_initfn
,
349 .class_size
= sizeof(CRISCPUClass
),
350 .class_init
= cris_cpu_class_init
,
352 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init
),
353 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init
),
354 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init
),
355 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init
),
356 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init
),
357 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init
),
360 DEFINE_TYPES(cris_cpu_model_type_infos
)