| blob | 3c38e868e2ec0350468b5e91ae326e3db468e88c |
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "elf.h"
26 #include "../tcg-ldst.c.inc"
27 #include "../tcg-pool.c.inc"
29 int arm_arch = __ARM_ARCH;
31 #ifndef use_idiv_instructions
32 bool use_idiv_instructions;
33 #endif
34 #ifndef use_neon_instructions
35 bool use_neon_instructions;
36 #endif
38 #ifdef CONFIG_DEBUG_TCG
39 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
40 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
41 "%r8", "%r9", "%r10", "%r11", "%r12", "%sp", "%r14", "%pc",
42 "%q0", "%q1", "%q2", "%q3", "%q4", "%q5", "%q6", "%q7",
43 "%q8", "%q9", "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
44 };
45 #endif
47 static const int tcg_target_reg_alloc_order[] = {
48 TCG_REG_R4,
49 TCG_REG_R5,
50 TCG_REG_R6,
51 TCG_REG_R7,
52 TCG_REG_R8,
53 TCG_REG_R9,
54 TCG_REG_R10,
55 TCG_REG_R11,
56 TCG_REG_R13,
57 TCG_REG_R0,
58 TCG_REG_R1,
59 TCG_REG_R2,
60 TCG_REG_R3,
61 TCG_REG_R12,
62 TCG_REG_R14,
64 TCG_REG_Q0,
65 TCG_REG_Q1,
66 TCG_REG_Q2,
67 TCG_REG_Q3,
68 /* Q4 - Q7 are call-saved, and skipped. */
69 TCG_REG_Q8,
70 TCG_REG_Q9,
71 TCG_REG_Q10,
72 TCG_REG_Q11,
73 TCG_REG_Q12,
74 TCG_REG_Q13,
75 TCG_REG_Q14,
76 TCG_REG_Q15,
77 };
79 static const int tcg_target_call_iarg_regs[4] = {
80 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
81 };
83 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
84 {
85 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
86 tcg_debug_assert(slot >= 0 && slot <= 3);
87 return TCG_REG_R0 + slot;
88 }
90 #define TCG_REG_TMP TCG_REG_R12
91 #define TCG_VEC_TMP TCG_REG_Q15
92 #ifndef CONFIG_SOFTMMU
93 #define TCG_REG_GUEST_BASE TCG_REG_R11
94 #endif
96 typedef enum {
97 COND_EQ = 0x0,
98 COND_NE = 0x1,
99 COND_CS = 0x2, /* Unsigned greater or equal */
100 COND_CC = 0x3, /* Unsigned less than */
101 COND_MI = 0x4, /* Negative */
102 COND_PL = 0x5, /* Zero or greater */
103 COND_VS = 0x6, /* Overflow */
104 COND_VC = 0x7, /* No overflow */
105 COND_HI = 0x8, /* Unsigned greater than */
106 COND_LS = 0x9, /* Unsigned less or equal */
107 COND_GE = 0xa,
108 COND_LT = 0xb,
109 COND_GT = 0xc,
110 COND_LE = 0xd,
111 COND_AL = 0xe,
112 } ARMCond;
114 #define TO_CPSR (1 << 20)
116 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
117 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
118 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
119 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
120 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
121 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
122 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
123 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
125 typedef enum {
126 ARITH_AND = 0x0 << 21,
127 ARITH_EOR = 0x1 << 21,
128 ARITH_SUB = 0x2 << 21,
129 ARITH_RSB = 0x3 << 21,
130 ARITH_ADD = 0x4 << 21,
131 ARITH_ADC = 0x5 << 21,
132 ARITH_SBC = 0x6 << 21,
133 ARITH_RSC = 0x7 << 21,
134 ARITH_TST = 0x8 << 21 | TO_CPSR,
135 ARITH_CMP = 0xa << 21 | TO_CPSR,
136 ARITH_CMN = 0xb << 21 | TO_CPSR,
137 ARITH_ORR = 0xc << 21,
138 ARITH_MOV = 0xd << 21,
139 ARITH_BIC = 0xe << 21,
140 ARITH_MVN = 0xf << 21,
142 INSN_B = 0x0a000000,
144 INSN_CLZ = 0x016f0f10,
145 INSN_RBIT = 0x06ff0f30,
147 INSN_LDMIA = 0x08b00000,
148 INSN_STMDB = 0x09200000,
150 INSN_LDR_IMM = 0x04100000,
151 INSN_LDR_REG = 0x06100000,
152 INSN_STR_IMM = 0x04000000,
153 INSN_STR_REG = 0x06000000,
155 INSN_LDRH_IMM = 0x005000b0,
156 INSN_LDRH_REG = 0x001000b0,
157 INSN_LDRSH_IMM = 0x005000f0,
158 INSN_LDRSH_REG = 0x001000f0,
159 INSN_STRH_IMM = 0x004000b0,
160 INSN_STRH_REG = 0x000000b0,
162 INSN_LDRB_IMM = 0x04500000,
163 INSN_LDRB_REG = 0x06500000,
164 INSN_LDRSB_IMM = 0x005000d0,
165 INSN_LDRSB_REG = 0x001000d0,
166 INSN_STRB_IMM = 0x04400000,
167 INSN_STRB_REG = 0x06400000,
169 INSN_LDRD_IMM = 0x004000d0,
170 INSN_LDRD_REG = 0x000000d0,
171 INSN_STRD_IMM = 0x004000f0,
172 INSN_STRD_REG = 0x000000f0,
174 INSN_DMB_ISH = 0xf57ff05b,
175 INSN_DMB_MCR = 0xee070fba,
177 /* Architected nop introduced in v6k. */
178 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
179 also Just So Happened to do nothing on pre-v6k so that we
180 don't need to conditionalize it? */
181 INSN_NOP_v6k = 0xe320f000,
182 /* Otherwise the assembler uses mov r0,r0 */
183 INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
185 INSN_VADD = 0xf2000800,
186 INSN_VAND = 0xf2000110,
187 INSN_VBIC = 0xf2100110,
188 INSN_VEOR = 0xf3000110,
189 INSN_VORN = 0xf2300110,
190 INSN_VORR = 0xf2200110,
191 INSN_VSUB = 0xf3000800,
192 INSN_VMUL = 0xf2000910,
193 INSN_VQADD = 0xf2000010,
194 INSN_VQADD_U = 0xf3000010,
195 INSN_VQSUB = 0xf2000210,
196 INSN_VQSUB_U = 0xf3000210,
197 INSN_VMAX = 0xf2000600,
198 INSN_VMAX_U = 0xf3000600,
199 INSN_VMIN = 0xf2000610,
200 INSN_VMIN_U = 0xf3000610,
202 INSN_VABS = 0xf3b10300,
203 INSN_VMVN = 0xf3b00580,
204 INSN_VNEG = 0xf3b10380,
206 INSN_VCEQ0 = 0xf3b10100,
207 INSN_VCGT0 = 0xf3b10000,
208 INSN_VCGE0 = 0xf3b10080,
209 INSN_VCLE0 = 0xf3b10180,
210 INSN_VCLT0 = 0xf3b10200,
212 INSN_VCEQ = 0xf3000810,
213 INSN_VCGE = 0xf2000310,
214 INSN_VCGT = 0xf2000300,
215 INSN_VCGE_U = 0xf3000310,
216 INSN_VCGT_U = 0xf3000300,
218 INSN_VSHLI = 0xf2800510, /* VSHL (immediate) */
219 INSN_VSARI = 0xf2800010, /* VSHR.S */
220 INSN_VSHRI = 0xf3800010, /* VSHR.U */
221 INSN_VSLI = 0xf3800510,
222 INSN_VSHL_S = 0xf2000400, /* VSHL.S (register) */
223 INSN_VSHL_U = 0xf3000400, /* VSHL.U (register) */
225 INSN_VBSL = 0xf3100110,
226 INSN_VBIT = 0xf3200110,
227 INSN_VBIF = 0xf3300110,
229 INSN_VTST = 0xf2000810,
231 INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
232 INSN_VDUP_S = 0xf3b00c00, /* VDUP (scalar) */
233 INSN_VLDR_D = 0xed100b00, /* VLDR.64 */
234 INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
235 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */
236 INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
237 INSN_VMOVI = 0xf2800010, /* VMOV (immediate) */
238 } ARMInsn;
240 #define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
242 static const uint8_t tcg_cond_to_arm_cond[] = {
243 [TCG_COND_EQ] = COND_EQ,
244 [TCG_COND_NE] = COND_NE,
245 [TCG_COND_LT] = COND_LT,
246 [TCG_COND_GE] = COND_GE,
247 [TCG_COND_LE] = COND_LE,
248 [TCG_COND_GT] = COND_GT,
249 /* unsigned */
250 [TCG_COND_LTU] = COND_CC,
251 [TCG_COND_GEU] = COND_CS,
252 [TCG_COND_LEU] = COND_LS,
253 [TCG_COND_GTU] = COND_HI,
254 };
256 static int encode_imm(uint32_t imm);
258 /* TCG private relocation type: add with pc+imm8 */
259 #define R_ARM_PC8 11
261 /* TCG private relocation type: vldr with imm8 << 2 */
262 #define R_ARM_PC11 12
264 static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
265 {
266 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
267 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2;
269 if (offset == sextract32(offset, 0, 24)) {
270 *src_rw = deposit32(*src_rw, 0, 24, offset);
271 return true;
272 }
273 return false;
274 }
276 static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
277 {
278 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
279 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
281 if (offset >= -0xfff && offset <= 0xfff) {
282 tcg_insn_unit insn = *src_rw;
283 bool u = (offset >= 0);
284 if (!u) {
285 offset = -offset;
286 }
287 insn = deposit32(insn, 23, 1, u);
288 insn = deposit32(insn, 0, 12, offset);
289 *src_rw = insn;
290 return true;
291 }
292 return false;
293 }
295 static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
296 {
297 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
298 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
300 if (offset >= -0xff && offset <= 0xff) {
301 tcg_insn_unit insn = *src_rw;
302 bool u = (offset >= 0);
303 if (!u) {
304 offset = -offset;
305 }
306 insn = deposit32(insn, 23, 1, u);
307 insn = deposit32(insn, 0, 8, offset);
308 *src_rw = insn;
309 return true;
310 }
311 return false;
312 }
314 static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
315 {
316 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
317 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
318 int imm12 = encode_imm(offset);
320 if (imm12 >= 0) {
321 *src_rw = deposit32(*src_rw, 0, 12, imm12);
322 return true;
323 }
324 return false;
325 }
327 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
328 intptr_t value, intptr_t addend)
329 {
330 tcg_debug_assert(addend == 0);
331 switch (type) {
332 case R_ARM_PC24:
333 return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
334 case R_ARM_PC13:
335 return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
336 case R_ARM_PC11:
337 return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
338 case R_ARM_PC8:
339 return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
340 default:
341 g_assert_not_reached();
342 }
343 }
345 #define TCG_CT_CONST_ARM 0x100
346 #define TCG_CT_CONST_INV 0x200
347 #define TCG_CT_CONST_NEG 0x400
348 #define TCG_CT_CONST_ZERO 0x800
349 #define TCG_CT_CONST_ORRI 0x1000
350 #define TCG_CT_CONST_ANDI 0x2000
352 #define ALL_GENERAL_REGS 0xffffu
353 #define ALL_VECTOR_REGS 0xffff0000u
355 /*
356 * r0-r3 will be overwritten when reading the tlb entry (softmmu only);
357 * r14 will be overwritten by the BLNE branching to the slow path.
358 */
359 #ifdef CONFIG_SOFTMMU
360 #define ALL_QLDST_REGS \
361 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
362 (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
363 (1 << TCG_REG_R14)))
364 #else
365 #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R14))
366 #endif
368 /*
369 * ARM immediates for ALU instructions are made of an unsigned 8-bit
370 * right-rotated by an even amount between 0 and 30.
371 *
372 * Return < 0 if @imm cannot be encoded, else the entire imm12 field.
373 */
374 static int encode_imm(uint32_t imm)
375 {
376 uint32_t rot, imm8;
378 /* Simple case, no rotation required. */
379 if ((imm & ~0xff) == 0) {
380 return imm;
381 }
383 /* Next, try a simple even shift. */
384 rot = ctz32(imm) & ~1;
385 imm8 = imm >> rot;
386 rot = 32 - rot;
387 if ((imm8 & ~0xff) == 0) {
388 goto found;
389 }
391 /*
392 * Finally, try harder with rotations.
393 * The ctz test above will have taken care of rotates >= 8.
394 */
395 for (rot = 2; rot < 8; rot += 2) {
396 imm8 = rol32(imm, rot);
397 if ((imm8 & ~0xff) == 0) {
398 goto found;
399 }
400 }
401 /* Fail: imm cannot be encoded. */
402 return -1;
404 found:
405 /* Note that rot is even, and we discard bit 0 by shifting by 7. */
406 return rot << 7 | imm8;
407 }
409 static int encode_imm_nofail(uint32_t imm)
410 {
411 int ret = encode_imm(imm);
412 tcg_debug_assert(ret >= 0);
413 return ret;
414 }
416 static bool check_fit_imm(uint32_t imm)
417 {
418 return encode_imm(imm) >= 0;
419 }
421 /* Return true if v16 is a valid 16-bit shifted immediate. */
422 static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
423 {
424 if (v16 == (v16 & 0xff)) {
425 *cmode = 0x8;
426 *imm8 = v16 & 0xff;
427 return true;
428 } else if (v16 == (v16 & 0xff00)) {
429 *cmode = 0xa;
430 *imm8 = v16 >> 8;
431 return true;
432 }
433 return false;
434 }
436 /* Return true if v32 is a valid 32-bit shifted immediate. */
437 static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
438 {
439 if (v32 == (v32 & 0xff)) {
440 *cmode = 0x0;
441 *imm8 = v32 & 0xff;
442 return true;
443 } else if (v32 == (v32 & 0xff00)) {
444 *cmode = 0x2;
445 *imm8 = (v32 >> 8) & 0xff;
446 return true;
447 } else if (v32 == (v32 & 0xff0000)) {
448 *cmode = 0x4;
449 *imm8 = (v32 >> 16) & 0xff;
450 return true;
451 } else if (v32 == (v32 & 0xff000000)) {
452 *cmode = 0x6;
453 *imm8 = v32 >> 24;
454 return true;
455 }
456 return false;
457 }
459 /* Return true if v32 is a valid 32-bit shifting ones immediate. */
460 static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
461 {
462 if ((v32 & 0xffff00ff) == 0xff) {
463 *cmode = 0xc;
464 *imm8 = (v32 >> 8) & 0xff;
465 return true;
466 } else if ((v32 & 0xff00ffff) == 0xffff) {
467 *cmode = 0xd;
468 *imm8 = (v32 >> 16) & 0xff;
469 return true;
470 }
471 return false;
472 }
474 /*
475 * Return non-zero if v32 can be formed by MOVI+ORR.
476 * Place the parameters for MOVI in (cmode, imm8).
477 * Return the cmode for ORR; the imm8 can be had via extraction from v32.
478 */
479 static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
480 {
481 int i;
483 for (i = 6; i > 0; i -= 2) {
484 /* Mask out one byte we can add with ORR. */
485 uint32_t tmp = v32 & ~(0xffu << (i * 4));
486 if (is_shimm32(tmp, cmode, imm8) ||
487 is_soimm32(tmp, cmode, imm8)) {
488 break;
489 }
490 }
491 return i;
492 }
494 /* Return true if V is a valid 16-bit or 32-bit shifted immediate. */
495 static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
496 {
497 if (v32 == deposit32(v32, 16, 16, v32)) {
498 return is_shimm16(v32, cmode, imm8);
499 } else {
500 return is_shimm32(v32, cmode, imm8);
501 }
502 }
504 /* Test if a constant matches the constraint.
505 * TODO: define constraints for:
506 *
507 * ldr/str offset: between -0xfff and 0xfff
508 * ldrh/strh offset: between -0xff and 0xff
509 * mov operand2: values represented with x << (2 * y), x < 0x100
510 * add, sub, eor...: ditto
511 */
512 static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
513 {
514 if (ct & TCG_CT_CONST) {
515 return 1;
516 } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
517 return 1;
518 } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) {
519 return 1;
520 } else if ((ct & TCG_CT_CONST_NEG) && check_fit_imm(-val)) {
521 return 1;
522 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
523 return 1;
524 }
526 switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
527 case 0:
528 break;
529 case TCG_CT_CONST_ANDI:
530 val = ~val;
531 /* fallthru */
532 case TCG_CT_CONST_ORRI:
533 if (val == deposit64(val, 32, 32, val)) {
534 int cmode, imm8;
535 return is_shimm1632(val, &cmode, &imm8);
536 }
537 break;
538 default:
539 /* Both bits should not be set for the same insn. */
540 g_assert_not_reached();
541 }
543 return 0;
544 }
546 static void tcg_out_b_imm(TCGContext *s, ARMCond cond, int32_t offset)
547 {
548 tcg_out32(s, (cond << 28) | INSN_B |
549 (((offset - 8) >> 2) & 0x00ffffff));
550 }
552 static void tcg_out_bl_imm(TCGContext *s, ARMCond cond, int32_t offset)
553 {
554 tcg_out32(s, (cond << 28) | 0x0b000000 |
555 (((offset - 8) >> 2) & 0x00ffffff));
556 }
558 static void tcg_out_blx_reg(TCGContext *s, ARMCond cond, TCGReg rn)
559 {
560 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
561 }
563 static void tcg_out_blx_imm(TCGContext *s, int32_t offset)
564 {
565 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
566 (((offset - 8) >> 2) & 0x00ffffff));
567 }
569 static void tcg_out_dat_reg(TCGContext *s, ARMCond cond, ARMInsn opc,
570 TCGReg rd, TCGReg rn, TCGReg rm, int shift)
571 {
572 tcg_out32(s, (cond << 28) | (0 << 25) | opc |
573 (rn << 16) | (rd << 12) | shift | rm);
574 }
576 static void tcg_out_mov_reg(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rm)
577 {
578 /* Simple reg-reg move, optimising out the 'do nothing' case */
579 if (rd != rm) {
580 tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0));
581 }
582 }
584 static void tcg_out_bx_reg(TCGContext *s, ARMCond cond, TCGReg rn)
585 {
586 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
587 }
589 static void tcg_out_b_reg(TCGContext *s, ARMCond cond, TCGReg rn)
590 {
591 /*
592 * Unless the C portion of QEMU is compiled as thumb, we don't need
593 * true BX semantics; merely a branch to an address held in a register.
594 */
595 tcg_out_bx_reg(s, cond, rn);
596 }
598 static void tcg_out_dat_imm(TCGContext *s, ARMCond cond, ARMInsn opc,
599 TCGReg rd, TCGReg rn, int im)
600 {
601 tcg_out32(s, (cond << 28) | (1 << 25) | opc |
602 (rn << 16) | (rd << 12) | im);
603 }
605 static void tcg_out_ldstm(TCGContext *s, ARMCond cond, ARMInsn opc,
606 TCGReg rn, uint16_t mask)
607 {
608 tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask);
609 }
611 /* Note that this routine is used for both LDR and LDRH formats, so we do
612 not wish to include an immediate shift at this point. */
613 static void tcg_out_memop_r(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
614 TCGReg rn, TCGReg rm, bool u, bool p, bool w)
615 {
616 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24)
617 | (w << 21) | (rn << 16) | (rt << 12) | rm);
618 }
620 static void tcg_out_memop_8(TCGContext *s, ARMCond cond, ARMInsn opc, TCGReg rt,
621 TCGReg rn, int imm8, bool p, bool w)
622 {
623 bool u = 1;
624 if (imm8 < 0) {
625 imm8 = -imm8;
626 u = 0;
627 }
628 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
629 (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf));
630 }
632 static void tcg_out_memop_12(TCGContext *s, ARMCond cond, ARMInsn opc,
633 TCGReg rt, TCGReg rn, int imm12, bool p, bool w)
634 {
635 bool u = 1;
636 if (imm12 < 0) {
637 imm12 = -imm12;
638 u = 0;
639 }
640 tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) |
641 (rn << 16) | (rt << 12) | imm12);
642 }
644 static void tcg_out_ld32_12(TCGContext *s, ARMCond cond, TCGReg rt,
645 TCGReg rn, int imm12)
646 {
647 tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
648 }
650 static void tcg_out_st32_12(TCGContext *s, ARMCond cond, TCGReg rt,
651 TCGReg rn, int imm12)
652 {
653 tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0);
654 }
656 static void tcg_out_ld32_r(TCGContext *s, ARMCond cond, TCGReg rt,
657 TCGReg rn, TCGReg rm)
658 {
659 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0);
660 }
662 static void tcg_out_st32_r(TCGContext *s, ARMCond cond, TCGReg rt,
663 TCGReg rn, TCGReg rm)
664 {
665 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0);
666 }
668 static void tcg_out_ldrd_8(TCGContext *s, ARMCond cond, TCGReg rt,
669 TCGReg rn, int imm8)
670 {
671 tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0);
672 }
674 static void tcg_out_ldrd_r(TCGContext *s, ARMCond cond, TCGReg rt,
675 TCGReg rn, TCGReg rm)
676 {
677 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0);
678 }
680 static void __attribute__((unused))
681 tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, TCGReg rm)
682 {
683 tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1);
684 }
686 static void __attribute__((unused))
687 tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8)
688 {
689 tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0);
690 }
692 static void tcg_out_strd_r(TCGContext *s, ARMCond cond, TCGReg rt,
693 TCGReg rn, TCGReg rm)
694 {
695 tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0);
696 }
698 /* Register pre-increment with base writeback. */
699 static void tcg_out_ld32_rwb(TCGContext *s, ARMCond cond, TCGReg rt,
700 TCGReg rn, TCGReg rm)
701 {
702 tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1);
703 }
705 static void tcg_out_st32_rwb(TCGContext *s, ARMCond cond, TCGReg rt,
706 TCGReg rn, TCGReg rm)
707 {
708 tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1);
709 }
711 static void tcg_out_ld16u_8(TCGContext *s, ARMCond cond, TCGReg rt,
712 TCGReg rn, int imm8)
713 {
714 tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0);
715 }
717 static void tcg_out_st16_8(TCGContext *s, ARMCond cond, TCGReg rt,
718 TCGReg rn, int imm8)
719 {
720 tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0);
721 }
723 static void tcg_out_ld16u_r(TCGContext *s, ARMCond cond, TCGReg rt,
724 TCGReg rn, TCGReg rm)
725 {
726 tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0);
727 }
729 static void tcg_out_st16_r(TCGContext *s, ARMCond cond, TCGReg rt,
730 TCGReg rn, TCGReg rm)
731 {
732 tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0);
733 }
735 static void tcg_out_ld16s_8(TCGContext *s, ARMCond cond, TCGReg rt,
736 TCGReg rn, int imm8)
737 {
738 tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0);
739 }
741 static void tcg_out_ld16s_r(TCGContext *s, ARMCond cond, TCGReg rt,
742 TCGReg rn, TCGReg rm)
743 {
744 tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0);
745 }
747 static void tcg_out_ld8_12(TCGContext *s, ARMCond cond, TCGReg rt,
748 TCGReg rn, int imm12)
749 {
750 tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0);
751 }
753 static void tcg_out_st8_12(TCGContext *s, ARMCond cond, TCGReg rt,
754 TCGReg rn, int imm12)
755 {
756 tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0);
757 }
759 static void tcg_out_ld8_r(TCGContext *s, ARMCond cond, TCGReg rt,
760 TCGReg rn, TCGReg rm)
761 {
762 tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0);
763 }
765 static void tcg_out_st8_r(TCGContext *s, ARMCond cond, TCGReg rt,
766 TCGReg rn, TCGReg rm)
767 {
768 tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0);
769 }
771 static void tcg_out_ld8s_8(TCGContext *s, ARMCond cond, TCGReg rt,
772 TCGReg rn, int imm8)
773 {
774 tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0);
775 }
777 static void tcg_out_ld8s_r(TCGContext *s, ARMCond cond, TCGReg rt,
778 TCGReg rn, TCGReg rm)
779 {
780 tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);
781 }
783 static void tcg_out_movi_pool(TCGContext *s, ARMCond cond,
784 TCGReg rd, uint32_t arg)
785 {
786 new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
787 tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
788 }
790 static void tcg_out_movi32(TCGContext *s, ARMCond cond,
791 TCGReg rd, uint32_t arg)
792 {
793 int imm12, diff, opc, sh1, sh2;
794 uint32_t tt0, tt1, tt2;
796 /* Check a single MOV/MVN before anything else. */
797 imm12 = encode_imm(arg);
798 if (imm12 >= 0) {
799 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, imm12);
800 return;
801 }
802 imm12 = encode_imm(~arg);
803 if (imm12 >= 0) {
804 tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, imm12);
805 return;
806 }
808 /* Check for a pc-relative address. This will usually be the TB,
809 or within the TB, which is immediately before the code block. */
810 diff = tcg_pcrel_diff(s, (void *)arg) - 8;
811 if (diff >= 0) {
812 imm12 = encode_imm(diff);
813 if (imm12 >= 0) {
814 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, TCG_REG_PC, imm12);
815 return;
816 }
817 } else {
818 imm12 = encode_imm(-diff);
819 if (imm12 >= 0) {
820 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, TCG_REG_PC, imm12);
821 return;
822 }
823 }
825 /* Use movw + movt. */
826 if (use_armv7_instructions) {
827 /* movw */
828 tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
829 | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
830 if (arg & 0xffff0000) {
831 /* movt */
832 tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
833 | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
834 }
835 return;
836 }
838 /* Look for sequences of two insns. If we have lots of 1's, we can
839 shorten the sequence by beginning with mvn and then clearing
840 higher bits with eor. */
841 tt0 = arg;
842 opc = ARITH_MOV;
843 if (ctpop32(arg) > 16) {
844 tt0 = ~arg;
845 opc = ARITH_MVN;
846 }
847 sh1 = ctz32(tt0) & ~1;
848 tt1 = tt0 & ~(0xff << sh1);
849 sh2 = ctz32(tt1) & ~1;
850 tt2 = tt1 & ~(0xff << sh2);
851 if (tt2 == 0) {
852 int rot;
854 rot = ((32 - sh1) << 7) & 0xf00;
855 tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot);
856 rot = ((32 - sh2) << 7) & 0xf00;
857 tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd,
858 ((tt0 >> sh2) & 0xff) | rot);
859 return;
860 }
862 /* Otherwise, drop it into the constant pool. */
863 tcg_out_movi_pool(s, cond, rd, arg);
864 }
866 /*
867 * Emit either the reg,imm or reg,reg form of a data-processing insn.
868 * rhs must satisfy the "rI" constraint.
869 */
870 static void tcg_out_dat_rI(TCGContext *s, ARMCond cond, ARMInsn opc,
871 TCGReg dst, TCGReg lhs, TCGArg rhs, int rhs_is_const)
872 {
873 if (rhs_is_const) {
874 tcg_out_dat_imm(s, cond, opc, dst, lhs, encode_imm_nofail(rhs));
875 } else {
876 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
877 }
878 }
880 /*
881 * Emit either the reg,imm or reg,reg form of a data-processing insn.
882 * rhs must satisfy the "rIK" constraint.
883 */
884 static void tcg_out_dat_rIK(TCGContext *s, ARMCond cond, ARMInsn opc,
885 ARMInsn opinv, TCGReg dst, TCGReg lhs, TCGArg rhs,
886 bool rhs_is_const)
887 {
888 if (rhs_is_const) {
889 int imm12 = encode_imm(rhs);
890 if (imm12 < 0) {
891 imm12 = encode_imm_nofail(~rhs);
892 opc = opinv;
893 }
894 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12);
895 } else {
896 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
897 }
898 }
900 static void tcg_out_dat_rIN(TCGContext *s, ARMCond cond, ARMInsn opc,
901 ARMInsn opneg, TCGReg dst, TCGReg lhs, TCGArg rhs,
902 bool rhs_is_const)
903 {
904 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
905 * rhs must satisfy the "rIN" constraint.
906 */
907 if (rhs_is_const) {
908 int imm12 = encode_imm(rhs);
909 if (imm12 < 0) {
910 imm12 = encode_imm_nofail(-rhs);
911 opc = opneg;
912 }
913 tcg_out_dat_imm(s, cond, opc, dst, lhs, imm12);
914 } else {
915 tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0));
916 }
917 }
919 static void tcg_out_mul32(TCGContext *s, ARMCond cond, TCGReg rd,
920 TCGReg rn, TCGReg rm)
921 {
922 /* mul */
923 tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn);
924 }
926 static void tcg_out_umull32(TCGContext *s, ARMCond cond, TCGReg rd0,
927 TCGReg rd1, TCGReg rn, TCGReg rm)
928 {
929 /* umull */
930 tcg_out32(s, (cond << 28) | 0x00800090 |
931 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
932 }
934 static void tcg_out_smull32(TCGContext *s, ARMCond cond, TCGReg rd0,
935 TCGReg rd1, TCGReg rn, TCGReg rm)
936 {
937 /* smull */
938 tcg_out32(s, (cond << 28) | 0x00c00090 |
939 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
940 }
942 static void tcg_out_sdiv(TCGContext *s, ARMCond cond,
943 TCGReg rd, TCGReg rn, TCGReg rm)
944 {
945 tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
946 }
948 static void tcg_out_udiv(TCGContext *s, ARMCond cond,
949 TCGReg rd, TCGReg rn, TCGReg rm)
950 {
951 tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8));
952 }
954 static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn)
955 {
956 /* sxtb */
957 tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn);
958 }
960 static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn)
961 {
962 tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff);
963 }
965 static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn)
966 {
967 /* sxth */
968 tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn);
969 }
971 static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn)
972 {
973 /* uxth */
974 tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn);
975 }
977 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn)
978 {
979 g_assert_not_reached();
980 }
982 static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn)
983 {
984 g_assert_not_reached();
985 }
987 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn)
988 {
989 g_assert_not_reached();
990 }
992 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn)
993 {
994 g_assert_not_reached();
995 }
997 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
998 {
999 g_assert_not_reached();
1000 }
1002 static void tcg_out_bswap16(TCGContext *s, ARMCond cond,
1003 TCGReg rd, TCGReg rn, int flags)
1004 {
1005 if (flags & TCG_BSWAP_OS) {
1006 /* revsh */
1007 tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
1008 return;
1009 }
1011 /* rev16 */
1012 tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
1013 if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1014 /* uxth */
1015 tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd);
1016 }
1017 }
1019 static void tcg_out_bswap32(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn)
1020 {
1021 /* rev */
1022 tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
1023 }
1025 static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd,
1026 TCGArg a1, int ofs, int len, bool const_a1)
1027 {
1028 if (const_a1) {
1029 /* bfi becomes bfc with rn == 15. */
1030 a1 = 15;
1031 }
1032 /* bfi/bfc */
1033 tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1
1034 | (ofs << 7) | ((ofs + len - 1) << 16));
1035 }
1037 static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
1038 TCGReg rn, int ofs, int len)
1039 {
1040 /* ubfx */
1041 tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn
1042 | (ofs << 7) | ((len - 1) << 16));
1043 }
1045 static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd,
1046 TCGReg rn, int ofs, int len)
1047 {
1048 /* sbfx */
1049 tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn
1050 | (ofs << 7) | ((len - 1) << 16));
1051 }
1053 static void tcg_out_ld32u(TCGContext *s, ARMCond cond,
1054 TCGReg rd, TCGReg rn, int32_t offset)
1055 {
1056 if (offset > 0xfff || offset < -0xfff) {
1057 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1058 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_TMP);
1059 } else
1060 tcg_out_ld32_12(s, cond, rd, rn, offset);
1061 }
1063 static void tcg_out_st32(TCGContext *s, ARMCond cond,
1064 TCGReg rd, TCGReg rn, int32_t offset)
1065 {
1066 if (offset > 0xfff || offset < -0xfff) {
1067 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1068 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_TMP);
1069 } else
1070 tcg_out_st32_12(s, cond, rd, rn, offset);
1071 }
1073 static void tcg_out_ld16u(TCGContext *s, ARMCond cond,
1074 TCGReg rd, TCGReg rn, int32_t offset)
1075 {
1076 if (offset > 0xff || offset < -0xff) {
1077 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1078 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_TMP);
1079 } else
1080 tcg_out_ld16u_8(s, cond, rd, rn, offset);
1081 }
1083 static void tcg_out_ld16s(TCGContext *s, ARMCond cond,
1084 TCGReg rd, TCGReg rn, int32_t offset)
1085 {
1086 if (offset > 0xff || offset < -0xff) {
1087 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1088 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_TMP);
1089 } else
1090 tcg_out_ld16s_8(s, cond, rd, rn, offset);
1091 }
1093 static void tcg_out_st16(TCGContext *s, ARMCond cond,
1094 TCGReg rd, TCGReg rn, int32_t offset)
1095 {
1096 if (offset > 0xff || offset < -0xff) {
1097 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1098 tcg_out_st16_r(s, cond, rd, rn, TCG_REG_TMP);
1099 } else
1100 tcg_out_st16_8(s, cond, rd, rn, offset);
1101 }
1103 static void tcg_out_ld8u(TCGContext *s, ARMCond cond,
1104 TCGReg rd, TCGReg rn, int32_t offset)
1105 {
1106 if (offset > 0xfff || offset < -0xfff) {
1107 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1108 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_TMP);
1109 } else
1110 tcg_out_ld8_12(s, cond, rd, rn, offset);
1111 }
1113 static void tcg_out_ld8s(TCGContext *s, ARMCond cond,
1114 TCGReg rd, TCGReg rn, int32_t offset)
1115 {
1116 if (offset > 0xff || offset < -0xff) {
1117 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1118 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_TMP);
1119 } else
1120 tcg_out_ld8s_8(s, cond, rd, rn, offset);
1121 }
1123 static void tcg_out_st8(TCGContext *s, ARMCond cond,
1124 TCGReg rd, TCGReg rn, int32_t offset)
1125 {
1126 if (offset > 0xfff || offset < -0xfff) {
1127 tcg_out_movi32(s, cond, TCG_REG_TMP, offset);
1128 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_TMP);
1129 } else
1130 tcg_out_st8_12(s, cond, rd, rn, offset);
1131 }
1133 /*
1134 * The _goto case is normally between TBs within the same code buffer, and
1135 * with the code buffer limited to 16MB we wouldn't need the long case.
1136 * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
1137 */
1138 static void tcg_out_goto(TCGContext *s, ARMCond cond, const tcg_insn_unit *addr)
1139 {
1140 intptr_t addri = (intptr_t)addr;
1141 ptrdiff_t disp = tcg_pcrel_diff(s, addr);
1142 bool arm_mode = !(addri & 1);
1144 if (arm_mode && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) {
1145 tcg_out_b_imm(s, cond, disp);
1146 return;
1147 }
1149 /* LDR is interworking from v5t. */
1150 tcg_out_movi_pool(s, cond, TCG_REG_PC, addri);
1151 }
1153 /*
1154 * The call case is mostly used for helpers - so it's not unreasonable
1155 * for them to be beyond branch range.
1156 */
1157 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *addr)
1158 {
1159 intptr_t addri = (intptr_t)addr;
1160 ptrdiff_t disp = tcg_pcrel_diff(s, addr);
1161 bool arm_mode = !(addri & 1);
1163 if (disp - 8 < 0x02000000 && disp - 8 >= -0x02000000) {
1164 if (arm_mode) {
1165 tcg_out_bl_imm(s, COND_AL, disp);
1166 } else {
1167 tcg_out_blx_imm(s, disp);
1168 }
1169 return;
1170 }
1172 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
1173 tcg_out_blx_reg(s, COND_AL, TCG_REG_TMP);
1174 }
1176 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr,
1177 const TCGHelperInfo *info)
1178 {
1179 tcg_out_call_int(s, addr);
1180 }
1182 static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l)
1183 {
1184 if (l->has_value) {
1185 tcg_out_goto(s, cond, l->u.value_ptr);
1186 } else {
1187 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, l, 0);
1188 tcg_out_b_imm(s, cond, 0);
1189 }
1190 }
1192 static void tcg_out_mb(TCGContext *s, TCGArg a0)
1193 {
1194 if (use_armv7_instructions) {
1195 tcg_out32(s, INSN_DMB_ISH);
1196 } else {
1197 tcg_out32(s, INSN_DMB_MCR);
1198 }
1199 }
1201 static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1202 const int *const_args)
1203 {
1204 TCGReg al = args[0];
1205 TCGReg ah = args[1];
1206 TCGArg bl = args[2];
1207 TCGArg bh = args[3];
1208 TCGCond cond = args[4];
1209 int const_bl = const_args[2];
1210 int const_bh = const_args[3];
1212 switch (cond) {
1213 case TCG_COND_EQ:
1214 case TCG_COND_NE:
1215 case TCG_COND_LTU:
1216 case TCG_COND_LEU:
1217 case TCG_COND_GTU:
1218 case TCG_COND_GEU:
1219 /* We perform a conditional comparision. If the high half is
1220 equal, then overwrite the flags with the comparison of the
1221 low half. The resulting flags cover the whole. */
1222 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh);
1223 tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
1224 return cond;
1226 case TCG_COND_LT:
1227 case TCG_COND_GE:
1228 /* We perform a double-word subtraction and examine the result.
1229 We do not actually need the result of the subtract, so the
1230 low part "subtract" is a compare. For the high half we have
1231 no choice but to compute into a temporary. */
1232 tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl);
1233 tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR,
1234 TCG_REG_TMP, ah, bh, const_bh);
1235 return cond;
1237 case TCG_COND_LE:
1238 case TCG_COND_GT:
1239 /* Similar, but with swapped arguments, via reversed subtract. */
1240 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR,
1241 TCG_REG_TMP, al, bl, const_bl);
1242 tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR,
1243 TCG_REG_TMP, ah, bh, const_bh);
1244 return tcg_swap_cond(cond);
1246 default:
1247 g_assert_not_reached();
1248 }
1249 }
1251 /*
1252 * Note that TCGReg references Q-registers.
1253 * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
1254 */
1255 static uint32_t encode_vd(TCGReg rd)
1256 {
1257 tcg_debug_assert(rd >= TCG_REG_Q0);
1258 return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
1259 }
1261 static uint32_t encode_vn(TCGReg rn)
1262 {
1263 tcg_debug_assert(rn >= TCG_REG_Q0);
1264 return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
1265 }
1267 static uint32_t encode_vm(TCGReg rm)
1268 {
1269 tcg_debug_assert(rm >= TCG_REG_Q0);
1270 return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
1271 }
1273 static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
1274 TCGReg d, TCGReg m)
1275 {
1276 tcg_out32(s, insn | (vece << 18) | (q << 6) |
1277 encode_vd(d) | encode_vm(m));
1278 }
1280 static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
1281 TCGReg d, TCGReg n, TCGReg m)
1282 {
1283 tcg_out32(s, insn | (vece << 20) | (q << 6) |
1284 encode_vd(d) | encode_vn(n) | encode_vm(m));
1285 }
1287 static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
1288 int q, int op, int cmode, uint8_t imm8)
1289 {
1290 tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
1291 | (cmode << 8) | extract32(imm8, 0, 4)
1292 | (extract32(imm8, 4, 3) << 16)
1293 | (extract32(imm8, 7, 1) << 24));
1294 }
1296 static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
1297 TCGReg rd, TCGReg rm, int l_imm6)
1298 {
1299 tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
1300 (extract32(l_imm6, 6, 1) << 7) |
1301 (extract32(l_imm6, 0, 6) << 16));
1302 }
1304 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
1305 TCGReg rd, TCGReg rn, int offset)
1306 {
1307 if (offset != 0) {
1308 if (check_fit_imm(offset) || check_fit_imm(-offset)) {
1309 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
1310 TCG_REG_TMP, rn, offset, true);
1311 } else {
1312 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
1313 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1314 TCG_REG_TMP, TCG_REG_TMP, rn, 0);
1315 }
1316 rn = TCG_REG_TMP;
1317 }
1318 tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
1319 }
1321 typedef struct {
1322 ARMCond cond;
1323 TCGReg base;
1324 int index;
1325 bool index_scratch;
1326 TCGAtomAlign aa;
1327 } HostAddress;
1329 bool tcg_target_has_memory_bswap(MemOp memop)
1330 {
1331 return false;
1332 }
1334 static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg)
1335 {
1336 /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */
1337 return TCG_REG_R14;
1338 }
1340 static const TCGLdstHelperParam ldst_helper_param = {
1341 .ra_gen = ldst_ra_gen,
1342 .ntmp = 1,
1343 .tmp = { TCG_REG_TMP },
1344 };
1346 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1347 {
1348 MemOp opc = get_memop(lb->oi);
1350 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1351 return false;
1352 }
1354 tcg_out_ld_helper_args(s, lb, &ldst_helper_param);
1355 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]);
1356 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param);
1358 tcg_out_goto(s, COND_AL, lb->raddr);
1359 return true;
1360 }
1362 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1363 {
1364 MemOp opc = get_memop(lb->oi);
1366 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1367 return false;
1368 }
1370 tcg_out_st_helper_args(s, lb, &ldst_helper_param);
1372 /* Tail-call to the helper, which will return to the fast path. */
1373 tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]);
1374 return true;
1375 }
1377 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1378 TCGReg addrlo, TCGReg addrhi,
1379 MemOpIdx oi, bool is_ld)
1380 {
1381 TCGLabelQemuLdst *ldst = NULL;
1382 MemOp opc = get_memop(oi);
1383 unsigned a_mask;
1385 #ifdef CONFIG_SOFTMMU
1386 *h = (HostAddress){
1387 .cond = COND_AL,
1388 .base = addrlo,
1389 .index = TCG_REG_R1,
1390 .index_scratch = true,
1391 };
1392 #else
1393 *h = (HostAddress){
1394 .cond = COND_AL,
1395 .base = addrlo,
1396 .index = guest_base ? TCG_REG_GUEST_BASE : -1,
1397 .index_scratch = false,
1398 };
1399 #endif
1401 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
1402 a_mask = (1 << h->aa.align) - 1;
1404 #ifdef CONFIG_SOFTMMU
1405 int mem_index = get_mmuidx(oi);
1406 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1407 : offsetof(CPUTLBEntry, addr_write);
1408 int fast_off = TLB_MASK_TABLE_OFS(mem_index);
1409 unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
1410 TCGReg t_addr;
1412 ldst = new_ldst_label(s);
1413 ldst->is_ld = is_ld;
1414 ldst->oi = oi;
1415 ldst->addrlo_reg = addrlo;
1416 ldst->addrhi_reg = addrhi;
1418 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */
1419 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
1420 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256);
1421 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
1422 QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
1423 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
1425 /* Extract the tlb index from the address into R0. */
1426 tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
1427 SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
1429 /*
1430 * Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
1431 * Load the tlb comparator into R2/R3 and the fast path addend into R1.
1432 */
1433 if (cmp_off == 0) {
1434 if (s->addr_type == TCG_TYPE_I32) {
1435 tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
1436 } else {
1437 tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
1438 }
1439 } else {
1440 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1441 TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
1442 if (s->addr_type == TCG_TYPE_I32) {
1443 tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
1444 } else {
1445 tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
1446 }
1447 }
1449 /* Load the tlb addend. */
1450 tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
1451 offsetof(CPUTLBEntry, addend));
1453 /*
1454 * Check alignment, check comparators.
1455 * Do this in 2-4 insns. Use MOVW for v7, if possible,
1456 * to reduce the number of sequential conditional instructions.
1457 * Almost all guests have at least 4k pages, which means that we need
1458 * to clear at least 9 bits even for an 8-byte memory, which means it
1459 * isn't worth checking for an immediate operand for BIC.
1460 *
1461 * For unaligned accesses, test the page of the last unit of alignment.
1462 * This leaves the least significant alignment bits unchanged, and of
1463 * course must be zero.
1464 */
1465 t_addr = addrlo;
1466 if (a_mask < s_mask) {
1467 t_addr = TCG_REG_R0;
1468 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
1469 addrlo, s_mask - a_mask);
1470 }
1471 if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
1472 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mask));
1473 tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
1474 t_addr, TCG_REG_TMP, 0);
1475 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
1476 } else {
1477 if (a_mask) {
1478 tcg_debug_assert(a_mask <= 0xff);
1479 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
1480 }
1481 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
1482 SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1483 tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
1484 0, TCG_REG_R2, TCG_REG_TMP,
1485 SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1486 }
1488 if (s->addr_type != TCG_TYPE_I32) {
1489 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
1490 }
1491 #else
1492 if (a_mask) {
1493 ldst = new_ldst_label(s);
1494 ldst->is_ld = is_ld;
1495 ldst->oi = oi;
1496 ldst->addrlo_reg = addrlo;
1497 ldst->addrhi_reg = addrhi;
1499 /* We are expecting alignment to max out at 7 */
1500 tcg_debug_assert(a_mask <= 0xff);
1501 /* tst addr, #mask */
1502 tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
1503 }
1504 #endif
1506 return ldst;
1507 }
1509 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
1510 TCGReg datahi, HostAddress h)
1511 {
1512 TCGReg base;
1514 /* Byte swapping is left to middle-end expansion. */
1515 tcg_debug_assert((opc & MO_BSWAP) == 0);
1517 switch (opc & MO_SSIZE) {
1518 case MO_UB:
1519 if (h.index < 0) {
1520 tcg_out_ld8_12(s, h.cond, datalo, h.base, 0);
1521 } else {
1522 tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index);
1523 }
1524 break;
1525 case MO_SB:
1526 if (h.index < 0) {
1527 tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0);
1528 } else {
1529 tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index);
1530 }
1531 break;
1532 case MO_UW:
1533 if (h.index < 0) {
1534 tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0);
1535 } else {
1536 tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index);
1537 }
1538 break;
1539 case MO_SW:
1540 if (h.index < 0) {
1541 tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0);
1542 } else {
1543 tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index);
1544 }
1545 break;
1546 case MO_UL:
1547 if (h.index < 0) {
1548 tcg_out_ld32_12(s, h.cond, datalo, h.base, 0);
1549 } else {
1550 tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index);
1551 }
1552 break;
1553 case MO_UQ:
1554 /* We used pair allocation for datalo, so already should be aligned. */
1555 tcg_debug_assert((datalo & 1) == 0);
1556 tcg_debug_assert(datahi == datalo + 1);
1557 /* LDRD requires alignment; double-check that. */
1558 if (get_alignment_bits(opc) >= MO_64) {
1559 if (h.index < 0) {
1560 tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0);
1561 break;
1562 }
1563 /*
1564 * Rm (the second address op) must not overlap Rt or Rt + 1.
1565 * Since datalo is aligned, we can simplify the test via alignment.
1566 * Flip the two address arguments if that works.
1567 */
1568 if ((h.index & ~1) != datalo) {
1569 tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index);
1570 break;
1571 }
1572 if ((h.base & ~1) != datalo) {
1573 tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base);
1574 break;
1575 }
1576 }
1577 if (h.index < 0) {
1578 base = h.base;
1579 if (datalo == h.base) {
1580 tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base);
1581 base = TCG_REG_TMP;
1582 }
1583 } else if (h.index_scratch) {
1584 tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base);
1585 tcg_out_ld32_12(s, h.cond, datahi, h.index, 4);
1586 break;
1587 } else {
1588 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
1589 h.base, h.index, SHIFT_IMM_LSL(0));
1590 base = TCG_REG_TMP;
1591 }
1592 tcg_out_ld32_12(s, h.cond, datalo, base, 0);
1593 tcg_out_ld32_12(s, h.cond, datahi, base, 4);
1594 break;
1595 default:
1596 g_assert_not_reached();
1597 }
1598 }
1600 static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
1601 TCGReg addrlo, TCGReg addrhi,
1602 MemOpIdx oi, TCGType data_type)
1603 {
1604 MemOp opc = get_memop(oi);
1605 TCGLabelQemuLdst *ldst;
1606 HostAddress h;
1608 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
1609 if (ldst) {
1610 ldst->type = data_type;
1611 ldst->datalo_reg = datalo;
1612 ldst->datahi_reg = datahi;
1614 /*
1615 * This a conditional BL only to load a pointer within this
1616 * opcode into LR for the slow path. We will not be using
1617 * the value for a tail call.
1618 */
1619 ldst->label_ptr[0] = s->code_ptr;
1620 tcg_out_bl_imm(s, COND_NE, 0);
1622 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
1623 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1624 } else {
1625 tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h);
1626 }
1627 }
1629 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
1630 TCGReg datahi, HostAddress h)
1631 {
1632 /* Byte swapping is left to middle-end expansion. */
1633 tcg_debug_assert((opc & MO_BSWAP) == 0);
1635 switch (opc & MO_SIZE) {
1636 case MO_8:
1637 if (h.index < 0) {
1638 tcg_out_st8_12(s, h.cond, datalo, h.base, 0);
1639 } else {
1640 tcg_out_st8_r(s, h.cond, datalo, h.base, h.index);
1641 }
1642 break;
1643 case MO_16:
1644 if (h.index < 0) {
1645 tcg_out_st16_8(s, h.cond, datalo, h.base, 0);
1646 } else {
1647 tcg_out_st16_r(s, h.cond, datalo, h.base, h.index);
1648 }
1649 break;
1650 case MO_32:
1651 if (h.index < 0) {
1652 tcg_out_st32_12(s, h.cond, datalo, h.base, 0);
1653 } else {
1654 tcg_out_st32_r(s, h.cond, datalo, h.base, h.index);
1655 }
1656 break;
1657 case MO_64:
1658 /* We used pair allocation for datalo, so already should be aligned. */
1659 tcg_debug_assert((datalo & 1) == 0);
1660 tcg_debug_assert(datahi == datalo + 1);
1661 /* STRD requires alignment; double-check that. */
1662 if (get_alignment_bits(opc) >= MO_64) {
1663 if (h.index < 0) {
1664 tcg_out_strd_8(s, h.cond, datalo, h.base, 0);
1665 } else {
1666 tcg_out_strd_r(s, h.cond, datalo, h.base, h.index);
1667 }
1668 } else if (h.index_scratch) {
1669 tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base);
1670 tcg_out_st32_12(s, h.cond, datahi, h.index, 4);
1671 } else {
1672 tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP,
1673 h.base, h.index, SHIFT_IMM_LSL(0));
1674 tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0);
1675 tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4);
1676 }
1677 break;
1678 default:
1679 g_assert_not_reached();
1680 }
1681 }
1683 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
1684 TCGReg addrlo, TCGReg addrhi,
1685 MemOpIdx oi, TCGType data_type)
1686 {
1687 MemOp opc = get_memop(oi);
1688 TCGLabelQemuLdst *ldst;
1689 HostAddress h;
1691 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
1692 if (ldst) {
1693 ldst->type = data_type;
1694 ldst->datalo_reg = datalo;
1695 ldst->datahi_reg = datahi;
1697 h.cond = COND_EQ;
1698 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
1700 /* The conditional call is last, as we're going to return here. */
1701 ldst->label_ptr[0] = s->code_ptr;
1702 tcg_out_bl_imm(s, COND_NE, 0);
1703 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1704 } else {
1705 tcg_out_qemu_st_direct(s, opc, datalo, datahi, h);
1706 }
1707 }
1709 static void tcg_out_epilogue(TCGContext *s);
1711 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg)
1712 {
1713 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, arg);
1714 tcg_out_epilogue(s);
1715 }
1717 static void tcg_out_goto_tb(TCGContext *s, int which)
1718 {
1719 uintptr_t i_addr;
1720 intptr_t i_disp;
1722 /* Direct branch will be patched by tb_target_set_jmp_target. */
1723 set_jmp_insn_offset(s, which);
1724 tcg_out32(s, INSN_NOP);
1726 /* When branch is out of range, fall through to indirect. */
1727 i_addr = get_jmp_target_addr(s, which);
1728 i_disp = tcg_pcrel_diff(s, (void *)i_addr) - 8;
1729 tcg_debug_assert(i_disp < 0);
1730 if (i_disp >= -0xfff) {
1731 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, i_disp);
1732 } else {
1733 /*
1734 * The TB is close, but outside the 12 bits addressable by
1735 * the load. We can extend this to 20 bits with a sub of a
1736 * shifted immediate from pc.
1737 */
1738 int h = -i_disp;
1739 int l = h & 0xfff;
1741 h = encode_imm_nofail(h - l);
1742 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, TCG_REG_R0, TCG_REG_PC, h);
1743 tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, l);
1744 }
1745 set_jmp_reset_offset(s, which);
1746 }
1748 void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1749 uintptr_t jmp_rx, uintptr_t jmp_rw)
1750 {
1751 uintptr_t addr = tb->jmp_target_addr[n];
1752 ptrdiff_t offset = addr - (jmp_rx + 8);
1753 tcg_insn_unit insn;
1755 /* Either directly branch, or fall through to indirect branch. */
1756 if (offset == sextract64(offset, 0, 26)) {
1757 /* B <addr> */
1758 insn = deposit32((COND_AL << 28) | INSN_B, 0, 24, offset >> 2);
1759 } else {
1760 insn = INSN_NOP;
1761 }
1763 qatomic_set((uint32_t *)jmp_rw, insn);
1764 flush_idcache_range(jmp_rx, jmp_rw, 4);
1765 }
1767 static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1768 const TCGArg args[TCG_MAX_OP_ARGS],
1769 const int const_args[TCG_MAX_OP_ARGS])
1770 {
1771 TCGArg a0, a1, a2, a3, a4, a5;
1772 int c;
1774 switch (opc) {
1775 case INDEX_op_goto_ptr:
1776 tcg_out_b_reg(s, COND_AL, args[0]);
1777 break;
1778 case INDEX_op_br:
1779 tcg_out_goto_label(s, COND_AL, arg_label(args[0]));
1780 break;
1782 case INDEX_op_ld8u_i32:
1783 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1784 break;
1785 case INDEX_op_ld8s_i32:
1786 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1787 break;
1788 case INDEX_op_ld16u_i32:
1789 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1790 break;
1791 case INDEX_op_ld16s_i32:
1792 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1793 break;
1794 case INDEX_op_ld_i32:
1795 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1796 break;
1797 case INDEX_op_st8_i32:
1798 tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
1799 break;
1800 case INDEX_op_st16_i32:
1801 tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
1802 break;
1803 case INDEX_op_st_i32:
1804 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1805 break;
1807 case INDEX_op_movcond_i32:
1808 /* Constraints mean that v2 is always in the same register as dest,
1809 * so we only need to do "if condition passed, move v1 to dest".
1810 */
1811 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
1812 args[1], args[2], const_args[2]);
1813 tcg_out_dat_rIK(s, tcg_cond_to_arm_cond[args[5]], ARITH_MOV,
1814 ARITH_MVN, args[0], 0, args[3], const_args[3]);
1815 break;
1816 case INDEX_op_add_i32:
1817 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
1818 args[0], args[1], args[2], const_args[2]);
1819 break;
1820 case INDEX_op_sub_i32:
1821 if (const_args[1]) {
1822 if (const_args[2]) {
1823 tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]);
1824 } else {
1825 tcg_out_dat_rI(s, COND_AL, ARITH_RSB,
1826 args[0], args[2], args[1], 1);
1827 }
1828 } else {
1829 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD,
1830 args[0], args[1], args[2], const_args[2]);
1831 }
1832 break;
1833 case INDEX_op_and_i32:
1834 tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC,
1835 args[0], args[1], args[2], const_args[2]);
1836 break;
1837 case INDEX_op_andc_i32:
1838 tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
1839 args[0], args[1], args[2], const_args[2]);
1840 break;
1841 case INDEX_op_or_i32:
1842 c = ARITH_ORR;
1843 goto gen_arith;
1844 case INDEX_op_xor_i32:
1845 c = ARITH_EOR;
1846 /* Fall through. */
1847 gen_arith:
1848 tcg_out_dat_rI(s, COND_AL, c, args[0], args[1], args[2], const_args[2]);
1849 break;
1850 case INDEX_op_add2_i32:
1851 a0 = args[0], a1 = args[1], a2 = args[2];
1852 a3 = args[3], a4 = args[4], a5 = args[5];
1853 if (a0 == a3 || (a0 == a5 && !const_args[5])) {
1854 a0 = TCG_REG_TMP;
1855 }
1856 tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
1857 a0, a2, a4, const_args[4]);
1858 tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC,
1859 a1, a3, a5, const_args[5]);
1860 tcg_out_mov_reg(s, COND_AL, args[0], a0);
1861 break;
1862 case INDEX_op_sub2_i32:
1863 a0 = args[0], a1 = args[1], a2 = args[2];
1864 a3 = args[3], a4 = args[4], a5 = args[5];
1865 if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) {
1866 a0 = TCG_REG_TMP;
1867 }
1868 if (const_args[2]) {
1869 if (const_args[4]) {
1870 tcg_out_movi32(s, COND_AL, a0, a4);
1871 a4 = a0;
1872 }
1873 tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1);
1874 } else {
1875 tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR,
1876 ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]);
1877 }
1878 if (const_args[3]) {
1879 if (const_args[5]) {
1880 tcg_out_movi32(s, COND_AL, a1, a5);
1881 a5 = a1;
1882 }
1883 tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1);
1884 } else {
1885 tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC,
1886 a1, a3, a5, const_args[5]);
1887 }
1888 tcg_out_mov_reg(s, COND_AL, args[0], a0);
1889 break;
1890 case INDEX_op_neg_i32:
1891 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1892 break;
1893 case INDEX_op_not_i32:
1894 tcg_out_dat_reg(s, COND_AL,
1895 ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1896 break;
1897 case INDEX_op_mul_i32:
1898 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1899 break;
1900 case INDEX_op_mulu2_i32:
1901 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1902 break;
1903 case INDEX_op_muls2_i32:
1904 tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1905 break;
1906 /* XXX: Perhaps args[2] & 0x1f is wrong */
1907 case INDEX_op_shl_i32:
1908 c = const_args[2] ?
1909 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1910 goto gen_shift32;
1911 case INDEX_op_shr_i32:
1912 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1913 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1914 goto gen_shift32;
1915 case INDEX_op_sar_i32:
1916 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1917 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1918 goto gen_shift32;
1919 case INDEX_op_rotr_i32:
1920 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1921 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
1922 /* Fall through. */
1923 gen_shift32:
1924 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1925 break;
1927 case INDEX_op_rotl_i32:
1928 if (const_args[2]) {
1929 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1930 ((0x20 - args[2]) & 0x1f) ?
1931 SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1932 SHIFT_IMM_LSL(0));
1933 } else {
1934 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_TMP, args[2], 0x20);
1935 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1936 SHIFT_REG_ROR(TCG_REG_TMP));
1937 }
1938 break;
1940 case INDEX_op_ctz_i32:
1941 tcg_out_dat_reg(s, COND_AL, INSN_RBIT, TCG_REG_TMP, 0, args[1], 0);
1942 a1 = TCG_REG_TMP;
1943 goto do_clz;
1945 case INDEX_op_clz_i32:
1946 a1 = args[1];
1947 do_clz:
1948 a0 = args[0];
1949 a2 = args[2];
1950 c = const_args[2];
1951 if (c && a2 == 32) {
1952 tcg_out_dat_reg(s, COND_AL, INSN_CLZ, a0, 0, a1, 0);
1953 break;
1954 }
1955 tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0, a1, 0);
1956 tcg_out_dat_reg(s, COND_NE, INSN_CLZ, a0, 0, a1, 0);
1957 if (c || a0 != a2) {
1958 tcg_out_dat_rIK(s, COND_EQ, ARITH_MOV, ARITH_MVN, a0, 0, a2, c);
1959 }
1960 break;
1962 case INDEX_op_brcond_i32:
1963 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
1964 args[0], args[1], const_args[1]);
1965 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]],
1966 arg_label(args[3]));
1967 break;
1968 case INDEX_op_setcond_i32:
1969 tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
1970 args[1], args[2], const_args[2]);
1971 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1972 ARITH_MOV, args[0], 0, 1);
1973 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1974 ARITH_MOV, args[0], 0, 0);
1975 break;
1977 case INDEX_op_brcond2_i32:
1978 c = tcg_out_cmp2(s, args, const_args);
1979 tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5]));
1980 break;
1981 case INDEX_op_setcond2_i32:
1982 c = tcg_out_cmp2(s, args + 1, const_args + 1);
1983 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1);
1984 tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)],
1985 ARITH_MOV, args[0], 0, 0);
1986 break;
1988 case INDEX_op_qemu_ld_a32_i32:
1989 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
1990 break;
1991 case INDEX_op_qemu_ld_a64_i32:
1992 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
1993 args[3], TCG_TYPE_I32);
1994 break;
1995 case INDEX_op_qemu_ld_a32_i64:
1996 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
1997 args[3], TCG_TYPE_I64);
1998 break;
1999 case INDEX_op_qemu_ld_a64_i64:
2000 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
2001 args[4], TCG_TYPE_I64);
2002 break;
2004 case INDEX_op_qemu_st_a32_i32:
2005 tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32);
2006 break;
2007 case INDEX_op_qemu_st_a64_i32:
2008 tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
2009 args[3], TCG_TYPE_I32);
2010 break;
2011 case INDEX_op_qemu_st_a32_i64:
2012 tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
2013 args[3], TCG_TYPE_I64);
2014 break;
2015 case INDEX_op_qemu_st_a64_i64:
2016 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
2017 args[4], TCG_TYPE_I64);
2018 break;
2020 case INDEX_op_bswap16_i32:
2021 tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]);
2022 break;
2023 case INDEX_op_bswap32_i32:
2024 tcg_out_bswap32(s, COND_AL, args[0], args[1]);
2025 break;
2027 case INDEX_op_deposit_i32:
2028 tcg_out_deposit(s, COND_AL, args[0], args[2],
2029 args[3], args[4], const_args[2]);
2030 break;
2031 case INDEX_op_extract_i32:
2032 tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
2033 break;
2034 case INDEX_op_sextract_i32:
2035 tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
2036 break;
2037 case INDEX_op_extract2_i32:
2038 /* ??? These optimization vs zero should be generic. */
2039 /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
2040 if (const_args[1]) {
2041 if (const_args[2]) {
2042 tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
2043 } else {
2044 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
2045 args[2], SHIFT_IMM_LSL(32 - args[3]));
2046 }
2047 } else if (const_args[2]) {
2048 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
2049 args[1], SHIFT_IMM_LSR(args[3]));
2050 } else {
2051 /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
2052 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
2053 args[2], SHIFT_IMM_LSL(32 - args[3]));
2054 tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
2055 args[1], SHIFT_IMM_LSR(args[3]));
2056 }
2057 break;
2059 case INDEX_op_div_i32:
2060 tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
2061 break;
2062 case INDEX_op_divu_i32:
2063 tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
2064 break;
2066 case INDEX_op_mb:
2067 tcg_out_mb(s, args[0]);
2068 break;
2070 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2071 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2072 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2073 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2074 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2075 case INDEX_op_ext8u_i32:
2076 case INDEX_op_ext16s_i32:
2077 case INDEX_op_ext16u_i32:
2078 default:
2079 g_assert_not_reached();
2080 }
2081 }
2083 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2084 {
2085 switch (op) {
2086 case INDEX_op_goto_ptr:
2087 return C_O0_I1(r);
2089 case INDEX_op_ld8u_i32:
2090 case INDEX_op_ld8s_i32:
2091 case INDEX_op_ld16u_i32:
2092 case INDEX_op_ld16s_i32:
2093 case INDEX_op_ld_i32:
2094 case INDEX_op_neg_i32:
2095 case INDEX_op_not_i32:
2096 case INDEX_op_bswap16_i32:
2097 case INDEX_op_bswap32_i32:
2098 case INDEX_op_ext8s_i32:
2099 case INDEX_op_ext16s_i32:
2100 case INDEX_op_ext16u_i32:
2101 case INDEX_op_extract_i32:
2102 case INDEX_op_sextract_i32:
2103 return C_O1_I1(r, r);
2105 case INDEX_op_st8_i32:
2106 case INDEX_op_st16_i32:
2107 case INDEX_op_st_i32:
2108 return C_O0_I2(r, r);
2110 case INDEX_op_add_i32:
2111 case INDEX_op_sub_i32:
2112 case INDEX_op_setcond_i32:
2113 return C_O1_I2(r, r, rIN);
2115 case INDEX_op_and_i32:
2116 case INDEX_op_andc_i32:
2117 case INDEX_op_clz_i32:
2118 case INDEX_op_ctz_i32:
2119 return C_O1_I2(r, r, rIK);
2121 case INDEX_op_mul_i32:
2122 case INDEX_op_div_i32:
2123 case INDEX_op_divu_i32:
2124 return C_O1_I2(r, r, r);
2126 case INDEX_op_mulu2_i32:
2127 case INDEX_op_muls2_i32:
2128 return C_O2_I2(r, r, r, r);
2130 case INDEX_op_or_i32:
2131 case INDEX_op_xor_i32:
2132 return C_O1_I2(r, r, rI);
2134 case INDEX_op_shl_i32:
2135 case INDEX_op_shr_i32:
2136 case INDEX_op_sar_i32:
2137 case INDEX_op_rotl_i32:
2138 case INDEX_op_rotr_i32:
2139 return C_O1_I2(r, r, ri);
2141 case INDEX_op_brcond_i32:
2142 return C_O0_I2(r, rIN);
2143 case INDEX_op_deposit_i32:
2144 return C_O1_I2(r, 0, rZ);
2145 case INDEX_op_extract2_i32:
2146 return C_O1_I2(r, rZ, rZ);
2147 case INDEX_op_movcond_i32:
2148 return C_O1_I4(r, r, rIN, rIK, 0);
2149 case INDEX_op_add2_i32:
2150 return C_O2_I4(r, r, r, r, rIN, rIK);
2151 case INDEX_op_sub2_i32:
2152 return C_O2_I4(r, r, rI, rI, rIN, rIK);
2153 case INDEX_op_brcond2_i32:
2154 return C_O0_I4(r, r, rI, rI);
2155 case INDEX_op_setcond2_i32:
2156 return C_O1_I4(r, r, r, rI, rI);
2158 case INDEX_op_qemu_ld_a32_i32:
2159 return C_O1_I1(r, q);
2160 case INDEX_op_qemu_ld_a64_i32:
2161 return C_O1_I2(r, q, q);
2162 case INDEX_op_qemu_ld_a32_i64:
2163 return C_O2_I1(e, p, q);
2164 case INDEX_op_qemu_ld_a64_i64:
2165 return C_O2_I2(e, p, q, q);
2166 case INDEX_op_qemu_st_a32_i32:
2167 return C_O0_I2(q, q);
2168 case INDEX_op_qemu_st_a64_i32:
2169 return C_O0_I3(q, q, q);
2170 case INDEX_op_qemu_st_a32_i64:
2171 return C_O0_I3(Q, p, q);
2172 case INDEX_op_qemu_st_a64_i64:
2173 return C_O0_I4(Q, p, q, q);
2175 case INDEX_op_st_vec:
2176 return C_O0_I2(w, r);
2177 case INDEX_op_ld_vec:
2178 case INDEX_op_dupm_vec:
2179 return C_O1_I1(w, r);
2180 case INDEX_op_dup_vec:
2181 return C_O1_I1(w, wr);
2182 case INDEX_op_abs_vec:
2183 case INDEX_op_neg_vec:
2184 case INDEX_op_not_vec:
2185 case INDEX_op_shli_vec:
2186 case INDEX_op_shri_vec:
2187 case INDEX_op_sari_vec:
2188 return C_O1_I1(w, w);
2189 case INDEX_op_dup2_vec:
2190 case INDEX_op_add_vec:
2191 case INDEX_op_mul_vec:
2192 case INDEX_op_smax_vec:
2193 case INDEX_op_smin_vec:
2194 case INDEX_op_ssadd_vec:
2195 case INDEX_op_sssub_vec:
2196 case INDEX_op_sub_vec:
2197 case INDEX_op_umax_vec:
2198 case INDEX_op_umin_vec:
2199 case INDEX_op_usadd_vec:
2200 case INDEX_op_ussub_vec:
2201 case INDEX_op_xor_vec:
2202 case INDEX_op_arm_sshl_vec:
2203 case INDEX_op_arm_ushl_vec:
2204 return C_O1_I2(w, w, w);
2205 case INDEX_op_arm_sli_vec:
2206 return C_O1_I2(w, 0, w);
2207 case INDEX_op_or_vec:
2208 case INDEX_op_andc_vec:
2209 return C_O1_I2(w, w, wO);
2210 case INDEX_op_and_vec:
2211 case INDEX_op_orc_vec:
2212 return C_O1_I2(w, w, wV);
2213 case INDEX_op_cmp_vec:
2214 return C_O1_I2(w, w, wZ);
2215 case INDEX_op_bitsel_vec:
2216 return C_O1_I3(w, w, w, w);
2217 default:
2218 g_assert_not_reached();
2219 }
2220 }
2222 static void tcg_target_init(TCGContext *s)
2223 {
2224 /*
2225 * Only probe for the platform and capabilities if we haven't already
2226 * determined maximum values at compile time.
2227 */
2228 #if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
2229 {
2230 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2231 #ifndef use_idiv_instructions
2232 use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
2233 #endif
2234 #ifndef use_neon_instructions
2235 use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
2236 #endif
2237 }
2238 #endif
2240 if (__ARM_ARCH < 7) {
2241 const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
2242 if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
2243 arm_arch = pl[1] - '0';
2244 }
2246 if (arm_arch < 6) {
2247 error_report("TCG: ARMv%d is unsupported; exiting", arm_arch);
2248 exit(EXIT_FAILURE);
2249 }
2250 }
2252 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2254 tcg_target_call_clobber_regs = 0;
2255 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2256 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2257 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2258 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2259 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
2260 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2262 if (use_neon_instructions) {
2263 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2264 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2266 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
2267 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
2268 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
2269 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
2270 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
2271 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
2272 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
2273 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
2274 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
2275 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
2276 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
2277 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
2278 }
2280 s->reserved_regs = 0;
2281 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2282 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
2283 tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
2284 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
2285 }
2287 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
2288 TCGReg arg1, intptr_t arg2)
2289 {
2290 switch (type) {
2291 case TCG_TYPE_I32:
2292 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
2293 return;
2294 case TCG_TYPE_V64:
2295 /* regs 1; size 8; align 8 */
2296 tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
2297 return;
2298 case TCG_TYPE_V128:
2299 /*
2300 * We have only 8-byte alignment for the stack per the ABI.
2301 * Rather than dynamically re-align the stack, it's easier
2302 * to simply not request alignment beyond that. So:
2303 * regs 2; size 8; align 8
2304 */
2305 tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2);
2306 return;
2307 default:
2308 g_assert_not_reached();
2309 }
2310 }
2312 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
2313 TCGReg arg1, intptr_t arg2)
2314 {
2315 switch (type) {
2316 case TCG_TYPE_I32:
2317 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
2318 return;
2319 case TCG_TYPE_V64:
2320 /* regs 1; size 8; align 8 */
2321 tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
2322 return;
2323 case TCG_TYPE_V128:
2324 /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */
2325 tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2);
2326 return;
2327 default:
2328 g_assert_not_reached();
2329 }
2330 }
2332 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
2333 TCGReg base, intptr_t ofs)
2334 {
2335 return false;
2336 }
2338 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
2339 {
2340 if (ret == arg) {
2341 return true;
2342 }
2343 switch (type) {
2344 case TCG_TYPE_I32:
2345 if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
2346 tcg_out_mov_reg(s, COND_AL, ret, arg);
2347 return true;
2348 }
2349 return false;
2351 case TCG_TYPE_V64:
2352 case TCG_TYPE_V128:
2353 /* "VMOV D,N" is an alias for "VORR D,N,N". */
2354 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
2355 return true;
2357 default:
2358 g_assert_not_reached();
2359 }
2360 }
2362 static void tcg_out_movi(TCGContext *s, TCGType type,
2363 TCGReg ret, tcg_target_long arg)
2364 {
2365 tcg_debug_assert(type == TCG_TYPE_I32);
2366 tcg_debug_assert(ret < TCG_REG_Q0);
2367 tcg_out_movi32(s, COND_AL, ret, arg);
2368 }
2370 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
2371 {
2372 return false;
2373 }
2375 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
2376 tcg_target_long imm)
2377 {
2378 int enc, opc = ARITH_ADD;
2380 /* All of the easiest immediates to encode are positive. */
2381 if (imm < 0) {
2382 imm = -imm;
2383 opc = ARITH_SUB;
2384 }
2385 enc = encode_imm(imm);
2386 if (enc >= 0) {
2387 tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc);
2388 } else {
2389 tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm);
2390 tcg_out_dat_reg(s, COND_AL, opc, rd, rs,
2391 TCG_REG_TMP, SHIFT_IMM_LSL(0));
2392 }
2393 }
2395 /* Type is always V128, with I64 elements. */
2396 static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
2397 {
2398 /* Move high element into place first. */
2399 /* VMOV Dd+1, Ds */
2400 tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
2401 /* Move low element into place; tcg_out_mov will check for nop. */
2402 tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
2403 }
2405 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
2406 TCGReg rd, TCGReg rs)
2407 {
2408 int q = type - TCG_TYPE_V64;
2410 if (vece == MO_64) {
2411 if (type == TCG_TYPE_V128) {
2412 tcg_out_dup2_vec(s, rd, rs, rs);
2413 } else {
2414 tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
2415 }
2416 } else if (rs < TCG_REG_Q0) {
2417 int b = (vece == MO_8);
2418 int e = (vece == MO_16);
2419 tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
2420 encode_vn(rd) | (rs << 12));
2421 } else {
2422 int imm4 = 1 << vece;
2423 tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
2424 encode_vd(rd) | encode_vm(rs));
2425 }
2426 return true;
2427 }
2429 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
2430 TCGReg rd, TCGReg base, intptr_t offset)
2431 {
2432 if (vece == MO_64) {
2433 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
2434 if (type == TCG_TYPE_V128) {
2435 tcg_out_dup2_vec(s, rd, rd, rd);
2436 }
2437 } else {
2438 int q = type - TCG_TYPE_V64;
2439 tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
2440 rd, base, offset);
2441 }
2442 return true;
2443 }
2445 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
2446 TCGReg rd, int64_t v64)
2447 {
2448 int q = type - TCG_TYPE_V64;
2449 int cmode, imm8, i;
2451 /* Test all bytes equal first. */
2452 if (vece == MO_8) {
2453 tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
2454 return;
2455 }
2457 /*
2458 * Test all bytes 0x00 or 0xff second. This can match cases that
2459 * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
2460 */
2461 for (i = imm8 = 0; i < 8; i++) {
2462 uint8_t byte = v64 >> (i * 8);
2463 if (byte == 0xff) {
2464 imm8 |= 1 << i;
2465 } else if (byte != 0) {
2466 goto fail_bytes;
2467 }
2468 }
2469 tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
2470 return;
2471 fail_bytes:
2473 /*
2474 * Tests for various replications. For each element width, if we
2475 * cannot find an expansion there's no point checking a larger
2476 * width because we already know by replication it cannot match.
2477 */
2478 if (vece == MO_16) {
2479 uint16_t v16 = v64;
2481 if (is_shimm16(v16, &cmode, &imm8)) {
2482 tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
2483 return;
2484 }
2485 if (is_shimm16(~v16, &cmode, &imm8)) {
2486 tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
2487 return;
2488 }
2490 /*
2491 * Otherwise, all remaining constants can be loaded in two insns:
2492 * rd = v16 & 0xff, rd |= v16 & 0xff00.
2493 */
2494 tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
2495 tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8); /* VORRI */
2496 return;
2497 }
2499 if (vece == MO_32) {
2500 uint32_t v32 = v64;
2502 if (is_shimm32(v32, &cmode, &imm8) ||
2503 is_soimm32(v32, &cmode, &imm8)) {
2504 tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
2505 return;
2506 }
2507 if (is_shimm32(~v32, &cmode, &imm8) ||
2508 is_soimm32(~v32, &cmode, &imm8)) {
2509 tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
2510 return;
2511 }
2513 /*
2514 * Restrict the set of constants to those we can load with
2515 * two instructions. Others we load from the pool.
2516 */
2517 i = is_shimm32_pair(v32, &cmode, &imm8);
2518 if (i) {
2519 tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
2520 tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
2521 return;
2522 }
2523 i = is_shimm32_pair(~v32, &cmode, &imm8);
2524 if (i) {
2525 tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
2526 tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
2527 return;
2528 }
2529 }
2531 /*
2532 * As a last resort, load from the constant pool.
2533 */
2534 if (!q || vece == MO_64) {
2535 new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
2536 /* VLDR Dd, [pc + offset] */
2537 tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
2538 if (q) {
2539 tcg_out_dup2_vec(s, rd, rd, rd);
2540 }
2541 } else {
2542 new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
2543 /* add tmp, pc, offset */
2544 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
2545 tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
2546 }
2547 }
2549 static const ARMInsn vec_cmp_insn[16] = {
2550 [TCG_COND_EQ] = INSN_VCEQ,
2551 [TCG_COND_GT] = INSN_VCGT,
2552 [TCG_COND_GE] = INSN_VCGE,
2553 [TCG_COND_GTU] = INSN_VCGT_U,
2554 [TCG_COND_GEU] = INSN_VCGE_U,
2555 };
2557 static const ARMInsn vec_cmp0_insn[16] = {
2558 [TCG_COND_EQ] = INSN_VCEQ0,
2559 [TCG_COND_GT] = INSN_VCGT0,
2560 [TCG_COND_GE] = INSN_VCGE0,
2561 [TCG_COND_LT] = INSN_VCLT0,
2562 [TCG_COND_LE] = INSN_VCLE0,
2563 };
2565 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
2566 unsigned vecl, unsigned vece,
2567 const TCGArg args[TCG_MAX_OP_ARGS],
2568 const int const_args[TCG_MAX_OP_ARGS])
2569 {
2570 TCGType type = vecl + TCG_TYPE_V64;
2571 unsigned q = vecl;
2572 TCGArg a0, a1, a2, a3;
2573 int cmode, imm8;
2575 a0 = args[0];
2576 a1 = args[1];
2577 a2 = args[2];
2579 switch (opc) {
2580 case INDEX_op_ld_vec:
2581 tcg_out_ld(s, type, a0, a1, a2);
2582 return;
2583 case INDEX_op_st_vec:
2584 tcg_out_st(s, type, a0, a1, a2);
2585 return;
2586 case INDEX_op_dupm_vec:
2587 tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
2588 return;
2589 case INDEX_op_dup2_vec:
2590 tcg_out_dup2_vec(s, a0, a1, a2);
2591 return;
2592 case INDEX_op_abs_vec:
2593 tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
2594 return;
2595 case INDEX_op_neg_vec:
2596 tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
2597 return;
2598 case INDEX_op_not_vec:
2599 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
2600 return;
2601 case INDEX_op_add_vec:
2602 tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
2603 return;
2604 case INDEX_op_mul_vec:
2605 tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
2606 return;
2607 case INDEX_op_smax_vec:
2608 tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
2609 return;
2610 case INDEX_op_smin_vec:
2611 tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
2612 return;
2613 case INDEX_op_sub_vec:
2614 tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
2615 return;
2616 case INDEX_op_ssadd_vec:
2617 tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
2618 return;
2619 case INDEX_op_sssub_vec:
2620 tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
2621 return;
2622 case INDEX_op_umax_vec:
2623 tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
2624 return;
2625 case INDEX_op_umin_vec:
2626 tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
2627 return;
2628 case INDEX_op_usadd_vec:
2629 tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
2630 return;
2631 case INDEX_op_ussub_vec:
2632 tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
2633 return;
2634 case INDEX_op_xor_vec:
2635 tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
2636 return;
2637 case INDEX_op_arm_sshl_vec:
2638 /*
2639 * Note that Vm is the data and Vn is the shift count,
2640 * therefore the arguments appear reversed.
2641 */
2642 tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
2643 return;
2644 case INDEX_op_arm_ushl_vec:
2645 /* See above. */
2646 tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
2647 return;
2648 case INDEX_op_shli_vec:
2649 tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
2650 return;
2651 case INDEX_op_shri_vec:
2652 tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
2653 return;
2654 case INDEX_op_sari_vec:
2655 tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
2656 return;
2657 case INDEX_op_arm_sli_vec:
2658 tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
2659 return;
2661 case INDEX_op_andc_vec:
2662 if (!const_args[2]) {
2663 tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
2664 return;
2665 }
2666 a2 = ~a2;
2667 /* fall through */
2668 case INDEX_op_and_vec:
2669 if (const_args[2]) {
2670 is_shimm1632(~a2, &cmode, &imm8);
2671 if (a0 == a1) {
2672 tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
2673 return;
2674 }
2675 tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
2676 a2 = a0;
2677 }
2678 tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
2679 return;
2681 case INDEX_op_orc_vec:
2682 if (!const_args[2]) {
2683 tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
2684 return;
2685 }
2686 a2 = ~a2;
2687 /* fall through */
2688 case INDEX_op_or_vec:
2689 if (const_args[2]) {
2690 is_shimm1632(a2, &cmode, &imm8);
2691 if (a0 == a1) {
2692 tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
2693 return;
2694 }
2695 tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
2696 a2 = a0;
2697 }
2698 tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
2699 return;
2701 case INDEX_op_cmp_vec:
2702 {
2703 TCGCond cond = args[3];
2705 if (cond == TCG_COND_NE) {
2706 if (const_args[2]) {
2707 tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
2708 } else {
2709 tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
2710 tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
2711 }
2712 } else {
2713 ARMInsn insn;
2715 if (const_args[2]) {
2716 insn = vec_cmp0_insn[cond];
2717 if (insn) {
2718 tcg_out_vreg2(s, insn, q, vece, a0, a1);
2719 return;
2720 }
2721 tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
2722 a2 = TCG_VEC_TMP;
2723 }
2724 insn = vec_cmp_insn[cond];
2725 if (insn == 0) {
2726 TCGArg t;
2727 t = a1, a1 = a2, a2 = t;
2728 cond = tcg_swap_cond(cond);
2729 insn = vec_cmp_insn[cond];
2730 tcg_debug_assert(insn != 0);
2731 }
2732 tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
2733 }
2734 }
2735 return;
2737 case INDEX_op_bitsel_vec:
2738 a3 = args[3];
2739 if (a0 == a3) {
2740 tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
2741 } else if (a0 == a2) {
2742 tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
2743 } else {
2744 tcg_out_mov(s, type, a0, a1);
2745 tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
2746 }
2747 return;
2749 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
2750 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
2751 default:
2752 g_assert_not_reached();
2753 }
2754 }
2756 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
2757 {
2758 switch (opc) {
2759 case INDEX_op_add_vec:
2760 case INDEX_op_sub_vec:
2761 case INDEX_op_and_vec:
2762 case INDEX_op_andc_vec:
2763 case INDEX_op_or_vec:
2764 case INDEX_op_orc_vec:
2765 case INDEX_op_xor_vec:
2766 case INDEX_op_not_vec:
2767 case INDEX_op_shli_vec:
2768 case INDEX_op_shri_vec:
2769 case INDEX_op_sari_vec:
2770 case INDEX_op_ssadd_vec:
2771 case INDEX_op_sssub_vec:
2772 case INDEX_op_usadd_vec:
2773 case INDEX_op_ussub_vec:
2774 case INDEX_op_bitsel_vec:
2775 return 1;
2776 case INDEX_op_abs_vec:
2777 case INDEX_op_cmp_vec:
2778 case INDEX_op_mul_vec:
2779 case INDEX_op_neg_vec:
2780 case INDEX_op_smax_vec:
2781 case INDEX_op_smin_vec:
2782 case INDEX_op_umax_vec:
2783 case INDEX_op_umin_vec:
2784 return vece < MO_64;
2785 case INDEX_op_shlv_vec:
2786 case INDEX_op_shrv_vec:
2787 case INDEX_op_sarv_vec:
2788 case INDEX_op_rotli_vec:
2789 case INDEX_op_rotlv_vec:
2790 case INDEX_op_rotrv_vec:
2791 return -1;
2792 default:
2793 return 0;
2794 }
2795 }
2797 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
2798 TCGArg a0, ...)
2799 {
2800 va_list va;
2801 TCGv_vec v0, v1, v2, t1, t2, c1;
2802 TCGArg a2;
2804 va_start(va, a0);
2805 v0 = temp_tcgv_vec(arg_temp(a0));
2806 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
2807 a2 = va_arg(va, TCGArg);
2808 va_end(va);
2810 switch (opc) {
2811 case INDEX_op_shlv_vec:
2812 /*
2813 * Merely propagate shlv_vec to arm_ushl_vec.
2814 * In this way we don't set TCG_TARGET_HAS_shv_vec
2815 * because everything is done via expansion.
2816 */
2817 v2 = temp_tcgv_vec(arg_temp(a2));
2818 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
2819 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
2820 break;
2822 case INDEX_op_shrv_vec:
2823 case INDEX_op_sarv_vec:
2824 /* Right shifts are negative left shifts for NEON. */
2825 v2 = temp_tcgv_vec(arg_temp(a2));
2826 t1 = tcg_temp_new_vec(type);
2827 tcg_gen_neg_vec(vece, t1, v2);
2828 if (opc == INDEX_op_shrv_vec) {
2829 opc = INDEX_op_arm_ushl_vec;
2830 } else {
2831 opc = INDEX_op_arm_sshl_vec;
2832 }
2833 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
2834 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
2835 tcg_temp_free_vec(t1);
2836 break;
2838 case INDEX_op_rotli_vec:
2839 t1 = tcg_temp_new_vec(type);
2840 tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
2841 vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
2842 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
2843 tcg_temp_free_vec(t1);
2844 break;
2846 case INDEX_op_rotlv_vec:
2847 v2 = temp_tcgv_vec(arg_temp(a2));
2848 t1 = tcg_temp_new_vec(type);
2849 c1 = tcg_constant_vec(type, vece, 8 << vece);
2850 tcg_gen_sub_vec(vece, t1, v2, c1);
2851 /* Right shifts are negative left shifts for NEON. */
2852 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
2853 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
2854 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
2855 tcgv_vec_arg(v1), tcgv_vec_arg(v2));
2856 tcg_gen_or_vec(vece, v0, v0, t1);
2857 tcg_temp_free_vec(t1);
2858 break;
2860 case INDEX_op_rotrv_vec:
2861 v2 = temp_tcgv_vec(arg_temp(a2));
2862 t1 = tcg_temp_new_vec(type);
2863 t2 = tcg_temp_new_vec(type);
2864 c1 = tcg_constant_vec(type, vece, 8 << vece);
2865 tcg_gen_neg_vec(vece, t1, v2);
2866 tcg_gen_sub_vec(vece, t2, c1, v2);
2867 /* Right shifts are negative left shifts for NEON. */
2868 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
2869 tcgv_vec_arg(v1), tcgv_vec_arg(t1));
2870 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
2871 tcgv_vec_arg(v1), tcgv_vec_arg(t2));
2872 tcg_gen_or_vec(vece, v0, t1, t2);
2873 tcg_temp_free_vec(t1);
2874 tcg_temp_free_vec(t2);
2875 break;
2877 default:
2878 g_assert_not_reached();
2879 }
2880 }
2882 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2883 {
2884 int i;
2885 for (i = 0; i < count; ++i) {
2886 p[i] = INSN_NOP;
2887 }
2888 }
2890 /* Compute frame size via macros, to share between tcg_target_qemu_prologue
2891 and tcg_register_jit. */
2893 #define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2895 #define FRAME_SIZE \
2896 ((PUSH_SIZE \
2897 + TCG_STATIC_CALL_ARGS_SIZE \
2898 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
2899 + TCG_TARGET_STACK_ALIGN - 1) \
2900 & -TCG_TARGET_STACK_ALIGN)
2902 #define STACK_ADDEND (FRAME_SIZE - PUSH_SIZE)
2904 static void tcg_target_qemu_prologue(TCGContext *s)
2905 {
2906 /* Calling convention requires us to save r4-r11 and lr. */
2907 /* stmdb sp!, { r4 - r11, lr } */
2908 tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK,
2909 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
2910 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
2911 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14));
2913 /* Reserve callee argument and tcg temp space. */
2914 tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
2915 TCG_REG_CALL_STACK, STACK_ADDEND, 1);
2916 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2917 CPU_TEMP_BUF_NLONGS * sizeof(long));
2919 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2921 #ifndef CONFIG_SOFTMMU
2922 if (guest_base) {
2923 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base);
2924 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
2925 }
2926 #endif
2928 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]);
2930 /*
2931 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2932 * and fall through to the rest of the epilogue.
2933 */
2934 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2935 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 0);
2936 tcg_out_epilogue(s);
2937 }
2939 static void tcg_out_epilogue(TCGContext *s)
2940 {
2941 /* Release local stack frame. */
2942 tcg_out_dat_rI(s, COND_AL, ARITH_ADD, TCG_REG_CALL_STACK,
2943 TCG_REG_CALL_STACK, STACK_ADDEND, 1);
2945 /* ldmia sp!, { r4 - r11, pc } */
2946 tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK,
2947 (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
2948 (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
2949 (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC));
2950 }
2952 typedef struct {
2953 DebugFrameHeader h;
2954 uint8_t fde_def_cfa[4];
2955 uint8_t fde_reg_ofs[18];
2956 } DebugFrame;
2958 #define ELF_HOST_MACHINE EM_ARM
2960 /* We're expecting a 2 byte uleb128 encoded value. */
2961 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2963 static const DebugFrame debug_frame = {
2964 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2965 .h.cie.id = -1,
2966 .h.cie.version = 1,
2967 .h.cie.code_align = 1,
2968 .h.cie.data_align = 0x7c, /* sleb128 -4 */
2969 .h.cie.return_column = 14,
2971 /* Total FDE size does not include the "len" member. */
2972 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2974 .fde_def_cfa = {
2975 12, 13, /* DW_CFA_def_cfa sp, ... */
2976 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2977 (FRAME_SIZE >> 7)
2978 },
2979 .fde_reg_ofs = {
2980 /* The following must match the stmdb in the prologue. */
2981 0x8e, 1, /* DW_CFA_offset, lr, -4 */
2982 0x8b, 2, /* DW_CFA_offset, r11, -8 */
2983 0x8a, 3, /* DW_CFA_offset, r10, -12 */
2984 0x89, 4, /* DW_CFA_offset, r9, -16 */
2985 0x88, 5, /* DW_CFA_offset, r8, -20 */
2986 0x87, 6, /* DW_CFA_offset, r7, -24 */
2987 0x86, 7, /* DW_CFA_offset, r6, -28 */
2988 0x85, 8, /* DW_CFA_offset, r5, -32 */
2989 0x84, 9, /* DW_CFA_offset, r4, -36 */
2990 }
2991 };
2993 void tcg_register_jit(const void *buf, size_t buf_size)
2994 {
2995 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2996 }