?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
block: Kill .bdrv_co_discard()
[qemu/kevin.git] / linux-user / main.c
blob462e820469d9d5d064e38fa95e560df413baeff9
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 unsigned long mmap_min_addr;
49 unsigned long guest_base;
50 int have_guest_base;
51
52 #define EXCP_DUMP(env, fmt, ...) \
53 do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61 } while (0)
62
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
71 # ifdef TARGET_MIPS
72 /* MIPS only supports 31 bits of virtual address space for user space */
73 unsigned long reserved_va = 0x77000000;
74 # else
75 unsigned long reserved_va = 0xf7000000;
76 # endif
77 #else
78 unsigned long reserved_va;
79 #endif
80
81 static void usage(int exitcode);
82
83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
84 const char *qemu_uname_release;
85
86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
89 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
90
91 void gemu_log(const char *fmt, ...)
92 {
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98 }
99
100 #if defined(TARGET_I386)
101 int cpu_get_pic_interrupt(CPUX86State *env)
102 {
103 return -1;
104 }
105 #endif
106
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
109
110 /* To implement exclusive operations we force all cpus to syncronise.
111 We don't require a full sync, only that no cpus are executing guest code.
112 The alternative is to map target atomic ops onto host equivalents,
113 which requires quite a lot of per host/target work. */
114 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
115 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
116 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
117 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
118 static int pending_cpus;
119
120 /* Make sure everything is in a consistent state for calling fork(). */
121 void fork_start(void)
122 {
123 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
124 pthread_mutex_lock(&exclusive_lock);
125 mmap_fork_start();
126 }
127
128 void fork_end(int child)
129 {
130 mmap_fork_end(child);
131 if (child) {
132 CPUState *cpu, *next_cpu;
133 /* Child processes created by fork() only have a single thread.
134 Discard information about the parent threads. */
135 CPU_FOREACH_SAFE(cpu, next_cpu) {
136 if (cpu != thread_cpu) {
137 QTAILQ_REMOVE(&cpus, cpu, node);
138 }
139 }
140 pending_cpus = 0;
141 pthread_mutex_init(&exclusive_lock, NULL);
142 pthread_mutex_init(&cpu_list_mutex, NULL);
143 pthread_cond_init(&exclusive_cond, NULL);
144 pthread_cond_init(&exclusive_resume, NULL);
145 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
146 gdbserver_fork(thread_cpu);
147 } else {
148 pthread_mutex_unlock(&exclusive_lock);
149 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
150 }
151 }
152
153 /* Wait for pending exclusive operations to complete. The exclusive lock
154 must be held. */
155 static inline void exclusive_idle(void)
156 {
157 while (pending_cpus) {
158 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
159 }
160 }
161
162 /* Start an exclusive operation.
163 Must only be called from outside cpu_exec. */
164 static inline void start_exclusive(void)
165 {
166 CPUState *other_cpu;
167
168 pthread_mutex_lock(&exclusive_lock);
169 exclusive_idle();
170
171 pending_cpus = 1;
172 /* Make all other cpus stop executing. */
173 CPU_FOREACH(other_cpu) {
174 if (other_cpu->running) {
175 pending_cpus++;
176 cpu_exit(other_cpu);
177 }
178 }
179 if (pending_cpus > 1) {
180 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
181 }
182 }
183
184 /* Finish an exclusive operation. */
185 static inline void __attribute__((unused)) end_exclusive(void)
186 {
187 pending_cpus = 0;
188 pthread_cond_broadcast(&exclusive_resume);
189 pthread_mutex_unlock(&exclusive_lock);
190 }
191
192 /* Wait for exclusive ops to finish, and begin cpu execution. */
193 static inline void cpu_exec_start(CPUState *cpu)
194 {
195 pthread_mutex_lock(&exclusive_lock);
196 exclusive_idle();
197 cpu->running = true;
198 pthread_mutex_unlock(&exclusive_lock);
199 }
200
201 /* Mark cpu as not executing, and release pending exclusive ops. */
202 static inline void cpu_exec_end(CPUState *cpu)
203 {
204 pthread_mutex_lock(&exclusive_lock);
205 cpu->running = false;
206 if (pending_cpus > 1) {
207 pending_cpus--;
208 if (pending_cpus == 1) {
209 pthread_cond_signal(&exclusive_cond);
210 }
211 }
212 exclusive_idle();
213 pthread_mutex_unlock(&exclusive_lock);
214 }
215
216 void cpu_list_lock(void)
217 {
218 pthread_mutex_lock(&cpu_list_mutex);
219 }
220
221 void cpu_list_unlock(void)
222 {
223 pthread_mutex_unlock(&cpu_list_mutex);
224 }
225
226
227 #ifdef TARGET_I386
228 /***********************************************************/
229 /* CPUX86 core interface */
230
231 uint64_t cpu_get_tsc(CPUX86State *env)
232 {
233 return cpu_get_host_ticks();
234 }
235
236 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
237 int flags)
238 {
239 unsigned int e1, e2;
240 uint32_t *p;
241 e1 = (addr << 16) | (limit & 0xffff);
242 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
243 e2 |= flags;
244 p = ptr;
245 p[0] = tswap32(e1);
246 p[1] = tswap32(e2);
247 }
248
249 static uint64_t *idt_table;
250 #ifdef TARGET_X86_64
251 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
252 uint64_t addr, unsigned int sel)
253 {
254 uint32_t *p, e1, e2;
255 e1 = (addr & 0xffff) | (sel << 16);
256 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
257 p = ptr;
258 p[0] = tswap32(e1);
259 p[1] = tswap32(e2);
260 p[2] = tswap32(addr >> 32);
261 p[3] = 0;
262 }
263 /* only dpl matters as we do only user space emulation */
264 static void set_idt(int n, unsigned int dpl)
265 {
266 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
267 }
268 #else
269 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
270 uint32_t addr, unsigned int sel)
271 {
272 uint32_t *p, e1, e2;
273 e1 = (addr & 0xffff) | (sel << 16);
274 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
275 p = ptr;
276 p[0] = tswap32(e1);
277 p[1] = tswap32(e2);
278 }
279
280 /* only dpl matters as we do only user space emulation */
281 static void set_idt(int n, unsigned int dpl)
282 {
283 set_gate(idt_table + n, 0, dpl, 0, 0);
284 }
285 #endif
286
287 void cpu_loop(CPUX86State *env)
288 {
289 CPUState *cs = CPU(x86_env_get_cpu(env));
290 int trapnr;
291 abi_ulong pc;
292 abi_ulong ret;
293 target_siginfo_t info;
294
295 for(;;) {
296 cpu_exec_start(cs);
297 trapnr = cpu_exec(cs);
298 cpu_exec_end(cs);
299 switch(trapnr) {
300 case 0x80:
301 /* linux syscall from int $0x80 */
302 ret = do_syscall(env,
303 env->regs[R_EAX],
304 env->regs[R_EBX],
305 env->regs[R_ECX],
306 env->regs[R_EDX],
307 env->regs[R_ESI],
308 env->regs[R_EDI],
309 env->regs[R_EBP],
310 0, 0);
311 if (ret == -TARGET_ERESTARTSYS) {
312 env->eip -= 2;
313 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
314 env->regs[R_EAX] = ret;
315 }
316 break;
317 #ifndef TARGET_ABI32
318 case EXCP_SYSCALL:
319 /* linux syscall from syscall instruction */
320 ret = do_syscall(env,
321 env->regs[R_EAX],
322 env->regs[R_EDI],
323 env->regs[R_ESI],
324 env->regs[R_EDX],
325 env->regs[10],
326 env->regs[8],
327 env->regs[9],
328 0, 0);
329 if (ret == -TARGET_ERESTARTSYS) {
330 env->eip -= 2;
331 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
332 env->regs[R_EAX] = ret;
333 }
334 break;
335 #endif
336 case EXCP0B_NOSEG:
337 case EXCP0C_STACK:
338 info.si_signo = TARGET_SIGBUS;
339 info.si_errno = 0;
340 info.si_code = TARGET_SI_KERNEL;
341 info._sifields._sigfault._addr = 0;
342 queue_signal(env, info.si_signo, &info);
343 break;
344 case EXCP0D_GPF:
345 /* XXX: potential problem if ABI32 */
346 #ifndef TARGET_X86_64
347 if (env->eflags & VM_MASK) {
348 handle_vm86_fault(env);
349 } else
350 #endif
351 {
352 info.si_signo = TARGET_SIGSEGV;
353 info.si_errno = 0;
354 info.si_code = TARGET_SI_KERNEL;
355 info._sifields._sigfault._addr = 0;
356 queue_signal(env, info.si_signo, &info);
357 }
358 break;
359 case EXCP0E_PAGE:
360 info.si_signo = TARGET_SIGSEGV;
361 info.si_errno = 0;
362 if (!(env->error_code & 1))
363 info.si_code = TARGET_SEGV_MAPERR;
364 else
365 info.si_code = TARGET_SEGV_ACCERR;
366 info._sifields._sigfault._addr = env->cr[2];
367 queue_signal(env, info.si_signo, &info);
368 break;
369 case EXCP00_DIVZ:
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_trap(env, trapnr);
373 } else
374 #endif
375 {
376 /* division by zero */
377 info.si_signo = TARGET_SIGFPE;
378 info.si_errno = 0;
379 info.si_code = TARGET_FPE_INTDIV;
380 info._sifields._sigfault._addr = env->eip;
381 queue_signal(env, info.si_signo, &info);
382 }
383 break;
384 case EXCP01_DB:
385 case EXCP03_INT3:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 info.si_signo = TARGET_SIGTRAP;
393 info.si_errno = 0;
394 if (trapnr == EXCP01_DB) {
395 info.si_code = TARGET_TRAP_BRKPT;
396 info._sifields._sigfault._addr = env->eip;
397 } else {
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 }
401 queue_signal(env, info.si_signo, &info);
402 }
403 break;
404 case EXCP04_INTO:
405 case EXCP05_BOUND:
406 #ifndef TARGET_X86_64
407 if (env->eflags & VM_MASK) {
408 handle_vm86_trap(env, trapnr);
409 } else
410 #endif
411 {
412 info.si_signo = TARGET_SIGSEGV;
413 info.si_errno = 0;
414 info.si_code = TARGET_SI_KERNEL;
415 info._sifields._sigfault._addr = 0;
416 queue_signal(env, info.si_signo, &info);
417 }
418 break;
419 case EXCP06_ILLOP:
420 info.si_signo = TARGET_SIGILL;
421 info.si_errno = 0;
422 info.si_code = TARGET_ILL_ILLOPN;
423 info._sifields._sigfault._addr = env->eip;
424 queue_signal(env, info.si_signo, &info);
425 break;
426 case EXCP_INTERRUPT:
427 /* just indicate that signals should be handled asap */
428 break;
429 case EXCP_DEBUG:
430 {
431 int sig;
432
433 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
434 if (sig)
435 {
436 info.si_signo = sig;
437 info.si_errno = 0;
438 info.si_code = TARGET_TRAP_BRKPT;
439 queue_signal(env, info.si_signo, &info);
440 }
441 }
442 break;
443 default:
444 pc = env->segs[R_CS].base + env->eip;
445 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
446 (long)pc, trapnr);
447 abort();
448 }
449 process_pending_signals(env);
450 }
451 }
452 #endif
453
454 #ifdef TARGET_ARM
455
456 #define get_user_code_u32(x, gaddr, env) \
457 ({ abi_long __r = get_user_u32((x), (gaddr)); \
458 if (!__r && bswap_code(arm_sctlr_b(env))) { \
459 (x) = bswap32(x); \
460 } \
461 __r; \
462 })
463
464 #define get_user_code_u16(x, gaddr, env) \
465 ({ abi_long __r = get_user_u16((x), (gaddr)); \
466 if (!__r && bswap_code(arm_sctlr_b(env))) { \
467 (x) = bswap16(x); \
468 } \
469 __r; \
470 })
471
472 #define get_user_data_u32(x, gaddr, env) \
473 ({ abi_long __r = get_user_u32((x), (gaddr)); \
474 if (!__r && arm_cpu_bswap_data(env)) { \
475 (x) = bswap32(x); \
476 } \
477 __r; \
478 })
479
480 #define get_user_data_u16(x, gaddr, env) \
481 ({ abi_long __r = get_user_u16((x), (gaddr)); \
482 if (!__r && arm_cpu_bswap_data(env)) { \
483 (x) = bswap16(x); \
484 } \
485 __r; \
486 })
487
488 #define put_user_data_u32(x, gaddr, env) \
489 ({ typeof(x) __x = (x); \
490 if (arm_cpu_bswap_data(env)) { \
491 __x = bswap32(__x); \
492 } \
493 put_user_u32(__x, (gaddr)); \
494 })
495
496 #define put_user_data_u16(x, gaddr, env) \
497 ({ typeof(x) __x = (x); \
498 if (arm_cpu_bswap_data(env)) { \
499 __x = bswap16(__x); \
500 } \
501 put_user_u16(__x, (gaddr)); \
502 })
503
504 #ifdef TARGET_ABI32
505 /* Commpage handling -- there is no commpage for AArch64 */
506
507 /*
508 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
509 * Input:
510 * r0 = pointer to oldval
511 * r1 = pointer to newval
512 * r2 = pointer to target value
513 *
514 * Output:
515 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
516 * C set if *ptr was changed, clear if no exchange happened
517 *
518 * Note segv's in kernel helpers are a bit tricky, we can set the
519 * data address sensibly but the PC address is just the entry point.
520 */
521 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
522 {
523 uint64_t oldval, newval, val;
524 uint32_t addr, cpsr;
525 target_siginfo_t info;
526
527 /* Based on the 32 bit code in do_kernel_trap */
528
529 /* XXX: This only works between threads, not between processes.
530 It's probably possible to implement this with native host
531 operations. However things like ldrex/strex are much harder so
532 there's not much point trying. */
533 start_exclusive();
534 cpsr = cpsr_read(env);
535 addr = env->regs[2];
536
537 if (get_user_u64(oldval, env->regs[0])) {
538 env->exception.vaddress = env->regs[0];
539 goto segv;
540 };
541
542 if (get_user_u64(newval, env->regs[1])) {
543 env->exception.vaddress = env->regs[1];
544 goto segv;
545 };
546
547 if (get_user_u64(val, addr)) {
548 env->exception.vaddress = addr;
549 goto segv;
550 }
551
552 if (val == oldval) {
553 val = newval;
554
555 if (put_user_u64(val, addr)) {
556 env->exception.vaddress = addr;
557 goto segv;
558 };
559
560 env->regs[0] = 0;
561 cpsr |= CPSR_C;
562 } else {
563 env->regs[0] = -1;
564 cpsr &= ~CPSR_C;
565 }
566 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
567 end_exclusive();
568 return;
569
570 segv:
571 end_exclusive();
572 /* We get the PC of the entry address - which is as good as anything,
573 on a real kernel what you get depends on which mode it uses. */
574 info.si_signo = TARGET_SIGSEGV;
575 info.si_errno = 0;
576 /* XXX: check env->error_code */
577 info.si_code = TARGET_SEGV_MAPERR;
578 info._sifields._sigfault._addr = env->exception.vaddress;
579 queue_signal(env, info.si_signo, &info);
580 }
581
582 /* Handle a jump to the kernel code page. */
583 static int
584 do_kernel_trap(CPUARMState *env)
585 {
586 uint32_t addr;
587 uint32_t cpsr;
588 uint32_t val;
589
590 switch (env->regs[15]) {
591 case 0xffff0fa0: /* __kernel_memory_barrier */
592 /* ??? No-op. Will need to do better for SMP. */
593 break;
594 case 0xffff0fc0: /* __kernel_cmpxchg */
595 /* XXX: This only works between threads, not between processes.
596 It's probably possible to implement this with native host
597 operations. However things like ldrex/strex are much harder so
598 there's not much point trying. */
599 start_exclusive();
600 cpsr = cpsr_read(env);
601 addr = env->regs[2];
602 /* FIXME: This should SEGV if the access fails. */
603 if (get_user_u32(val, addr))
604 val = ~env->regs[0];
605 if (val == env->regs[0]) {
606 val = env->regs[1];
607 /* FIXME: Check for segfaults. */
608 put_user_u32(val, addr);
609 env->regs[0] = 0;
610 cpsr |= CPSR_C;
611 } else {
612 env->regs[0] = -1;
613 cpsr &= ~CPSR_C;
614 }
615 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
616 end_exclusive();
617 break;
618 case 0xffff0fe0: /* __kernel_get_tls */
619 env->regs[0] = cpu_get_tls(env);
620 break;
621 case 0xffff0f60: /* __kernel_cmpxchg64 */
622 arm_kernel_cmpxchg64_helper(env);
623 break;
624
625 default:
626 return 1;
627 }
628 /* Jump back to the caller. */
629 addr = env->regs[14];
630 if (addr & 1) {
631 env->thumb = 1;
632 addr &= ~1;
633 }
634 env->regs[15] = addr;
635
636 return 0;
637 }
638
639 /* Store exclusive handling for AArch32 */
640 static int do_strex(CPUARMState *env)
641 {
642 uint64_t val;
643 int size;
644 int rc = 1;
645 int segv = 0;
646 uint32_t addr;
647 start_exclusive();
648 if (env->exclusive_addr != env->exclusive_test) {
649 goto fail;
650 }
651 /* We know we're always AArch32 so the address is in uint32_t range
652 * unless it was the -1 exclusive-monitor-lost value (which won't
653 * match exclusive_test above).
654 */
655 assert(extract64(env->exclusive_addr, 32, 32) == 0);
656 addr = env->exclusive_addr;
657 size = env->exclusive_info & 0xf;
658 switch (size) {
659 case 0:
660 segv = get_user_u8(val, addr);
661 break;
662 case 1:
663 segv = get_user_data_u16(val, addr, env);
664 break;
665 case 2:
666 case 3:
667 segv = get_user_data_u32(val, addr, env);
668 break;
669 default:
670 abort();
671 }
672 if (segv) {
673 env->exception.vaddress = addr;
674 goto done;
675 }
676 if (size == 3) {
677 uint32_t valhi;
678 segv = get_user_data_u32(valhi, addr + 4, env);
679 if (segv) {
680 env->exception.vaddress = addr + 4;
681 goto done;
682 }
683 if (arm_cpu_bswap_data(env)) {
684 val = deposit64((uint64_t)valhi, 32, 32, val);
685 } else {
686 val = deposit64(val, 32, 32, valhi);
687 }
688 }
689 if (val != env->exclusive_val) {
690 goto fail;
691 }
692
693 val = env->regs[(env->exclusive_info >> 8) & 0xf];
694 switch (size) {
695 case 0:
696 segv = put_user_u8(val, addr);
697 break;
698 case 1:
699 segv = put_user_data_u16(val, addr, env);
700 break;
701 case 2:
702 case 3:
703 segv = put_user_data_u32(val, addr, env);
704 break;
705 }
706 if (segv) {
707 env->exception.vaddress = addr;
708 goto done;
709 }
710 if (size == 3) {
711 val = env->regs[(env->exclusive_info >> 12) & 0xf];
712 segv = put_user_data_u32(val, addr + 4, env);
713 if (segv) {
714 env->exception.vaddress = addr + 4;
715 goto done;
716 }
717 }
718 rc = 0;
719 fail:
720 env->regs[15] += 4;
721 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
722 done:
723 end_exclusive();
724 return segv;
725 }
726
727 void cpu_loop(CPUARMState *env)
728 {
729 CPUState *cs = CPU(arm_env_get_cpu(env));
730 int trapnr;
731 unsigned int n, insn;
732 target_siginfo_t info;
733 uint32_t addr;
734 abi_ulong ret;
735
736 for(;;) {
737 cpu_exec_start(cs);
738 trapnr = cpu_exec(cs);
739 cpu_exec_end(cs);
740 switch(trapnr) {
741 case EXCP_UDEF:
742 {
743 TaskState *ts = cs->opaque;
744 uint32_t opcode;
745 int rc;
746
747 /* we handle the FPU emulation here, as Linux */
748 /* we get the opcode */
749 /* FIXME - what to do if get_user() fails? */
750 get_user_code_u32(opcode, env->regs[15], env);
751
752 rc = EmulateAll(opcode, &ts->fpa, env);
753 if (rc == 0) { /* illegal instruction */
754 info.si_signo = TARGET_SIGILL;
755 info.si_errno = 0;
756 info.si_code = TARGET_ILL_ILLOPN;
757 info._sifields._sigfault._addr = env->regs[15];
758 queue_signal(env, info.si_signo, &info);
759 } else if (rc < 0) { /* FP exception */
760 int arm_fpe=0;
761
762 /* translate softfloat flags to FPSR flags */
763 if (-rc & float_flag_invalid)
764 arm_fpe |= BIT_IOC;
765 if (-rc & float_flag_divbyzero)
766 arm_fpe |= BIT_DZC;
767 if (-rc & float_flag_overflow)
768 arm_fpe |= BIT_OFC;
769 if (-rc & float_flag_underflow)
770 arm_fpe |= BIT_UFC;
771 if (-rc & float_flag_inexact)
772 arm_fpe |= BIT_IXC;
773
774 FPSR fpsr = ts->fpa.fpsr;
775 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
776
777 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
778 info.si_signo = TARGET_SIGFPE;
779 info.si_errno = 0;
780
781 /* ordered by priority, least first */
782 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
783 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
784 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
785 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
786 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
787
788 info._sifields._sigfault._addr = env->regs[15];
789 queue_signal(env, info.si_signo, &info);
790 } else {
791 env->regs[15] += 4;
792 }
793
794 /* accumulate unenabled exceptions */
795 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
796 fpsr |= BIT_IXC;
797 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
798 fpsr |= BIT_UFC;
799 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
800 fpsr |= BIT_OFC;
801 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
802 fpsr |= BIT_DZC;
803 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
804 fpsr |= BIT_IOC;
805 ts->fpa.fpsr=fpsr;
806 } else { /* everything OK */
807 /* increment PC */
808 env->regs[15] += 4;
809 }
810 }
811 break;
812 case EXCP_SWI:
813 case EXCP_BKPT:
814 {
815 env->eabi = 1;
816 /* system call */
817 if (trapnr == EXCP_BKPT) {
818 if (env->thumb) {
819 /* FIXME - what to do if get_user() fails? */
820 get_user_code_u16(insn, env->regs[15], env);
821 n = insn & 0xff;
822 env->regs[15] += 2;
823 } else {
824 /* FIXME - what to do if get_user() fails? */
825 get_user_code_u32(insn, env->regs[15], env);
826 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
827 env->regs[15] += 4;
828 }
829 } else {
830 if (env->thumb) {
831 /* FIXME - what to do if get_user() fails? */
832 get_user_code_u16(insn, env->regs[15] - 2, env);
833 n = insn & 0xff;
834 } else {
835 /* FIXME - what to do if get_user() fails? */
836 get_user_code_u32(insn, env->regs[15] - 4, env);
837 n = insn & 0xffffff;
838 }
839 }
840
841 if (n == ARM_NR_cacheflush) {
842 /* nop */
843 } else if (n == ARM_NR_semihosting
844 || n == ARM_NR_thumb_semihosting) {
845 env->regs[0] = do_arm_semihosting (env);
846 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
847 /* linux syscall */
848 if (env->thumb || n == 0) {
849 n = env->regs[7];
850 } else {
851 n -= ARM_SYSCALL_BASE;
852 env->eabi = 0;
853 }
854 if ( n > ARM_NR_BASE) {
855 switch (n) {
856 case ARM_NR_cacheflush:
857 /* nop */
858 break;
859 case ARM_NR_set_tls:
860 cpu_set_tls(env, env->regs[0]);
861 env->regs[0] = 0;
862 break;
863 case ARM_NR_breakpoint:
864 env->regs[15] -= env->thumb ? 2 : 4;
865 goto excp_debug;
866 default:
867 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
868 n);
869 env->regs[0] = -TARGET_ENOSYS;
870 break;
871 }
872 } else {
873 ret = do_syscall(env,
874 n,
875 env->regs[0],
876 env->regs[1],
877 env->regs[2],
878 env->regs[3],
879 env->regs[4],
880 env->regs[5],
881 0, 0);
882 if (ret == -TARGET_ERESTARTSYS) {
883 env->regs[15] -= env->thumb ? 2 : 4;
884 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
885 env->regs[0] = ret;
886 }
887 }
888 } else {
889 goto error;
890 }
891 }
892 break;
893 case EXCP_INTERRUPT:
894 /* just indicate that signals should be handled asap */
895 break;
896 case EXCP_STREX:
897 if (!do_strex(env)) {
898 break;
899 }
900 /* fall through for segv */
901 case EXCP_PREFETCH_ABORT:
902 case EXCP_DATA_ABORT:
903 addr = env->exception.vaddress;
904 {
905 info.si_signo = TARGET_SIGSEGV;
906 info.si_errno = 0;
907 /* XXX: check env->error_code */
908 info.si_code = TARGET_SEGV_MAPERR;
909 info._sifields._sigfault._addr = addr;
910 queue_signal(env, info.si_signo, &info);
911 }
912 break;
913 case EXCP_DEBUG:
914 excp_debug:
915 {
916 int sig;
917
918 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
919 if (sig)
920 {
921 info.si_signo = sig;
922 info.si_errno = 0;
923 info.si_code = TARGET_TRAP_BRKPT;
924 queue_signal(env, info.si_signo, &info);
925 }
926 }
927 break;
928 case EXCP_KERNEL_TRAP:
929 if (do_kernel_trap(env))
930 goto error;
931 break;
932 case EXCP_YIELD:
933 /* nothing to do here for user-mode, just resume guest code */
934 break;
935 default:
936 error:
937 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
938 abort();
939 }
940 process_pending_signals(env);
941 }
942 }
943
944 #else
945
946 /*
947 * Handle AArch64 store-release exclusive
948 *
949 * rs = gets the status result of store exclusive
950 * rt = is the register that is stored
951 * rt2 = is the second register store (in STP)
952 *
953 */
954 static int do_strex_a64(CPUARMState *env)
955 {
956 uint64_t val;
957 int size;
958 bool is_pair;
959 int rc = 1;
960 int segv = 0;
961 uint64_t addr;
962 int rs, rt, rt2;
963
964 start_exclusive();
965 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
966 size = extract32(env->exclusive_info, 0, 2);
967 is_pair = extract32(env->exclusive_info, 2, 1);
968 rs = extract32(env->exclusive_info, 4, 5);
969 rt = extract32(env->exclusive_info, 9, 5);
970 rt2 = extract32(env->exclusive_info, 14, 5);
971
972 addr = env->exclusive_addr;
973
974 if (addr != env->exclusive_test) {
975 goto finish;
976 }
977
978 switch (size) {
979 case 0:
980 segv = get_user_u8(val, addr);
981 break;
982 case 1:
983 segv = get_user_u16(val, addr);
984 break;
985 case 2:
986 segv = get_user_u32(val, addr);
987 break;
988 case 3:
989 segv = get_user_u64(val, addr);
990 break;
991 default:
992 abort();
993 }
994 if (segv) {
995 env->exception.vaddress = addr;
996 goto error;
997 }
998 if (val != env->exclusive_val) {
999 goto finish;
1000 }
1001 if (is_pair) {
1002 if (size == 2) {
1003 segv = get_user_u32(val, addr + 4);
1004 } else {
1005 segv = get_user_u64(val, addr + 8);
1006 }
1007 if (segv) {
1008 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1009 goto error;
1010 }
1011 if (val != env->exclusive_high) {
1012 goto finish;
1013 }
1014 }
1015 /* handle the zero register */
1016 val = rt == 31 ? 0 : env->xregs[rt];
1017 switch (size) {
1018 case 0:
1019 segv = put_user_u8(val, addr);
1020 break;
1021 case 1:
1022 segv = put_user_u16(val, addr);
1023 break;
1024 case 2:
1025 segv = put_user_u32(val, addr);
1026 break;
1027 case 3:
1028 segv = put_user_u64(val, addr);
1029 break;
1030 }
1031 if (segv) {
1032 goto error;
1033 }
1034 if (is_pair) {
1035 /* handle the zero register */
1036 val = rt2 == 31 ? 0 : env->xregs[rt2];
1037 if (size == 2) {
1038 segv = put_user_u32(val, addr + 4);
1039 } else {
1040 segv = put_user_u64(val, addr + 8);
1041 }
1042 if (segv) {
1043 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1044 goto error;
1045 }
1046 }
1047 rc = 0;
1048 finish:
1049 env->pc += 4;
1050 /* rs == 31 encodes a write to the ZR, thus throwing away
1051 * the status return. This is rather silly but valid.
1052 */
1053 if (rs < 31) {
1054 env->xregs[rs] = rc;
1055 }
1056 error:
1057 /* instruction faulted, PC does not advance */
1058 /* either way a strex releases any exclusive lock we have */
1059 env->exclusive_addr = -1;
1060 end_exclusive();
1061 return segv;
1062 }
1063
1064 /* AArch64 main loop */
1065 void cpu_loop(CPUARMState *env)
1066 {
1067 CPUState *cs = CPU(arm_env_get_cpu(env));
1068 int trapnr, sig;
1069 abi_long ret;
1070 target_siginfo_t info;
1071
1072 for (;;) {
1073 cpu_exec_start(cs);
1074 trapnr = cpu_exec(cs);
1075 cpu_exec_end(cs);
1076
1077 switch (trapnr) {
1078 case EXCP_SWI:
1079 ret = do_syscall(env,
1080 env->xregs[8],
1081 env->xregs[0],
1082 env->xregs[1],
1083 env->xregs[2],
1084 env->xregs[3],
1085 env->xregs[4],
1086 env->xregs[5],
1087 0, 0);
1088 if (ret == -TARGET_ERESTARTSYS) {
1089 env->pc -= 4;
1090 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1091 env->xregs[0] = ret;
1092 }
1093 break;
1094 case EXCP_INTERRUPT:
1095 /* just indicate that signals should be handled asap */
1096 break;
1097 case EXCP_UDEF:
1098 info.si_signo = TARGET_SIGILL;
1099 info.si_errno = 0;
1100 info.si_code = TARGET_ILL_ILLOPN;
1101 info._sifields._sigfault._addr = env->pc;
1102 queue_signal(env, info.si_signo, &info);
1103 break;
1104 case EXCP_STREX:
1105 if (!do_strex_a64(env)) {
1106 break;
1107 }
1108 /* fall through for segv */
1109 case EXCP_PREFETCH_ABORT:
1110 case EXCP_DATA_ABORT:
1111 info.si_signo = TARGET_SIGSEGV;
1112 info.si_errno = 0;
1113 /* XXX: check env->error_code */
1114 info.si_code = TARGET_SEGV_MAPERR;
1115 info._sifields._sigfault._addr = env->exception.vaddress;
1116 queue_signal(env, info.si_signo, &info);
1117 break;
1118 case EXCP_DEBUG:
1119 case EXCP_BKPT:
1120 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1121 if (sig) {
1122 info.si_signo = sig;
1123 info.si_errno = 0;
1124 info.si_code = TARGET_TRAP_BRKPT;
1125 queue_signal(env, info.si_signo, &info);
1126 }
1127 break;
1128 case EXCP_SEMIHOST:
1129 env->xregs[0] = do_arm_semihosting(env);
1130 break;
1131 case EXCP_YIELD:
1132 /* nothing to do here for user-mode, just resume guest code */
1133 break;
1134 default:
1135 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1136 abort();
1137 }
1138 process_pending_signals(env);
1139 /* Exception return on AArch64 always clears the exclusive monitor,
1140 * so any return to running guest code implies this.
1141 * A strex (successful or otherwise) also clears the monitor, so
1142 * we don't need to specialcase EXCP_STREX.
1143 */
1144 env->exclusive_addr = -1;
1145 }
1146 }
1147 #endif /* ndef TARGET_ABI32 */
1148
1149 #endif
1150
1151 #ifdef TARGET_UNICORE32
1152
1153 void cpu_loop(CPUUniCore32State *env)
1154 {
1155 CPUState *cs = CPU(uc32_env_get_cpu(env));
1156 int trapnr;
1157 unsigned int n, insn;
1158 target_siginfo_t info;
1159
1160 for (;;) {
1161 cpu_exec_start(cs);
1162 trapnr = cpu_exec(cs);
1163 cpu_exec_end(cs);
1164 switch (trapnr) {
1165 case UC32_EXCP_PRIV:
1166 {
1167 /* system call */
1168 get_user_u32(insn, env->regs[31] - 4);
1169 n = insn & 0xffffff;
1170
1171 if (n >= UC32_SYSCALL_BASE) {
1172 /* linux syscall */
1173 n -= UC32_SYSCALL_BASE;
1174 if (n == UC32_SYSCALL_NR_set_tls) {
1175 cpu_set_tls(env, env->regs[0]);
1176 env->regs[0] = 0;
1177 } else {
1178 abi_long ret = do_syscall(env,
1179 n,
1180 env->regs[0],
1181 env->regs[1],
1182 env->regs[2],
1183 env->regs[3],
1184 env->regs[4],
1185 env->regs[5],
1186 0, 0);
1187 if (ret == -TARGET_ERESTARTSYS) {
1188 env->regs[31] -= 4;
1189 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1190 env->regs[0] = ret;
1191 }
1192 }
1193 } else {
1194 goto error;
1195 }
1196 }
1197 break;
1198 case UC32_EXCP_DTRAP:
1199 case UC32_EXCP_ITRAP:
1200 info.si_signo = TARGET_SIGSEGV;
1201 info.si_errno = 0;
1202 /* XXX: check env->error_code */
1203 info.si_code = TARGET_SEGV_MAPERR;
1204 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1205 queue_signal(env, info.si_signo, &info);
1206 break;
1207 case EXCP_INTERRUPT:
1208 /* just indicate that signals should be handled asap */
1209 break;
1210 case EXCP_DEBUG:
1211 {
1212 int sig;
1213
1214 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1215 if (sig) {
1216 info.si_signo = sig;
1217 info.si_errno = 0;
1218 info.si_code = TARGET_TRAP_BRKPT;
1219 queue_signal(env, info.si_signo, &info);
1220 }
1221 }
1222 break;
1223 default:
1224 goto error;
1225 }
1226 process_pending_signals(env);
1227 }
1228
1229 error:
1230 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1231 abort();
1232 }
1233 #endif
1234
1235 #ifdef TARGET_SPARC
1236 #define SPARC64_STACK_BIAS 2047
1237
1238 //#define DEBUG_WIN
1239
1240 /* WARNING: dealing with register windows _is_ complicated. More info
1241 can be found at http://www.sics.se/~psm/sparcstack.html */
1242 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1243 {
1244 index = (index + cwp * 16) % (16 * env->nwindows);
1245 /* wrap handling : if cwp is on the last window, then we use the
1246 registers 'after' the end */
1247 if (index < 8 && env->cwp == env->nwindows - 1)
1248 index += 16 * env->nwindows;
1249 return index;
1250 }
1251
1252 /* save the register window 'cwp1' */
1253 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1254 {
1255 unsigned int i;
1256 abi_ulong sp_ptr;
1257
1258 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1259 #ifdef TARGET_SPARC64
1260 if (sp_ptr & 3)
1261 sp_ptr += SPARC64_STACK_BIAS;
1262 #endif
1263 #if defined(DEBUG_WIN)
1264 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1265 sp_ptr, cwp1);
1266 #endif
1267 for(i = 0; i < 16; i++) {
1268 /* FIXME - what to do if put_user() fails? */
1269 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1270 sp_ptr += sizeof(abi_ulong);
1271 }
1272 }
1273
1274 static void save_window(CPUSPARCState *env)
1275 {
1276 #ifndef TARGET_SPARC64
1277 unsigned int new_wim;
1278 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1279 ((1LL << env->nwindows) - 1);
1280 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1281 env->wim = new_wim;
1282 #else
1283 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1284 env->cansave++;
1285 env->canrestore--;
1286 #endif
1287 }
1288
1289 static void restore_window(CPUSPARCState *env)
1290 {
1291 #ifndef TARGET_SPARC64
1292 unsigned int new_wim;
1293 #endif
1294 unsigned int i, cwp1;
1295 abi_ulong sp_ptr;
1296
1297 #ifndef TARGET_SPARC64
1298 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1299 ((1LL << env->nwindows) - 1);
1300 #endif
1301
1302 /* restore the invalid window */
1303 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1304 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1305 #ifdef TARGET_SPARC64
1306 if (sp_ptr & 3)
1307 sp_ptr += SPARC64_STACK_BIAS;
1308 #endif
1309 #if defined(DEBUG_WIN)
1310 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1311 sp_ptr, cwp1);
1312 #endif
1313 for(i = 0; i < 16; i++) {
1314 /* FIXME - what to do if get_user() fails? */
1315 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1316 sp_ptr += sizeof(abi_ulong);
1317 }
1318 #ifdef TARGET_SPARC64
1319 env->canrestore++;
1320 if (env->cleanwin < env->nwindows - 1)
1321 env->cleanwin++;
1322 env->cansave--;
1323 #else
1324 env->wim = new_wim;
1325 #endif
1326 }
1327
1328 static void flush_windows(CPUSPARCState *env)
1329 {
1330 int offset, cwp1;
1331
1332 offset = 1;
1333 for(;;) {
1334 /* if restore would invoke restore_window(), then we can stop */
1335 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1336 #ifndef TARGET_SPARC64
1337 if (env->wim & (1 << cwp1))
1338 break;
1339 #else
1340 if (env->canrestore == 0)
1341 break;
1342 env->cansave++;
1343 env->canrestore--;
1344 #endif
1345 save_window_offset(env, cwp1);
1346 offset++;
1347 }
1348 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1349 #ifndef TARGET_SPARC64
1350 /* set wim so that restore will reload the registers */
1351 env->wim = 1 << cwp1;
1352 #endif
1353 #if defined(DEBUG_WIN)
1354 printf("flush_windows: nb=%d\n", offset - 1);
1355 #endif
1356 }
1357
1358 void cpu_loop (CPUSPARCState *env)
1359 {
1360 CPUState *cs = CPU(sparc_env_get_cpu(env));
1361 int trapnr;
1362 abi_long ret;
1363 target_siginfo_t info;
1364
1365 while (1) {
1366 cpu_exec_start(cs);
1367 trapnr = cpu_exec(cs);
1368 cpu_exec_end(cs);
1369
1370 /* Compute PSR before exposing state. */
1371 if (env->cc_op != CC_OP_FLAGS) {
1372 cpu_get_psr(env);
1373 }
1374
1375 switch (trapnr) {
1376 #ifndef TARGET_SPARC64
1377 case 0x88:
1378 case 0x90:
1379 #else
1380 case 0x110:
1381 case 0x16d:
1382 #endif
1383 ret = do_syscall (env, env->gregs[1],
1384 env->regwptr[0], env->regwptr[1],
1385 env->regwptr[2], env->regwptr[3],
1386 env->regwptr[4], env->regwptr[5],
1387 0, 0);
1388 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1389 break;
1390 }
1391 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1392 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1393 env->xcc |= PSR_CARRY;
1394 #else
1395 env->psr |= PSR_CARRY;
1396 #endif
1397 ret = -ret;
1398 } else {
1399 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1400 env->xcc &= ~PSR_CARRY;
1401 #else
1402 env->psr &= ~PSR_CARRY;
1403 #endif
1404 }
1405 env->regwptr[0] = ret;
1406 /* next instruction */
1407 env->pc = env->npc;
1408 env->npc = env->npc + 4;
1409 break;
1410 case 0x83: /* flush windows */
1411 #ifdef TARGET_ABI32
1412 case 0x103:
1413 #endif
1414 flush_windows(env);
1415 /* next instruction */
1416 env->pc = env->npc;
1417 env->npc = env->npc + 4;
1418 break;
1419 #ifndef TARGET_SPARC64
1420 case TT_WIN_OVF: /* window overflow */
1421 save_window(env);
1422 break;
1423 case TT_WIN_UNF: /* window underflow */
1424 restore_window(env);
1425 break;
1426 case TT_TFAULT:
1427 case TT_DFAULT:
1428 {
1429 info.si_signo = TARGET_SIGSEGV;
1430 info.si_errno = 0;
1431 /* XXX: check env->error_code */
1432 info.si_code = TARGET_SEGV_MAPERR;
1433 info._sifields._sigfault._addr = env->mmuregs[4];
1434 queue_signal(env, info.si_signo, &info);
1435 }
1436 break;
1437 #else
1438 case TT_SPILL: /* window overflow */
1439 save_window(env);
1440 break;
1441 case TT_FILL: /* window underflow */
1442 restore_window(env);
1443 break;
1444 case TT_TFAULT:
1445 case TT_DFAULT:
1446 {
1447 info.si_signo = TARGET_SIGSEGV;
1448 info.si_errno = 0;
1449 /* XXX: check env->error_code */
1450 info.si_code = TARGET_SEGV_MAPERR;
1451 if (trapnr == TT_DFAULT)
1452 info._sifields._sigfault._addr = env->dmmuregs[4];
1453 else
1454 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1455 queue_signal(env, info.si_signo, &info);
1456 }
1457 break;
1458 #ifndef TARGET_ABI32
1459 case 0x16e:
1460 flush_windows(env);
1461 sparc64_get_context(env);
1462 break;
1463 case 0x16f:
1464 flush_windows(env);
1465 sparc64_set_context(env);
1466 break;
1467 #endif
1468 #endif
1469 case EXCP_INTERRUPT:
1470 /* just indicate that signals should be handled asap */
1471 break;
1472 case TT_ILL_INSN:
1473 {
1474 info.si_signo = TARGET_SIGILL;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_ILL_ILLOPC;
1477 info._sifields._sigfault._addr = env->pc;
1478 queue_signal(env, info.si_signo, &info);
1479 }
1480 break;
1481 case EXCP_DEBUG:
1482 {
1483 int sig;
1484
1485 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1486 if (sig)
1487 {
1488 info.si_signo = sig;
1489 info.si_errno = 0;
1490 info.si_code = TARGET_TRAP_BRKPT;
1491 queue_signal(env, info.si_signo, &info);
1492 }
1493 }
1494 break;
1495 default:
1496 printf ("Unhandled trap: 0x%x\n", trapnr);
1497 cpu_dump_state(cs, stderr, fprintf, 0);
1498 exit(EXIT_FAILURE);
1499 }
1500 process_pending_signals (env);
1501 }
1502 }
1503
1504 #endif
1505
1506 #ifdef TARGET_PPC
1507 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1508 {
1509 return cpu_get_host_ticks();
1510 }
1511
1512 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1513 {
1514 return cpu_ppc_get_tb(env);
1515 }
1516
1517 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1518 {
1519 return cpu_ppc_get_tb(env) >> 32;
1520 }
1521
1522 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1523 {
1524 return cpu_ppc_get_tb(env);
1525 }
1526
1527 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1528 {
1529 return cpu_ppc_get_tb(env) >> 32;
1530 }
1531
1532 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1533 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1534
1535 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1536 {
1537 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1538 }
1539
1540 /* XXX: to be fixed */
1541 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1542 {
1543 return -1;
1544 }
1545
1546 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1547 {
1548 return -1;
1549 }
1550
1551 static int do_store_exclusive(CPUPPCState *env)
1552 {
1553 target_ulong addr;
1554 target_ulong page_addr;
1555 target_ulong val, val2 __attribute__((unused)) = 0;
1556 int flags;
1557 int segv = 0;
1558
1559 addr = env->reserve_ea;
1560 page_addr = addr & TARGET_PAGE_MASK;
1561 start_exclusive();
1562 mmap_lock();
1563 flags = page_get_flags(page_addr);
1564 if ((flags & PAGE_READ) == 0) {
1565 segv = 1;
1566 } else {
1567 int reg = env->reserve_info & 0x1f;
1568 int size = env->reserve_info >> 5;
1569 int stored = 0;
1570
1571 if (addr == env->reserve_addr) {
1572 switch (size) {
1573 case 1: segv = get_user_u8(val, addr); break;
1574 case 2: segv = get_user_u16(val, addr); break;
1575 case 4: segv = get_user_u32(val, addr); break;
1576 #if defined(TARGET_PPC64)
1577 case 8: segv = get_user_u64(val, addr); break;
1578 case 16: {
1579 segv = get_user_u64(val, addr);
1580 if (!segv) {
1581 segv = get_user_u64(val2, addr + 8);
1582 }
1583 break;
1584 }
1585 #endif
1586 default: abort();
1587 }
1588 if (!segv && val == env->reserve_val) {
1589 val = env->gpr[reg];
1590 switch (size) {
1591 case 1: segv = put_user_u8(val, addr); break;
1592 case 2: segv = put_user_u16(val, addr); break;
1593 case 4: segv = put_user_u32(val, addr); break;
1594 #if defined(TARGET_PPC64)
1595 case 8: segv = put_user_u64(val, addr); break;
1596 case 16: {
1597 if (val2 == env->reserve_val2) {
1598 if (msr_le) {
1599 val2 = val;
1600 val = env->gpr[reg+1];
1601 } else {
1602 val2 = env->gpr[reg+1];
1603 }
1604 segv = put_user_u64(val, addr);
1605 if (!segv) {
1606 segv = put_user_u64(val2, addr + 8);
1607 }
1608 }
1609 break;
1610 }
1611 #endif
1612 default: abort();
1613 }
1614 if (!segv) {
1615 stored = 1;
1616 }
1617 }
1618 }
1619 env->crf[0] = (stored << 1) | xer_so;
1620 env->reserve_addr = (target_ulong)-1;
1621 }
1622 if (!segv) {
1623 env->nip += 4;
1624 }
1625 mmap_unlock();
1626 end_exclusive();
1627 return segv;
1628 }
1629
1630 void cpu_loop(CPUPPCState *env)
1631 {
1632 CPUState *cs = CPU(ppc_env_get_cpu(env));
1633 target_siginfo_t info;
1634 int trapnr;
1635 target_ulong ret;
1636
1637 for(;;) {
1638 cpu_exec_start(cs);
1639 trapnr = cpu_exec(cs);
1640 cpu_exec_end(cs);
1641 switch(trapnr) {
1642 case POWERPC_EXCP_NONE:
1643 /* Just go on */
1644 break;
1645 case POWERPC_EXCP_CRITICAL: /* Critical input */
1646 cpu_abort(cs, "Critical interrupt while in user mode. "
1647 "Aborting\n");
1648 break;
1649 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1650 cpu_abort(cs, "Machine check exception while in user mode. "
1651 "Aborting\n");
1652 break;
1653 case POWERPC_EXCP_DSI: /* Data storage exception */
1654 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1655 env->spr[SPR_DAR]);
1656 /* XXX: check this. Seems bugged */
1657 switch (env->error_code & 0xFF000000) {
1658 case 0x40000000:
1659 info.si_signo = TARGET_SIGSEGV;
1660 info.si_errno = 0;
1661 info.si_code = TARGET_SEGV_MAPERR;
1662 break;
1663 case 0x04000000:
1664 info.si_signo = TARGET_SIGILL;
1665 info.si_errno = 0;
1666 info.si_code = TARGET_ILL_ILLADR;
1667 break;
1668 case 0x08000000:
1669 info.si_signo = TARGET_SIGSEGV;
1670 info.si_errno = 0;
1671 info.si_code = TARGET_SEGV_ACCERR;
1672 break;
1673 default:
1674 /* Let's send a regular segfault... */
1675 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1676 env->error_code);
1677 info.si_signo = TARGET_SIGSEGV;
1678 info.si_errno = 0;
1679 info.si_code = TARGET_SEGV_MAPERR;
1680 break;
1681 }
1682 info._sifields._sigfault._addr = env->nip;
1683 queue_signal(env, info.si_signo, &info);
1684 break;
1685 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1686 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1687 "\n", env->spr[SPR_SRR0]);
1688 /* XXX: check this */
1689 switch (env->error_code & 0xFF000000) {
1690 case 0x40000000:
1691 info.si_signo = TARGET_SIGSEGV;
1692 info.si_errno = 0;
1693 info.si_code = TARGET_SEGV_MAPERR;
1694 break;
1695 case 0x10000000:
1696 case 0x08000000:
1697 info.si_signo = TARGET_SIGSEGV;
1698 info.si_errno = 0;
1699 info.si_code = TARGET_SEGV_ACCERR;
1700 break;
1701 default:
1702 /* Let's send a regular segfault... */
1703 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1704 env->error_code);
1705 info.si_signo = TARGET_SIGSEGV;
1706 info.si_errno = 0;
1707 info.si_code = TARGET_SEGV_MAPERR;
1708 break;
1709 }
1710 info._sifields._sigfault._addr = env->nip - 4;
1711 queue_signal(env, info.si_signo, &info);
1712 break;
1713 case POWERPC_EXCP_EXTERNAL: /* External input */
1714 cpu_abort(cs, "External interrupt while in user mode. "
1715 "Aborting\n");
1716 break;
1717 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1718 EXCP_DUMP(env, "Unaligned memory access\n");
1719 /* XXX: check this */
1720 info.si_signo = TARGET_SIGBUS;
1721 info.si_errno = 0;
1722 info.si_code = TARGET_BUS_ADRALN;
1723 info._sifields._sigfault._addr = env->nip;
1724 queue_signal(env, info.si_signo, &info);
1725 break;
1726 case POWERPC_EXCP_PROGRAM: /* Program exception */
1727 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1728 /* XXX: check this */
1729 switch (env->error_code & ~0xF) {
1730 case POWERPC_EXCP_FP:
1731 EXCP_DUMP(env, "Floating point program exception\n");
1732 info.si_signo = TARGET_SIGFPE;
1733 info.si_errno = 0;
1734 switch (env->error_code & 0xF) {
1735 case POWERPC_EXCP_FP_OX:
1736 info.si_code = TARGET_FPE_FLTOVF;
1737 break;
1738 case POWERPC_EXCP_FP_UX:
1739 info.si_code = TARGET_FPE_FLTUND;
1740 break;
1741 case POWERPC_EXCP_FP_ZX:
1742 case POWERPC_EXCP_FP_VXZDZ:
1743 info.si_code = TARGET_FPE_FLTDIV;
1744 break;
1745 case POWERPC_EXCP_FP_XX:
1746 info.si_code = TARGET_FPE_FLTRES;
1747 break;
1748 case POWERPC_EXCP_FP_VXSOFT:
1749 info.si_code = TARGET_FPE_FLTINV;
1750 break;
1751 case POWERPC_EXCP_FP_VXSNAN:
1752 case POWERPC_EXCP_FP_VXISI:
1753 case POWERPC_EXCP_FP_VXIDI:
1754 case POWERPC_EXCP_FP_VXIMZ:
1755 case POWERPC_EXCP_FP_VXVC:
1756 case POWERPC_EXCP_FP_VXSQRT:
1757 case POWERPC_EXCP_FP_VXCVI:
1758 info.si_code = TARGET_FPE_FLTSUB;
1759 break;
1760 default:
1761 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1762 env->error_code);
1763 break;
1764 }
1765 break;
1766 case POWERPC_EXCP_INVAL:
1767 EXCP_DUMP(env, "Invalid instruction\n");
1768 info.si_signo = TARGET_SIGILL;
1769 info.si_errno = 0;
1770 switch (env->error_code & 0xF) {
1771 case POWERPC_EXCP_INVAL_INVAL:
1772 info.si_code = TARGET_ILL_ILLOPC;
1773 break;
1774 case POWERPC_EXCP_INVAL_LSWX:
1775 info.si_code = TARGET_ILL_ILLOPN;
1776 break;
1777 case POWERPC_EXCP_INVAL_SPR:
1778 info.si_code = TARGET_ILL_PRVREG;
1779 break;
1780 case POWERPC_EXCP_INVAL_FP:
1781 info.si_code = TARGET_ILL_COPROC;
1782 break;
1783 default:
1784 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1785 env->error_code & 0xF);
1786 info.si_code = TARGET_ILL_ILLADR;
1787 break;
1788 }
1789 break;
1790 case POWERPC_EXCP_PRIV:
1791 EXCP_DUMP(env, "Privilege violation\n");
1792 info.si_signo = TARGET_SIGILL;
1793 info.si_errno = 0;
1794 switch (env->error_code & 0xF) {
1795 case POWERPC_EXCP_PRIV_OPC:
1796 info.si_code = TARGET_ILL_PRVOPC;
1797 break;
1798 case POWERPC_EXCP_PRIV_REG:
1799 info.si_code = TARGET_ILL_PRVREG;
1800 break;
1801 default:
1802 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1803 env->error_code & 0xF);
1804 info.si_code = TARGET_ILL_PRVOPC;
1805 break;
1806 }
1807 break;
1808 case POWERPC_EXCP_TRAP:
1809 cpu_abort(cs, "Tried to call a TRAP\n");
1810 break;
1811 default:
1812 /* Should not happen ! */
1813 cpu_abort(cs, "Unknown program exception (%02x)\n",
1814 env->error_code);
1815 break;
1816 }
1817 info._sifields._sigfault._addr = env->nip - 4;
1818 queue_signal(env, info.si_signo, &info);
1819 break;
1820 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1821 EXCP_DUMP(env, "No floating point allowed\n");
1822 info.si_signo = TARGET_SIGILL;
1823 info.si_errno = 0;
1824 info.si_code = TARGET_ILL_COPROC;
1825 info._sifields._sigfault._addr = env->nip - 4;
1826 queue_signal(env, info.si_signo, &info);
1827 break;
1828 case POWERPC_EXCP_SYSCALL: /* System call exception */
1829 cpu_abort(cs, "Syscall exception while in user mode. "
1830 "Aborting\n");
1831 break;
1832 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1833 EXCP_DUMP(env, "No APU instruction allowed\n");
1834 info.si_signo = TARGET_SIGILL;
1835 info.si_errno = 0;
1836 info.si_code = TARGET_ILL_COPROC;
1837 info._sifields._sigfault._addr = env->nip - 4;
1838 queue_signal(env, info.si_signo, &info);
1839 break;
1840 case POWERPC_EXCP_DECR: /* Decrementer exception */
1841 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1842 "Aborting\n");
1843 break;
1844 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1845 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1849 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1850 "Aborting\n");
1851 break;
1852 case POWERPC_EXCP_DTLB: /* Data TLB error */
1853 cpu_abort(cs, "Data TLB exception while in user mode. "
1854 "Aborting\n");
1855 break;
1856 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1857 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1858 "Aborting\n");
1859 break;
1860 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1861 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1862 info.si_signo = TARGET_SIGILL;
1863 info.si_errno = 0;
1864 info.si_code = TARGET_ILL_COPROC;
1865 info._sifields._sigfault._addr = env->nip - 4;
1866 queue_signal(env, info.si_signo, &info);
1867 break;
1868 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1869 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1870 break;
1871 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1872 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1873 break;
1874 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1875 cpu_abort(cs, "Performance monitor exception not handled\n");
1876 break;
1877 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1878 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1879 "Aborting\n");
1880 break;
1881 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1882 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1883 "Aborting\n");
1884 break;
1885 case POWERPC_EXCP_RESET: /* System reset exception */
1886 cpu_abort(cs, "Reset interrupt while in user mode. "
1887 "Aborting\n");
1888 break;
1889 case POWERPC_EXCP_DSEG: /* Data segment exception */
1890 cpu_abort(cs, "Data segment exception while in user mode. "
1891 "Aborting\n");
1892 break;
1893 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1894 cpu_abort(cs, "Instruction segment exception "
1895 "while in user mode. Aborting\n");
1896 break;
1897 /* PowerPC 64 with hypervisor mode support */
1898 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1899 cpu_abort(cs, "Hypervisor decrementer interrupt "
1900 "while in user mode. Aborting\n");
1901 break;
1902 case POWERPC_EXCP_TRACE: /* Trace exception */
1903 /* Nothing to do:
1904 * we use this exception to emulate step-by-step execution mode.
1905 */
1906 break;
1907 /* PowerPC 64 with hypervisor mode support */
1908 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1909 cpu_abort(cs, "Hypervisor data storage exception "
1910 "while in user mode. Aborting\n");
1911 break;
1912 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1913 cpu_abort(cs, "Hypervisor instruction storage exception "
1914 "while in user mode. Aborting\n");
1915 break;
1916 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1917 cpu_abort(cs, "Hypervisor data segment exception "
1918 "while in user mode. Aborting\n");
1919 break;
1920 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1921 cpu_abort(cs, "Hypervisor instruction segment exception "
1922 "while in user mode. Aborting\n");
1923 break;
1924 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1925 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1926 info.si_signo = TARGET_SIGILL;
1927 info.si_errno = 0;
1928 info.si_code = TARGET_ILL_COPROC;
1929 info._sifields._sigfault._addr = env->nip - 4;
1930 queue_signal(env, info.si_signo, &info);
1931 break;
1932 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1933 cpu_abort(cs, "Programmable interval timer interrupt "
1934 "while in user mode. Aborting\n");
1935 break;
1936 case POWERPC_EXCP_IO: /* IO error exception */
1937 cpu_abort(cs, "IO error exception while in user mode. "
1938 "Aborting\n");
1939 break;
1940 case POWERPC_EXCP_RUNM: /* Run mode exception */
1941 cpu_abort(cs, "Run mode exception while in user mode. "
1942 "Aborting\n");
1943 break;
1944 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1945 cpu_abort(cs, "Emulation trap exception not handled\n");
1946 break;
1947 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1948 cpu_abort(cs, "Instruction fetch TLB exception "
1949 "while in user-mode. Aborting");
1950 break;
1951 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1952 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1953 "Aborting");
1954 break;
1955 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1956 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1957 "Aborting");
1958 break;
1959 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1960 cpu_abort(cs, "Floating-point assist exception not handled\n");
1961 break;
1962 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1963 cpu_abort(cs, "Instruction address breakpoint exception "
1964 "not handled\n");
1965 break;
1966 case POWERPC_EXCP_SMI: /* System management interrupt */
1967 cpu_abort(cs, "System management interrupt while in user mode. "
1968 "Aborting\n");
1969 break;
1970 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1971 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1972 "Aborting\n");
1973 break;
1974 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1975 cpu_abort(cs, "Performance monitor exception not handled\n");
1976 break;
1977 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1978 cpu_abort(cs, "Vector assist exception not handled\n");
1979 break;
1980 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1981 cpu_abort(cs, "Soft patch exception not handled\n");
1982 break;
1983 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1984 cpu_abort(cs, "Maintenance exception while in user mode. "
1985 "Aborting\n");
1986 break;
1987 case POWERPC_EXCP_STOP: /* stop translation */
1988 /* We did invalidate the instruction cache. Go on */
1989 break;
1990 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1991 /* We just stopped because of a branch. Go on */
1992 break;
1993 case POWERPC_EXCP_SYSCALL_USER:
1994 /* system call in user-mode emulation */
1995 /* WARNING:
1996 * PPC ABI uses overflow flag in cr0 to signal an error
1997 * in syscalls.
1998 */
1999 env->crf[0] &= ~0x1;
2000 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
2001 env->gpr[5], env->gpr[6], env->gpr[7],
2002 env->gpr[8], 0, 0);
2003 if (ret == -TARGET_ERESTARTSYS) {
2004 env->nip -= 4;
2005 break;
2006 }
2007 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
2008 /* Returning from a successful sigreturn syscall.
2009 Avoid corrupting register state. */
2010 break;
2011 }
2012 if (ret > (target_ulong)(-515)) {
2013 env->crf[0] |= 0x1;
2014 ret = -ret;
2015 }
2016 env->gpr[3] = ret;
2017 break;
2018 case POWERPC_EXCP_STCX:
2019 if (do_store_exclusive(env)) {
2020 info.si_signo = TARGET_SIGSEGV;
2021 info.si_errno = 0;
2022 info.si_code = TARGET_SEGV_MAPERR;
2023 info._sifields._sigfault._addr = env->nip;
2024 queue_signal(env, info.si_signo, &info);
2025 }
2026 break;
2027 case EXCP_DEBUG:
2028 {
2029 int sig;
2030
2031 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2032 if (sig) {
2033 info.si_signo = sig;
2034 info.si_errno = 0;
2035 info.si_code = TARGET_TRAP_BRKPT;
2036 queue_signal(env, info.si_signo, &info);
2037 }
2038 }
2039 break;
2040 case EXCP_INTERRUPT:
2041 /* just indicate that signals should be handled asap */
2042 break;
2043 default:
2044 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2045 break;
2046 }
2047 process_pending_signals(env);
2048 }
2049 }
2050 #endif
2051
2052 #ifdef TARGET_MIPS
2053
2054 # ifdef TARGET_ABI_MIPSO32
2055 # define MIPS_SYS(name, args) args,
2056 static const uint8_t mips_syscall_args[] = {
2057 MIPS_SYS(sys_syscall , 8) /* 4000 */
2058 MIPS_SYS(sys_exit , 1)
2059 MIPS_SYS(sys_fork , 0)
2060 MIPS_SYS(sys_read , 3)
2061 MIPS_SYS(sys_write , 3)
2062 MIPS_SYS(sys_open , 3) /* 4005 */
2063 MIPS_SYS(sys_close , 1)
2064 MIPS_SYS(sys_waitpid , 3)
2065 MIPS_SYS(sys_creat , 2)
2066 MIPS_SYS(sys_link , 2)
2067 MIPS_SYS(sys_unlink , 1) /* 4010 */
2068 MIPS_SYS(sys_execve , 0)
2069 MIPS_SYS(sys_chdir , 1)
2070 MIPS_SYS(sys_time , 1)
2071 MIPS_SYS(sys_mknod , 3)
2072 MIPS_SYS(sys_chmod , 2) /* 4015 */
2073 MIPS_SYS(sys_lchown , 3)
2074 MIPS_SYS(sys_ni_syscall , 0)
2075 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2076 MIPS_SYS(sys_lseek , 3)
2077 MIPS_SYS(sys_getpid , 0) /* 4020 */
2078 MIPS_SYS(sys_mount , 5)
2079 MIPS_SYS(sys_umount , 1)
2080 MIPS_SYS(sys_setuid , 1)
2081 MIPS_SYS(sys_getuid , 0)
2082 MIPS_SYS(sys_stime , 1) /* 4025 */
2083 MIPS_SYS(sys_ptrace , 4)
2084 MIPS_SYS(sys_alarm , 1)
2085 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2086 MIPS_SYS(sys_pause , 0)
2087 MIPS_SYS(sys_utime , 2) /* 4030 */
2088 MIPS_SYS(sys_ni_syscall , 0)
2089 MIPS_SYS(sys_ni_syscall , 0)
2090 MIPS_SYS(sys_access , 2)
2091 MIPS_SYS(sys_nice , 1)
2092 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2093 MIPS_SYS(sys_sync , 0)
2094 MIPS_SYS(sys_kill , 2)
2095 MIPS_SYS(sys_rename , 2)
2096 MIPS_SYS(sys_mkdir , 2)
2097 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2098 MIPS_SYS(sys_dup , 1)
2099 MIPS_SYS(sys_pipe , 0)
2100 MIPS_SYS(sys_times , 1)
2101 MIPS_SYS(sys_ni_syscall , 0)
2102 MIPS_SYS(sys_brk , 1) /* 4045 */
2103 MIPS_SYS(sys_setgid , 1)
2104 MIPS_SYS(sys_getgid , 0)
2105 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2106 MIPS_SYS(sys_geteuid , 0)
2107 MIPS_SYS(sys_getegid , 0) /* 4050 */
2108 MIPS_SYS(sys_acct , 0)
2109 MIPS_SYS(sys_umount2 , 2)
2110 MIPS_SYS(sys_ni_syscall , 0)
2111 MIPS_SYS(sys_ioctl , 3)
2112 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2113 MIPS_SYS(sys_ni_syscall , 2)
2114 MIPS_SYS(sys_setpgid , 2)
2115 MIPS_SYS(sys_ni_syscall , 0)
2116 MIPS_SYS(sys_olduname , 1)
2117 MIPS_SYS(sys_umask , 1) /* 4060 */
2118 MIPS_SYS(sys_chroot , 1)
2119 MIPS_SYS(sys_ustat , 2)
2120 MIPS_SYS(sys_dup2 , 2)
2121 MIPS_SYS(sys_getppid , 0)
2122 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2123 MIPS_SYS(sys_setsid , 0)
2124 MIPS_SYS(sys_sigaction , 3)
2125 MIPS_SYS(sys_sgetmask , 0)
2126 MIPS_SYS(sys_ssetmask , 1)
2127 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2128 MIPS_SYS(sys_setregid , 2)
2129 MIPS_SYS(sys_sigsuspend , 0)
2130 MIPS_SYS(sys_sigpending , 1)
2131 MIPS_SYS(sys_sethostname , 2)
2132 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2133 MIPS_SYS(sys_getrlimit , 2)
2134 MIPS_SYS(sys_getrusage , 2)
2135 MIPS_SYS(sys_gettimeofday, 2)
2136 MIPS_SYS(sys_settimeofday, 2)
2137 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2138 MIPS_SYS(sys_setgroups , 2)
2139 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2140 MIPS_SYS(sys_symlink , 2)
2141 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2142 MIPS_SYS(sys_readlink , 3) /* 4085 */
2143 MIPS_SYS(sys_uselib , 1)
2144 MIPS_SYS(sys_swapon , 2)
2145 MIPS_SYS(sys_reboot , 3)
2146 MIPS_SYS(old_readdir , 3)
2147 MIPS_SYS(old_mmap , 6) /* 4090 */
2148 MIPS_SYS(sys_munmap , 2)
2149 MIPS_SYS(sys_truncate , 2)
2150 MIPS_SYS(sys_ftruncate , 2)
2151 MIPS_SYS(sys_fchmod , 2)
2152 MIPS_SYS(sys_fchown , 3) /* 4095 */
2153 MIPS_SYS(sys_getpriority , 2)
2154 MIPS_SYS(sys_setpriority , 3)
2155 MIPS_SYS(sys_ni_syscall , 0)
2156 MIPS_SYS(sys_statfs , 2)
2157 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2158 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2159 MIPS_SYS(sys_socketcall , 2)
2160 MIPS_SYS(sys_syslog , 3)
2161 MIPS_SYS(sys_setitimer , 3)
2162 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2163 MIPS_SYS(sys_newstat , 2)
2164 MIPS_SYS(sys_newlstat , 2)
2165 MIPS_SYS(sys_newfstat , 2)
2166 MIPS_SYS(sys_uname , 1)
2167 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2168 MIPS_SYS(sys_vhangup , 0)
2169 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2170 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2171 MIPS_SYS(sys_wait4 , 4)
2172 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2173 MIPS_SYS(sys_sysinfo , 1)
2174 MIPS_SYS(sys_ipc , 6)
2175 MIPS_SYS(sys_fsync , 1)
2176 MIPS_SYS(sys_sigreturn , 0)
2177 MIPS_SYS(sys_clone , 6) /* 4120 */
2178 MIPS_SYS(sys_setdomainname, 2)
2179 MIPS_SYS(sys_newuname , 1)
2180 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2181 MIPS_SYS(sys_adjtimex , 1)
2182 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2183 MIPS_SYS(sys_sigprocmask , 3)
2184 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2185 MIPS_SYS(sys_init_module , 5)
2186 MIPS_SYS(sys_delete_module, 1)
2187 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2188 MIPS_SYS(sys_quotactl , 0)
2189 MIPS_SYS(sys_getpgid , 1)
2190 MIPS_SYS(sys_fchdir , 1)
2191 MIPS_SYS(sys_bdflush , 2)
2192 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2193 MIPS_SYS(sys_personality , 1)
2194 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2195 MIPS_SYS(sys_setfsuid , 1)
2196 MIPS_SYS(sys_setfsgid , 1)
2197 MIPS_SYS(sys_llseek , 5) /* 4140 */
2198 MIPS_SYS(sys_getdents , 3)
2199 MIPS_SYS(sys_select , 5)
2200 MIPS_SYS(sys_flock , 2)
2201 MIPS_SYS(sys_msync , 3)
2202 MIPS_SYS(sys_readv , 3) /* 4145 */
2203 MIPS_SYS(sys_writev , 3)
2204 MIPS_SYS(sys_cacheflush , 3)
2205 MIPS_SYS(sys_cachectl , 3)
2206 MIPS_SYS(sys_sysmips , 4)
2207 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2208 MIPS_SYS(sys_getsid , 1)
2209 MIPS_SYS(sys_fdatasync , 0)
2210 MIPS_SYS(sys_sysctl , 1)
2211 MIPS_SYS(sys_mlock , 2)
2212 MIPS_SYS(sys_munlock , 2) /* 4155 */
2213 MIPS_SYS(sys_mlockall , 1)
2214 MIPS_SYS(sys_munlockall , 0)
2215 MIPS_SYS(sys_sched_setparam, 2)
2216 MIPS_SYS(sys_sched_getparam, 2)
2217 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2218 MIPS_SYS(sys_sched_getscheduler, 1)
2219 MIPS_SYS(sys_sched_yield , 0)
2220 MIPS_SYS(sys_sched_get_priority_max, 1)
2221 MIPS_SYS(sys_sched_get_priority_min, 1)
2222 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2223 MIPS_SYS(sys_nanosleep, 2)
2224 MIPS_SYS(sys_mremap , 5)
2225 MIPS_SYS(sys_accept , 3)
2226 MIPS_SYS(sys_bind , 3)
2227 MIPS_SYS(sys_connect , 3) /* 4170 */
2228 MIPS_SYS(sys_getpeername , 3)
2229 MIPS_SYS(sys_getsockname , 3)
2230 MIPS_SYS(sys_getsockopt , 5)
2231 MIPS_SYS(sys_listen , 2)
2232 MIPS_SYS(sys_recv , 4) /* 4175 */
2233 MIPS_SYS(sys_recvfrom , 6)
2234 MIPS_SYS(sys_recvmsg , 3)
2235 MIPS_SYS(sys_send , 4)
2236 MIPS_SYS(sys_sendmsg , 3)
2237 MIPS_SYS(sys_sendto , 6) /* 4180 */
2238 MIPS_SYS(sys_setsockopt , 5)
2239 MIPS_SYS(sys_shutdown , 2)
2240 MIPS_SYS(sys_socket , 3)
2241 MIPS_SYS(sys_socketpair , 4)
2242 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2243 MIPS_SYS(sys_getresuid , 3)
2244 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2245 MIPS_SYS(sys_poll , 3)
2246 MIPS_SYS(sys_nfsservctl , 3)
2247 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2248 MIPS_SYS(sys_getresgid , 3)
2249 MIPS_SYS(sys_prctl , 5)
2250 MIPS_SYS(sys_rt_sigreturn, 0)
2251 MIPS_SYS(sys_rt_sigaction, 4)
2252 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2253 MIPS_SYS(sys_rt_sigpending, 2)
2254 MIPS_SYS(sys_rt_sigtimedwait, 4)
2255 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2256 MIPS_SYS(sys_rt_sigsuspend, 0)
2257 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2258 MIPS_SYS(sys_pwrite64 , 6)
2259 MIPS_SYS(sys_chown , 3)
2260 MIPS_SYS(sys_getcwd , 2)
2261 MIPS_SYS(sys_capget , 2)
2262 MIPS_SYS(sys_capset , 2) /* 4205 */
2263 MIPS_SYS(sys_sigaltstack , 2)
2264 MIPS_SYS(sys_sendfile , 4)
2265 MIPS_SYS(sys_ni_syscall , 0)
2266 MIPS_SYS(sys_ni_syscall , 0)
2267 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2268 MIPS_SYS(sys_truncate64 , 4)
2269 MIPS_SYS(sys_ftruncate64 , 4)
2270 MIPS_SYS(sys_stat64 , 2)
2271 MIPS_SYS(sys_lstat64 , 2)
2272 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2273 MIPS_SYS(sys_pivot_root , 2)
2274 MIPS_SYS(sys_mincore , 3)
2275 MIPS_SYS(sys_madvise , 3)
2276 MIPS_SYS(sys_getdents64 , 3)
2277 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2278 MIPS_SYS(sys_ni_syscall , 0)
2279 MIPS_SYS(sys_gettid , 0)
2280 MIPS_SYS(sys_readahead , 5)
2281 MIPS_SYS(sys_setxattr , 5)
2282 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2283 MIPS_SYS(sys_fsetxattr , 5)
2284 MIPS_SYS(sys_getxattr , 4)
2285 MIPS_SYS(sys_lgetxattr , 4)
2286 MIPS_SYS(sys_fgetxattr , 4)
2287 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2288 MIPS_SYS(sys_llistxattr , 3)
2289 MIPS_SYS(sys_flistxattr , 3)
2290 MIPS_SYS(sys_removexattr , 2)
2291 MIPS_SYS(sys_lremovexattr, 2)
2292 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2293 MIPS_SYS(sys_tkill , 2)
2294 MIPS_SYS(sys_sendfile64 , 5)
2295 MIPS_SYS(sys_futex , 6)
2296 MIPS_SYS(sys_sched_setaffinity, 3)
2297 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2298 MIPS_SYS(sys_io_setup , 2)
2299 MIPS_SYS(sys_io_destroy , 1)
2300 MIPS_SYS(sys_io_getevents, 5)
2301 MIPS_SYS(sys_io_submit , 3)
2302 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2303 MIPS_SYS(sys_exit_group , 1)
2304 MIPS_SYS(sys_lookup_dcookie, 3)
2305 MIPS_SYS(sys_epoll_create, 1)
2306 MIPS_SYS(sys_epoll_ctl , 4)
2307 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2308 MIPS_SYS(sys_remap_file_pages, 5)
2309 MIPS_SYS(sys_set_tid_address, 1)
2310 MIPS_SYS(sys_restart_syscall, 0)
2311 MIPS_SYS(sys_fadvise64_64, 7)
2312 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2313 MIPS_SYS(sys_fstatfs64 , 2)
2314 MIPS_SYS(sys_timer_create, 3)
2315 MIPS_SYS(sys_timer_settime, 4)
2316 MIPS_SYS(sys_timer_gettime, 2)
2317 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2318 MIPS_SYS(sys_timer_delete, 1)
2319 MIPS_SYS(sys_clock_settime, 2)
2320 MIPS_SYS(sys_clock_gettime, 2)
2321 MIPS_SYS(sys_clock_getres, 2)
2322 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2323 MIPS_SYS(sys_tgkill , 3)
2324 MIPS_SYS(sys_utimes , 2)
2325 MIPS_SYS(sys_mbind , 4)
2326 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2327 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2328 MIPS_SYS(sys_mq_open , 4)
2329 MIPS_SYS(sys_mq_unlink , 1)
2330 MIPS_SYS(sys_mq_timedsend, 5)
2331 MIPS_SYS(sys_mq_timedreceive, 5)
2332 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2333 MIPS_SYS(sys_mq_getsetattr, 3)
2334 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2335 MIPS_SYS(sys_waitid , 4)
2336 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2337 MIPS_SYS(sys_add_key , 5)
2338 MIPS_SYS(sys_request_key, 4)
2339 MIPS_SYS(sys_keyctl , 5)
2340 MIPS_SYS(sys_set_thread_area, 1)
2341 MIPS_SYS(sys_inotify_init, 0)
2342 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2343 MIPS_SYS(sys_inotify_rm_watch, 2)
2344 MIPS_SYS(sys_migrate_pages, 4)
2345 MIPS_SYS(sys_openat, 4)
2346 MIPS_SYS(sys_mkdirat, 3)
2347 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2348 MIPS_SYS(sys_fchownat, 5)
2349 MIPS_SYS(sys_futimesat, 3)
2350 MIPS_SYS(sys_fstatat64, 4)
2351 MIPS_SYS(sys_unlinkat, 3)
2352 MIPS_SYS(sys_renameat, 4) /* 4295 */
2353 MIPS_SYS(sys_linkat, 5)
2354 MIPS_SYS(sys_symlinkat, 3)
2355 MIPS_SYS(sys_readlinkat, 4)
2356 MIPS_SYS(sys_fchmodat, 3)
2357 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2358 MIPS_SYS(sys_pselect6, 6)
2359 MIPS_SYS(sys_ppoll, 5)
2360 MIPS_SYS(sys_unshare, 1)
2361 MIPS_SYS(sys_splice, 6)
2362 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2363 MIPS_SYS(sys_tee, 4)
2364 MIPS_SYS(sys_vmsplice, 4)
2365 MIPS_SYS(sys_move_pages, 6)
2366 MIPS_SYS(sys_set_robust_list, 2)
2367 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2368 MIPS_SYS(sys_kexec_load, 4)
2369 MIPS_SYS(sys_getcpu, 3)
2370 MIPS_SYS(sys_epoll_pwait, 6)
2371 MIPS_SYS(sys_ioprio_set, 3)
2372 MIPS_SYS(sys_ioprio_get, 2)
2373 MIPS_SYS(sys_utimensat, 4)
2374 MIPS_SYS(sys_signalfd, 3)
2375 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2376 MIPS_SYS(sys_eventfd, 1)
2377 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2378 MIPS_SYS(sys_timerfd_create, 2)
2379 MIPS_SYS(sys_timerfd_gettime, 2)
2380 MIPS_SYS(sys_timerfd_settime, 4)
2381 MIPS_SYS(sys_signalfd4, 4)
2382 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2383 MIPS_SYS(sys_epoll_create1, 1)
2384 MIPS_SYS(sys_dup3, 3)
2385 MIPS_SYS(sys_pipe2, 2)
2386 MIPS_SYS(sys_inotify_init1, 1)
2387 MIPS_SYS(sys_preadv, 6) /* 4330 */
2388 MIPS_SYS(sys_pwritev, 6)
2389 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2390 MIPS_SYS(sys_perf_event_open, 5)
2391 MIPS_SYS(sys_accept4, 4)
2392 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2393 MIPS_SYS(sys_fanotify_init, 2)
2394 MIPS_SYS(sys_fanotify_mark, 6)
2395 MIPS_SYS(sys_prlimit64, 4)
2396 MIPS_SYS(sys_name_to_handle_at, 5)
2397 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2398 MIPS_SYS(sys_clock_adjtime, 2)
2399 MIPS_SYS(sys_syncfs, 1)
2400 };
2401 # undef MIPS_SYS
2402 # endif /* O32 */
2403
2404 static int do_store_exclusive(CPUMIPSState *env)
2405 {
2406 target_ulong addr;
2407 target_ulong page_addr;
2408 target_ulong val;
2409 int flags;
2410 int segv = 0;
2411 int reg;
2412 int d;
2413
2414 addr = env->lladdr;
2415 page_addr = addr & TARGET_PAGE_MASK;
2416 start_exclusive();
2417 mmap_lock();
2418 flags = page_get_flags(page_addr);
2419 if ((flags & PAGE_READ) == 0) {
2420 segv = 1;
2421 } else {
2422 reg = env->llreg & 0x1f;
2423 d = (env->llreg & 0x20) != 0;
2424 if (d) {
2425 segv = get_user_s64(val, addr);
2426 } else {
2427 segv = get_user_s32(val, addr);
2428 }
2429 if (!segv) {
2430 if (val != env->llval) {
2431 env->active_tc.gpr[reg] = 0;
2432 } else {
2433 if (d) {
2434 segv = put_user_u64(env->llnewval, addr);
2435 } else {
2436 segv = put_user_u32(env->llnewval, addr);
2437 }
2438 if (!segv) {
2439 env->active_tc.gpr[reg] = 1;
2440 }
2441 }
2442 }
2443 }
2444 env->lladdr = -1;
2445 if (!segv) {
2446 env->active_tc.PC += 4;
2447 }
2448 mmap_unlock();
2449 end_exclusive();
2450 return segv;
2451 }
2452
2453 /* Break codes */
2454 enum {
2455 BRK_OVERFLOW = 6,
2456 BRK_DIVZERO = 7
2457 };
2458
2459 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2460 unsigned int code)
2461 {
2462 int ret = -1;
2463
2464 switch (code) {
2465 case BRK_OVERFLOW:
2466 case BRK_DIVZERO:
2467 info->si_signo = TARGET_SIGFPE;
2468 info->si_errno = 0;
2469 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2470 queue_signal(env, info->si_signo, &*info);
2471 ret = 0;
2472 break;
2473 default:
2474 info->si_signo = TARGET_SIGTRAP;
2475 info->si_errno = 0;
2476 queue_signal(env, info->si_signo, &*info);
2477 ret = 0;
2478 break;
2479 }
2480
2481 return ret;
2482 }
2483
2484 void cpu_loop(CPUMIPSState *env)
2485 {
2486 CPUState *cs = CPU(mips_env_get_cpu(env));
2487 target_siginfo_t info;
2488 int trapnr;
2489 abi_long ret;
2490 # ifdef TARGET_ABI_MIPSO32
2491 unsigned int syscall_num;
2492 # endif
2493
2494 for(;;) {
2495 cpu_exec_start(cs);
2496 trapnr = cpu_exec(cs);
2497 cpu_exec_end(cs);
2498 switch(trapnr) {
2499 case EXCP_SYSCALL:
2500 env->active_tc.PC += 4;
2501 # ifdef TARGET_ABI_MIPSO32
2502 syscall_num = env->active_tc.gpr[2] - 4000;
2503 if (syscall_num >= sizeof(mips_syscall_args)) {
2504 ret = -TARGET_ENOSYS;
2505 } else {
2506 int nb_args;
2507 abi_ulong sp_reg;
2508 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2509
2510 nb_args = mips_syscall_args[syscall_num];
2511 sp_reg = env->active_tc.gpr[29];
2512 switch (nb_args) {
2513 /* these arguments are taken from the stack */
2514 case 8:
2515 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2516 goto done_syscall;
2517 }
2518 case 7:
2519 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2520 goto done_syscall;
2521 }
2522 case 6:
2523 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2524 goto done_syscall;
2525 }
2526 case 5:
2527 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2528 goto done_syscall;
2529 }
2530 default:
2531 break;
2532 }
2533 ret = do_syscall(env, env->active_tc.gpr[2],
2534 env->active_tc.gpr[4],
2535 env->active_tc.gpr[5],
2536 env->active_tc.gpr[6],
2537 env->active_tc.gpr[7],
2538 arg5, arg6, arg7, arg8);
2539 }
2540 done_syscall:
2541 # else
2542 ret = do_syscall(env, env->active_tc.gpr[2],
2543 env->active_tc.gpr[4], env->active_tc.gpr[5],
2544 env->active_tc.gpr[6], env->active_tc.gpr[7],
2545 env->active_tc.gpr[8], env->active_tc.gpr[9],
2546 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2547 # endif /* O32 */
2548 if (ret == -TARGET_ERESTARTSYS) {
2549 env->active_tc.PC -= 4;
2550 break;
2551 }
2552 if (ret == -TARGET_QEMU_ESIGRETURN) {
2553 /* Returning from a successful sigreturn syscall.
2554 Avoid clobbering register state. */
2555 break;
2556 }
2557 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2558 env->active_tc.gpr[7] = 1; /* error flag */
2559 ret = -ret;
2560 } else {
2561 env->active_tc.gpr[7] = 0; /* error flag */
2562 }
2563 env->active_tc.gpr[2] = ret;
2564 break;
2565 case EXCP_TLBL:
2566 case EXCP_TLBS:
2567 case EXCP_AdEL:
2568 case EXCP_AdES:
2569 info.si_signo = TARGET_SIGSEGV;
2570 info.si_errno = 0;
2571 /* XXX: check env->error_code */
2572 info.si_code = TARGET_SEGV_MAPERR;
2573 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2574 queue_signal(env, info.si_signo, &info);
2575 break;
2576 case EXCP_CpU:
2577 case EXCP_RI:
2578 info.si_signo = TARGET_SIGILL;
2579 info.si_errno = 0;
2580 info.si_code = 0;
2581 queue_signal(env, info.si_signo, &info);
2582 break;
2583 case EXCP_INTERRUPT:
2584 /* just indicate that signals should be handled asap */
2585 break;
2586 case EXCP_DEBUG:
2587 {
2588 int sig;
2589
2590 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2591 if (sig)
2592 {
2593 info.si_signo = sig;
2594 info.si_errno = 0;
2595 info.si_code = TARGET_TRAP_BRKPT;
2596 queue_signal(env, info.si_signo, &info);
2597 }
2598 }
2599 break;
2600 case EXCP_SC:
2601 if (do_store_exclusive(env)) {
2602 info.si_signo = TARGET_SIGSEGV;
2603 info.si_errno = 0;
2604 info.si_code = TARGET_SEGV_MAPERR;
2605 info._sifields._sigfault._addr = env->active_tc.PC;
2606 queue_signal(env, info.si_signo, &info);
2607 }
2608 break;
2609 case EXCP_DSPDIS:
2610 info.si_signo = TARGET_SIGILL;
2611 info.si_errno = 0;
2612 info.si_code = TARGET_ILL_ILLOPC;
2613 queue_signal(env, info.si_signo, &info);
2614 break;
2615 /* The code below was inspired by the MIPS Linux kernel trap
2616 * handling code in arch/mips/kernel/traps.c.
2617 */
2618 case EXCP_BREAK:
2619 {
2620 abi_ulong trap_instr;
2621 unsigned int code;
2622
2623 if (env->hflags & MIPS_HFLAG_M16) {
2624 if (env->insn_flags & ASE_MICROMIPS) {
2625 /* microMIPS mode */
2626 ret = get_user_u16(trap_instr, env->active_tc.PC);
2627 if (ret != 0) {
2628 goto error;
2629 }
2630
2631 if ((trap_instr >> 10) == 0x11) {
2632 /* 16-bit instruction */
2633 code = trap_instr & 0xf;
2634 } else {
2635 /* 32-bit instruction */
2636 abi_ulong instr_lo;
2637
2638 ret = get_user_u16(instr_lo,
2639 env->active_tc.PC + 2);
2640 if (ret != 0) {
2641 goto error;
2642 }
2643 trap_instr = (trap_instr << 16) | instr_lo;
2644 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2645 /* Unfortunately, microMIPS also suffers from
2646 the old assembler bug... */
2647 if (code >= (1 << 10)) {
2648 code >>= 10;
2649 }
2650 }
2651 } else {
2652 /* MIPS16e mode */
2653 ret = get_user_u16(trap_instr, env->active_tc.PC);
2654 if (ret != 0) {
2655 goto error;
2656 }
2657 code = (trap_instr >> 6) & 0x3f;
2658 }
2659 } else {
2660 ret = get_user_u32(trap_instr, env->active_tc.PC);
2661 if (ret != 0) {
2662 goto error;
2663 }
2664
2665 /* As described in the original Linux kernel code, the
2666 * below checks on 'code' are to work around an old
2667 * assembly bug.
2668 */
2669 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2670 if (code >= (1 << 10)) {
2671 code >>= 10;
2672 }
2673 }
2674
2675 if (do_break(env, &info, code) != 0) {
2676 goto error;
2677 }
2678 }
2679 break;
2680 case EXCP_TRAP:
2681 {
2682 abi_ulong trap_instr;
2683 unsigned int code = 0;
2684
2685 if (env->hflags & MIPS_HFLAG_M16) {
2686 /* microMIPS mode */
2687 abi_ulong instr[2];
2688
2689 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2690 get_user_u16(instr[1], env->active_tc.PC + 2);
2691
2692 trap_instr = (instr[0] << 16) | instr[1];
2693 } else {
2694 ret = get_user_u32(trap_instr, env->active_tc.PC);
2695 }
2696
2697 if (ret != 0) {
2698 goto error;
2699 }
2700
2701 /* The immediate versions don't provide a code. */
2702 if (!(trap_instr & 0xFC000000)) {
2703 if (env->hflags & MIPS_HFLAG_M16) {
2704 /* microMIPS mode */
2705 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2706 } else {
2707 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2708 }
2709 }
2710
2711 if (do_break(env, &info, code) != 0) {
2712 goto error;
2713 }
2714 }
2715 break;
2716 default:
2717 error:
2718 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2719 abort();
2720 }
2721 process_pending_signals(env);
2722 }
2723 }
2724 #endif
2725
2726 #ifdef TARGET_OPENRISC
2727
2728 void cpu_loop(CPUOpenRISCState *env)
2729 {
2730 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2731 int trapnr, gdbsig;
2732 abi_long ret;
2733
2734 for (;;) {
2735 cpu_exec_start(cs);
2736 trapnr = cpu_exec(cs);
2737 cpu_exec_end(cs);
2738 gdbsig = 0;
2739
2740 switch (trapnr) {
2741 case EXCP_RESET:
2742 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2743 exit(EXIT_FAILURE);
2744 break;
2745 case EXCP_BUSERR:
2746 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2747 gdbsig = TARGET_SIGBUS;
2748 break;
2749 case EXCP_DPF:
2750 case EXCP_IPF:
2751 cpu_dump_state(cs, stderr, fprintf, 0);
2752 gdbsig = TARGET_SIGSEGV;
2753 break;
2754 case EXCP_TICK:
2755 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2756 break;
2757 case EXCP_ALIGN:
2758 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2759 gdbsig = TARGET_SIGBUS;
2760 break;
2761 case EXCP_ILLEGAL:
2762 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2763 gdbsig = TARGET_SIGILL;
2764 break;
2765 case EXCP_INT:
2766 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2767 break;
2768 case EXCP_DTLBMISS:
2769 case EXCP_ITLBMISS:
2770 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2771 break;
2772 case EXCP_RANGE:
2773 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2774 gdbsig = TARGET_SIGSEGV;
2775 break;
2776 case EXCP_SYSCALL:
2777 env->pc += 4; /* 0xc00; */
2778 ret = do_syscall(env,
2779 env->gpr[11], /* return value */
2780 env->gpr[3], /* r3 - r7 are params */
2781 env->gpr[4],
2782 env->gpr[5],
2783 env->gpr[6],
2784 env->gpr[7],
2785 env->gpr[8], 0, 0);
2786 if (ret == -TARGET_ERESTARTSYS) {
2787 env->pc -= 4;
2788 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2789 env->gpr[11] = ret;
2790 }
2791 break;
2792 case EXCP_FPE:
2793 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2794 break;
2795 case EXCP_TRAP:
2796 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2797 gdbsig = TARGET_SIGTRAP;
2798 break;
2799 case EXCP_NR:
2800 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2801 break;
2802 default:
2803 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2804 trapnr);
2805 gdbsig = TARGET_SIGILL;
2806 break;
2807 }
2808 if (gdbsig) {
2809 gdb_handlesig(cs, gdbsig);
2810 if (gdbsig != TARGET_SIGTRAP) {
2811 exit(EXIT_FAILURE);
2812 }
2813 }
2814
2815 process_pending_signals(env);
2816 }
2817 }
2818
2819 #endif /* TARGET_OPENRISC */
2820
2821 #ifdef TARGET_SH4
2822 void cpu_loop(CPUSH4State *env)
2823 {
2824 CPUState *cs = CPU(sh_env_get_cpu(env));
2825 int trapnr, ret;
2826 target_siginfo_t info;
2827
2828 while (1) {
2829 cpu_exec_start(cs);
2830 trapnr = cpu_exec(cs);
2831 cpu_exec_end(cs);
2832
2833 switch (trapnr) {
2834 case 0x160:
2835 env->pc += 2;
2836 ret = do_syscall(env,
2837 env->gregs[3],
2838 env->gregs[4],
2839 env->gregs[5],
2840 env->gregs[6],
2841 env->gregs[7],
2842 env->gregs[0],
2843 env->gregs[1],
2844 0, 0);
2845 if (ret == -TARGET_ERESTARTSYS) {
2846 env->pc -= 2;
2847 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2848 env->gregs[0] = ret;
2849 }
2850 break;
2851 case EXCP_INTERRUPT:
2852 /* just indicate that signals should be handled asap */
2853 break;
2854 case EXCP_DEBUG:
2855 {
2856 int sig;
2857
2858 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2859 if (sig)
2860 {
2861 info.si_signo = sig;
2862 info.si_errno = 0;
2863 info.si_code = TARGET_TRAP_BRKPT;
2864 queue_signal(env, info.si_signo, &info);
2865 }
2866 }
2867 break;
2868 case 0xa0:
2869 case 0xc0:
2870 info.si_signo = TARGET_SIGSEGV;
2871 info.si_errno = 0;
2872 info.si_code = TARGET_SEGV_MAPERR;
2873 info._sifields._sigfault._addr = env->tea;
2874 queue_signal(env, info.si_signo, &info);
2875 break;
2876
2877 default:
2878 printf ("Unhandled trap: 0x%x\n", trapnr);
2879 cpu_dump_state(cs, stderr, fprintf, 0);
2880 exit(EXIT_FAILURE);
2881 }
2882 process_pending_signals (env);
2883 }
2884 }
2885 #endif
2886
2887 #ifdef TARGET_CRIS
2888 void cpu_loop(CPUCRISState *env)
2889 {
2890 CPUState *cs = CPU(cris_env_get_cpu(env));
2891 int trapnr, ret;
2892 target_siginfo_t info;
2893
2894 while (1) {
2895 cpu_exec_start(cs);
2896 trapnr = cpu_exec(cs);
2897 cpu_exec_end(cs);
2898 switch (trapnr) {
2899 case 0xaa:
2900 {
2901 info.si_signo = TARGET_SIGSEGV;
2902 info.si_errno = 0;
2903 /* XXX: check env->error_code */
2904 info.si_code = TARGET_SEGV_MAPERR;
2905 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2906 queue_signal(env, info.si_signo, &info);
2907 }
2908 break;
2909 case EXCP_INTERRUPT:
2910 /* just indicate that signals should be handled asap */
2911 break;
2912 case EXCP_BREAK:
2913 ret = do_syscall(env,
2914 env->regs[9],
2915 env->regs[10],
2916 env->regs[11],
2917 env->regs[12],
2918 env->regs[13],
2919 env->pregs[7],
2920 env->pregs[11],
2921 0, 0);
2922 if (ret == -TARGET_ERESTARTSYS) {
2923 env->pc -= 2;
2924 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2925 env->regs[10] = ret;
2926 }
2927 break;
2928 case EXCP_DEBUG:
2929 {
2930 int sig;
2931
2932 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2933 if (sig)
2934 {
2935 info.si_signo = sig;
2936 info.si_errno = 0;
2937 info.si_code = TARGET_TRAP_BRKPT;
2938 queue_signal(env, info.si_signo, &info);
2939 }
2940 }
2941 break;
2942 default:
2943 printf ("Unhandled trap: 0x%x\n", trapnr);
2944 cpu_dump_state(cs, stderr, fprintf, 0);
2945 exit(EXIT_FAILURE);
2946 }
2947 process_pending_signals (env);
2948 }
2949 }
2950 #endif
2951
2952 #ifdef TARGET_MICROBLAZE
2953 void cpu_loop(CPUMBState *env)
2954 {
2955 CPUState *cs = CPU(mb_env_get_cpu(env));
2956 int trapnr, ret;
2957 target_siginfo_t info;
2958
2959 while (1) {
2960 cpu_exec_start(cs);
2961 trapnr = cpu_exec(cs);
2962 cpu_exec_end(cs);
2963 switch (trapnr) {
2964 case 0xaa:
2965 {
2966 info.si_signo = TARGET_SIGSEGV;
2967 info.si_errno = 0;
2968 /* XXX: check env->error_code */
2969 info.si_code = TARGET_SEGV_MAPERR;
2970 info._sifields._sigfault._addr = 0;
2971 queue_signal(env, info.si_signo, &info);
2972 }
2973 break;
2974 case EXCP_INTERRUPT:
2975 /* just indicate that signals should be handled asap */
2976 break;
2977 case EXCP_BREAK:
2978 /* Return address is 4 bytes after the call. */
2979 env->regs[14] += 4;
2980 env->sregs[SR_PC] = env->regs[14];
2981 ret = do_syscall(env,
2982 env->regs[12],
2983 env->regs[5],
2984 env->regs[6],
2985 env->regs[7],
2986 env->regs[8],
2987 env->regs[9],
2988 env->regs[10],
2989 0, 0);
2990 if (ret == -TARGET_ERESTARTSYS) {
2991 /* Wind back to before the syscall. */
2992 env->sregs[SR_PC] -= 4;
2993 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2994 env->regs[3] = ret;
2995 }
2996 /* All syscall exits result in guest r14 being equal to the
2997 * PC we return to, because the kernel syscall exit "rtbd" does
2998 * this. (This is true even for sigreturn(); note that r14 is
2999 * not a userspace-usable register, as the kernel may clobber it
3000 * at any point.)
3001 */
3002 env->regs[14] = env->sregs[SR_PC];
3003 break;
3004 case EXCP_HW_EXCP:
3005 env->regs[17] = env->sregs[SR_PC] + 4;
3006 if (env->iflags & D_FLAG) {
3007 env->sregs[SR_ESR] |= 1 << 12;
3008 env->sregs[SR_PC] -= 4;
3009 /* FIXME: if branch was immed, replay the imm as well. */
3010 }
3011
3012 env->iflags &= ~(IMM_FLAG | D_FLAG);
3013
3014 switch (env->sregs[SR_ESR] & 31) {
3015 case ESR_EC_DIVZERO:
3016 info.si_signo = TARGET_SIGFPE;
3017 info.si_errno = 0;
3018 info.si_code = TARGET_FPE_FLTDIV;
3019 info._sifields._sigfault._addr = 0;
3020 queue_signal(env, info.si_signo, &info);
3021 break;
3022 case ESR_EC_FPU:
3023 info.si_signo = TARGET_SIGFPE;
3024 info.si_errno = 0;
3025 if (env->sregs[SR_FSR] & FSR_IO) {
3026 info.si_code = TARGET_FPE_FLTINV;
3027 }
3028 if (env->sregs[SR_FSR] & FSR_DZ) {
3029 info.si_code = TARGET_FPE_FLTDIV;
3030 }
3031 info._sifields._sigfault._addr = 0;
3032 queue_signal(env, info.si_signo, &info);
3033 break;
3034 default:
3035 printf ("Unhandled hw-exception: 0x%x\n",
3036 env->sregs[SR_ESR] & ESR_EC_MASK);
3037 cpu_dump_state(cs, stderr, fprintf, 0);
3038 exit(EXIT_FAILURE);
3039 break;
3040 }
3041 break;
3042 case EXCP_DEBUG:
3043 {
3044 int sig;
3045
3046 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3047 if (sig)
3048 {
3049 info.si_signo = sig;
3050 info.si_errno = 0;
3051 info.si_code = TARGET_TRAP_BRKPT;
3052 queue_signal(env, info.si_signo, &info);
3053 }
3054 }
3055 break;
3056 default:
3057 printf ("Unhandled trap: 0x%x\n", trapnr);
3058 cpu_dump_state(cs, stderr, fprintf, 0);
3059 exit(EXIT_FAILURE);
3060 }
3061 process_pending_signals (env);
3062 }
3063 }
3064 #endif
3065
3066 #ifdef TARGET_M68K
3067
3068 void cpu_loop(CPUM68KState *env)
3069 {
3070 CPUState *cs = CPU(m68k_env_get_cpu(env));
3071 int trapnr;
3072 unsigned int n;
3073 target_siginfo_t info;
3074 TaskState *ts = cs->opaque;
3075
3076 for(;;) {
3077 cpu_exec_start(cs);
3078 trapnr = cpu_exec(cs);
3079 cpu_exec_end(cs);
3080 switch(trapnr) {
3081 case EXCP_ILLEGAL:
3082 {
3083 if (ts->sim_syscalls) {
3084 uint16_t nr;
3085 get_user_u16(nr, env->pc + 2);
3086 env->pc += 4;
3087 do_m68k_simcall(env, nr);
3088 } else {
3089 goto do_sigill;
3090 }
3091 }
3092 break;
3093 case EXCP_HALT_INSN:
3094 /* Semihosing syscall. */
3095 env->pc += 4;
3096 do_m68k_semihosting(env, env->dregs[0]);
3097 break;
3098 case EXCP_LINEA:
3099 case EXCP_LINEF:
3100 case EXCP_UNSUPPORTED:
3101 do_sigill:
3102 info.si_signo = TARGET_SIGILL;
3103 info.si_errno = 0;
3104 info.si_code = TARGET_ILL_ILLOPN;
3105 info._sifields._sigfault._addr = env->pc;
3106 queue_signal(env, info.si_signo, &info);
3107 break;
3108 case EXCP_TRAP0:
3109 {
3110 abi_long ret;
3111 ts->sim_syscalls = 0;
3112 n = env->dregs[0];
3113 env->pc += 2;
3114 ret = do_syscall(env,
3115 n,
3116 env->dregs[1],
3117 env->dregs[2],
3118 env->dregs[3],
3119 env->dregs[4],
3120 env->dregs[5],
3121 env->aregs[0],
3122 0, 0);
3123 if (ret == -TARGET_ERESTARTSYS) {
3124 env->pc -= 2;
3125 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3126 env->dregs[0] = ret;
3127 }
3128 }
3129 break;
3130 case EXCP_INTERRUPT:
3131 /* just indicate that signals should be handled asap */
3132 break;
3133 case EXCP_ACCESS:
3134 {
3135 info.si_signo = TARGET_SIGSEGV;
3136 info.si_errno = 0;
3137 /* XXX: check env->error_code */
3138 info.si_code = TARGET_SEGV_MAPERR;
3139 info._sifields._sigfault._addr = env->mmu.ar;
3140 queue_signal(env, info.si_signo, &info);
3141 }
3142 break;
3143 case EXCP_DEBUG:
3144 {
3145 int sig;
3146
3147 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3148 if (sig)
3149 {
3150 info.si_signo = sig;
3151 info.si_errno = 0;
3152 info.si_code = TARGET_TRAP_BRKPT;
3153 queue_signal(env, info.si_signo, &info);
3154 }
3155 }
3156 break;
3157 default:
3158 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3159 abort();
3160 }
3161 process_pending_signals(env);
3162 }
3163 }
3164 #endif /* TARGET_M68K */
3165
3166 #ifdef TARGET_ALPHA
3167 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3168 {
3169 target_ulong addr, val, tmp;
3170 target_siginfo_t info;
3171 int ret = 0;
3172
3173 addr = env->lock_addr;
3174 tmp = env->lock_st_addr;
3175 env->lock_addr = -1;
3176 env->lock_st_addr = 0;
3177
3178 start_exclusive();
3179 mmap_lock();
3180
3181 if (addr == tmp) {
3182 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3183 goto do_sigsegv;
3184 }
3185
3186 if (val == env->lock_value) {
3187 tmp = env->ir[reg];
3188 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3189 goto do_sigsegv;
3190 }
3191 ret = 1;
3192 }
3193 }
3194 env->ir[reg] = ret;
3195 env->pc += 4;
3196
3197 mmap_unlock();
3198 end_exclusive();
3199 return;
3200
3201 do_sigsegv:
3202 mmap_unlock();
3203 end_exclusive();
3204
3205 info.si_signo = TARGET_SIGSEGV;
3206 info.si_errno = 0;
3207 info.si_code = TARGET_SEGV_MAPERR;
3208 info._sifields._sigfault._addr = addr;
3209 queue_signal(env, TARGET_SIGSEGV, &info);
3210 }
3211
3212 void cpu_loop(CPUAlphaState *env)
3213 {
3214 CPUState *cs = CPU(alpha_env_get_cpu(env));
3215 int trapnr;
3216 target_siginfo_t info;
3217 abi_long sysret;
3218
3219 while (1) {
3220 cpu_exec_start(cs);
3221 trapnr = cpu_exec(cs);
3222 cpu_exec_end(cs);
3223
3224 /* All of the traps imply a transition through PALcode, which
3225 implies an REI instruction has been executed. Which means
3226 that the intr_flag should be cleared. */
3227 env->intr_flag = 0;
3228
3229 switch (trapnr) {
3230 case EXCP_RESET:
3231 fprintf(stderr, "Reset requested. Exit\n");
3232 exit(EXIT_FAILURE);
3233 break;
3234 case EXCP_MCHK:
3235 fprintf(stderr, "Machine check exception. Exit\n");
3236 exit(EXIT_FAILURE);
3237 break;
3238 case EXCP_SMP_INTERRUPT:
3239 case EXCP_CLK_INTERRUPT:
3240 case EXCP_DEV_INTERRUPT:
3241 fprintf(stderr, "External interrupt. Exit\n");
3242 exit(EXIT_FAILURE);
3243 break;
3244 case EXCP_MMFAULT:
3245 env->lock_addr = -1;
3246 info.si_signo = TARGET_SIGSEGV;
3247 info.si_errno = 0;
3248 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3249 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3250 info._sifields._sigfault._addr = env->trap_arg0;
3251 queue_signal(env, info.si_signo, &info);
3252 break;
3253 case EXCP_UNALIGN:
3254 env->lock_addr = -1;
3255 info.si_signo = TARGET_SIGBUS;
3256 info.si_errno = 0;
3257 info.si_code = TARGET_BUS_ADRALN;
3258 info._sifields._sigfault._addr = env->trap_arg0;
3259 queue_signal(env, info.si_signo, &info);
3260 break;
3261 case EXCP_OPCDEC:
3262 do_sigill:
3263 env->lock_addr = -1;
3264 info.si_signo = TARGET_SIGILL;
3265 info.si_errno = 0;
3266 info.si_code = TARGET_ILL_ILLOPC;
3267 info._sifields._sigfault._addr = env->pc;
3268 queue_signal(env, info.si_signo, &info);
3269 break;
3270 case EXCP_ARITH:
3271 env->lock_addr = -1;
3272 info.si_signo = TARGET_SIGFPE;
3273 info.si_errno = 0;
3274 info.si_code = TARGET_FPE_FLTINV;
3275 info._sifields._sigfault._addr = env->pc;
3276 queue_signal(env, info.si_signo, &info);
3277 break;
3278 case EXCP_FEN:
3279 /* No-op. Linux simply re-enables the FPU. */
3280 break;
3281 case EXCP_CALL_PAL:
3282 env->lock_addr = -1;
3283 switch (env->error_code) {
3284 case 0x80:
3285 /* BPT */
3286 info.si_signo = TARGET_SIGTRAP;
3287 info.si_errno = 0;
3288 info.si_code = TARGET_TRAP_BRKPT;
3289 info._sifields._sigfault._addr = env->pc;
3290 queue_signal(env, info.si_signo, &info);
3291 break;
3292 case 0x81:
3293 /* BUGCHK */
3294 info.si_signo = TARGET_SIGTRAP;
3295 info.si_errno = 0;
3296 info.si_code = 0;
3297 info._sifields._sigfault._addr = env->pc;
3298 queue_signal(env, info.si_signo, &info);
3299 break;
3300 case 0x83:
3301 /* CALLSYS */
3302 trapnr = env->ir[IR_V0];
3303 sysret = do_syscall(env, trapnr,
3304 env->ir[IR_A0], env->ir[IR_A1],
3305 env->ir[IR_A2], env->ir[IR_A3],
3306 env->ir[IR_A4], env->ir[IR_A5],
3307 0, 0);
3308 if (sysret == -TARGET_ERESTARTSYS) {
3309 env->pc -= 4;
3310 break;
3311 }
3312 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3313 break;
3314 }
3315 /* Syscall writes 0 to V0 to bypass error check, similar
3316 to how this is handled internal to Linux kernel.
3317 (Ab)use trapnr temporarily as boolean indicating error. */
3318 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3319 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3320 env->ir[IR_A3] = trapnr;
3321 break;
3322 case 0x86:
3323 /* IMB */
3324 /* ??? We can probably elide the code using page_unprotect
3325 that is checking for self-modifying code. Instead we
3326 could simply call tb_flush here. Until we work out the
3327 changes required to turn off the extra write protection,
3328 this can be a no-op. */
3329 break;
3330 case 0x9E:
3331 /* RDUNIQUE */
3332 /* Handled in the translator for usermode. */
3333 abort();
3334 case 0x9F:
3335 /* WRUNIQUE */
3336 /* Handled in the translator for usermode. */
3337 abort();
3338 case 0xAA:
3339 /* GENTRAP */
3340 info.si_signo = TARGET_SIGFPE;
3341 switch (env->ir[IR_A0]) {
3342 case TARGET_GEN_INTOVF:
3343 info.si_code = TARGET_FPE_INTOVF;
3344 break;
3345 case TARGET_GEN_INTDIV:
3346 info.si_code = TARGET_FPE_INTDIV;
3347 break;
3348 case TARGET_GEN_FLTOVF:
3349 info.si_code = TARGET_FPE_FLTOVF;
3350 break;
3351 case TARGET_GEN_FLTUND:
3352 info.si_code = TARGET_FPE_FLTUND;
3353 break;
3354 case TARGET_GEN_FLTINV:
3355 info.si_code = TARGET_FPE_FLTINV;
3356 break;
3357 case TARGET_GEN_FLTINE:
3358 info.si_code = TARGET_FPE_FLTRES;
3359 break;
3360 case TARGET_GEN_ROPRAND:
3361 info.si_code = 0;
3362 break;
3363 default:
3364 info.si_signo = TARGET_SIGTRAP;
3365 info.si_code = 0;
3366 break;
3367 }
3368 info.si_errno = 0;
3369 info._sifields._sigfault._addr = env->pc;
3370 queue_signal(env, info.si_signo, &info);
3371 break;
3372 default:
3373 goto do_sigill;
3374 }
3375 break;
3376 case EXCP_DEBUG:
3377 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3378 if (info.si_signo) {
3379 env->lock_addr = -1;
3380 info.si_errno = 0;
3381 info.si_code = TARGET_TRAP_BRKPT;
3382 queue_signal(env, info.si_signo, &info);
3383 }
3384 break;
3385 case EXCP_STL_C:
3386 case EXCP_STQ_C:
3387 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3388 break;
3389 case EXCP_INTERRUPT:
3390 /* Just indicate that signals should be handled asap. */
3391 break;
3392 default:
3393 printf ("Unhandled trap: 0x%x\n", trapnr);
3394 cpu_dump_state(cs, stderr, fprintf, 0);
3395 exit(EXIT_FAILURE);
3396 }
3397 process_pending_signals (env);
3398 }
3399 }
3400 #endif /* TARGET_ALPHA */
3401
3402 #ifdef TARGET_S390X
3403 void cpu_loop(CPUS390XState *env)
3404 {
3405 CPUState *cs = CPU(s390_env_get_cpu(env));
3406 int trapnr, n, sig;
3407 target_siginfo_t info;
3408 target_ulong addr;
3409 abi_long ret;
3410
3411 while (1) {
3412 cpu_exec_start(cs);
3413 trapnr = cpu_exec(cs);
3414 cpu_exec_end(cs);
3415 switch (trapnr) {
3416 case EXCP_INTERRUPT:
3417 /* Just indicate that signals should be handled asap. */
3418 break;
3419
3420 case EXCP_SVC:
3421 n = env->int_svc_code;
3422 if (!n) {
3423 /* syscalls > 255 */
3424 n = env->regs[1];
3425 }
3426 env->psw.addr += env->int_svc_ilen;
3427 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3428 env->regs[4], env->regs[5],
3429 env->regs[6], env->regs[7], 0, 0);
3430 if (ret == -TARGET_ERESTARTSYS) {
3431 env->psw.addr -= env->int_svc_ilen;
3432 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3433 env->regs[2] = ret;
3434 }
3435 break;
3436
3437 case EXCP_DEBUG:
3438 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3439 if (sig) {
3440 n = TARGET_TRAP_BRKPT;
3441 goto do_signal_pc;
3442 }
3443 break;
3444 case EXCP_PGM:
3445 n = env->int_pgm_code;
3446 switch (n) {
3447 case PGM_OPERATION:
3448 case PGM_PRIVILEGED:
3449 sig = TARGET_SIGILL;
3450 n = TARGET_ILL_ILLOPC;
3451 goto do_signal_pc;
3452 case PGM_PROTECTION:
3453 case PGM_ADDRESSING:
3454 sig = TARGET_SIGSEGV;
3455 /* XXX: check env->error_code */
3456 n = TARGET_SEGV_MAPERR;
3457 addr = env->__excp_addr;
3458 goto do_signal;
3459 case PGM_EXECUTE:
3460 case PGM_SPECIFICATION:
3461 case PGM_SPECIAL_OP:
3462 case PGM_OPERAND:
3463 do_sigill_opn:
3464 sig = TARGET_SIGILL;
3465 n = TARGET_ILL_ILLOPN;
3466 goto do_signal_pc;
3467
3468 case PGM_FIXPT_OVERFLOW:
3469 sig = TARGET_SIGFPE;
3470 n = TARGET_FPE_INTOVF;
3471 goto do_signal_pc;
3472 case PGM_FIXPT_DIVIDE:
3473 sig = TARGET_SIGFPE;
3474 n = TARGET_FPE_INTDIV;
3475 goto do_signal_pc;
3476
3477 case PGM_DATA:
3478 n = (env->fpc >> 8) & 0xff;
3479 if (n == 0xff) {
3480 /* compare-and-trap */
3481 goto do_sigill_opn;
3482 } else {
3483 /* An IEEE exception, simulated or otherwise. */
3484 if (n & 0x80) {
3485 n = TARGET_FPE_FLTINV;
3486 } else if (n & 0x40) {
3487 n = TARGET_FPE_FLTDIV;
3488 } else if (n & 0x20) {
3489 n = TARGET_FPE_FLTOVF;
3490 } else if (n & 0x10) {
3491 n = TARGET_FPE_FLTUND;
3492 } else if (n & 0x08) {
3493 n = TARGET_FPE_FLTRES;
3494 } else {
3495 /* ??? Quantum exception; BFP, DFP error. */
3496 goto do_sigill_opn;
3497 }
3498 sig = TARGET_SIGFPE;
3499 goto do_signal_pc;
3500 }
3501
3502 default:
3503 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3504 cpu_dump_state(cs, stderr, fprintf, 0);
3505 exit(EXIT_FAILURE);
3506 }
3507 break;
3508
3509 do_signal_pc:
3510 addr = env->psw.addr;
3511 do_signal:
3512 info.si_signo = sig;
3513 info.si_errno = 0;
3514 info.si_code = n;
3515 info._sifields._sigfault._addr = addr;
3516 queue_signal(env, info.si_signo, &info);
3517 break;
3518
3519 default:
3520 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3521 cpu_dump_state(cs, stderr, fprintf, 0);
3522 exit(EXIT_FAILURE);
3523 }
3524 process_pending_signals (env);
3525 }
3526 }
3527
3528 #endif /* TARGET_S390X */
3529
3530 #ifdef TARGET_TILEGX
3531
3532 static void gen_sigill_reg(CPUTLGState *env)
3533 {
3534 target_siginfo_t info;
3535
3536 info.si_signo = TARGET_SIGILL;
3537 info.si_errno = 0;
3538 info.si_code = TARGET_ILL_PRVREG;
3539 info._sifields._sigfault._addr = env->pc;
3540 queue_signal(env, info.si_signo, &info);
3541 }
3542
3543 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3544 {
3545 target_siginfo_t info;
3546
3547 info.si_signo = signo;
3548 info.si_errno = 0;
3549 info._sifields._sigfault._addr = env->pc;
3550
3551 if (signo == TARGET_SIGSEGV) {
3552 /* The passed in sigcode is a dummy; check for a page mapping
3553 and pass either MAPERR or ACCERR. */
3554 target_ulong addr = env->excaddr;
3555 info._sifields._sigfault._addr = addr;
3556 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3557 sigcode = TARGET_SEGV_MAPERR;
3558 } else {
3559 sigcode = TARGET_SEGV_ACCERR;
3560 }
3561 }
3562 info.si_code = sigcode;
3563
3564 queue_signal(env, info.si_signo, &info);
3565 }
3566
3567 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3568 {
3569 env->excaddr = addr;
3570 do_signal(env, TARGET_SIGSEGV, 0);
3571 }
3572
3573 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3574 {
3575 if (unlikely(reg >= TILEGX_R_COUNT)) {
3576 switch (reg) {
3577 case TILEGX_R_SN:
3578 case TILEGX_R_ZERO:
3579 return;
3580 case TILEGX_R_IDN0:
3581 case TILEGX_R_IDN1:
3582 case TILEGX_R_UDN0:
3583 case TILEGX_R_UDN1:
3584 case TILEGX_R_UDN2:
3585 case TILEGX_R_UDN3:
3586 gen_sigill_reg(env);
3587 return;
3588 default:
3589 g_assert_not_reached();
3590 }
3591 }
3592 env->regs[reg] = val;
3593 }
3594
3595 /*
3596 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3597 * memory at the address held in the first source register. If the values are
3598 * not equal, then no memory operation is performed. If the values are equal,
3599 * the 8-byte quantity from the second source register is written into memory
3600 * at the address held in the first source register. In either case, the result
3601 * of the instruction is the value read from memory. The compare and write to
3602 * memory are atomic and thus can be used for synchronization purposes. This
3603 * instruction only operates for addresses aligned to a 8-byte boundary.
3604 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3605 *
3606 * Functional Description (64-bit)
3607 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3608 * rf[Dest] = memVal;
3609 * if (memVal == SPR[CmpValueSPR])
3610 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3611 *
3612 * Functional Description (32-bit)
3613 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3614 * rf[Dest] = memVal;
3615 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3616 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3617 *
3618 *
3619 * This function also processes exch and exch4 which need not process SPR.
3620 */
3621 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3622 {
3623 target_ulong addr;
3624 target_long val, sprval;
3625
3626 start_exclusive();
3627
3628 addr = env->atomic_srca;
3629 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3630 goto sigsegv_maperr;
3631 }
3632
3633 if (cmp) {
3634 if (quad) {
3635 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3636 } else {
3637 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3638 }
3639 }
3640
3641 if (!cmp || val == sprval) {
3642 target_long valb = env->atomic_srcb;
3643 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3644 goto sigsegv_maperr;
3645 }
3646 }
3647
3648 set_regval(env, env->atomic_dstr, val);
3649 end_exclusive();
3650 return;
3651
3652 sigsegv_maperr:
3653 end_exclusive();
3654 gen_sigsegv_maperr(env, addr);
3655 }
3656
3657 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3658 {
3659 int8_t write = 1;
3660 target_ulong addr;
3661 target_long val, valb;
3662
3663 start_exclusive();
3664
3665 addr = env->atomic_srca;
3666 valb = env->atomic_srcb;
3667 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3668 goto sigsegv_maperr;
3669 }
3670
3671 switch (trapnr) {
3672 case TILEGX_EXCP_OPCODE_FETCHADD:
3673 case TILEGX_EXCP_OPCODE_FETCHADD4:
3674 valb += val;
3675 break;
3676 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3677 valb += val;
3678 if (valb < 0) {
3679 write = 0;
3680 }
3681 break;
3682 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3683 valb += val;
3684 if ((int32_t)valb < 0) {
3685 write = 0;
3686 }
3687 break;
3688 case TILEGX_EXCP_OPCODE_FETCHAND:
3689 case TILEGX_EXCP_OPCODE_FETCHAND4:
3690 valb &= val;
3691 break;
3692 case TILEGX_EXCP_OPCODE_FETCHOR:
3693 case TILEGX_EXCP_OPCODE_FETCHOR4:
3694 valb |= val;
3695 break;
3696 default:
3697 g_assert_not_reached();
3698 }
3699
3700 if (write) {
3701 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3702 goto sigsegv_maperr;
3703 }
3704 }
3705
3706 set_regval(env, env->atomic_dstr, val);
3707 end_exclusive();
3708 return;
3709
3710 sigsegv_maperr:
3711 end_exclusive();
3712 gen_sigsegv_maperr(env, addr);
3713 }
3714
3715 void cpu_loop(CPUTLGState *env)
3716 {
3717 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3718 int trapnr;
3719
3720 while (1) {
3721 cpu_exec_start(cs);
3722 trapnr = cpu_exec(cs);
3723 cpu_exec_end(cs);
3724 switch (trapnr) {
3725 case TILEGX_EXCP_SYSCALL:
3726 {
3727 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3728 env->regs[0], env->regs[1],
3729 env->regs[2], env->regs[3],
3730 env->regs[4], env->regs[5],
3731 env->regs[6], env->regs[7]);
3732 if (ret == -TARGET_ERESTARTSYS) {
3733 env->pc -= 8;
3734 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3735 env->regs[TILEGX_R_RE] = ret;
3736 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3737 }
3738 break;
3739 }
3740 case TILEGX_EXCP_OPCODE_EXCH:
3741 do_exch(env, true, false);
3742 break;
3743 case TILEGX_EXCP_OPCODE_EXCH4:
3744 do_exch(env, false, false);
3745 break;
3746 case TILEGX_EXCP_OPCODE_CMPEXCH:
3747 do_exch(env, true, true);
3748 break;
3749 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3750 do_exch(env, false, true);
3751 break;
3752 case TILEGX_EXCP_OPCODE_FETCHADD:
3753 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3754 case TILEGX_EXCP_OPCODE_FETCHAND:
3755 case TILEGX_EXCP_OPCODE_FETCHOR:
3756 do_fetch(env, trapnr, true);
3757 break;
3758 case TILEGX_EXCP_OPCODE_FETCHADD4:
3759 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3760 case TILEGX_EXCP_OPCODE_FETCHAND4:
3761 case TILEGX_EXCP_OPCODE_FETCHOR4:
3762 do_fetch(env, trapnr, false);
3763 break;
3764 case TILEGX_EXCP_SIGNAL:
3765 do_signal(env, env->signo, env->sigcode);
3766 break;
3767 case TILEGX_EXCP_REG_IDN_ACCESS:
3768 case TILEGX_EXCP_REG_UDN_ACCESS:
3769 gen_sigill_reg(env);
3770 break;
3771 default:
3772 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3773 g_assert_not_reached();
3774 }
3775 process_pending_signals(env);
3776 }
3777 }
3778
3779 #endif
3780
3781 THREAD CPUState *thread_cpu;
3782
3783 void task_settid(TaskState *ts)
3784 {
3785 if (ts->ts_tid == 0) {
3786 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3787 }
3788 }
3789
3790 void stop_all_tasks(void)
3791 {
3792 /*
3793 * We trust that when using NPTL, start_exclusive()
3794 * handles thread stopping correctly.
3795 */
3796 start_exclusive();
3797 }
3798
3799 /* Assumes contents are already zeroed. */
3800 void init_task_state(TaskState *ts)
3801 {
3802 ts->used = 1;
3803 }
3804
3805 CPUArchState *cpu_copy(CPUArchState *env)
3806 {
3807 CPUState *cpu = ENV_GET_CPU(env);
3808 CPUState *new_cpu = cpu_init(cpu_model);
3809 CPUArchState *new_env = new_cpu->env_ptr;
3810 CPUBreakpoint *bp;
3811 CPUWatchpoint *wp;
3812
3813 /* Reset non arch specific state */
3814 cpu_reset(new_cpu);
3815
3816 memcpy(new_env, env, sizeof(CPUArchState));
3817
3818 /* Clone all break/watchpoints.
3819 Note: Once we support ptrace with hw-debug register access, make sure
3820 BP_CPU break/watchpoints are handled correctly on clone. */
3821 QTAILQ_INIT(&new_cpu->breakpoints);
3822 QTAILQ_INIT(&new_cpu->watchpoints);
3823 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3824 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3825 }
3826 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3827 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3828 }
3829
3830 return new_env;
3831 }
3832
3833 static void handle_arg_help(const char *arg)
3834 {
3835 usage(EXIT_SUCCESS);
3836 }
3837
3838 static void handle_arg_log(const char *arg)
3839 {
3840 int mask;
3841
3842 mask = qemu_str_to_log_mask(arg);
3843 if (!mask) {
3844 qemu_print_log_usage(stdout);
3845 exit(EXIT_FAILURE);
3846 }
3847 qemu_log_needs_buffers();
3848 qemu_set_log(mask);
3849 }
3850
3851 static void handle_arg_log_filename(const char *arg)
3852 {
3853 qemu_set_log_filename(arg, &error_fatal);
3854 }
3855
3856 static void handle_arg_set_env(const char *arg)
3857 {
3858 char *r, *p, *token;
3859 r = p = strdup(arg);
3860 while ((token = strsep(&p, ",")) != NULL) {
3861 if (envlist_setenv(envlist, token) != 0) {
3862 usage(EXIT_FAILURE);
3863 }
3864 }
3865 free(r);
3866 }
3867
3868 static void handle_arg_unset_env(const char *arg)
3869 {
3870 char *r, *p, *token;
3871 r = p = strdup(arg);
3872 while ((token = strsep(&p, ",")) != NULL) {
3873 if (envlist_unsetenv(envlist, token) != 0) {
3874 usage(EXIT_FAILURE);
3875 }
3876 }
3877 free(r);
3878 }
3879
3880 static void handle_arg_argv0(const char *arg)
3881 {
3882 argv0 = strdup(arg);
3883 }
3884
3885 static void handle_arg_stack_size(const char *arg)
3886 {
3887 char *p;
3888 guest_stack_size = strtoul(arg, &p, 0);
3889 if (guest_stack_size == 0) {
3890 usage(EXIT_FAILURE);
3891 }
3892
3893 if (*p == 'M') {
3894 guest_stack_size *= 1024 * 1024;
3895 } else if (*p == 'k' || *p == 'K') {
3896 guest_stack_size *= 1024;
3897 }
3898 }
3899
3900 static void handle_arg_ld_prefix(const char *arg)
3901 {
3902 interp_prefix = strdup(arg);
3903 }
3904
3905 static void handle_arg_pagesize(const char *arg)
3906 {
3907 qemu_host_page_size = atoi(arg);
3908 if (qemu_host_page_size == 0 ||
3909 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3910 fprintf(stderr, "page size must be a power of two\n");
3911 exit(EXIT_FAILURE);
3912 }
3913 }
3914
3915 static void handle_arg_randseed(const char *arg)
3916 {
3917 unsigned long long seed;
3918
3919 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3920 fprintf(stderr, "Invalid seed number: %s\n", arg);
3921 exit(EXIT_FAILURE);
3922 }
3923 srand(seed);
3924 }
3925
3926 static void handle_arg_gdb(const char *arg)
3927 {
3928 gdbstub_port = atoi(arg);
3929 }
3930
3931 static void handle_arg_uname(const char *arg)
3932 {
3933 qemu_uname_release = strdup(arg);
3934 }
3935
3936 static void handle_arg_cpu(const char *arg)
3937 {
3938 cpu_model = strdup(arg);
3939 if (cpu_model == NULL || is_help_option(cpu_model)) {
3940 /* XXX: implement xxx_cpu_list for targets that still miss it */
3941 #if defined(cpu_list)
3942 cpu_list(stdout, &fprintf);
3943 #endif
3944 exit(EXIT_FAILURE);
3945 }
3946 }
3947
3948 static void handle_arg_guest_base(const char *arg)
3949 {
3950 guest_base = strtol(arg, NULL, 0);
3951 have_guest_base = 1;
3952 }
3953
3954 static void handle_arg_reserved_va(const char *arg)
3955 {
3956 char *p;
3957 int shift = 0;
3958 reserved_va = strtoul(arg, &p, 0);
3959 switch (*p) {
3960 case 'k':
3961 case 'K':
3962 shift = 10;
3963 break;
3964 case 'M':
3965 shift = 20;
3966 break;
3967 case 'G':
3968 shift = 30;
3969 break;
3970 }
3971 if (shift) {
3972 unsigned long unshifted = reserved_va;
3973 p++;
3974 reserved_va <<= shift;
3975 if (((reserved_va >> shift) != unshifted)
3976 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3977 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3978 #endif
3979 ) {
3980 fprintf(stderr, "Reserved virtual address too big\n");
3981 exit(EXIT_FAILURE);
3982 }
3983 }
3984 if (*p) {
3985 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3986 exit(EXIT_FAILURE);
3987 }
3988 }
3989
3990 static void handle_arg_singlestep(const char *arg)
3991 {
3992 singlestep = 1;
3993 }
3994
3995 static void handle_arg_strace(const char *arg)
3996 {
3997 do_strace = 1;
3998 }
3999
4000 static void handle_arg_version(const char *arg)
4001 {
4002 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
4003 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4004 exit(EXIT_SUCCESS);
4005 }
4006
4007 static char *trace_file;
4008 static void handle_arg_trace(const char *arg)
4009 {
4010 g_free(trace_file);
4011 trace_file = trace_opt_parse(arg);
4012 }
4013
4014 struct qemu_argument {
4015 const char *argv;
4016 const char *env;
4017 bool has_arg;
4018 void (*handle_opt)(const char *arg);
4019 const char *example;
4020 const char *help;
4021 };
4022
4023 static const struct qemu_argument arg_table[] = {
4024 {"h", "", false, handle_arg_help,
4025 "", "print this help"},
4026 {"help", "", false, handle_arg_help,
4027 "", ""},
4028 {"g", "QEMU_GDB", true, handle_arg_gdb,
4029 "port", "wait gdb connection to 'port'"},
4030 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4031 "path", "set the elf interpreter prefix to 'path'"},
4032 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4033 "size", "set the stack size to 'size' bytes"},
4034 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4035 "model", "select CPU (-cpu help for list)"},
4036 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4037 "var=value", "sets targets environment variable (see below)"},
4038 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4039 "var", "unsets targets environment variable (see below)"},
4040 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4041 "argv0", "forces target process argv[0] to be 'argv0'"},
4042 {"r", "QEMU_UNAME", true, handle_arg_uname,
4043 "uname", "set qemu uname release string to 'uname'"},
4044 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4045 "address", "set guest_base address to 'address'"},
4046 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4047 "size", "reserve 'size' bytes for guest virtual address space"},
4048 {"d", "QEMU_LOG", true, handle_arg_log,
4049 "item[,...]", "enable logging of specified items "
4050 "(use '-d help' for a list of items)"},
4051 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4052 "logfile", "write logs to 'logfile' (default stderr)"},
4053 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4054 "pagesize", "set the host page size to 'pagesize'"},
4055 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4056 "", "run in singlestep mode"},
4057 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4058 "", "log system calls"},
4059 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4060 "", "Seed for pseudo-random number generator"},
4061 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4062 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4063 {"version", "QEMU_VERSION", false, handle_arg_version,
4064 "", "display version information and exit"},
4065 {NULL, NULL, false, NULL, NULL, NULL}
4066 };
4067
4068 static void usage(int exitcode)
4069 {
4070 const struct qemu_argument *arginfo;
4071 int maxarglen;
4072 int maxenvlen;
4073
4074 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4075 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4076 "\n"
4077 "Options and associated environment variables:\n"
4078 "\n");
4079
4080 /* Calculate column widths. We must always have at least enough space
4081 * for the column header.
4082 */
4083 maxarglen = strlen("Argument");
4084 maxenvlen = strlen("Env-variable");
4085
4086 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4087 int arglen = strlen(arginfo->argv);
4088 if (arginfo->has_arg) {
4089 arglen += strlen(arginfo->example) + 1;
4090 }
4091 if (strlen(arginfo->env) > maxenvlen) {
4092 maxenvlen = strlen(arginfo->env);
4093 }
4094 if (arglen > maxarglen) {
4095 maxarglen = arglen;
4096 }
4097 }
4098
4099 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4100 maxenvlen, "Env-variable");
4101
4102 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4103 if (arginfo->has_arg) {
4104 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4105 (int)(maxarglen - strlen(arginfo->argv) - 1),
4106 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4107 } else {
4108 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4109 maxenvlen, arginfo->env,
4110 arginfo->help);
4111 }
4112 }
4113
4114 printf("\n"
4115 "Defaults:\n"
4116 "QEMU_LD_PREFIX = %s\n"
4117 "QEMU_STACK_SIZE = %ld byte\n",
4118 interp_prefix,
4119 guest_stack_size);
4120
4121 printf("\n"
4122 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4123 "QEMU_UNSET_ENV environment variables to set and unset\n"
4124 "environment variables for the target process.\n"
4125 "It is possible to provide several variables by separating them\n"
4126 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4127 "provide the -E and -U options multiple times.\n"
4128 "The following lines are equivalent:\n"
4129 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4130 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4131 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4132 "Note that if you provide several changes to a single variable\n"
4133 "the last change will stay in effect.\n");
4134
4135 exit(exitcode);
4136 }
4137
4138 static int parse_args(int argc, char **argv)
4139 {
4140 const char *r;
4141 int optind;
4142 const struct qemu_argument *arginfo;
4143
4144 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4145 if (arginfo->env == NULL) {
4146 continue;
4147 }
4148
4149 r = getenv(arginfo->env);
4150 if (r != NULL) {
4151 arginfo->handle_opt(r);
4152 }
4153 }
4154
4155 optind = 1;
4156 for (;;) {
4157 if (optind >= argc) {
4158 break;
4159 }
4160 r = argv[optind];
4161 if (r[0] != '-') {
4162 break;
4163 }
4164 optind++;
4165 r++;
4166 if (!strcmp(r, "-")) {
4167 break;
4168 }
4169 /* Treat --foo the same as -foo. */
4170 if (r[0] == '-') {
4171 r++;
4172 }
4173
4174 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4175 if (!strcmp(r, arginfo->argv)) {
4176 if (arginfo->has_arg) {
4177 if (optind >= argc) {
4178 (void) fprintf(stderr,
4179 "qemu: missing argument for option '%s'\n", r);
4180 exit(EXIT_FAILURE);
4181 }
4182 arginfo->handle_opt(argv[optind]);
4183 optind++;
4184 } else {
4185 arginfo->handle_opt(NULL);
4186 }
4187 break;
4188 }
4189 }
4190
4191 /* no option matched the current argv */
4192 if (arginfo->handle_opt == NULL) {
4193 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4194 exit(EXIT_FAILURE);
4195 }
4196 }
4197
4198 if (optind >= argc) {
4199 (void) fprintf(stderr, "qemu: no user program specified\n");
4200 exit(EXIT_FAILURE);
4201 }
4202
4203 filename = argv[optind];
4204 exec_path = argv[optind];
4205
4206 return optind;
4207 }
4208
4209 int main(int argc, char **argv, char **envp)
4210 {
4211 struct target_pt_regs regs1, *regs = &regs1;
4212 struct image_info info1, *info = &info1;
4213 struct linux_binprm bprm;
4214 TaskState *ts;
4215 CPUArchState *env;
4216 CPUState *cpu;
4217 int optind;
4218 char **target_environ, **wrk;
4219 char **target_argv;
4220 int target_argc;
4221 int i;
4222 int ret;
4223 int execfd;
4224
4225 module_call_init(MODULE_INIT_QOM);
4226
4227 if ((envlist = envlist_create()) == NULL) {
4228 (void) fprintf(stderr, "Unable to allocate envlist\n");
4229 exit(EXIT_FAILURE);
4230 }
4231
4232 /* add current environment into the list */
4233 for (wrk = environ; *wrk != NULL; wrk++) {
4234 (void) envlist_setenv(envlist, *wrk);
4235 }
4236
4237 /* Read the stack limit from the kernel. If it's "unlimited",
4238 then we can do little else besides use the default. */
4239 {
4240 struct rlimit lim;
4241 if (getrlimit(RLIMIT_STACK, &lim) == 0
4242 && lim.rlim_cur != RLIM_INFINITY
4243 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4244 guest_stack_size = lim.rlim_cur;
4245 }
4246 }
4247
4248 cpu_model = NULL;
4249
4250 srand(time(NULL));
4251
4252 qemu_add_opts(&qemu_trace_opts);
4253
4254 optind = parse_args(argc, argv);
4255
4256 if (!trace_init_backends()) {
4257 exit(1);
4258 }
4259 trace_init_file(trace_file);
4260
4261 /* Zero out regs */
4262 memset(regs, 0, sizeof(struct target_pt_regs));
4263
4264 /* Zero out image_info */
4265 memset(info, 0, sizeof(struct image_info));
4266
4267 memset(&bprm, 0, sizeof (bprm));
4268
4269 /* Scan interp_prefix dir for replacement files. */
4270 init_paths(interp_prefix);
4271
4272 init_qemu_uname_release();
4273
4274 if (cpu_model == NULL) {
4275 #if defined(TARGET_I386)
4276 #ifdef TARGET_X86_64
4277 cpu_model = "qemu64";
4278 #else
4279 cpu_model = "qemu32";
4280 #endif
4281 #elif defined(TARGET_ARM)
4282 cpu_model = "any";
4283 #elif defined(TARGET_UNICORE32)
4284 cpu_model = "any";
4285 #elif defined(TARGET_M68K)
4286 cpu_model = "any";
4287 #elif defined(TARGET_SPARC)
4288 #ifdef TARGET_SPARC64
4289 cpu_model = "TI UltraSparc II";
4290 #else
4291 cpu_model = "Fujitsu MB86904";
4292 #endif
4293 #elif defined(TARGET_MIPS)
4294 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4295 cpu_model = "5KEf";
4296 #else
4297 cpu_model = "24Kf";
4298 #endif
4299 #elif defined TARGET_OPENRISC
4300 cpu_model = "or1200";
4301 #elif defined(TARGET_PPC)
4302 # ifdef TARGET_PPC64
4303 cpu_model = "POWER8";
4304 # else
4305 cpu_model = "750";
4306 # endif
4307 #elif defined TARGET_SH4
4308 cpu_model = TYPE_SH7785_CPU;
4309 #else
4310 cpu_model = "any";
4311 #endif
4312 }
4313 tcg_exec_init(0);
4314 /* NOTE: we need to init the CPU at this stage to get
4315 qemu_host_page_size */
4316 cpu = cpu_init(cpu_model);
4317 if (!cpu) {
4318 fprintf(stderr, "Unable to find CPU definition\n");
4319 exit(EXIT_FAILURE);
4320 }
4321 env = cpu->env_ptr;
4322 cpu_reset(cpu);
4323
4324 thread_cpu = cpu;
4325
4326 if (getenv("QEMU_STRACE")) {
4327 do_strace = 1;
4328 }
4329
4330 if (getenv("QEMU_RAND_SEED")) {
4331 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4332 }
4333
4334 target_environ = envlist_to_environ(envlist, NULL);
4335 envlist_free(envlist);
4336
4337 /*
4338 * Now that page sizes are configured in cpu_init() we can do
4339 * proper page alignment for guest_base.
4340 */
4341 guest_base = HOST_PAGE_ALIGN(guest_base);
4342
4343 if (reserved_va || have_guest_base) {
4344 guest_base = init_guest_space(guest_base, reserved_va, 0,
4345 have_guest_base);
4346 if (guest_base == (unsigned long)-1) {
4347 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4348 "space for use as guest address space (check your virtual "
4349 "memory ulimit setting or reserve less using -R option)\n",
4350 reserved_va);
4351 exit(EXIT_FAILURE);
4352 }
4353
4354 if (reserved_va) {
4355 mmap_next_start = reserved_va;
4356 }
4357 }
4358
4359 /*
4360 * Read in mmap_min_addr kernel parameter. This value is used
4361 * When loading the ELF image to determine whether guest_base
4362 * is needed. It is also used in mmap_find_vma.
4363 */
4364 {
4365 FILE *fp;
4366
4367 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4368 unsigned long tmp;
4369 if (fscanf(fp, "%lu", &tmp) == 1) {
4370 mmap_min_addr = tmp;
4371 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4372 }
4373 fclose(fp);
4374 }
4375 }
4376
4377 /*
4378 * Prepare copy of argv vector for target.
4379 */
4380 target_argc = argc - optind;
4381 target_argv = calloc(target_argc + 1, sizeof (char *));
4382 if (target_argv == NULL) {
4383 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4384 exit(EXIT_FAILURE);
4385 }
4386
4387 /*
4388 * If argv0 is specified (using '-0' switch) we replace
4389 * argv[0] pointer with the given one.
4390 */
4391 i = 0;
4392 if (argv0 != NULL) {
4393 target_argv[i++] = strdup(argv0);
4394 }
4395 for (; i < target_argc; i++) {
4396 target_argv[i] = strdup(argv[optind + i]);
4397 }
4398 target_argv[target_argc] = NULL;
4399
4400 ts = g_new0(TaskState, 1);
4401 init_task_state(ts);
4402 /* build Task State */
4403 ts->info = info;
4404 ts->bprm = &bprm;
4405 cpu->opaque = ts;
4406 task_settid(ts);
4407
4408 execfd = qemu_getauxval(AT_EXECFD);
4409 if (execfd == 0) {
4410 execfd = open(filename, O_RDONLY);
4411 if (execfd < 0) {
4412 printf("Error while loading %s: %s\n", filename, strerror(errno));
4413 _exit(EXIT_FAILURE);
4414 }
4415 }
4416
4417 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4418 info, &bprm);
4419 if (ret != 0) {
4420 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4421 _exit(EXIT_FAILURE);
4422 }
4423
4424 for (wrk = target_environ; *wrk; wrk++) {
4425 free(*wrk);
4426 }
4427
4428 free(target_environ);
4429
4430 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4431 qemu_log("guest_base 0x%lx\n", guest_base);
4432 log_page_dump();
4433
4434 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4435 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4436 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4437 info->start_code);
4438 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4439 info->start_data);
4440 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4441 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4442 info->start_stack);
4443 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4444 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4445 }
4446
4447 target_set_brk(info->brk);
4448 syscall_init();
4449 signal_init();
4450
4451 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4452 generating the prologue until now so that the prologue can take
4453 the real value of GUEST_BASE into account. */
4454 tcg_prologue_init(&tcg_ctx);
4455
4456 #if defined(TARGET_I386)
4457 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4458 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4459 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4460 env->cr[4] |= CR4_OSFXSR_MASK;
4461 env->hflags |= HF_OSFXSR_MASK;
4462 }
4463 #ifndef TARGET_ABI32
4464 /* enable 64 bit mode if possible */
4465 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4466 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4467 exit(EXIT_FAILURE);
4468 }
4469 env->cr[4] |= CR4_PAE_MASK;
4470 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4471 env->hflags |= HF_LMA_MASK;
4472 #endif
4473
4474 /* flags setup : we activate the IRQs by default as in user mode */
4475 env->eflags |= IF_MASK;
4476
4477 /* linux register setup */
4478 #ifndef TARGET_ABI32
4479 env->regs[R_EAX] = regs->rax;
4480 env->regs[R_EBX] = regs->rbx;
4481 env->regs[R_ECX] = regs->rcx;
4482 env->regs[R_EDX] = regs->rdx;
4483 env->regs[R_ESI] = regs->rsi;
4484 env->regs[R_EDI] = regs->rdi;
4485 env->regs[R_EBP] = regs->rbp;
4486 env->regs[R_ESP] = regs->rsp;
4487 env->eip = regs->rip;
4488 #else
4489 env->regs[R_EAX] = regs->eax;
4490 env->regs[R_EBX] = regs->ebx;
4491 env->regs[R_ECX] = regs->ecx;
4492 env->regs[R_EDX] = regs->edx;
4493 env->regs[R_ESI] = regs->esi;
4494 env->regs[R_EDI] = regs->edi;
4495 env->regs[R_EBP] = regs->ebp;
4496 env->regs[R_ESP] = regs->esp;
4497 env->eip = regs->eip;
4498 #endif
4499
4500 /* linux interrupt setup */
4501 #ifndef TARGET_ABI32
4502 env->idt.limit = 511;
4503 #else
4504 env->idt.limit = 255;
4505 #endif
4506 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4507 PROT_READ|PROT_WRITE,
4508 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4509 idt_table = g2h(env->idt.base);
4510 set_idt(0, 0);
4511 set_idt(1, 0);
4512 set_idt(2, 0);
4513 set_idt(3, 3);
4514 set_idt(4, 3);
4515 set_idt(5, 0);
4516 set_idt(6, 0);
4517 set_idt(7, 0);
4518 set_idt(8, 0);
4519 set_idt(9, 0);
4520 set_idt(10, 0);
4521 set_idt(11, 0);
4522 set_idt(12, 0);
4523 set_idt(13, 0);
4524 set_idt(14, 0);
4525 set_idt(15, 0);
4526 set_idt(16, 0);
4527 set_idt(17, 0);
4528 set_idt(18, 0);
4529 set_idt(19, 0);
4530 set_idt(0x80, 3);
4531
4532 /* linux segment setup */
4533 {
4534 uint64_t *gdt_table;
4535 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4536 PROT_READ|PROT_WRITE,
4537 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4538 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4539 gdt_table = g2h(env->gdt.base);
4540 #ifdef TARGET_ABI32
4541 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4542 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4543 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4544 #else
4545 /* 64 bit code segment */
4546 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4547 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4548 DESC_L_MASK |
4549 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4550 #endif
4551 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4552 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4553 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4554 }
4555 cpu_x86_load_seg(env, R_CS, __USER_CS);
4556 cpu_x86_load_seg(env, R_SS, __USER_DS);
4557 #ifdef TARGET_ABI32
4558 cpu_x86_load_seg(env, R_DS, __USER_DS);
4559 cpu_x86_load_seg(env, R_ES, __USER_DS);
4560 cpu_x86_load_seg(env, R_FS, __USER_DS);
4561 cpu_x86_load_seg(env, R_GS, __USER_DS);
4562 /* This hack makes Wine work... */
4563 env->segs[R_FS].selector = 0;
4564 #else
4565 cpu_x86_load_seg(env, R_DS, 0);
4566 cpu_x86_load_seg(env, R_ES, 0);
4567 cpu_x86_load_seg(env, R_FS, 0);
4568 cpu_x86_load_seg(env, R_GS, 0);
4569 #endif
4570 #elif defined(TARGET_AARCH64)
4571 {
4572 int i;
4573
4574 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4575 fprintf(stderr,
4576 "The selected ARM CPU does not support 64 bit mode\n");
4577 exit(EXIT_FAILURE);
4578 }
4579
4580 for (i = 0; i < 31; i++) {
4581 env->xregs[i] = regs->regs[i];
4582 }
4583 env->pc = regs->pc;
4584 env->xregs[31] = regs->sp;
4585 }
4586 #elif defined(TARGET_ARM)
4587 {
4588 int i;
4589 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4590 CPSRWriteByInstr);
4591 for(i = 0; i < 16; i++) {
4592 env->regs[i] = regs->uregs[i];
4593 }
4594 #ifdef TARGET_WORDS_BIGENDIAN
4595 /* Enable BE8. */
4596 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4597 && (info->elf_flags & EF_ARM_BE8)) {
4598 env->uncached_cpsr |= CPSR_E;
4599 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4600 } else {
4601 env->cp15.sctlr_el[1] |= SCTLR_B;
4602 }
4603 #endif
4604 }
4605 #elif defined(TARGET_UNICORE32)
4606 {
4607 int i;
4608 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4609 for (i = 0; i < 32; i++) {
4610 env->regs[i] = regs->uregs[i];
4611 }
4612 }
4613 #elif defined(TARGET_SPARC)
4614 {
4615 int i;
4616 env->pc = regs->pc;
4617 env->npc = regs->npc;
4618 env->y = regs->y;
4619 for(i = 0; i < 8; i++)
4620 env->gregs[i] = regs->u_regs[i];
4621 for(i = 0; i < 8; i++)
4622 env->regwptr[i] = regs->u_regs[i + 8];
4623 }
4624 #elif defined(TARGET_PPC)
4625 {
4626 int i;
4627
4628 #if defined(TARGET_PPC64)
4629 #if defined(TARGET_ABI32)
4630 env->msr &= ~((target_ulong)1 << MSR_SF);
4631 #else
4632 env->msr |= (target_ulong)1 << MSR_SF;
4633 #endif
4634 #endif
4635 env->nip = regs->nip;
4636 for(i = 0; i < 32; i++) {
4637 env->gpr[i] = regs->gpr[i];
4638 }
4639 }
4640 #elif defined(TARGET_M68K)
4641 {
4642 env->pc = regs->pc;
4643 env->dregs[0] = regs->d0;
4644 env->dregs[1] = regs->d1;
4645 env->dregs[2] = regs->d2;
4646 env->dregs[3] = regs->d3;
4647 env->dregs[4] = regs->d4;
4648 env->dregs[5] = regs->d5;
4649 env->dregs[6] = regs->d6;
4650 env->dregs[7] = regs->d7;
4651 env->aregs[0] = regs->a0;
4652 env->aregs[1] = regs->a1;
4653 env->aregs[2] = regs->a2;
4654 env->aregs[3] = regs->a3;
4655 env->aregs[4] = regs->a4;
4656 env->aregs[5] = regs->a5;
4657 env->aregs[6] = regs->a6;
4658 env->aregs[7] = regs->usp;
4659 env->sr = regs->sr;
4660 ts->sim_syscalls = 1;
4661 }
4662 #elif defined(TARGET_MICROBLAZE)
4663 {
4664 env->regs[0] = regs->r0;
4665 env->regs[1] = regs->r1;
4666 env->regs[2] = regs->r2;
4667 env->regs[3] = regs->r3;
4668 env->regs[4] = regs->r4;
4669 env->regs[5] = regs->r5;
4670 env->regs[6] = regs->r6;
4671 env->regs[7] = regs->r7;
4672 env->regs[8] = regs->r8;
4673 env->regs[9] = regs->r9;
4674 env->regs[10] = regs->r10;
4675 env->regs[11] = regs->r11;
4676 env->regs[12] = regs->r12;
4677 env->regs[13] = regs->r13;
4678 env->regs[14] = regs->r14;
4679 env->regs[15] = regs->r15;
4680 env->regs[16] = regs->r16;
4681 env->regs[17] = regs->r17;
4682 env->regs[18] = regs->r18;
4683 env->regs[19] = regs->r19;
4684 env->regs[20] = regs->r20;
4685 env->regs[21] = regs->r21;
4686 env->regs[22] = regs->r22;
4687 env->regs[23] = regs->r23;
4688 env->regs[24] = regs->r24;
4689 env->regs[25] = regs->r25;
4690 env->regs[26] = regs->r26;
4691 env->regs[27] = regs->r27;
4692 env->regs[28] = regs->r28;
4693 env->regs[29] = regs->r29;
4694 env->regs[30] = regs->r30;
4695 env->regs[31] = regs->r31;
4696 env->sregs[SR_PC] = regs->pc;
4697 }
4698 #elif defined(TARGET_MIPS)
4699 {
4700 int i;
4701
4702 for(i = 0; i < 32; i++) {
4703 env->active_tc.gpr[i] = regs->regs[i];
4704 }
4705 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4706 if (regs->cp0_epc & 1) {
4707 env->hflags |= MIPS_HFLAG_M16;
4708 }
4709 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4710 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4711 if ((env->active_fpu.fcr31_rw_bitmask &
4712 (1 << FCR31_NAN2008)) == 0) {
4713 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4714 exit(1);
4715 }
4716 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4717 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4718 } else {
4719 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4720 }
4721 restore_snan_bit_mode(env);
4722 }
4723 }
4724 #elif defined(TARGET_OPENRISC)
4725 {
4726 int i;
4727
4728 for (i = 0; i < 32; i++) {
4729 env->gpr[i] = regs->gpr[i];
4730 }
4731
4732 env->sr = regs->sr;
4733 env->pc = regs->pc;
4734 }
4735 #elif defined(TARGET_SH4)
4736 {
4737 int i;
4738
4739 for(i = 0; i < 16; i++) {
4740 env->gregs[i] = regs->regs[i];
4741 }
4742 env->pc = regs->pc;
4743 }
4744 #elif defined(TARGET_ALPHA)
4745 {
4746 int i;
4747
4748 for(i = 0; i < 28; i++) {
4749 env->ir[i] = ((abi_ulong *)regs)[i];
4750 }
4751 env->ir[IR_SP] = regs->usp;
4752 env->pc = regs->pc;
4753 }
4754 #elif defined(TARGET_CRIS)
4755 {
4756 env->regs[0] = regs->r0;
4757 env->regs[1] = regs->r1;
4758 env->regs[2] = regs->r2;
4759 env->regs[3] = regs->r3;
4760 env->regs[4] = regs->r4;
4761 env->regs[5] = regs->r5;
4762 env->regs[6] = regs->r6;
4763 env->regs[7] = regs->r7;
4764 env->regs[8] = regs->r8;
4765 env->regs[9] = regs->r9;
4766 env->regs[10] = regs->r10;
4767 env->regs[11] = regs->r11;
4768 env->regs[12] = regs->r12;
4769 env->regs[13] = regs->r13;
4770 env->regs[14] = info->start_stack;
4771 env->regs[15] = regs->acr;
4772 env->pc = regs->erp;
4773 }
4774 #elif defined(TARGET_S390X)
4775 {
4776 int i;
4777 for (i = 0; i < 16; i++) {
4778 env->regs[i] = regs->gprs[i];
4779 }
4780 env->psw.mask = regs->psw.mask;
4781 env->psw.addr = regs->psw.addr;
4782 }
4783 #elif defined(TARGET_TILEGX)
4784 {
4785 int i;
4786 for (i = 0; i < TILEGX_R_COUNT; i++) {
4787 env->regs[i] = regs->regs[i];
4788 }
4789 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4790 env->spregs[i] = 0;
4791 }
4792 env->pc = regs->pc;
4793 }
4794 #else
4795 #error unsupported target CPU
4796 #endif
4797
4798 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4799 ts->stack_base = info->start_stack;
4800 ts->heap_base = info->brk;
4801 /* This will be filled in on the first SYS_HEAPINFO call. */
4802 ts->heap_limit = 0;
4803 #endif
4804
4805 if (gdbstub_port) {
4806 if (gdbserver_start(gdbstub_port) < 0) {
4807 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4808 gdbstub_port);
4809 exit(EXIT_FAILURE);
4810 }
4811 gdb_handlesig(cpu, 0);
4812 }
4813 trace_init_vcpu_events();
4814 cpu_loop(env);
4815 /* never exits */
4816 return 0;
4817 }
Random patches