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.travis.yml: Shorten the runtime of the problematic jobs
[qemu/kevin.git] / hw / ssi / aspeed_smc.c
blob6e1a84c197130118d022d1b9fb607e74e844f4e2
1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/block/flash.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
29 #include "qemu/log.h"
30 #include "qemu/module.h"
31 #include "qemu/error-report.h"
32 #include "qapi/error.h"
33 #include "qemu/units.h"
34 #include "trace.h"
35
36 #include "hw/irq.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ssi/aspeed_smc.h"
39
40 /* CE Type Setting Register */
41 #define R_CONF (0x00 / 4)
42 #define CONF_LEGACY_DISABLE (1 << 31)
43 #define CONF_ENABLE_W4 20
44 #define CONF_ENABLE_W3 19
45 #define CONF_ENABLE_W2 18
46 #define CONF_ENABLE_W1 17
47 #define CONF_ENABLE_W0 16
48 #define CONF_FLASH_TYPE4 8
49 #define CONF_FLASH_TYPE3 6
50 #define CONF_FLASH_TYPE2 4
51 #define CONF_FLASH_TYPE1 2
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
56
57 /* CE Control Register */
58 #define R_CE_CTRL (0x04 / 4)
59 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
60 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
61 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
62 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
64
65 /* Interrupt Control and Status Register */
66 #define R_INTR_CTRL (0x08 / 4)
67 #define INTR_CTRL_DMA_STATUS (1 << 11)
68 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
69 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
70 #define INTR_CTRL_DMA_EN (1 << 3)
71 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
72 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
73
74 /* Command Control Register */
75 #define R_CE_CMD_CTRL (0x0C / 4)
76 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
78
79 #define aspeed_smc_addr_byte_enabled(s, i) \
80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
81 #define aspeed_smc_data_byte_enabled(s, i) \
82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
83
84 /* CEx Control Register */
85 #define R_CTRL0 (0x10 / 4)
86 #define CTRL_IO_QPI (1 << 31)
87 #define CTRL_IO_QUAD_DATA (1 << 30)
88 #define CTRL_IO_DUAL_DATA (1 << 29)
89 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
90 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
91 #define CTRL_CMD_SHIFT 16
92 #define CTRL_CMD_MASK 0xff
93 #define CTRL_DUMMY_HIGH_SHIFT 14
94 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
95 #define CE_CTRL_CLOCK_FREQ_SHIFT 8
96 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
97 #define CE_CTRL_CLOCK_FREQ(div) \
98 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
99 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
100 #define CTRL_CE_STOP_ACTIVE (1 << 2)
101 #define CTRL_CMD_MODE_MASK 0x3
102 #define CTRL_READMODE 0x0
103 #define CTRL_FREADMODE 0x1
104 #define CTRL_WRITEMODE 0x2
105 #define CTRL_USERMODE 0x3
106 #define R_CTRL1 (0x14 / 4)
107 #define R_CTRL2 (0x18 / 4)
108 #define R_CTRL3 (0x1C / 4)
109 #define R_CTRL4 (0x20 / 4)
110
111 /* CEx Segment Address Register */
112 #define R_SEG_ADDR0 (0x30 / 4)
113 #define SEG_END_SHIFT 24 /* 8MB units */
114 #define SEG_END_MASK 0xff
115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
116 #define SEG_START_MASK 0xff
117 #define R_SEG_ADDR1 (0x34 / 4)
118 #define R_SEG_ADDR2 (0x38 / 4)
119 #define R_SEG_ADDR3 (0x3C / 4)
120 #define R_SEG_ADDR4 (0x40 / 4)
121
122 /* Misc Control Register #1 */
123 #define R_MISC_CTRL1 (0x50 / 4)
124
125 /* SPI dummy cycle data */
126 #define R_DUMMY_DATA (0x54 / 4)
127
128 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */
129 #define R_FMC_WDT2_CTRL (0x64 / 4)
130 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */
131 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5)
132 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */
133 #define FMC_WDT2_CTRL_EN BIT(0)
134
135 /* DMA Control/Status Register */
136 #define R_DMA_CTRL (0x80 / 4)
137 #define DMA_CTRL_REQUEST (1 << 31)
138 #define DMA_CTRL_GRANT (1 << 30)
139 #define DMA_CTRL_DELAY_MASK 0xf
140 #define DMA_CTRL_DELAY_SHIFT 8
141 #define DMA_CTRL_FREQ_MASK 0xf
142 #define DMA_CTRL_FREQ_SHIFT 4
143 #define DMA_CTRL_CALIB (1 << 3)
144 #define DMA_CTRL_CKSUM (1 << 2)
145 #define DMA_CTRL_WRITE (1 << 1)
146 #define DMA_CTRL_ENABLE (1 << 0)
147
148 /* DMA Flash Side Address */
149 #define R_DMA_FLASH_ADDR (0x84 / 4)
150
151 /* DMA DRAM Side Address */
152 #define R_DMA_DRAM_ADDR (0x88 / 4)
153
154 /* DMA Length Register */
155 #define R_DMA_LEN (0x8C / 4)
156
157 /* Checksum Calculation Result */
158 #define R_DMA_CHECKSUM (0x90 / 4)
159
160 /* Read Timing Compensation Register */
161 #define R_TIMINGS (0x94 / 4)
162
163 /* SPI controller registers and bits (AST2400) */
164 #define R_SPI_CONF (0x00 / 4)
165 #define SPI_CONF_ENABLE_W0 0
166 #define R_SPI_CTRL0 (0x4 / 4)
167 #define R_SPI_MISC_CTRL (0x10 / 4)
168 #define R_SPI_TIMINGS (0x14 / 4)
169
170 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
171 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
172
173 /*
174 * DMA DRAM addresses should be 4 bytes aligned and the valid address
175 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
176 * 0x80000000 - 0xBFFFFFFF (AST2500)
177 *
178 * DMA flash addresses should be 4 bytes aligned and the valid address
179 * range is 0x20000000 - 0x2FFFFFFF.
180 *
181 * DMA length is from 4 bytes to 32MB
182 * 0: 4 bytes
183 * 0x7FFFFF: 32M bytes
184 */
185 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
186 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
187 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
188
189 /* Flash opcodes. */
190 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
191
192 #define SNOOP_OFF 0xFF
193 #define SNOOP_START 0x0
194
195 /*
196 * Default segments mapping addresses and size for each peripheral per
197 * controller. These can be changed when board is initialized with the
198 * Segment Address Registers.
199 */
200 static const AspeedSegments aspeed_2500_spi1_segments[];
201 static const AspeedSegments aspeed_2500_spi2_segments[];
202
203 #define ASPEED_SMC_FEATURE_DMA 0x1
204 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
205 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
206
207 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
208 {
209 return !!(asc->features & ASPEED_SMC_FEATURE_DMA);
210 }
211
212 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)
213 {
214 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
215 }
216
217 #define aspeed_smc_error(fmt, ...) \
218 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
219
220 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
221 const AspeedSegments *new,
222 int cs)
223 {
224 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
225 AspeedSegments seg;
226 int i;
227
228 for (i = 0; i < asc->cs_num_max; i++) {
229 if (i == cs) {
230 continue;
231 }
232
233 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
234
235 if (new->addr + new->size > seg.addr &&
236 new->addr < seg.addr + seg.size) {
237 aspeed_smc_error("new segment CS%d [ 0x%"
238 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
239 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
240 cs, new->addr, new->addr + new->size,
241 i, seg.addr, seg.addr + seg.size);
242 return true;
243 }
244 }
245 return false;
246 }
247
248 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
249 uint64_t regval)
250 {
251 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
252 AspeedSMCFlash *fl = &s->flashes[cs];
253 AspeedSegments seg;
254
255 asc->reg_to_segment(s, regval, &seg);
256
257 memory_region_transaction_begin();
258 memory_region_set_size(&fl->mmio, seg.size);
259 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base);
260 memory_region_set_enabled(&fl->mmio, !!seg.size);
261 memory_region_transaction_commit();
262
263 if (asc->segment_addr_mask) {
264 regval &= asc->segment_addr_mask;
265 }
266
267 s->regs[R_SEG_ADDR0 + cs] = regval;
268 }
269
270 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
271 uint64_t new)
272 {
273 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
274 AspeedSegments seg;
275
276 asc->reg_to_segment(s, new, &seg);
277
278 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
279
280 /* The start address of CS0 is read-only */
281 if (cs == 0 && seg.addr != asc->flash_window_base) {
282 aspeed_smc_error("Tried to change CS0 start address to 0x%"
283 HWADDR_PRIx, seg.addr);
284 seg.addr = asc->flash_window_base;
285 new = asc->segment_to_reg(s, &seg);
286 }
287
288 /*
289 * The end address of the AST2500 spi controllers is also
290 * read-only.
291 */
292 if ((asc->segments == aspeed_2500_spi1_segments ||
293 asc->segments == aspeed_2500_spi2_segments) &&
294 cs == asc->cs_num_max &&
295 seg.addr + seg.size != asc->segments[cs].addr +
296 asc->segments[cs].size) {
297 aspeed_smc_error("Tried to change CS%d end address to 0x%"
298 HWADDR_PRIx, cs, seg.addr + seg.size);
299 seg.size = asc->segments[cs].addr + asc->segments[cs].size -
300 seg.addr;
301 new = asc->segment_to_reg(s, &seg);
302 }
303
304 /* Keep the segment in the overall flash window */
305 if (seg.size &&
306 (seg.addr + seg.size <= asc->flash_window_base ||
307 seg.addr > asc->flash_window_base + asc->flash_window_size)) {
308 aspeed_smc_error("new segment for CS%d is invalid : "
309 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
310 cs, seg.addr, seg.addr + seg.size);
311 return;
312 }
313
314 /* Check start address vs. alignment */
315 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
316 aspeed_smc_error("new segment for CS%d is not "
317 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
318 cs, seg.addr, seg.addr + seg.size);
319 }
320
321 /* And segments should not overlap (in the specs) */
322 aspeed_smc_flash_overlap(s, &seg, cs);
323
324 /* All should be fine now to move the region */
325 aspeed_smc_flash_set_segment_region(s, cs, new);
326 }
327
328 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
329 unsigned size)
330 {
331 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size);
332 return 0;
333 }
334
335 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
336 uint64_t data, unsigned size)
337 {
338 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64,
339 addr, size, data);
340 }
341
342 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
343 .read = aspeed_smc_flash_default_read,
344 .write = aspeed_smc_flash_default_write,
345 .endianness = DEVICE_LITTLE_ENDIAN,
346 .valid = {
347 .min_access_size = 1,
348 .max_access_size = 4,
349 },
350 };
351
352 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
353 {
354 const AspeedSMCState *s = fl->controller;
355
356 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
357 }
358
359 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
360 {
361 const AspeedSMCState *s = fl->controller;
362
363 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs));
364 }
365
366 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
367 {
368 const AspeedSMCState *s = fl->controller;
369 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
370
371 /*
372 * In read mode, the default SPI command is READ (0x3). In other
373 * modes, the command should necessarily be defined
374 *
375 * TODO: add support for READ4 (0x13) on AST2600
376 */
377 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
378 cmd = SPI_OP_READ;
379 }
380
381 if (!cmd) {
382 aspeed_smc_error("no command defined for mode %d",
383 aspeed_smc_flash_mode(fl));
384 }
385
386 return cmd;
387 }
388
389 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
390 {
391 const AspeedSMCState *s = fl->controller;
392 AspeedSMCClass *asc = fl->asc;
393
394 if (asc->addr_width) {
395 return asc->addr_width(s);
396 } else {
397 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3;
398 }
399 }
400
401 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
402 {
403 AspeedSMCState *s = fl->controller;
404
405 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : "");
406
407 qemu_set_irq(s->cs_lines[fl->cs], unselect);
408 }
409
410 static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
411 {
412 aspeed_smc_flash_do_select(fl, false);
413 }
414
415 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
416 {
417 aspeed_smc_flash_do_select(fl, true);
418 }
419
420 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
421 uint32_t addr)
422 {
423 const AspeedSMCState *s = fl->controller;
424 AspeedSMCClass *asc = fl->asc;
425 AspeedSegments seg;
426
427 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
428 if ((addr % seg.size) != addr) {
429 aspeed_smc_error("invalid address 0x%08x for CS%d segment : "
430 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
431 addr, fl->cs, seg.addr, seg.addr + seg.size);
432 addr %= seg.size;
433 }
434
435 return addr;
436 }
437
438 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
439 {
440 const AspeedSMCState *s = fl->controller;
441 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs];
442 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
443 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
444 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
445
446 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
447 dummies /= 2;
448 }
449
450 return dummies;
451 }
452
453 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
454 {
455 const AspeedSMCState *s = fl->controller;
456 uint8_t cmd = aspeed_smc_flash_cmd(fl);
457 int i = aspeed_smc_flash_addr_width(fl);
458
459 /* Flash access can not exceed CS segment */
460 addr = aspeed_smc_check_segment_addr(fl, addr);
461
462 ssi_transfer(s->spi, cmd);
463 while (i--) {
464 if (aspeed_smc_addr_byte_enabled(s, i)) {
465 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
466 }
467 }
468
469 /*
470 * Use fake transfers to model dummy bytes. The value should
471 * be configured to some non-zero value in fast read mode and
472 * zero in read mode. But, as the HW allows inconsistent
473 * settings, let's check for fast read mode.
474 */
475 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
476 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
477 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
478 }
479 }
480 }
481
482 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
483 {
484 AspeedSMCFlash *fl = opaque;
485 AspeedSMCState *s = fl->controller;
486 uint64_t ret = 0;
487 int i;
488
489 switch (aspeed_smc_flash_mode(fl)) {
490 case CTRL_USERMODE:
491 for (i = 0; i < size; i++) {
492 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
493 }
494 break;
495 case CTRL_READMODE:
496 case CTRL_FREADMODE:
497 aspeed_smc_flash_select(fl);
498 aspeed_smc_flash_setup(fl, addr);
499
500 for (i = 0; i < size; i++) {
501 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i);
502 }
503
504 aspeed_smc_flash_unselect(fl);
505 break;
506 default:
507 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
508 }
509
510 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
511 aspeed_smc_flash_mode(fl));
512 return ret;
513 }
514
515 /*
516 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
517 * common include header.
518 */
519 typedef enum {
520 READ = 0x3, READ_4 = 0x13,
521 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
522 DOR = 0x3b, DOR_4 = 0x3c,
523 QOR = 0x6b, QOR_4 = 0x6c,
524 DIOR = 0xbb, DIOR_4 = 0xbc,
525 QIOR = 0xeb, QIOR_4 = 0xec,
526
527 PP = 0x2, PP_4 = 0x12,
528 DPP = 0xa2,
529 QPP = 0x32, QPP_4 = 0x34,
530 } FlashCMD;
531
532 static int aspeed_smc_num_dummies(uint8_t command)
533 {
534 switch (command) { /* check for dummies */
535 case READ: /* no dummy bytes/cycles */
536 case PP:
537 case DPP:
538 case QPP:
539 case READ_4:
540 case PP_4:
541 case QPP_4:
542 return 0;
543 case FAST_READ:
544 case DOR:
545 case QOR:
546 case FAST_READ_4:
547 case DOR_4:
548 case QOR_4:
549 return 1;
550 case DIOR:
551 case DIOR_4:
552 return 2;
553 case QIOR:
554 case QIOR_4:
555 return 4;
556 default:
557 return -1;
558 }
559 }
560
561 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
562 unsigned size)
563 {
564 AspeedSMCState *s = fl->controller;
565 uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
566
567 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
568 (uint8_t) data & 0xff);
569
570 if (s->snoop_index == SNOOP_OFF) {
571 return false; /* Do nothing */
572
573 } else if (s->snoop_index == SNOOP_START) {
574 uint8_t cmd = data & 0xff;
575 int ndummies = aspeed_smc_num_dummies(cmd);
576
577 /*
578 * No dummy cycles are expected with the current command. Turn
579 * off snooping and let the transfer proceed normally.
580 */
581 if (ndummies <= 0) {
582 s->snoop_index = SNOOP_OFF;
583 return false;
584 }
585
586 s->snoop_dummies = ndummies * 8;
587
588 } else if (s->snoop_index >= addr_width + 1) {
589
590 /* The SPI transfer has reached the dummy cycles sequence */
591 for (; s->snoop_dummies; s->snoop_dummies--) {
592 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
593 }
594
595 /* If no more dummy cycles are expected, turn off snooping */
596 if (!s->snoop_dummies) {
597 s->snoop_index = SNOOP_OFF;
598 } else {
599 s->snoop_index += size;
600 }
601
602 /*
603 * Dummy cycles have been faked already. Ignore the current
604 * SPI transfer
605 */
606 return true;
607 }
608
609 s->snoop_index += size;
610 return false;
611 }
612
613 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
614 unsigned size)
615 {
616 AspeedSMCFlash *fl = opaque;
617 AspeedSMCState *s = fl->controller;
618 int i;
619
620 trace_aspeed_smc_flash_write(fl->cs, addr, size, data,
621 aspeed_smc_flash_mode(fl));
622
623 if (!aspeed_smc_is_writable(fl)) {
624 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
625 return;
626 }
627
628 switch (aspeed_smc_flash_mode(fl)) {
629 case CTRL_USERMODE:
630 if (aspeed_smc_do_snoop(fl, data, size)) {
631 break;
632 }
633
634 for (i = 0; i < size; i++) {
635 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
636 }
637 break;
638 case CTRL_WRITEMODE:
639 aspeed_smc_flash_select(fl);
640 aspeed_smc_flash_setup(fl, addr);
641
642 for (i = 0; i < size; i++) {
643 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
644 }
645
646 aspeed_smc_flash_unselect(fl);
647 break;
648 default:
649 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
650 }
651 }
652
653 static const MemoryRegionOps aspeed_smc_flash_ops = {
654 .read = aspeed_smc_flash_read,
655 .write = aspeed_smc_flash_write,
656 .endianness = DEVICE_LITTLE_ENDIAN,
657 .valid = {
658 .min_access_size = 1,
659 .max_access_size = 4,
660 },
661 };
662
663 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
664 {
665 AspeedSMCState *s = fl->controller;
666 bool unselect;
667
668 /* User mode selects the CS, other modes unselect */
669 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
670
671 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
672 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) &&
673 value & CTRL_CE_STOP_ACTIVE) {
674 unselect = true;
675 }
676
677 s->regs[s->r_ctrl0 + fl->cs] = value;
678
679 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
680
681 aspeed_smc_flash_do_select(fl, unselect);
682 }
683
684 static void aspeed_smc_reset(DeviceState *d)
685 {
686 AspeedSMCState *s = ASPEED_SMC(d);
687 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
688 int i;
689
690 if (asc->resets) {
691 memcpy(s->regs, asc->resets, sizeof s->regs);
692 } else {
693 memset(s->regs, 0, sizeof s->regs);
694 }
695
696 for (i = 0; i < asc->cs_num_max; i++) {
697 DeviceState *dev = ssi_get_cs(s->spi, i);
698 if (dev) {
699 Object *o = OBJECT(dev);
700
701 if (!object_dynamic_cast(o, TYPE_M25P80)) {
702 warn_report("Aspeed SMC %s.%d : Invalid %s device type",
703 BUS(s->spi)->name, i, object_get_typename(o));
704 continue;
705 }
706
707 qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
708 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
709 }
710 }
711
712 /* Unselect all peripherals */
713 for (i = 0; i < asc->cs_num_max; ++i) {
714 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
715 qemu_set_irq(s->cs_lines[i], true);
716 }
717
718 /* setup the default segment register values and regions for all */
719 for (i = 0; i < asc->cs_num_max; ++i) {
720 aspeed_smc_flash_set_segment_region(s, i,
721 asc->segment_to_reg(s, &asc->segments[i]));
722 }
723
724 s->snoop_index = SNOOP_OFF;
725 s->snoop_dummies = 0;
726 }
727
728 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
729 {
730 AspeedSMCState *s = ASPEED_SMC(opaque);
731 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
732
733 addr >>= 2;
734
735 if (addr == s->r_conf ||
736 (addr >= s->r_timings &&
737 addr < s->r_timings + asc->nregs_timings) ||
738 addr == s->r_ce_ctrl ||
739 addr == R_CE_CMD_CTRL ||
740 addr == R_INTR_CTRL ||
741 addr == R_DUMMY_DATA ||
742 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) ||
743 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
744 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
745 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
746 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
747 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
748 (addr >= R_SEG_ADDR0 &&
749 addr < R_SEG_ADDR0 + asc->cs_num_max) ||
750 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) {
751
752 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);
753
754 return s->regs[addr];
755 } else {
756 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
757 __func__, addr);
758 return -1;
759 }
760 }
761
762 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
763 {
764 /* HCLK/1 .. HCLK/16 */
765 const uint8_t hclk_divisors[] = {
766 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
767 };
768 int i;
769
770 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
771 if (hclk_mask == hclk_divisors[i]) {
772 return i + 1;
773 }
774 }
775
776 aspeed_smc_error("invalid HCLK mask %x", hclk_mask);
777 return 0;
778 }
779
780 /*
781 * When doing calibration, the SPI clock rate in the CE0 Control
782 * Register and the read delay cycles in the Read Timing Compensation
783 * Register are set using bit[11:4] of the DMA Control Register.
784 */
785 static void aspeed_smc_dma_calibration(AspeedSMCState *s)
786 {
787 uint8_t delay =
788 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
789 uint8_t hclk_mask =
790 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
791 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
792 uint32_t hclk_shift = (hclk_div - 1) << 2;
793 uint8_t cs;
794
795 /*
796 * The Read Timing Compensation Register values apply to all CS on
797 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
798 */
799 if (hclk_div && hclk_div < 6) {
800 s->regs[s->r_timings] &= ~(0xf << hclk_shift);
801 s->regs[s->r_timings] |= delay << hclk_shift;
802 }
803
804 /*
805 * TODO: compute the CS from the DMA address and the segment
806 * registers. This is not really a problem for now because the
807 * Timing Register values apply to all CS and software uses CS0 to
808 * do calibration.
809 */
810 cs = 0;
811 s->regs[s->r_ctrl0 + cs] &=
812 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
813 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
814 }
815
816 /*
817 * Emulate read errors in the DMA Checksum Register for high
818 * frequencies and optimistic settings of the Read Timing Compensation
819 * Register. This will help in tuning the SPI timing calibration
820 * algorithm.
821 */
822 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
823 {
824 uint8_t delay =
825 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
826 uint8_t hclk_mask =
827 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
828
829 /*
830 * Typical values of a palmetto-bmc machine.
831 */
832 switch (aspeed_smc_hclk_divisor(hclk_mask)) {
833 case 4 ... 16:
834 return false;
835 case 3: /* at least one HCLK cycle delay */
836 return (delay & 0x7) < 1;
837 case 2: /* at least two HCLK cycle delay */
838 return (delay & 0x7) < 2;
839 case 1: /* (> 100MHz) is above the max freq of the controller */
840 return true;
841 default:
842 g_assert_not_reached();
843 }
844 }
845
846 /*
847 * Accumulate the result of the reads to provide a checksum that will
848 * be used to validate the read timing settings.
849 */
850 static void aspeed_smc_dma_checksum(AspeedSMCState *s)
851 {
852 MemTxResult result;
853 uint32_t data;
854
855 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
856 aspeed_smc_error("invalid direction for DMA checksum");
857 return;
858 }
859
860 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
861 aspeed_smc_dma_calibration(s);
862 }
863
864 while (s->regs[R_DMA_LEN]) {
865 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
866 MEMTXATTRS_UNSPECIFIED, &result);
867 if (result != MEMTX_OK) {
868 aspeed_smc_error("Flash read failed @%08x",
869 s->regs[R_DMA_FLASH_ADDR]);
870 return;
871 }
872 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
873
874 /*
875 * When the DMA is on-going, the DMA registers are updated
876 * with the current working addresses and length.
877 */
878 s->regs[R_DMA_CHECKSUM] += data;
879 s->regs[R_DMA_FLASH_ADDR] += 4;
880 s->regs[R_DMA_LEN] -= 4;
881 }
882
883 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
884 s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
885 }
886
887 }
888
889 static void aspeed_smc_dma_rw(AspeedSMCState *s)
890 {
891 MemTxResult result;
892 uint32_t data;
893
894 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
895 "write" : "read",
896 s->regs[R_DMA_FLASH_ADDR],
897 s->regs[R_DMA_DRAM_ADDR],
898 s->regs[R_DMA_LEN]);
899 while (s->regs[R_DMA_LEN]) {
900 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
901 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
902 MEMTXATTRS_UNSPECIFIED, &result);
903 if (result != MEMTX_OK) {
904 aspeed_smc_error("DRAM read failed @%08x",
905 s->regs[R_DMA_DRAM_ADDR]);
906 return;
907 }
908
909 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
910 data, MEMTXATTRS_UNSPECIFIED, &result);
911 if (result != MEMTX_OK) {
912 aspeed_smc_error("Flash write failed @%08x",
913 s->regs[R_DMA_FLASH_ADDR]);
914 return;
915 }
916 } else {
917 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
918 MEMTXATTRS_UNSPECIFIED, &result);
919 if (result != MEMTX_OK) {
920 aspeed_smc_error("Flash read failed @%08x",
921 s->regs[R_DMA_FLASH_ADDR]);
922 return;
923 }
924
925 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
926 data, MEMTXATTRS_UNSPECIFIED, &result);
927 if (result != MEMTX_OK) {
928 aspeed_smc_error("DRAM write failed @%08x",
929 s->regs[R_DMA_DRAM_ADDR]);
930 return;
931 }
932 }
933
934 /*
935 * When the DMA is on-going, the DMA registers are updated
936 * with the current working addresses and length.
937 */
938 s->regs[R_DMA_FLASH_ADDR] += 4;
939 s->regs[R_DMA_DRAM_ADDR] += 4;
940 s->regs[R_DMA_LEN] -= 4;
941 s->regs[R_DMA_CHECKSUM] += data;
942 }
943 }
944
945 static void aspeed_smc_dma_stop(AspeedSMCState *s)
946 {
947 /*
948 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
949 * engine is idle
950 */
951 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
952 s->regs[R_DMA_CHECKSUM] = 0;
953
954 /*
955 * Lower the DMA irq in any case. The IRQ control register could
956 * have been cleared before disabling the DMA.
957 */
958 qemu_irq_lower(s->irq);
959 }
960
961 /*
962 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
963 * can start even if the result of the previous was not collected.
964 */
965 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
966 {
967 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
968 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
969 }
970
971 static void aspeed_smc_dma_done(AspeedSMCState *s)
972 {
973 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
974 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
975 qemu_irq_raise(s->irq);
976 }
977 }
978
979 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
980 {
981 if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
982 s->regs[R_DMA_CTRL] = dma_ctrl;
983
984 aspeed_smc_dma_stop(s);
985 return;
986 }
987
988 if (aspeed_smc_dma_in_progress(s)) {
989 aspeed_smc_error("DMA in progress !");
990 return;
991 }
992
993 s->regs[R_DMA_CTRL] = dma_ctrl;
994
995 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
996 aspeed_smc_dma_checksum(s);
997 } else {
998 aspeed_smc_dma_rw(s);
999 }
1000
1001 aspeed_smc_dma_done(s);
1002 }
1003
1004 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
1005 {
1006 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1007
1008 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
1009 return true;
1010 }
1011
1012 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
1013 aspeed_smc_error("DMA not granted");
1014 return false;
1015 }
1016
1017 return true;
1018 }
1019
1020 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1021 {
1022 /* Preserve DMA bits */
1023 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1024
1025 if (dma_ctrl == 0xAEED0000) {
1026 /* automatically grant request */
1027 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1028 return;
1029 }
1030
1031 /* clear request */
1032 if (dma_ctrl == 0xDEEA0000) {
1033 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1034 return;
1035 }
1036
1037 if (!aspeed_smc_dma_granted(s)) {
1038 aspeed_smc_error("DMA not granted");
1039 return;
1040 }
1041
1042 aspeed_smc_dma_ctrl(s, dma_ctrl);
1043 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1044 }
1045
1046 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
1047 unsigned int size)
1048 {
1049 AspeedSMCState *s = ASPEED_SMC(opaque);
1050 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1051 uint32_t value = data;
1052
1053 trace_aspeed_smc_write(addr, size, data);
1054
1055 addr >>= 2;
1056
1057 if (addr == s->r_conf ||
1058 (addr >= s->r_timings &&
1059 addr < s->r_timings + asc->nregs_timings) ||
1060 addr == s->r_ce_ctrl) {
1061 s->regs[addr] = value;
1062 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) {
1063 int cs = addr - s->r_ctrl0;
1064 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
1065 } else if (addr >= R_SEG_ADDR0 &&
1066 addr < R_SEG_ADDR0 + asc->cs_num_max) {
1067 int cs = addr - R_SEG_ADDR0;
1068
1069 if (value != s->regs[R_SEG_ADDR0 + cs]) {
1070 aspeed_smc_flash_set_segment(s, cs, value);
1071 }
1072 } else if (addr == R_CE_CMD_CTRL) {
1073 s->regs[addr] = value & 0xff;
1074 } else if (addr == R_DUMMY_DATA) {
1075 s->regs[addr] = value & 0xff;
1076 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
1077 s->regs[addr] = value & FMC_WDT2_CTRL_EN;
1078 } else if (addr == R_INTR_CTRL) {
1079 s->regs[addr] = value;
1080 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {
1081 asc->dma_ctrl(s, value);
1082 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR &&
1083 aspeed_smc_dma_granted(s)) {
1084 s->regs[addr] = DMA_DRAM_ADDR(asc, value);
1085 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR &&
1086 aspeed_smc_dma_granted(s)) {
1087 s->regs[addr] = DMA_FLASH_ADDR(asc, value);
1088 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
1089 aspeed_smc_dma_granted(s)) {
1090 s->regs[addr] = DMA_LENGTH(value);
1091 } else {
1092 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
1093 __func__, addr);
1094 return;
1095 }
1096 }
1097
1098 static const MemoryRegionOps aspeed_smc_ops = {
1099 .read = aspeed_smc_read,
1100 .write = aspeed_smc_write,
1101 .endianness = DEVICE_LITTLE_ENDIAN,
1102 };
1103
1104 static void aspeed_smc_instance_init(Object *obj)
1105 {
1106 AspeedSMCState *s = ASPEED_SMC(obj);
1107 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1108 int i;
1109
1110 for (i = 0; i < asc->cs_num_max; i++) {
1111 object_initialize_child(obj, "flash[*]", &s->flashes[i],
1112 TYPE_ASPEED_SMC_FLASH);
1113 }
1114 }
1115
1116 /*
1117 * Initialize the custom address spaces for DMAs
1118 */
1119 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1120 {
1121 if (!s->dram_mr) {
1122 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1123 return;
1124 }
1125
1126 address_space_init(&s->flash_as, &s->mmio_flash,
1127 TYPE_ASPEED_SMC ".dma-flash");
1128 address_space_init(&s->dram_as, s->dram_mr,
1129 TYPE_ASPEED_SMC ".dma-dram");
1130 }
1131
1132 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
1133 {
1134 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1135 AspeedSMCState *s = ASPEED_SMC(dev);
1136 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1137 int i;
1138 hwaddr offset = 0;
1139
1140 /* keep a copy under AspeedSMCState to speed up accesses */
1141 s->r_conf = asc->r_conf;
1142 s->r_ce_ctrl = asc->r_ce_ctrl;
1143 s->r_ctrl0 = asc->r_ctrl0;
1144 s->r_timings = asc->r_timings;
1145 s->conf_enable_w0 = asc->conf_enable_w0;
1146
1147 /* DMA irq. Keep it first for the initialization in the SoC */
1148 sysbus_init_irq(sbd, &s->irq);
1149
1150 s->spi = ssi_create_bus(dev, NULL);
1151
1152 /* Setup cs_lines for peripherals */
1153 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max);
1154 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max);
1155
1156 /* The memory region for the controller registers */
1157 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
1158 TYPE_ASPEED_SMC, asc->nregs * 4);
1159 sysbus_init_mmio(sbd, &s->mmio);
1160
1161 /*
1162 * The container memory region representing the address space
1163 * window in which the flash modules are mapped. The size and
1164 * address depends on the SoC model and controller type.
1165 */
1166 memory_region_init(&s->mmio_flash_container, OBJECT(s),
1167 TYPE_ASPEED_SMC ".container",
1168 asc->flash_window_size);
1169 sysbus_init_mmio(sbd, &s->mmio_flash_container);
1170
1171 memory_region_init_io(&s->mmio_flash, OBJECT(s),
1172 &aspeed_smc_flash_default_ops, s,
1173 TYPE_ASPEED_SMC ".flash",
1174 asc->flash_window_size);
1175 memory_region_add_subregion(&s->mmio_flash_container, 0x0,
1176 &s->mmio_flash);
1177
1178 /*
1179 * Let's create a sub memory region for each possible peripheral. All
1180 * have a configurable memory segment in the overall flash mapping
1181 * window of the controller but, there is not necessarily a flash
1182 * module behind to handle the memory accesses. This depends on
1183 * the board configuration.
1184 */
1185 for (i = 0; i < asc->cs_num_max; ++i) {
1186 AspeedSMCFlash *fl = &s->flashes[i];
1187
1188 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s),
1189 errp)) {
1190 return;
1191 }
1192 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) {
1193 return;
1194 }
1195 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) {
1196 return;
1197 }
1198
1199 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
1200 offset += asc->segments[i].size;
1201 }
1202
1203 /* DMA support */
1204 if (aspeed_smc_has_dma(asc)) {
1205 aspeed_smc_dma_setup(s, errp);
1206 }
1207 }
1208
1209 static const VMStateDescription vmstate_aspeed_smc = {
1210 .name = "aspeed.smc",
1211 .version_id = 2,
1212 .minimum_version_id = 2,
1213 .fields = (const VMStateField[]) {
1214 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1215 VMSTATE_UINT8(snoop_index, AspeedSMCState),
1216 VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
1217 VMSTATE_END_OF_LIST()
1218 }
1219 };
1220
1221 static Property aspeed_smc_properties[] = {
1222 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1223 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1224 TYPE_MEMORY_REGION, MemoryRegion *),
1225 DEFINE_PROP_END_OF_LIST(),
1226 };
1227
1228 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
1229 {
1230 DeviceClass *dc = DEVICE_CLASS(klass);
1231
1232 dc->realize = aspeed_smc_realize;
1233 dc->reset = aspeed_smc_reset;
1234 device_class_set_props(dc, aspeed_smc_properties);
1235 dc->vmsd = &vmstate_aspeed_smc;
1236 }
1237
1238 static const TypeInfo aspeed_smc_info = {
1239 .name = TYPE_ASPEED_SMC,
1240 .parent = TYPE_SYS_BUS_DEVICE,
1241 .instance_init = aspeed_smc_instance_init,
1242 .instance_size = sizeof(AspeedSMCState),
1243 .class_size = sizeof(AspeedSMCClass),
1244 .class_init = aspeed_smc_class_init,
1245 .abstract = true,
1246 };
1247
1248 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
1249 {
1250 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
1251 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
1252
1253 if (!s->controller) {
1254 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set");
1255 return;
1256 }
1257
1258 s->asc = ASPEED_SMC_GET_CLASS(s->controller);
1259
1260 /*
1261 * Use the default segment value to size the memory region. This
1262 * can be changed by FW at runtime.
1263 */
1264 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
1265 s, name, s->asc->segments[s->cs].size);
1266 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
1267 }
1268
1269 static Property aspeed_smc_flash_properties[] = {
1270 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1271 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1272 AspeedSMCState *),
1273 DEFINE_PROP_END_OF_LIST(),
1274 };
1275
1276 static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data)
1277 {
1278 DeviceClass *dc = DEVICE_CLASS(klass);
1279
1280 dc->desc = "Aspeed SMC Flash device region";
1281 dc->realize = aspeed_smc_flash_realize;
1282 device_class_set_props(dc, aspeed_smc_flash_properties);
1283 }
1284
1285 static const TypeInfo aspeed_smc_flash_info = {
1286 .name = TYPE_ASPEED_SMC_FLASH,
1287 .parent = TYPE_SYS_BUS_DEVICE,
1288 .instance_size = sizeof(AspeedSMCFlash),
1289 .class_init = aspeed_smc_flash_class_init,
1290 };
1291
1292 /*
1293 * The Segment Registers of the AST2400 and AST2500 have a 8MB
1294 * unit. The address range of a flash SPI peripheral is encoded with
1295 * absolute addresses which should be part of the overall controller
1296 * window.
1297 */
1298 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
1299 const AspeedSegments *seg)
1300 {
1301 uint32_t reg = 0;
1302 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
1303 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
1304 return reg;
1305 }
1306
1307 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
1308 uint32_t reg, AspeedSegments *seg)
1309 {
1310 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
1311 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
1312 }
1313
1314 static const AspeedSegments aspeed_2400_smc_segments[] = {
1315 { 0x10000000, 32 * MiB },
1316 };
1317
1318 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data)
1319 {
1320 DeviceClass *dc = DEVICE_CLASS(klass);
1321 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1322
1323 dc->desc = "Aspeed 2400 SMC Controller";
1324 asc->r_conf = R_CONF;
1325 asc->r_ce_ctrl = R_CE_CTRL;
1326 asc->r_ctrl0 = R_CTRL0;
1327 asc->r_timings = R_TIMINGS;
1328 asc->nregs_timings = 1;
1329 asc->conf_enable_w0 = CONF_ENABLE_W0;
1330 asc->cs_num_max = 1;
1331 asc->segments = aspeed_2400_smc_segments;
1332 asc->flash_window_base = 0x10000000;
1333 asc->flash_window_size = 0x6000000;
1334 asc->features = 0x0;
1335 asc->nregs = ASPEED_SMC_R_SMC_MAX;
1336 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1337 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1338 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1339 }
1340
1341 static const TypeInfo aspeed_2400_smc_info = {
1342 .name = "aspeed.smc-ast2400",
1343 .parent = TYPE_ASPEED_SMC,
1344 .class_init = aspeed_2400_smc_class_init,
1345 };
1346
1347 static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = {
1348 /*
1349 * CE0 and CE1 types are HW strapped in SCU70. Do it here to
1350 * simplify the model.
1351 */
1352 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0,
1353 };
1354
1355 static const AspeedSegments aspeed_2400_fmc_segments[] = {
1356 { 0x20000000, 64 * MiB }, /* start address is readonly */
1357 { 0x24000000, 32 * MiB },
1358 { 0x26000000, 32 * MiB },
1359 { 0x28000000, 32 * MiB },
1360 { 0x2A000000, 32 * MiB }
1361 };
1362
1363 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
1364 {
1365 DeviceClass *dc = DEVICE_CLASS(klass);
1366 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1367
1368 dc->desc = "Aspeed 2400 FMC Controller";
1369 asc->r_conf = R_CONF;
1370 asc->r_ce_ctrl = R_CE_CTRL;
1371 asc->r_ctrl0 = R_CTRL0;
1372 asc->r_timings = R_TIMINGS;
1373 asc->nregs_timings = 1;
1374 asc->conf_enable_w0 = CONF_ENABLE_W0;
1375 asc->cs_num_max = 5;
1376 asc->segments = aspeed_2400_fmc_segments;
1377 asc->segment_addr_mask = 0xffff0000;
1378 asc->resets = aspeed_2400_fmc_resets;
1379 asc->flash_window_base = 0x20000000;
1380 asc->flash_window_size = 0x10000000;
1381 asc->features = ASPEED_SMC_FEATURE_DMA;
1382 asc->dma_flash_mask = 0x0FFFFFFC;
1383 asc->dma_dram_mask = 0x1FFFFFFC;
1384 asc->nregs = ASPEED_SMC_R_MAX;
1385 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1386 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1387 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1388 }
1389
1390 static const TypeInfo aspeed_2400_fmc_info = {
1391 .name = "aspeed.fmc-ast2400",
1392 .parent = TYPE_ASPEED_SMC,
1393 .class_init = aspeed_2400_fmc_class_init,
1394 };
1395
1396 static const AspeedSegments aspeed_2400_spi1_segments[] = {
1397 { 0x30000000, 64 * MiB },
1398 };
1399
1400 static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s)
1401 {
1402 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3;
1403 }
1404
1405 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
1406 {
1407 DeviceClass *dc = DEVICE_CLASS(klass);
1408 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1409
1410 dc->desc = "Aspeed 2400 SPI1 Controller";
1411 asc->r_conf = R_SPI_CONF;
1412 asc->r_ce_ctrl = 0xff;
1413 asc->r_ctrl0 = R_SPI_CTRL0;
1414 asc->r_timings = R_SPI_TIMINGS;
1415 asc->nregs_timings = 1;
1416 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0;
1417 asc->cs_num_max = 1;
1418 asc->segments = aspeed_2400_spi1_segments;
1419 asc->flash_window_base = 0x30000000;
1420 asc->flash_window_size = 0x10000000;
1421 asc->features = 0x0;
1422 asc->nregs = ASPEED_SMC_R_SPI_MAX;
1423 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1424 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1425 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1426 asc->addr_width = aspeed_2400_spi1_addr_width;
1427 }
1428
1429 static const TypeInfo aspeed_2400_spi1_info = {
1430 .name = "aspeed.spi1-ast2400",
1431 .parent = TYPE_ASPEED_SMC,
1432 .class_init = aspeed_2400_spi1_class_init,
1433 };
1434
1435 static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = {
1436 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1437 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1438 };
1439
1440 static const AspeedSegments aspeed_2500_fmc_segments[] = {
1441 { 0x20000000, 128 * MiB }, /* start address is readonly */
1442 { 0x28000000, 32 * MiB },
1443 { 0x2A000000, 32 * MiB },
1444 };
1445
1446 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
1447 {
1448 DeviceClass *dc = DEVICE_CLASS(klass);
1449 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1450
1451 dc->desc = "Aspeed 2600 FMC Controller";
1452 asc->r_conf = R_CONF;
1453 asc->r_ce_ctrl = R_CE_CTRL;
1454 asc->r_ctrl0 = R_CTRL0;
1455 asc->r_timings = R_TIMINGS;
1456 asc->nregs_timings = 1;
1457 asc->conf_enable_w0 = CONF_ENABLE_W0;
1458 asc->cs_num_max = 3;
1459 asc->segments = aspeed_2500_fmc_segments;
1460 asc->segment_addr_mask = 0xffff0000;
1461 asc->resets = aspeed_2500_fmc_resets;
1462 asc->flash_window_base = 0x20000000;
1463 asc->flash_window_size = 0x10000000;
1464 asc->features = ASPEED_SMC_FEATURE_DMA;
1465 asc->dma_flash_mask = 0x0FFFFFFC;
1466 asc->dma_dram_mask = 0x3FFFFFFC;
1467 asc->nregs = ASPEED_SMC_R_MAX;
1468 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1469 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1470 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1471 }
1472
1473 static const TypeInfo aspeed_2500_fmc_info = {
1474 .name = "aspeed.fmc-ast2500",
1475 .parent = TYPE_ASPEED_SMC,
1476 .class_init = aspeed_2500_fmc_class_init,
1477 };
1478
1479 static const AspeedSegments aspeed_2500_spi1_segments[] = {
1480 { 0x30000000, 32 * MiB }, /* start address is readonly */
1481 { 0x32000000, 96 * MiB }, /* end address is readonly */
1482 };
1483
1484 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
1485 {
1486 DeviceClass *dc = DEVICE_CLASS(klass);
1487 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1488
1489 dc->desc = "Aspeed 2600 SPI1 Controller";
1490 asc->r_conf = R_CONF;
1491 asc->r_ce_ctrl = R_CE_CTRL;
1492 asc->r_ctrl0 = R_CTRL0;
1493 asc->r_timings = R_TIMINGS;
1494 asc->nregs_timings = 1;
1495 asc->conf_enable_w0 = CONF_ENABLE_W0;
1496 asc->cs_num_max = 2;
1497 asc->segments = aspeed_2500_spi1_segments;
1498 asc->segment_addr_mask = 0xffff0000;
1499 asc->flash_window_base = 0x30000000;
1500 asc->flash_window_size = 0x8000000;
1501 asc->features = 0x0;
1502 asc->nregs = ASPEED_SMC_R_MAX;
1503 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1504 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1505 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1506 }
1507
1508 static const TypeInfo aspeed_2500_spi1_info = {
1509 .name = "aspeed.spi1-ast2500",
1510 .parent = TYPE_ASPEED_SMC,
1511 .class_init = aspeed_2500_spi1_class_init,
1512 };
1513
1514 static const AspeedSegments aspeed_2500_spi2_segments[] = {
1515 { 0x38000000, 32 * MiB }, /* start address is readonly */
1516 { 0x3A000000, 96 * MiB }, /* end address is readonly */
1517 };
1518
1519 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
1520 {
1521 DeviceClass *dc = DEVICE_CLASS(klass);
1522 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1523
1524 dc->desc = "Aspeed 2600 SPI2 Controller";
1525 asc->r_conf = R_CONF;
1526 asc->r_ce_ctrl = R_CE_CTRL;
1527 asc->r_ctrl0 = R_CTRL0;
1528 asc->r_timings = R_TIMINGS;
1529 asc->nregs_timings = 1;
1530 asc->conf_enable_w0 = CONF_ENABLE_W0;
1531 asc->cs_num_max = 2;
1532 asc->segments = aspeed_2500_spi2_segments;
1533 asc->segment_addr_mask = 0xffff0000;
1534 asc->flash_window_base = 0x38000000;
1535 asc->flash_window_size = 0x8000000;
1536 asc->features = 0x0;
1537 asc->nregs = ASPEED_SMC_R_MAX;
1538 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1539 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1540 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1541 }
1542
1543 static const TypeInfo aspeed_2500_spi2_info = {
1544 .name = "aspeed.spi2-ast2500",
1545 .parent = TYPE_ASPEED_SMC,
1546 .class_init = aspeed_2500_spi2_class_init,
1547 };
1548
1549 /*
1550 * The Segment Registers of the AST2600 have a 1MB unit. The address
1551 * range of a flash SPI peripheral is encoded with offsets in the overall
1552 * controller window. The previous SoC AST2400 and AST2500 used
1553 * absolute addresses. Only bits [27:20] are relevant and the end
1554 * address is an upper bound limit.
1555 */
1556 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1557
1558 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
1559 const AspeedSegments *seg)
1560 {
1561 uint32_t reg = 0;
1562
1563 /* Disabled segments have a nil register */
1564 if (!seg->size) {
1565 return 0;
1566 }
1567
1568 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
1569 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
1570 return reg;
1571 }
1572
1573 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
1574 uint32_t reg, AspeedSegments *seg)
1575 {
1576 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
1577 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
1578 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1579
1580 if (reg) {
1581 seg->addr = asc->flash_window_base + start_offset;
1582 seg->size = end_offset + MiB - start_offset;
1583 } else {
1584 seg->addr = asc->flash_window_base;
1585 seg->size = 0;
1586 }
1587 }
1588
1589 static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = {
1590 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1591 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |
1592 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2),
1593 };
1594
1595 static const AspeedSegments aspeed_2600_fmc_segments[] = {
1596 { 0x0, 128 * MiB }, /* start address is readonly */
1597 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1598 { 0x0, 0 }, /* disabled */
1599 };
1600
1601 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
1602 {
1603 DeviceClass *dc = DEVICE_CLASS(klass);
1604 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1605
1606 dc->desc = "Aspeed 2600 FMC Controller";
1607 asc->r_conf = R_CONF;
1608 asc->r_ce_ctrl = R_CE_CTRL;
1609 asc->r_ctrl0 = R_CTRL0;
1610 asc->r_timings = R_TIMINGS;
1611 asc->nregs_timings = 1;
1612 asc->conf_enable_w0 = CONF_ENABLE_W0;
1613 asc->cs_num_max = 3;
1614 asc->segments = aspeed_2600_fmc_segments;
1615 asc->segment_addr_mask = 0x0ff00ff0;
1616 asc->resets = aspeed_2600_fmc_resets;
1617 asc->flash_window_base = 0x20000000;
1618 asc->flash_window_size = 0x10000000;
1619 asc->features = ASPEED_SMC_FEATURE_DMA |
1620 ASPEED_SMC_FEATURE_WDT_CONTROL;
1621 asc->dma_flash_mask = 0x0FFFFFFC;
1622 asc->dma_dram_mask = 0x3FFFFFFC;
1623 asc->nregs = ASPEED_SMC_R_MAX;
1624 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1625 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1626 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1627 }
1628
1629 static const TypeInfo aspeed_2600_fmc_info = {
1630 .name = "aspeed.fmc-ast2600",
1631 .parent = TYPE_ASPEED_SMC,
1632 .class_init = aspeed_2600_fmc_class_init,
1633 };
1634
1635 static const AspeedSegments aspeed_2600_spi1_segments[] = {
1636 { 0x0, 128 * MiB }, /* start address is readonly */
1637 { 0x0, 0 }, /* disabled */
1638 };
1639
1640 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
1641 {
1642 DeviceClass *dc = DEVICE_CLASS(klass);
1643 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1644
1645 dc->desc = "Aspeed 2600 SPI1 Controller";
1646 asc->r_conf = R_CONF;
1647 asc->r_ce_ctrl = R_CE_CTRL;
1648 asc->r_ctrl0 = R_CTRL0;
1649 asc->r_timings = R_TIMINGS;
1650 asc->nregs_timings = 2;
1651 asc->conf_enable_w0 = CONF_ENABLE_W0;
1652 asc->cs_num_max = 2;
1653 asc->segments = aspeed_2600_spi1_segments;
1654 asc->segment_addr_mask = 0x0ff00ff0;
1655 asc->flash_window_base = 0x30000000;
1656 asc->flash_window_size = 0x10000000;
1657 asc->features = ASPEED_SMC_FEATURE_DMA |
1658 ASPEED_SMC_FEATURE_DMA_GRANT;
1659 asc->dma_flash_mask = 0x0FFFFFFC;
1660 asc->dma_dram_mask = 0x3FFFFFFC;
1661 asc->nregs = ASPEED_SMC_R_MAX;
1662 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1663 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1664 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1665 }
1666
1667 static const TypeInfo aspeed_2600_spi1_info = {
1668 .name = "aspeed.spi1-ast2600",
1669 .parent = TYPE_ASPEED_SMC,
1670 .class_init = aspeed_2600_spi1_class_init,
1671 };
1672
1673 static const AspeedSegments aspeed_2600_spi2_segments[] = {
1674 { 0x0, 128 * MiB }, /* start address is readonly */
1675 { 0x0, 0 }, /* disabled */
1676 { 0x0, 0 }, /* disabled */
1677 };
1678
1679 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
1680 {
1681 DeviceClass *dc = DEVICE_CLASS(klass);
1682 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1683
1684 dc->desc = "Aspeed 2600 SPI2 Controller";
1685 asc->r_conf = R_CONF;
1686 asc->r_ce_ctrl = R_CE_CTRL;
1687 asc->r_ctrl0 = R_CTRL0;
1688 asc->r_timings = R_TIMINGS;
1689 asc->nregs_timings = 3;
1690 asc->conf_enable_w0 = CONF_ENABLE_W0;
1691 asc->cs_num_max = 3;
1692 asc->segments = aspeed_2600_spi2_segments;
1693 asc->segment_addr_mask = 0x0ff00ff0;
1694 asc->flash_window_base = 0x50000000;
1695 asc->flash_window_size = 0x10000000;
1696 asc->features = ASPEED_SMC_FEATURE_DMA |
1697 ASPEED_SMC_FEATURE_DMA_GRANT;
1698 asc->dma_flash_mask = 0x0FFFFFFC;
1699 asc->dma_dram_mask = 0x3FFFFFFC;
1700 asc->nregs = ASPEED_SMC_R_MAX;
1701 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1702 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1703 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1704 }
1705
1706 static const TypeInfo aspeed_2600_spi2_info = {
1707 .name = "aspeed.spi2-ast2600",
1708 .parent = TYPE_ASPEED_SMC,
1709 .class_init = aspeed_2600_spi2_class_init,
1710 };
1711
1712 /*
1713 * The FMC Segment Registers of the AST1030 have a 512KB unit.
1714 * Only bits [27:19] are used for decoding.
1715 */
1716 #define AST1030_SEG_ADDR_MASK 0x0ff80000
1717
1718 static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s,
1719 const AspeedSegments *seg)
1720 {
1721 uint32_t reg = 0;
1722
1723 /* Disabled segments have a nil register */
1724 if (!seg->size) {
1725 return 0;
1726 }
1727
1728 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */
1729 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */
1730 return reg;
1731 }
1732
1733 static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s,
1734 uint32_t reg, AspeedSegments *seg)
1735 {
1736 uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK;
1737 uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK;
1738 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1739
1740 if (reg) {
1741 seg->addr = asc->flash_window_base + start_offset;
1742 seg->size = end_offset + (512 * KiB) - start_offset;
1743 } else {
1744 seg->addr = asc->flash_window_base;
1745 seg->size = 0;
1746 }
1747 }
1748
1749 static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = {
1750 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1751 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1752 };
1753
1754 static const AspeedSegments aspeed_1030_fmc_segments[] = {
1755 { 0x0, 128 * MiB }, /* start address is readonly */
1756 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1757 { 0x0, 0 }, /* disabled */
1758 };
1759
1760 static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data)
1761 {
1762 DeviceClass *dc = DEVICE_CLASS(klass);
1763 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1764
1765 dc->desc = "Aspeed 1030 FMC Controller";
1766 asc->r_conf = R_CONF;
1767 asc->r_ce_ctrl = R_CE_CTRL;
1768 asc->r_ctrl0 = R_CTRL0;
1769 asc->r_timings = R_TIMINGS;
1770 asc->nregs_timings = 2;
1771 asc->conf_enable_w0 = CONF_ENABLE_W0;
1772 asc->cs_num_max = 2;
1773 asc->segments = aspeed_1030_fmc_segments;
1774 asc->segment_addr_mask = 0x0ff80ff8;
1775 asc->resets = aspeed_1030_fmc_resets;
1776 asc->flash_window_base = 0x80000000;
1777 asc->flash_window_size = 0x10000000;
1778 asc->features = ASPEED_SMC_FEATURE_DMA;
1779 asc->dma_flash_mask = 0x0FFFFFFC;
1780 asc->dma_dram_mask = 0x000BFFFC;
1781 asc->nregs = ASPEED_SMC_R_MAX;
1782 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg;
1783 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment;
1784 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1785 }
1786
1787 static const TypeInfo aspeed_1030_fmc_info = {
1788 .name = "aspeed.fmc-ast1030",
1789 .parent = TYPE_ASPEED_SMC,
1790 .class_init = aspeed_1030_fmc_class_init,
1791 };
1792
1793 static const AspeedSegments aspeed_1030_spi1_segments[] = {
1794 { 0x0, 128 * MiB }, /* start address is readonly */
1795 { 0x0, 0 }, /* disabled */
1796 };
1797
1798 static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data)
1799 {
1800 DeviceClass *dc = DEVICE_CLASS(klass);
1801 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1802
1803 dc->desc = "Aspeed 1030 SPI1 Controller";
1804 asc->r_conf = R_CONF;
1805 asc->r_ce_ctrl = R_CE_CTRL;
1806 asc->r_ctrl0 = R_CTRL0;
1807 asc->r_timings = R_TIMINGS;
1808 asc->nregs_timings = 2;
1809 asc->conf_enable_w0 = CONF_ENABLE_W0;
1810 asc->cs_num_max = 2;
1811 asc->segments = aspeed_1030_spi1_segments;
1812 asc->segment_addr_mask = 0x0ff00ff0;
1813 asc->flash_window_base = 0x90000000;
1814 asc->flash_window_size = 0x10000000;
1815 asc->features = ASPEED_SMC_FEATURE_DMA;
1816 asc->dma_flash_mask = 0x0FFFFFFC;
1817 asc->dma_dram_mask = 0x000BFFFC;
1818 asc->nregs = ASPEED_SMC_R_MAX;
1819 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1820 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1821 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1822 }
1823
1824 static const TypeInfo aspeed_1030_spi1_info = {
1825 .name = "aspeed.spi1-ast1030",
1826 .parent = TYPE_ASPEED_SMC,
1827 .class_init = aspeed_1030_spi1_class_init,
1828 };
1829 static const AspeedSegments aspeed_1030_spi2_segments[] = {
1830 { 0x0, 128 * MiB }, /* start address is readonly */
1831 { 0x0, 0 }, /* disabled */
1832 };
1833
1834 static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data)
1835 {
1836 DeviceClass *dc = DEVICE_CLASS(klass);
1837 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1838
1839 dc->desc = "Aspeed 1030 SPI2 Controller";
1840 asc->r_conf = R_CONF;
1841 asc->r_ce_ctrl = R_CE_CTRL;
1842 asc->r_ctrl0 = R_CTRL0;
1843 asc->r_timings = R_TIMINGS;
1844 asc->nregs_timings = 2;
1845 asc->conf_enable_w0 = CONF_ENABLE_W0;
1846 asc->cs_num_max = 2;
1847 asc->segments = aspeed_1030_spi2_segments;
1848 asc->segment_addr_mask = 0x0ff00ff0;
1849 asc->flash_window_base = 0xb0000000;
1850 asc->flash_window_size = 0x10000000;
1851 asc->features = ASPEED_SMC_FEATURE_DMA;
1852 asc->dma_flash_mask = 0x0FFFFFFC;
1853 asc->dma_dram_mask = 0x000BFFFC;
1854 asc->nregs = ASPEED_SMC_R_MAX;
1855 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1856 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1857 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1858 }
1859
1860 static const TypeInfo aspeed_1030_spi2_info = {
1861 .name = "aspeed.spi2-ast1030",
1862 .parent = TYPE_ASPEED_SMC,
1863 .class_init = aspeed_1030_spi2_class_init,
1864 };
1865
1866 static void aspeed_smc_register_types(void)
1867 {
1868 type_register_static(&aspeed_smc_flash_info);
1869 type_register_static(&aspeed_smc_info);
1870 type_register_static(&aspeed_2400_smc_info);
1871 type_register_static(&aspeed_2400_fmc_info);
1872 type_register_static(&aspeed_2400_spi1_info);
1873 type_register_static(&aspeed_2500_fmc_info);
1874 type_register_static(&aspeed_2500_spi1_info);
1875 type_register_static(&aspeed_2500_spi2_info);
1876 type_register_static(&aspeed_2600_fmc_info);
1877 type_register_static(&aspeed_2600_spi1_info);
1878 type_register_static(&aspeed_2600_spi2_info);
1879 type_register_static(&aspeed_1030_fmc_info);
1880 type_register_static(&aspeed_1030_spi1_info);
1881 type_register_static(&aspeed_1030_spi2_info);
1882 }
1883
1884 type_init(aspeed_smc_register_types)
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