4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/datadir.h"
27 #include "qemu/units.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bridge.h"
31 #include "hw/pci/pci_bus.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
35 #include "migration/qemu-file-types.h"
36 #include "migration/vmstate.h"
38 #include "sysemu/numa.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "hw/loader.h"
42 #include "qemu/error-report.h"
43 #include "qemu/range.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "hw/hotplug.h"
48 #include "hw/boards.h"
49 #include "qapi/error.h"
50 #include "qemu/cutils.h"
51 #include "pci-internal.h"
53 #include "hw/xen/xen.h"
54 #include "hw/i386/kvm/xen_evtchn.h"
58 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
60 # define PCI_DPRINTF(format, ...) do { } while (0)
63 bool pci_available
= true;
65 static char *pcibus_get_dev_path(DeviceState
*dev
);
66 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
67 static void pcibus_reset_hold(Object
*obj
);
68 static bool pcie_has_upstream_port(PCIDevice
*dev
);
70 static Property pci_props
[] = {
71 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
72 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
73 DEFINE_PROP_UINT32("romsize", PCIDevice
, romsize
, -1),
74 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
75 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
76 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
77 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
78 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
79 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
80 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
81 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
83 DEFINE_PROP_UINT32("acpi-index", PCIDevice
, acpi_index
, 0),
84 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice
, cap_present
,
85 QEMU_PCIE_ERR_UNC_MASK_BITNR
, true),
86 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice
, cap_present
,
87 QEMU_PCIE_ARI_NEXTFN_1_BITNR
, false),
88 DEFINE_PROP_END_OF_LIST()
91 static const VMStateDescription vmstate_pcibus
= {
94 .minimum_version_id
= 1,
95 .fields
= (const VMStateField
[]) {
96 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
97 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
98 nirq
, 0, vmstate_info_int32
,
100 VMSTATE_END_OF_LIST()
104 static gint
g_cmp_uint32(gconstpointer a
, gconstpointer b
, gpointer user_data
)
109 static GSequence
*pci_acpi_index_list(void)
111 static GSequence
*used_acpi_index_list
;
113 if (!used_acpi_index_list
) {
114 used_acpi_index_list
= g_sequence_new(NULL
);
116 return used_acpi_index_list
;
119 static void pci_init_bus_master(PCIDevice
*pci_dev
)
121 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
123 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
124 OBJECT(pci_dev
), "bus master",
125 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
126 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
127 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
128 &pci_dev
->bus_master_enable_region
);
131 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
133 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
136 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
137 if (bus
->devices
[i
]) {
138 pci_init_bus_master(bus
->devices
[i
]);
143 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
145 PCIBus
*bus
= PCI_BUS(qbus
);
147 bus
->machine_done
.notify
= pcibus_machine_done
;
148 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
150 vmstate_register_any(NULL
, &vmstate_pcibus
, bus
);
153 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
155 PCIBus
*bus
= PCI_BUS(qbus
);
156 Error
*local_err
= NULL
;
158 pci_bus_realize(qbus
, &local_err
);
160 error_propagate(errp
, local_err
);
165 * A PCI-E bus can support extended config space if it's the root
166 * bus, or if the bus/bridge above it does as well
168 if (pci_bus_is_root(bus
)) {
169 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
171 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
173 if (pci_bus_allows_extended_config_space(parent_bus
)) {
174 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
179 static void pci_bus_unrealize(BusState
*qbus
)
181 PCIBus
*bus
= PCI_BUS(qbus
);
183 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
185 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
188 static int pcibus_num(PCIBus
*bus
)
190 if (pci_bus_is_root(bus
)) {
191 return 0; /* pci host bridge */
193 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
196 static uint16_t pcibus_numa_node(PCIBus
*bus
)
198 return NUMA_NODE_UNASSIGNED
;
201 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
203 BusClass
*k
= BUS_CLASS(klass
);
204 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
205 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
207 k
->print_dev
= pcibus_dev_print
;
208 k
->get_dev_path
= pcibus_get_dev_path
;
209 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
210 k
->realize
= pci_bus_realize
;
211 k
->unrealize
= pci_bus_unrealize
;
213 rc
->phases
.hold
= pcibus_reset_hold
;
215 pbc
->bus_num
= pcibus_num
;
216 pbc
->numa_node
= pcibus_numa_node
;
219 static const TypeInfo pci_bus_info
= {
220 .name
= TYPE_PCI_BUS
,
222 .instance_size
= sizeof(PCIBus
),
223 .class_size
= sizeof(PCIBusClass
),
224 .class_init
= pci_bus_class_init
,
227 static const TypeInfo cxl_interface_info
= {
228 .name
= INTERFACE_CXL_DEVICE
,
229 .parent
= TYPE_INTERFACE
,
232 static const TypeInfo pcie_interface_info
= {
233 .name
= INTERFACE_PCIE_DEVICE
,
234 .parent
= TYPE_INTERFACE
,
237 static const TypeInfo conventional_pci_interface_info
= {
238 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
239 .parent
= TYPE_INTERFACE
,
242 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
244 BusClass
*k
= BUS_CLASS(klass
);
246 k
->realize
= pcie_bus_realize
;
249 static const TypeInfo pcie_bus_info
= {
250 .name
= TYPE_PCIE_BUS
,
251 .parent
= TYPE_PCI_BUS
,
252 .class_init
= pcie_bus_class_init
,
255 static const TypeInfo cxl_bus_info
= {
256 .name
= TYPE_CXL_BUS
,
257 .parent
= TYPE_PCIE_BUS
,
258 .class_init
= pcie_bus_class_init
,
261 static void pci_update_mappings(PCIDevice
*d
);
262 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
263 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
264 static void pci_del_option_rom(PCIDevice
*pdev
);
266 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
267 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
269 PCIHostStateList pci_host_bridges
;
271 int pci_bar(PCIDevice
*d
, int reg
)
275 /* PCIe virtual functions do not have their own BARs */
276 assert(!pci_is_vf(d
));
278 if (reg
!= PCI_ROM_SLOT
)
279 return PCI_BASE_ADDRESS_0
+ reg
* 4;
281 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
282 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
285 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
287 return (d
->irq_state
>> irq_num
) & 0x1;
290 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
292 d
->irq_state
&= ~(0x1 << irq_num
);
293 d
->irq_state
|= level
<< irq_num
;
296 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
298 assert(irq_num
>= 0);
299 assert(irq_num
< bus
->nirq
);
300 bus
->irq_count
[irq_num
] += change
;
301 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
304 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
308 int dev_irq
= irq_num
;
309 bus
= pci_get_bus(pci_dev
);
310 assert(bus
->map_irq
);
311 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
312 trace_pci_route_irq(dev_irq
, DEVICE(pci_dev
)->canonical_path
, irq_num
,
313 pci_bus_is_root(bus
) ? "root-complex"
314 : DEVICE(bus
->parent_dev
)->canonical_path
);
317 pci_dev
= bus
->parent_dev
;
319 pci_bus_change_irq_level(bus
, irq_num
, change
);
322 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
324 assert(irq_num
>= 0);
325 assert(irq_num
< bus
->nirq
);
326 return !!bus
->irq_count
[irq_num
];
329 /* Update interrupt status bit in config space on interrupt
331 static void pci_update_irq_status(PCIDevice
*dev
)
333 if (dev
->irq_state
) {
334 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
336 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
340 void pci_device_deassert_intx(PCIDevice
*dev
)
343 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
344 pci_irq_handler(dev
, i
, 0);
348 static void pci_msi_trigger(PCIDevice
*dev
, MSIMessage msg
)
350 MemTxAttrs attrs
= {};
353 * Xen uses the high bits of the address to contain some of the bits
354 * of the PIRQ#. Therefore we can't just send the write cycle and
355 * trust that it's caught by the APIC at 0xfee00000 because the
356 * target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166.
357 * So we intercept the delivery here instead of in kvm_send_msi().
359 if (xen_mode
== XEN_EMULATE
&&
360 xen_evtchn_deliver_pirq_msi(msg
.address
, msg
.data
)) {
363 attrs
.requester_id
= pci_requester_id(dev
);
364 address_space_stl_le(&dev
->bus_master_as
, msg
.address
, msg
.data
,
368 static void pci_reset_regions(PCIDevice
*dev
)
371 if (pci_is_vf(dev
)) {
375 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
376 PCIIORegion
*region
= &dev
->io_regions
[r
];
381 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
382 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
383 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
385 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
390 static void pci_do_device_reset(PCIDevice
*dev
)
392 pci_device_deassert_intx(dev
);
393 assert(dev
->irq_state
== 0);
395 /* Clear all writable bits */
396 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
397 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
398 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
399 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
400 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
401 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
402 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
403 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
404 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
405 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
406 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
407 pci_reset_regions(dev
);
408 pci_update_mappings(dev
);
412 pcie_sriov_pf_reset(dev
);
416 * This function is called on #RST and FLR.
417 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
419 void pci_device_reset(PCIDevice
*dev
)
421 device_cold_reset(&dev
->qdev
);
422 pci_do_device_reset(dev
);
426 * Trigger pci bus reset under a given bus.
427 * Called via bus_cold_reset on RST# assert, after the devices
428 * have been reset device_cold_reset-ed already.
430 static void pcibus_reset_hold(Object
*obj
)
432 PCIBus
*bus
= PCI_BUS(obj
);
435 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
436 if (bus
->devices
[i
]) {
437 pci_do_device_reset(bus
->devices
[i
]);
441 for (i
= 0; i
< bus
->nirq
; i
++) {
442 assert(bus
->irq_count
[i
] == 0);
446 static void pci_host_bus_register(DeviceState
*host
)
448 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
450 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
453 static void pci_host_bus_unregister(DeviceState
*host
)
455 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
457 QLIST_REMOVE(host_bridge
, next
);
460 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
462 PCIBus
*bus
= pci_get_bus(d
);
464 while (!pci_bus_is_root(bus
)) {
468 bus
= pci_get_bus(d
);
474 const char *pci_root_bus_path(PCIDevice
*dev
)
476 PCIBus
*rootbus
= pci_device_root_bus(dev
);
477 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
478 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
480 assert(host_bridge
->bus
== rootbus
);
482 if (hc
->root_bus_path
) {
483 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
486 return rootbus
->qbus
.name
;
489 bool pci_bus_bypass_iommu(PCIBus
*bus
)
491 PCIBus
*rootbus
= bus
;
492 PCIHostState
*host_bridge
;
494 if (!pci_bus_is_root(bus
)) {
495 rootbus
= pci_device_root_bus(bus
->parent_dev
);
498 host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
500 assert(host_bridge
->bus
== rootbus
);
502 return host_bridge
->bypass_iommu
;
505 static void pci_root_bus_internal_init(PCIBus
*bus
, DeviceState
*parent
,
506 MemoryRegion
*mem
, MemoryRegion
*io
,
509 assert(PCI_FUNC(devfn_min
) == 0);
510 bus
->devfn_min
= devfn_min
;
511 bus
->slot_reserved_mask
= 0x0;
512 bus
->address_space_mem
= mem
;
513 bus
->address_space_io
= io
;
514 bus
->flags
|= PCI_BUS_IS_ROOT
;
517 QLIST_INIT(&bus
->child
);
519 pci_host_bus_register(parent
);
522 static void pci_bus_uninit(PCIBus
*bus
)
524 pci_host_bus_unregister(BUS(bus
)->parent
);
527 bool pci_bus_is_express(const PCIBus
*bus
)
529 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
532 void pci_root_bus_init(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
534 MemoryRegion
*mem
, MemoryRegion
*io
,
535 uint8_t devfn_min
, const char *typename
)
537 qbus_init(bus
, bus_size
, typename
, parent
, name
);
538 pci_root_bus_internal_init(bus
, parent
, mem
, io
, devfn_min
);
541 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
542 MemoryRegion
*mem
, MemoryRegion
*io
,
543 uint8_t devfn_min
, const char *typename
)
547 bus
= PCI_BUS(qbus_new(typename
, parent
, name
));
548 pci_root_bus_internal_init(bus
, parent
, mem
, io
, devfn_min
);
552 void pci_root_bus_cleanup(PCIBus
*bus
)
555 /* the caller of the unplug hotplug handler will delete this device */
556 qbus_unrealize(BUS(bus
));
559 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
,
560 void *irq_opaque
, int nirq
)
562 bus
->set_irq
= set_irq
;
563 bus
->irq_opaque
= irq_opaque
;
565 g_free(bus
->irq_count
);
566 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
569 void pci_bus_map_irqs(PCIBus
*bus
, pci_map_irq_fn map_irq
)
571 bus
->map_irq
= map_irq
;
574 void pci_bus_irqs_cleanup(PCIBus
*bus
)
578 bus
->irq_opaque
= NULL
;
580 g_free(bus
->irq_count
);
581 bus
->irq_count
= NULL
;
584 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
585 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
587 MemoryRegion
*mem
, MemoryRegion
*io
,
588 uint8_t devfn_min
, int nirq
,
589 const char *typename
)
593 bus
= pci_root_bus_new(parent
, name
, mem
, io
, devfn_min
, typename
);
594 pci_bus_irqs(bus
, set_irq
, irq_opaque
, nirq
);
595 pci_bus_map_irqs(bus
, map_irq
);
599 void pci_unregister_root_bus(PCIBus
*bus
)
601 pci_bus_irqs_cleanup(bus
);
602 pci_root_bus_cleanup(bus
);
605 int pci_bus_num(PCIBus
*s
)
607 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
610 /* Returns the min and max bus numbers of a PCI bus hierarchy */
611 void pci_bus_range(PCIBus
*bus
, int *min_bus
, int *max_bus
)
614 *min_bus
= *max_bus
= pci_bus_num(bus
);
616 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
617 PCIDevice
*dev
= bus
->devices
[i
];
619 if (dev
&& IS_PCI_BRIDGE(dev
)) {
620 *min_bus
= MIN(*min_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
621 *max_bus
= MAX(*max_bus
, dev
->config
[PCI_SUBORDINATE_BUS
]);
626 int pci_bus_numa_node(PCIBus
*bus
)
628 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
631 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
632 const VMStateField
*field
)
634 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
638 assert(size
== pci_config_size(s
));
639 config
= g_malloc(size
);
641 qemu_get_buffer(f
, config
, size
);
642 for (i
= 0; i
< size
; ++i
) {
643 if ((config
[i
] ^ s
->config
[i
]) &
644 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
645 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
646 "cmask: %x wmask: %x w1cmask:%x", __func__
,
647 i
, config
[i
], s
->config
[i
],
648 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
653 memcpy(s
->config
, config
, size
);
655 pci_update_mappings(s
);
656 if (IS_PCI_BRIDGE(s
)) {
657 pci_bridge_update_mappings(PCI_BRIDGE(s
));
660 memory_region_set_enabled(&s
->bus_master_enable_region
,
661 pci_get_word(s
->config
+ PCI_COMMAND
)
662 & PCI_COMMAND_MASTER
);
668 /* just put buffer */
669 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
670 const VMStateField
*field
, JSONWriter
*vmdesc
)
672 const uint8_t **v
= pv
;
673 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
674 qemu_put_buffer(f
, *v
, size
);
679 static const VMStateInfo vmstate_info_pci_config
= {
680 .name
= "pci config",
681 .get
= get_pci_config_device
,
682 .put
= put_pci_config_device
,
685 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
686 const VMStateField
*field
)
688 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
689 uint32_t irq_state
[PCI_NUM_PINS
];
691 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
692 irq_state
[i
] = qemu_get_be32(f
);
693 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
694 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
700 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
701 pci_set_irq_state(s
, i
, irq_state
[i
]);
707 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
708 const VMStateField
*field
, JSONWriter
*vmdesc
)
711 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
713 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
714 qemu_put_be32(f
, pci_irq_state(s
, i
));
720 static const VMStateInfo vmstate_info_pci_irq_state
= {
721 .name
= "pci irq state",
722 .get
= get_pci_irq_state
,
723 .put
= put_pci_irq_state
,
726 static bool migrate_is_pcie(void *opaque
, int version_id
)
728 return pci_is_express((PCIDevice
*)opaque
);
731 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
733 return !pci_is_express((PCIDevice
*)opaque
);
736 const VMStateDescription vmstate_pci_device
= {
739 .minimum_version_id
= 1,
740 .fields
= (const VMStateField
[]) {
741 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
742 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
744 0, vmstate_info_pci_config
,
745 PCI_CONFIG_SPACE_SIZE
),
746 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
748 0, vmstate_info_pci_config
,
749 PCIE_CONFIG_SPACE_SIZE
),
750 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
751 vmstate_info_pci_irq_state
,
752 PCI_NUM_PINS
* sizeof(int32_t)),
753 VMSTATE_END_OF_LIST()
758 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
760 /* Clear interrupt status bit: it is implicit
761 * in irq_state which we are saving.
762 * This makes us compatible with old devices
763 * which never set or clear this bit. */
764 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
765 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
766 /* Restore the interrupt status bit. */
767 pci_update_irq_status(s
);
770 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
773 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
774 /* Restore the interrupt status bit. */
775 pci_update_irq_status(s
);
779 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
781 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
782 pci_default_sub_vendor_id
);
783 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
784 pci_default_sub_device_id
);
788 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
789 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
791 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
792 unsigned int *slotp
, unsigned int *funcp
)
797 unsigned long dom
= 0, bus
= 0;
798 unsigned int slot
= 0;
799 unsigned int func
= 0;
802 val
= strtoul(p
, &e
, 16);
808 val
= strtoul(p
, &e
, 16);
815 val
= strtoul(p
, &e
, 16);
828 val
= strtoul(p
, &e
, 16);
835 /* if funcp == NULL func is 0 */
836 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
850 static void pci_init_cmask(PCIDevice
*dev
)
852 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
853 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
854 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
855 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
856 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
857 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
858 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
859 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
862 static void pci_init_wmask(PCIDevice
*dev
)
864 int config_size
= pci_config_size(dev
);
866 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
867 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
868 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
869 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
870 PCI_COMMAND_INTX_DISABLE
);
871 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
873 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
874 config_size
- PCI_CONFIG_HEADER_SIZE
);
877 static void pci_init_w1cmask(PCIDevice
*dev
)
880 * Note: It's okay to set w1cmask even for readonly bits as
881 * long as their value is hardwired to 0.
883 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
884 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
885 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
886 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
889 static void pci_init_mask_bridge(PCIDevice
*d
)
891 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
892 PCI_SEC_LATENCY_TIMER */
893 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
896 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
897 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
898 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
899 PCI_MEMORY_RANGE_MASK
& 0xffff);
900 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
901 PCI_MEMORY_RANGE_MASK
& 0xffff);
902 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
903 PCI_PREF_RANGE_MASK
& 0xffff);
904 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
905 PCI_PREF_RANGE_MASK
& 0xffff);
907 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
908 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
910 /* Supported memory and i/o types */
911 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
912 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
913 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
914 PCI_PREF_RANGE_TYPE_64
);
915 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
916 PCI_PREF_RANGE_TYPE_64
);
919 * TODO: Bridges default to 10-bit VGA decoding but we currently only
920 * implement 16-bit decoding (no alias support).
922 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
923 PCI_BRIDGE_CTL_PARITY
|
924 PCI_BRIDGE_CTL_SERR
|
927 PCI_BRIDGE_CTL_VGA_16BIT
|
928 PCI_BRIDGE_CTL_MASTER_ABORT
|
929 PCI_BRIDGE_CTL_BUS_RESET
|
930 PCI_BRIDGE_CTL_FAST_BACK
|
931 PCI_BRIDGE_CTL_DISCARD
|
932 PCI_BRIDGE_CTL_SEC_DISCARD
|
933 PCI_BRIDGE_CTL_DISCARD_SERR
);
934 /* Below does not do anything as we never set this bit, put here for
936 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
937 PCI_BRIDGE_CTL_DISCARD_STATUS
);
938 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
939 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
940 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
941 PCI_PREF_RANGE_TYPE_MASK
);
942 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
943 PCI_PREF_RANGE_TYPE_MASK
);
946 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
948 uint8_t slot
= PCI_SLOT(dev
->devfn
);
951 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
952 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
956 * With SR/IOV and ARI, a device at function 0 need not be a multifunction
957 * device, as it may just be a VF that ended up with function 0 in
958 * the legacy PCI interpretation. Avoid failing in such cases:
960 if (pci_is_vf(dev
) &&
961 dev
->exp
.sriov_vf
.pf
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
966 * multifunction bit is interpreted in two ways as follows.
967 * - all functions must set the bit to 1.
969 * - function 0 must set the bit, but the rest function (> 0)
970 * is allowed to leave the bit to 0.
971 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
973 * So OS (at least Linux) checks the bit of only function 0,
974 * and doesn't see the bit of function > 0.
976 * The below check allows both interpretation.
978 if (PCI_FUNC(dev
->devfn
)) {
979 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
980 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
981 /* function 0 should set multifunction bit */
982 error_setg(errp
, "PCI: single function device can't be populated "
983 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
989 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
992 /* function 0 indicates single function, so function > 0 must be NULL */
993 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
994 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
995 error_setg(errp
, "PCI: %x.0 indicates single function, "
996 "but %x.%x is already populated.",
1003 static void pci_config_alloc(PCIDevice
*pci_dev
)
1005 int config_size
= pci_config_size(pci_dev
);
1007 pci_dev
->config
= g_malloc0(config_size
);
1008 pci_dev
->cmask
= g_malloc0(config_size
);
1009 pci_dev
->wmask
= g_malloc0(config_size
);
1010 pci_dev
->w1cmask
= g_malloc0(config_size
);
1011 pci_dev
->used
= g_malloc0(config_size
);
1014 static void pci_config_free(PCIDevice
*pci_dev
)
1016 g_free(pci_dev
->config
);
1017 g_free(pci_dev
->cmask
);
1018 g_free(pci_dev
->wmask
);
1019 g_free(pci_dev
->w1cmask
);
1020 g_free(pci_dev
->used
);
1023 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
1025 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
1026 pci_config_free(pci_dev
);
1028 if (xen_mode
== XEN_EMULATE
) {
1029 xen_evtchn_remove_pci_device(pci_dev
);
1031 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
1032 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
1033 &pci_dev
->bus_master_enable_region
);
1035 address_space_destroy(&pci_dev
->bus_master_as
);
1038 /* Extract PCIReqIDCache into BDF format */
1039 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
1044 switch (cache
->type
) {
1045 case PCI_REQ_ID_BDF
:
1046 result
= pci_get_bdf(cache
->dev
);
1048 case PCI_REQ_ID_SECONDARY_BUS
:
1049 bus_n
= pci_dev_bus_num(cache
->dev
);
1050 result
= PCI_BUILD_BDF(bus_n
, 0);
1053 error_report("Invalid PCI requester ID cache type: %d",
1062 /* Parse bridges up to the root complex and return requester ID
1063 * cache for specific device. For full PCIe topology, the cache
1064 * result would be exactly the same as getting BDF of the device.
1065 * However, several tricks are required when system mixed up with
1066 * legacy PCI devices and PCIe-to-PCI bridges.
1068 * Here we cache the proxy device (and type) not requester ID since
1069 * bus number might change from time to time.
1071 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
1074 PCIReqIDCache cache
= {
1076 .type
= PCI_REQ_ID_BDF
,
1079 while (!pci_bus_is_root(pci_get_bus(dev
))) {
1080 /* We are under PCI/PCIe bridges */
1081 parent
= pci_get_bus(dev
)->parent_dev
;
1082 if (pci_is_express(parent
)) {
1083 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
1084 /* When we pass through PCIe-to-PCI/PCIX bridges, we
1085 * override the requester ID using secondary bus
1086 * number of parent bridge with zeroed devfn
1087 * (pcie-to-pci bridge spec chap 2.3). */
1088 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
1092 /* Legacy PCI, override requester ID with the bridge's
1093 * BDF upstream. When the root complex connects to
1094 * legacy PCI devices (including buses), it can only
1095 * obtain requester ID info from directly attached
1096 * devices. If devices are attached under bridges, only
1097 * the requester ID of the bridge that is directly
1098 * attached to the root complex can be recognized. */
1099 cache
.type
= PCI_REQ_ID_BDF
;
1108 uint16_t pci_requester_id(PCIDevice
*dev
)
1110 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
1113 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
1115 return !(bus
->devices
[devfn
]);
1118 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
1120 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
1123 uint32_t pci_bus_get_slot_reserved_mask(PCIBus
*bus
)
1125 return bus
->slot_reserved_mask
;
1128 void pci_bus_set_slot_reserved_mask(PCIBus
*bus
, uint32_t mask
)
1130 bus
->slot_reserved_mask
|= mask
;
1133 void pci_bus_clear_slot_reserved_mask(PCIBus
*bus
, uint32_t mask
)
1135 bus
->slot_reserved_mask
&= ~mask
;
1138 /* -1 for devfn means auto assign */
1139 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1140 const char *name
, int devfn
,
1143 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1144 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1145 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1146 Error
*local_err
= NULL
;
1147 DeviceState
*dev
= DEVICE(pci_dev
);
1148 PCIBus
*bus
= pci_get_bus(pci_dev
);
1149 bool is_bridge
= IS_PCI_BRIDGE(pci_dev
);
1151 /* Only pci bridges can be attached to extra PCI root buses */
1152 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !is_bridge
) {
1154 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1155 bus
->parent_dev
->name
);
1160 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1161 devfn
+= PCI_FUNC_MAX
) {
1162 if (pci_bus_devfn_available(bus
, devfn
) &&
1163 !pci_bus_devfn_reserved(bus
, devfn
)) {
1167 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1168 "or reserved", name
);
1171 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1172 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1174 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1176 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1177 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1178 " in use by %s,id=%s",
1179 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1180 bus
->devices
[devfn
]->name
, bus
->devices
[devfn
]->qdev
.id
);
1183 * Populating function 0 triggers a scan from the guest that
1184 * exposes other non-zero functions. Hence we need to ensure that
1185 * function 0 wasn't added yet.
1187 else if (dev
->hotplugged
&&
1188 !pci_is_vf(pci_dev
) &&
1189 pci_get_function_0(pci_dev
)) {
1190 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1191 " new func %s cannot be exposed to guest.",
1192 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1193 pci_get_function_0(pci_dev
)->name
,
1199 pci_dev
->devfn
= devfn
;
1200 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1201 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1203 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1204 "bus master container", UINT64_MAX
);
1205 address_space_init(&pci_dev
->bus_master_as
,
1206 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1208 if (phase_check(PHASE_MACHINE_READY
)) {
1209 pci_init_bus_master(pci_dev
);
1211 pci_dev
->irq_state
= 0;
1212 pci_config_alloc(pci_dev
);
1214 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1215 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1216 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1217 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1220 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1221 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1222 pc
->subsystem_vendor_id
);
1223 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1226 pci_set_default_subsystem_id(pci_dev
);
1229 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1230 assert(!pc
->subsystem_vendor_id
);
1231 assert(!pc
->subsystem_id
);
1233 pci_init_cmask(pci_dev
);
1234 pci_init_wmask(pci_dev
);
1235 pci_init_w1cmask(pci_dev
);
1237 pci_init_mask_bridge(pci_dev
);
1239 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1241 error_propagate(errp
, local_err
);
1242 do_pci_unregister_device(pci_dev
);
1247 config_read
= pci_default_read_config
;
1249 config_write
= pci_default_write_config
;
1250 pci_dev
->config_read
= config_read
;
1251 pci_dev
->config_write
= config_write
;
1252 bus
->devices
[devfn
] = pci_dev
;
1253 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1257 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1262 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1263 r
= &pci_dev
->io_regions
[i
];
1264 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1266 memory_region_del_subregion(r
->address_space
, r
->memory
);
1269 pci_unregister_vga(pci_dev
);
1272 static void pci_qdev_unrealize(DeviceState
*dev
)
1274 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1275 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1277 pci_unregister_io_regions(pci_dev
);
1278 pci_del_option_rom(pci_dev
);
1284 pci_device_deassert_intx(pci_dev
);
1285 do_pci_unregister_device(pci_dev
);
1287 pci_dev
->msi_trigger
= NULL
;
1290 * clean up acpi-index so it could reused by another device
1292 if (pci_dev
->acpi_index
) {
1293 GSequence
*used_indexes
= pci_acpi_index_list();
1295 g_sequence_remove(g_sequence_lookup(used_indexes
,
1296 GINT_TO_POINTER(pci_dev
->acpi_index
),
1297 g_cmp_uint32
, NULL
));
1301 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1302 uint8_t type
, MemoryRegion
*memory
)
1305 uint32_t addr
; /* offset in pci config space */
1307 pcibus_t size
= memory_region_size(memory
);
1310 assert(!pci_is_vf(pci_dev
)); /* VFs must use pcie_sriov_vf_register_bar */
1311 assert(region_num
>= 0);
1312 assert(region_num
< PCI_NUM_REGIONS
);
1313 assert(is_power_of_2(size
));
1315 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
1317 pci_dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1318 assert(hdr_type
!= PCI_HEADER_TYPE_BRIDGE
|| region_num
< 2);
1320 r
= &pci_dev
->io_regions
[region_num
];
1321 r
->addr
= PCI_BAR_UNMAPPED
;
1325 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1326 ? pci_get_bus(pci_dev
)->address_space_io
1327 : pci_get_bus(pci_dev
)->address_space_mem
;
1329 wmask
= ~(size
- 1);
1330 if (region_num
== PCI_ROM_SLOT
) {
1331 /* ROM enable bit is writable */
1332 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1335 addr
= pci_bar(pci_dev
, region_num
);
1336 pci_set_long(pci_dev
->config
+ addr
, type
);
1338 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1339 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1340 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1341 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1343 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1344 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1348 static void pci_update_vga(PCIDevice
*pci_dev
)
1352 if (!pci_dev
->has_vga
) {
1356 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1358 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1359 cmd
& PCI_COMMAND_MEMORY
);
1360 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1361 cmd
& PCI_COMMAND_IO
);
1362 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1363 cmd
& PCI_COMMAND_IO
);
1366 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1367 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1369 PCIBus
*bus
= pci_get_bus(pci_dev
);
1371 assert(!pci_dev
->has_vga
);
1373 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1374 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1375 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1376 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1378 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1379 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1380 memory_region_add_subregion_overlap(bus
->address_space_io
,
1381 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1383 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1384 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1385 memory_region_add_subregion_overlap(bus
->address_space_io
,
1386 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1387 pci_dev
->has_vga
= true;
1389 pci_update_vga(pci_dev
);
1392 void pci_unregister_vga(PCIDevice
*pci_dev
)
1394 PCIBus
*bus
= pci_get_bus(pci_dev
);
1396 if (!pci_dev
->has_vga
) {
1400 memory_region_del_subregion(bus
->address_space_mem
,
1401 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1402 memory_region_del_subregion(bus
->address_space_io
,
1403 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1404 memory_region_del_subregion(bus
->address_space_io
,
1405 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1406 pci_dev
->has_vga
= false;
1409 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1411 return pci_dev
->io_regions
[region_num
].addr
;
1414 static pcibus_t
pci_config_get_bar_addr(PCIDevice
*d
, int reg
,
1415 uint8_t type
, pcibus_t size
)
1418 if (!pci_is_vf(d
)) {
1419 int bar
= pci_bar(d
, reg
);
1420 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1421 new_addr
= pci_get_quad(d
->config
+ bar
);
1423 new_addr
= pci_get_long(d
->config
+ bar
);
1426 PCIDevice
*pf
= d
->exp
.sriov_vf
.pf
;
1427 uint16_t sriov_cap
= pf
->exp
.sriov_cap
;
1428 int bar
= sriov_cap
+ PCI_SRIOV_BAR
+ reg
* 4;
1429 uint16_t vf_offset
=
1430 pci_get_word(pf
->config
+ sriov_cap
+ PCI_SRIOV_VF_OFFSET
);
1431 uint16_t vf_stride
=
1432 pci_get_word(pf
->config
+ sriov_cap
+ PCI_SRIOV_VF_STRIDE
);
1433 uint32_t vf_num
= (d
->devfn
- (pf
->devfn
+ vf_offset
)) / vf_stride
;
1435 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1436 new_addr
= pci_get_quad(pf
->config
+ bar
);
1438 new_addr
= pci_get_long(pf
->config
+ bar
);
1440 new_addr
+= vf_num
* size
;
1442 /* The ROM slot has a specific enable bit, keep it intact */
1443 if (reg
!= PCI_ROM_SLOT
) {
1444 new_addr
&= ~(size
- 1);
1449 pcibus_t
pci_bar_address(PCIDevice
*d
,
1450 int reg
, uint8_t type
, pcibus_t size
)
1452 pcibus_t new_addr
, last_addr
;
1453 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1454 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
1455 bool allow_0_address
= mc
->pci_allow_0_address
;
1457 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1458 if (!(cmd
& PCI_COMMAND_IO
)) {
1459 return PCI_BAR_UNMAPPED
;
1461 new_addr
= pci_config_get_bar_addr(d
, reg
, type
, size
);
1462 last_addr
= new_addr
+ size
- 1;
1463 /* Check if 32 bit BAR wraps around explicitly.
1464 * TODO: make priorities correct and remove this work around.
1466 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1467 (!allow_0_address
&& new_addr
== 0)) {
1468 return PCI_BAR_UNMAPPED
;
1473 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1474 return PCI_BAR_UNMAPPED
;
1476 new_addr
= pci_config_get_bar_addr(d
, reg
, type
, size
);
1477 /* the ROM slot has a specific enable bit */
1478 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1479 return PCI_BAR_UNMAPPED
;
1481 new_addr
&= ~(size
- 1);
1482 last_addr
= new_addr
+ size
- 1;
1483 /* NOTE: we do not support wrapping */
1484 /* XXX: as we cannot support really dynamic
1485 mappings, we handle specific values as invalid
1487 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1488 (!allow_0_address
&& new_addr
== 0)) {
1489 return PCI_BAR_UNMAPPED
;
1492 /* Now pcibus_t is 64bit.
1493 * Check if 32 bit BAR wraps around explicitly.
1494 * Without this, PC ide doesn't work well.
1495 * TODO: remove this work around.
1497 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1498 return PCI_BAR_UNMAPPED
;
1502 * OS is allowed to set BAR beyond its addressable
1503 * bits. For example, 32 bit OS can set 64bit bar
1504 * to >4G. Check it. TODO: we might need to support
1505 * it in the future for e.g. PAE.
1507 if (last_addr
>= HWADDR_MAX
) {
1508 return PCI_BAR_UNMAPPED
;
1514 static void pci_update_mappings(PCIDevice
*d
)
1520 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1521 r
= &d
->io_regions
[i
];
1523 /* this region isn't registered */
1527 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1528 if (!d
->has_power
) {
1529 new_addr
= PCI_BAR_UNMAPPED
;
1532 /* This bar isn't changed */
1533 if (new_addr
== r
->addr
)
1536 /* now do the real mapping */
1537 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1538 trace_pci_update_mappings_del(d
->name
, pci_dev_bus_num(d
),
1541 i
, r
->addr
, r
->size
);
1542 memory_region_del_subregion(r
->address_space
, r
->memory
);
1545 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1546 trace_pci_update_mappings_add(d
->name
, pci_dev_bus_num(d
),
1549 i
, r
->addr
, r
->size
);
1550 memory_region_add_subregion_overlap(r
->address_space
,
1551 r
->addr
, r
->memory
, 1);
1558 static inline int pci_irq_disabled(PCIDevice
*d
)
1560 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1563 /* Called after interrupt disabled field update in config space,
1564 * assert/deassert interrupts if necessary.
1565 * Gets original interrupt disable bit value (before update). */
1566 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1568 int i
, disabled
= pci_irq_disabled(d
);
1569 if (disabled
== was_irq_disabled
)
1571 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1572 int state
= pci_irq_state(d
, i
);
1573 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1577 uint32_t pci_default_read_config(PCIDevice
*d
,
1578 uint32_t address
, int len
)
1582 assert(address
+ len
<= pci_config_size(d
));
1584 if (pci_is_express_downstream_port(d
) &&
1585 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1586 pcie_sync_bridge_lnk(d
);
1588 memcpy(&val
, d
->config
+ address
, len
);
1589 return le32_to_cpu(val
);
1592 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1594 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1595 uint32_t val
= val_in
;
1597 assert(addr
+ l
<= pci_config_size(d
));
1599 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1600 uint8_t wmask
= d
->wmask
[addr
+ i
];
1601 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1602 assert(!(wmask
& w1cmask
));
1603 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1604 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1606 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1607 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1608 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1609 range_covers_byte(addr
, l
, PCI_COMMAND
))
1610 pci_update_mappings(d
);
1612 if (ranges_overlap(addr
, l
, PCI_COMMAND
, 2)) {
1613 pci_update_irq_disabled(d
, was_irq_disabled
);
1614 memory_region_set_enabled(&d
->bus_master_enable_region
,
1615 (pci_get_word(d
->config
+ PCI_COMMAND
)
1616 & PCI_COMMAND_MASTER
) && d
->has_power
);
1619 msi_write_config(d
, addr
, val_in
, l
);
1620 msix_write_config(d
, addr
, val_in
, l
);
1621 pcie_sriov_config_write(d
, addr
, val_in
, l
);
1624 /***********************************************************/
1625 /* generic PCI irq support */
1627 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1628 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1630 PCIDevice
*pci_dev
= opaque
;
1633 assert(0 <= irq_num
&& irq_num
< PCI_NUM_PINS
);
1634 assert(level
== 0 || level
== 1);
1635 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1639 pci_set_irq_state(pci_dev
, irq_num
, level
);
1640 pci_update_irq_status(pci_dev
);
1641 if (pci_irq_disabled(pci_dev
))
1643 pci_change_irq_level(pci_dev
, irq_num
, change
);
1646 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1648 int intx
= pci_intx(pci_dev
);
1649 assert(0 <= intx
&& intx
< PCI_NUM_PINS
);
1651 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1654 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1656 int intx
= pci_intx(pci_dev
);
1657 pci_irq_handler(pci_dev
, intx
, level
);
1660 /* Special hooks used by device assignment */
1661 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1663 assert(pci_bus_is_root(bus
));
1664 bus
->route_intx_to_irq
= route_intx_to_irq
;
1667 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1673 bus
= pci_get_bus(dev
);
1674 pin
= bus
->map_irq(dev
, pin
);
1675 trace_pci_route_irq(dev_irq
, DEVICE(dev
)->canonical_path
, pin
,
1676 pci_bus_is_root(bus
) ? "root-complex"
1677 : DEVICE(bus
->parent_dev
)->canonical_path
);
1678 dev
= bus
->parent_dev
;
1681 if (!bus
->route_intx_to_irq
) {
1682 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1683 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1684 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1687 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1690 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1692 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1695 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1701 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1702 dev
= bus
->devices
[i
];
1703 if (dev
&& dev
->intx_routing_notifier
) {
1704 dev
->intx_routing_notifier(dev
);
1708 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1709 pci_bus_fire_intx_routing_notifier(sec
);
1713 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1714 PCIINTxRoutingNotifier notifier
)
1716 dev
->intx_routing_notifier
= notifier
;
1720 * PCI-to-PCI bridge specification
1721 * 9.1: Interrupt routing. Table 9-1
1723 * the PCI Express Base Specification, Revision 2.1
1724 * 2.2.8.1: INTx interrupt signaling - Rules
1725 * the Implementation Note
1729 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1730 * 0-origin unlike PCI interrupt pin register.
1732 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1734 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1737 /***********************************************************/
1738 /* monitor info on PCI */
1740 static const pci_class_desc pci_class_descriptions
[] =
1742 { 0x0001, "VGA controller", "display"},
1743 { 0x0100, "SCSI controller", "scsi"},
1744 { 0x0101, "IDE controller", "ide"},
1745 { 0x0102, "Floppy controller", "fdc"},
1746 { 0x0103, "IPI controller", "ipi"},
1747 { 0x0104, "RAID controller", "raid"},
1748 { 0x0106, "SATA controller"},
1749 { 0x0107, "SAS controller"},
1750 { 0x0180, "Storage controller"},
1751 { 0x0200, "Ethernet controller", "ethernet"},
1752 { 0x0201, "Token Ring controller", "token-ring"},
1753 { 0x0202, "FDDI controller", "fddi"},
1754 { 0x0203, "ATM controller", "atm"},
1755 { 0x0280, "Network controller"},
1756 { 0x0300, "VGA controller", "display", 0x00ff},
1757 { 0x0301, "XGA controller"},
1758 { 0x0302, "3D controller"},
1759 { 0x0380, "Display controller"},
1760 { 0x0400, "Video controller", "video"},
1761 { 0x0401, "Audio controller", "sound"},
1763 { 0x0403, "Audio controller", "sound"},
1764 { 0x0480, "Multimedia controller"},
1765 { 0x0500, "RAM controller", "memory"},
1766 { 0x0501, "Flash controller", "flash"},
1767 { 0x0580, "Memory controller"},
1768 { 0x0600, "Host bridge", "host"},
1769 { 0x0601, "ISA bridge", "isa"},
1770 { 0x0602, "EISA bridge", "eisa"},
1771 { 0x0603, "MC bridge", "mca"},
1772 { 0x0604, "PCI bridge", "pci-bridge"},
1773 { 0x0605, "PCMCIA bridge", "pcmcia"},
1774 { 0x0606, "NUBUS bridge", "nubus"},
1775 { 0x0607, "CARDBUS bridge", "cardbus"},
1776 { 0x0608, "RACEWAY bridge"},
1777 { 0x0680, "Bridge"},
1778 { 0x0700, "Serial port", "serial"},
1779 { 0x0701, "Parallel port", "parallel"},
1780 { 0x0800, "Interrupt controller", "interrupt-controller"},
1781 { 0x0801, "DMA controller", "dma-controller"},
1782 { 0x0802, "Timer", "timer"},
1783 { 0x0803, "RTC", "rtc"},
1784 { 0x0900, "Keyboard", "keyboard"},
1785 { 0x0901, "Pen", "pen"},
1786 { 0x0902, "Mouse", "mouse"},
1787 { 0x0A00, "Dock station", "dock", 0x00ff},
1788 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1789 { 0x0c00, "Firewire controller", "firewire"},
1790 { 0x0c01, "Access bus controller", "access-bus"},
1791 { 0x0c02, "SSA controller", "ssa"},
1792 { 0x0c03, "USB controller", "usb"},
1793 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1798 void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1805 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1806 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1813 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1814 pci_bus_dev_fn fn
, void *opaque
)
1816 bus
= pci_find_bus_nr(bus
, bus_num
);
1819 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1823 void pci_for_each_device_under_bus(PCIBus
*bus
,
1824 pci_bus_dev_fn fn
, void *opaque
)
1829 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1830 d
= bus
->devices
[devfn
];
1837 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1838 pci_bus_dev_fn fn
, void *opaque
)
1840 bus
= pci_find_bus_nr(bus
, bus_num
);
1843 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1847 const pci_class_desc
*get_class_desc(int class)
1849 const pci_class_desc
*desc
;
1851 desc
= pci_class_descriptions
;
1852 while (desc
->desc
&& class != desc
->class) {
1859 void pci_init_nic_devices(PCIBus
*bus
, const char *default_model
)
1861 qemu_create_nic_bus_devices(&bus
->qbus
, TYPE_PCI_DEVICE
, default_model
,
1862 "virtio", "virtio-net-pci");
1865 bool pci_init_nic_in_slot(PCIBus
*rootbus
, const char *model
,
1866 const char *alias
, const char *devaddr
)
1868 NICInfo
*nd
= qemu_find_nic_info(model
, true, alias
);
1869 int dom
, busnr
, devfn
;
1878 if (!devaddr
|| pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1879 error_report("Invalid PCI device address %s for device %s",
1885 error_report("No support for non-zero PCI domains");
1889 devfn
= PCI_DEVFN(slot
, 0);
1891 bus
= pci_find_bus_nr(rootbus
, busnr
);
1893 error_report("Invalid PCI device address %s for device %s",
1898 pci_dev
= pci_new(devfn
, model
);
1899 qdev_set_nic_properties(&pci_dev
->qdev
, nd
);
1900 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1904 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1906 vga_interface_created
= true;
1907 switch (vga_interface_type
) {
1909 return pci_create_simple(bus
, -1, "cirrus-vga");
1911 return pci_create_simple(bus
, -1, "qxl-vga");
1913 return pci_create_simple(bus
, -1, "VGA");
1915 return pci_create_simple(bus
, -1, "vmware-svga");
1917 return pci_create_simple(bus
, -1, "virtio-vga");
1919 default: /* Other non-PCI types. Checking for unsupported types is already
1925 /* Whether a given bus number is in range of the secondary
1926 * bus of the given bridge device. */
1927 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1929 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1930 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1931 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1932 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1935 /* Whether a given bus number is in a range of a root bus */
1936 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
1940 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1941 PCIDevice
*dev
= bus
->devices
[i
];
1943 if (dev
&& IS_PCI_BRIDGE(dev
)) {
1944 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
1953 PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1961 if (pci_bus_num(bus
) == bus_num
) {
1965 /* Consider all bus numbers in range for the host pci bridge. */
1966 if (!pci_bus_is_root(bus
) &&
1967 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1972 for (; bus
; bus
= sec
) {
1973 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1974 if (pci_bus_num(sec
) == bus_num
) {
1977 /* PXB buses assumed to be children of bus 0 */
1978 if (pci_bus_is_root(sec
)) {
1979 if (pci_root_bus_in_range(sec
, bus_num
)) {
1983 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1993 void pci_for_each_bus_depth_first(PCIBus
*bus
, pci_bus_ret_fn begin
,
1994 pci_bus_fn end
, void *parent_state
)
2004 state
= begin(bus
, parent_state
);
2006 state
= parent_state
;
2009 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2010 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2019 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2021 bus
= pci_find_bus_nr(bus
, bus_num
);
2026 return bus
->devices
[devfn
];
2029 #define ONBOARD_INDEX_MAX (16 * 1024 - 1)
2031 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2033 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2034 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2035 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2036 Error
*local_err
= NULL
;
2037 bool is_default_rom
;
2041 * capped by systemd (see: udev-builtin-net_id.c)
2042 * as it's the only known user honor it to avoid users
2043 * misconfigure QEMU and then wonder why acpi-index doesn't work
2045 if (pci_dev
->acpi_index
> ONBOARD_INDEX_MAX
) {
2046 error_setg(errp
, "acpi-index should be less or equal to %u",
2052 * make sure that acpi-index is unique across all present PCI devices
2054 if (pci_dev
->acpi_index
) {
2055 GSequence
*used_indexes
= pci_acpi_index_list();
2057 if (g_sequence_lookup(used_indexes
,
2058 GINT_TO_POINTER(pci_dev
->acpi_index
),
2059 g_cmp_uint32
, NULL
)) {
2060 error_setg(errp
, "a PCI device with acpi-index = %" PRIu32
2061 " already exist", pci_dev
->acpi_index
);
2064 g_sequence_insert_sorted(used_indexes
,
2065 GINT_TO_POINTER(pci_dev
->acpi_index
),
2066 g_cmp_uint32
, NULL
);
2069 if (pci_dev
->romsize
!= -1 && !is_power_of_2(pci_dev
->romsize
)) {
2070 error_setg(errp
, "ROM size %u is not a power of two", pci_dev
->romsize
);
2074 /* initialize cap_present for pci_is_express() and pci_config_size(),
2075 * Note that hybrid PCIs are not set automatically and need to manage
2076 * QEMU_PCI_CAP_EXPRESS manually */
2077 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2078 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2079 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2082 if (object_class_dynamic_cast(klass
, INTERFACE_CXL_DEVICE
)) {
2083 pci_dev
->cap_present
|= QEMU_PCIE_CAP_CXL
;
2086 pci_dev
= do_pci_register_device(pci_dev
,
2087 object_get_typename(OBJECT(qdev
)),
2088 pci_dev
->devfn
, errp
);
2089 if (pci_dev
== NULL
)
2093 pc
->realize(pci_dev
, &local_err
);
2095 error_propagate(errp
, local_err
);
2096 do_pci_unregister_device(pci_dev
);
2102 * A PCIe Downstream Port that do not have ARI Forwarding enabled must
2103 * associate only Device 0 with the device attached to the bus
2104 * representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3,
2106 * With ARI, PCI_SLOT() can return non-zero value as the traditional
2107 * 5-bit Device Number and 3-bit Function Number fields in its associated
2108 * Routing IDs, Requester IDs and Completer IDs are interpreted as a
2109 * single 8-bit Function Number. Hence, ignore ARI capable devices.
2111 if (pci_is_express(pci_dev
) &&
2112 !pcie_find_capability(pci_dev
, PCI_EXT_CAP_ID_ARI
) &&
2113 pcie_has_upstream_port(pci_dev
) &&
2114 PCI_SLOT(pci_dev
->devfn
)) {
2115 warn_report("PCI: slot %d is not valid for %s,"
2116 " parent device only allows plugging into slot 0.",
2117 PCI_SLOT(pci_dev
->devfn
), pci_dev
->name
);
2120 if (pci_dev
->failover_pair_id
) {
2121 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2122 error_setg(errp
, "failover primary device must be on "
2124 pci_qdev_unrealize(DEVICE(pci_dev
));
2127 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2128 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2129 error_setg(errp
, "failover primary device is not an "
2131 pci_qdev_unrealize(DEVICE(pci_dev
));
2134 if ((pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2135 || (PCI_FUNC(pci_dev
->devfn
) != 0)) {
2136 error_setg(errp
, "failover: primary device must be in its own "
2138 pci_qdev_unrealize(DEVICE(pci_dev
));
2141 qdev
->allow_unplug_during_migration
= true;
2145 is_default_rom
= false;
2146 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2147 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2148 is_default_rom
= true;
2151 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2153 error_propagate(errp
, local_err
);
2154 pci_qdev_unrealize(DEVICE(pci_dev
));
2158 pci_set_power(pci_dev
, true);
2160 pci_dev
->msi_trigger
= pci_msi_trigger
;
2163 static PCIDevice
*pci_new_internal(int devfn
, bool multifunction
,
2168 dev
= qdev_new(name
);
2169 qdev_prop_set_int32(dev
, "addr", devfn
);
2170 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2171 return PCI_DEVICE(dev
);
2174 PCIDevice
*pci_new_multifunction(int devfn
, const char *name
)
2176 return pci_new_internal(devfn
, true, name
);
2179 PCIDevice
*pci_new(int devfn
, const char *name
)
2181 return pci_new_internal(devfn
, false, name
);
2184 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2186 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2189 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2192 PCIDevice
*dev
= pci_new_multifunction(devfn
, name
);
2193 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2197 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2199 PCIDevice
*dev
= pci_new(devfn
, name
);
2200 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2204 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2206 int offset
= PCI_CONFIG_HEADER_SIZE
;
2208 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2211 else if (i
- offset
+ 1 == size
)
2217 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2222 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2225 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2226 prev
= next
+ PCI_CAP_LIST_NEXT
)
2227 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2235 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2237 uint8_t next
, prev
, found
= 0;
2239 if (!(pdev
->used
[offset
])) {
2243 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2245 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2246 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2247 if (next
<= offset
&& next
> found
) {
2254 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2255 This is needed for an option rom which is used for more than one device. */
2256 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, uint32_t size
)
2260 uint16_t rom_vendor_id
;
2261 uint16_t rom_device_id
;
2263 uint16_t pcir_offset
;
2266 /* Words in rom data are little endian (like in PCI configuration),
2267 so they can be read / written with pci_get_word / pci_set_word. */
2269 /* Only a valid rom will be patched. */
2270 rom_magic
= pci_get_word(ptr
);
2271 if (rom_magic
!= 0xaa55) {
2272 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2275 pcir_offset
= pci_get_word(ptr
+ 0x18);
2276 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2277 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2281 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2282 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2283 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2284 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2286 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2287 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2291 if (vendor_id
!= rom_vendor_id
) {
2292 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2293 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2294 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2295 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2297 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2300 if (device_id
!= rom_device_id
) {
2301 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2302 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2303 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2304 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2306 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2310 /* Add an option rom for the device */
2311 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2315 g_autofree
char *path
= NULL
;
2317 const VMStateDescription
*vmsd
;
2320 * In case of incoming migration ROM will come with migration stream, no
2321 * reason to load the file. Neither we want to fail if local ROM file
2322 * mismatches with specified romsize.
2324 bool load_file
= !runstate_check(RUN_STATE_INMIGRATE
);
2326 if (!pdev
->romfile
|| !strlen(pdev
->romfile
)) {
2330 if (!pdev
->rom_bar
) {
2332 * Load rom via fw_cfg instead of creating a rom bar,
2333 * for 0.11 compatibility.
2335 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2338 * Hot-plugged devices can't use the option ROM
2339 * if the rom bar is disabled.
2341 if (DEVICE(pdev
)->hotplugged
) {
2342 error_setg(errp
, "Hot-plugged device without ROM bar"
2343 " can't have an option ROM");
2347 if (class == 0x0300) {
2348 rom_add_vga(pdev
->romfile
);
2350 rom_add_option(pdev
->romfile
, -1);
2355 if (load_file
|| pdev
->romsize
== -1) {
2356 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2358 path
= g_strdup(pdev
->romfile
);
2361 size
= get_image_size(path
);
2363 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2365 } else if (size
== 0) {
2366 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2368 } else if (size
> 2 * GiB
) {
2370 "romfile \"%s\" too large (size cannot exceed 2 GiB)",
2374 if (pdev
->romsize
!= -1) {
2375 if (size
> pdev
->romsize
) {
2376 error_setg(errp
, "romfile \"%s\" (%u bytes) "
2377 "is too large for ROM size %u",
2378 pdev
->romfile
, (uint32_t)size
, pdev
->romsize
);
2382 pdev
->romsize
= pow2ceil(size
);
2386 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2387 snprintf(name
, sizeof(name
), "%s.rom",
2388 vmsd
? vmsd
->name
: object_get_typename(OBJECT(pdev
)));
2390 pdev
->has_rom
= true;
2391 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, pdev
->romsize
,
2395 void *ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2397 if (load_image_size(path
, ptr
, size
) < 0) {
2398 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2402 if (is_default_rom
) {
2403 /* Only the default rom images will be patched (if needed). */
2404 pci_patch_ids(pdev
, ptr
, size
);
2408 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2411 static void pci_del_option_rom(PCIDevice
*pdev
)
2416 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2417 pdev
->has_rom
= false;
2421 * On success, pci_add_capability() returns a positive value
2422 * that the offset of the pci capability.
2423 * On failure, it sets an error and returns a negative error
2426 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2427 uint8_t offset
, uint8_t size
,
2431 int i
, overlapping_cap
;
2434 offset
= pci_find_space(pdev
, size
);
2435 /* out of PCI config space is programming error */
2438 /* Verify that capabilities don't overlap. Note: device assignment
2439 * depends on this check to verify that the device is not broken.
2440 * Should never trigger for emulated devices, but it's helpful
2441 * for debugging these. */
2442 for (i
= offset
; i
< offset
+ size
; i
++) {
2443 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2444 if (overlapping_cap
) {
2445 error_setg(errp
, "%s:%02x:%02x.%x "
2446 "Attempt to add PCI capability %x at offset "
2447 "%x overlaps existing capability %x at offset %x",
2448 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2449 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2450 cap_id
, offset
, overlapping_cap
, i
);
2456 config
= pdev
->config
+ offset
;
2457 config
[PCI_CAP_LIST_ID
] = cap_id
;
2458 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2459 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2460 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2461 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2462 /* Make capability read-only by default */
2463 memset(pdev
->wmask
+ offset
, 0, size
);
2464 /* Check capability by default */
2465 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2469 /* Unlink capability from the pci config space. */
2470 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2472 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2475 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2476 /* Make capability writable again */
2477 memset(pdev
->wmask
+ offset
, 0xff, size
);
2478 memset(pdev
->w1cmask
+ offset
, 0, size
);
2479 /* Clear cmask as device-specific registers can't be checked */
2480 memset(pdev
->cmask
+ offset
, 0, size
);
2481 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2483 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2484 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2487 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2489 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2492 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2494 PCIDevice
*d
= (PCIDevice
*)dev
;
2495 const char *name
= NULL
;
2496 const pci_class_desc
*desc
= pci_class_descriptions
;
2497 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2499 while (desc
->desc
&&
2500 (class & ~desc
->fw_ign_bits
) !=
2501 (desc
->class & ~desc
->fw_ign_bits
)) {
2506 name
= desc
->fw_name
;
2510 pstrcpy(buf
, len
, name
);
2512 snprintf(buf
, len
, "pci%04x,%04x",
2513 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2514 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2520 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2522 PCIDevice
*d
= (PCIDevice
*)dev
;
2524 int has_func
= !!PCI_FUNC(d
->devfn
);
2526 return g_strdup_printf("%s@%x%s%.*x",
2527 pci_dev_fw_name(dev
, name
, sizeof(name
)),
2529 has_func
? "," : "",
2531 PCI_FUNC(d
->devfn
));
2534 static char *pcibus_get_dev_path(DeviceState
*dev
)
2536 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2539 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2540 * 00 is added here to make this format compatible with
2541 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2542 * Slot.Function list specifies the slot and function numbers for all
2543 * devices on the path from root to the specific device. */
2544 const char *root_bus_path
;
2546 char slot
[] = ":SS.F";
2547 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2552 root_bus_path
= pci_root_bus_path(d
);
2553 root_bus_len
= strlen(root_bus_path
);
2555 /* Calculate # of slots on path between device and root. */;
2557 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2561 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2563 /* Allocate memory, fill in the terminating null byte. */
2564 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2565 path
[path_len
] = '\0';
2567 memcpy(path
, root_bus_path
, root_bus_len
);
2569 /* Fill in slot numbers. We walk up from device to root, so need to print
2570 * them in the reverse order, last to first. */
2571 p
= path
+ path_len
;
2572 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2574 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2575 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2576 assert(s
== slot_len
);
2577 memcpy(p
, slot
, slot_len
);
2583 static int pci_qdev_find_recursive(PCIBus
*bus
,
2584 const char *id
, PCIDevice
**pdev
)
2586 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2591 /* roughly check if given qdev is pci device */
2592 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2593 *pdev
= PCI_DEVICE(qdev
);
2599 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2601 PCIHostState
*host_bridge
;
2604 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2605 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2610 if (tmp
!= -ENODEV
) {
2618 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2620 return pci_get_bus(dev
)->address_space_mem
;
2623 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2625 return pci_get_bus(dev
)->address_space_io
;
2628 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2630 DeviceClass
*k
= DEVICE_CLASS(klass
);
2632 k
->realize
= pci_qdev_realize
;
2633 k
->unrealize
= pci_qdev_unrealize
;
2634 k
->bus_type
= TYPE_PCI_BUS
;
2635 device_class_set_props(k
, pci_props
);
2638 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2640 if (!object_class_is_abstract(klass
)) {
2641 ObjectClass
*conventional
=
2642 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2644 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2646 object_class_dynamic_cast(klass
, INTERFACE_CXL_DEVICE
);
2647 assert(conventional
|| pcie
|| cxl
);
2651 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2653 PCIBus
*bus
= pci_get_bus(dev
);
2654 PCIBus
*iommu_bus
= bus
;
2655 uint8_t devfn
= dev
->devfn
;
2657 while (iommu_bus
&& !iommu_bus
->iommu_ops
&& iommu_bus
->parent_dev
) {
2658 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2661 * The requester ID of the provided device may be aliased, as seen from
2662 * the IOMMU, due to topology limitations. The IOMMU relies on a
2663 * requester ID to provide a unique AddressSpace for devices, but
2664 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2665 * to-PCI bridge creates and accepts transactions on behalf of down-
2666 * stream devices. When doing so, all downstream devices are masked
2667 * (aliased) behind a single requester ID. The requester ID used
2668 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2669 * bridges, with a PCIe capability indicating such, follow the
2670 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2671 * where the bridge uses the seconary bus as the bridge portion of the
2672 * requester ID and devfn of 00.0. For other bridges, typically those
2673 * found on the root complex such as the dmi-to-pci-bridge, we follow
2674 * the convention of typical bare-metal hardware, which uses the
2675 * requester ID of the bridge itself. There are device specific
2676 * exceptions to these rules, but these are the defaults that the
2677 * Linux kernel uses when determining DMA aliases itself and believed
2678 * to be true for the bare metal equivalents of the devices emulated
2681 if (!pci_bus_is_express(iommu_bus
)) {
2682 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2684 if (pci_is_express(parent
) &&
2685 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2686 devfn
= PCI_DEVFN(0, 0);
2689 devfn
= parent
->devfn
;
2694 iommu_bus
= parent_bus
;
2696 if (!pci_bus_bypass_iommu(bus
) && iommu_bus
->iommu_ops
) {
2697 return iommu_bus
->iommu_ops
->get_address_space(bus
,
2698 iommu_bus
->iommu_opaque
, devfn
);
2700 return &address_space_memory
;
2703 void pci_setup_iommu(PCIBus
*bus
, const PCIIOMMUOps
*ops
, void *opaque
)
2706 * If called, pci_setup_iommu() should provide a minimum set of
2707 * useful callbacks for the bus.
2710 assert(ops
->get_address_space
);
2712 bus
->iommu_ops
= ops
;
2713 bus
->iommu_opaque
= opaque
;
2716 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2718 Range
*range
= opaque
;
2719 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2722 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2726 if (IS_PCI_BRIDGE(dev
)) {
2727 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2728 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2730 base
= MAX(base
, 0x1ULL
<< 32);
2732 if (limit
>= base
) {
2734 range_set_bounds(&pref_range
, base
, limit
);
2735 range_extend(range
, &pref_range
);
2738 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2739 PCIIORegion
*r
= &dev
->io_regions
[i
];
2744 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2745 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2749 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2750 upb
= lob
+ r
->size
- 1;
2751 if (lob
== PCI_BAR_UNMAPPED
) {
2755 lob
= MAX(lob
, 0x1ULL
<< 32);
2758 range_set_bounds(®ion_range
, lob
, upb
);
2759 range_extend(range
, ®ion_range
);
2764 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2766 range_make_empty(range
);
2767 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2770 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2772 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2774 /* Device associated with an upstream port.
2775 * As there are several types of these, it's easier to check the
2776 * parent device: upstream ports are always connected to
2777 * root or downstream ports.
2779 return parent_dev
&&
2780 pci_is_express(parent_dev
) &&
2781 parent_dev
->exp
.exp_cap
&&
2782 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2783 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2786 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2788 PCIBus
*bus
= pci_get_bus(pci_dev
);
2790 if(pcie_has_upstream_port(pci_dev
)) {
2791 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2792 return bus
->devices
[0];
2794 /* Other bus types might support multiple devices at slots 0-31 */
2795 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2799 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2802 if (msix_enabled(dev
)) {
2803 msg
= msix_get_message(dev
, vector
);
2804 } else if (msi_enabled(dev
)) {
2805 msg
= msi_get_message(dev
, vector
);
2807 /* Should never happen */
2808 error_report("%s: unknown interrupt type", __func__
);
2814 void pci_set_power(PCIDevice
*d
, bool state
)
2816 if (d
->has_power
== state
) {
2820 d
->has_power
= state
;
2821 pci_update_mappings(d
);
2822 memory_region_set_enabled(&d
->bus_master_enable_region
,
2823 (pci_get_word(d
->config
+ PCI_COMMAND
)
2824 & PCI_COMMAND_MASTER
) && d
->has_power
);
2825 if (!d
->has_power
) {
2826 pci_device_reset(d
);
2830 static const TypeInfo pci_device_type_info
= {
2831 .name
= TYPE_PCI_DEVICE
,
2832 .parent
= TYPE_DEVICE
,
2833 .instance_size
= sizeof(PCIDevice
),
2835 .class_size
= sizeof(PCIDeviceClass
),
2836 .class_init
= pci_device_class_init
,
2837 .class_base_init
= pci_device_class_base_init
,
2840 static void pci_register_types(void)
2842 type_register_static(&pci_bus_info
);
2843 type_register_static(&pcie_bus_info
);
2844 type_register_static(&cxl_bus_info
);
2845 type_register_static(&conventional_pci_interface_info
);
2846 type_register_static(&cxl_interface_info
);
2847 type_register_static(&pcie_interface_info
);
2848 type_register_static(&pci_device_type_info
);
2851 type_init(pci_register_types
)