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Revert "Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging"
[qemu/kevin.git] / hw / nseries.c
blobf7aae7a59eb04881abfb60ac59482396870bfc2c
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu.h"
23 #include "omap.h"
24 #include "arm-misc.h"
25 #include "irq.h"
26 #include "console.h"
27 #include "boards.h"
28 #include "i2c.h"
29 #include "devices.h"
30 #include "flash.h"
31 #include "hw.h"
32 #include "bt.h"
33 #include "loader.h"
34 #include "blockdev.h"
35 #include "tusb6010.h"
36
37 /* Nokia N8x0 support */
38 struct n800_s {
39 struct omap_mpu_state_s *cpu;
40
41 struct rfbi_chip_s blizzard;
42 struct {
43 void *opaque;
44 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
45 uWireSlave *chip;
46 } ts;
47 i2c_bus *i2c;
48
49 int keymap[0x80];
50 DeviceState *kbd;
51
52 TUSBState *usb;
53 void *retu;
54 void *tahvo;
55 void *nand;
56 };
57
58 /* GPIO pins */
59 #define N8X0_TUSB_ENABLE_GPIO 0
60 #define N800_MMC2_WP_GPIO 8
61 #define N800_UNKNOWN_GPIO0 9 /* out */
62 #define N810_MMC2_VIOSD_GPIO 9
63 #define N810_HEADSET_AMP_GPIO 10
64 #define N800_CAM_TURN_GPIO 12
65 #define N810_GPS_RESET_GPIO 12
66 #define N800_BLIZZARD_POWERDOWN_GPIO 15
67 #define N800_MMC1_WP_GPIO 23
68 #define N810_MMC2_VSD_GPIO 23
69 #define N8X0_ONENAND_GPIO 26
70 #define N810_BLIZZARD_RESET_GPIO 30
71 #define N800_UNKNOWN_GPIO2 53 /* out */
72 #define N8X0_TUSB_INT_GPIO 58
73 #define N8X0_BT_WKUP_GPIO 61
74 #define N8X0_STI_GPIO 62
75 #define N8X0_CBUS_SEL_GPIO 64
76 #define N8X0_CBUS_DAT_GPIO 65
77 #define N8X0_CBUS_CLK_GPIO 66
78 #define N8X0_WLAN_IRQ_GPIO 87
79 #define N8X0_BT_RESET_GPIO 92
80 #define N8X0_TEA5761_CS_GPIO 93
81 #define N800_UNKNOWN_GPIO 94
82 #define N810_TSC_RESET_GPIO 94
83 #define N800_CAM_ACT_GPIO 95
84 #define N810_GPS_WAKEUP_GPIO 95
85 #define N8X0_MMC_CS_GPIO 96
86 #define N8X0_WLAN_PWR_GPIO 97
87 #define N8X0_BT_HOST_WKUP_GPIO 98
88 #define N810_SPEAKER_AMP_GPIO 101
89 #define N810_KB_LOCK_GPIO 102
90 #define N800_TSC_TS_GPIO 103
91 #define N810_TSC_TS_GPIO 106
92 #define N8X0_HEADPHONE_GPIO 107
93 #define N8X0_RETU_GPIO 108
94 #define N800_TSC_KP_IRQ_GPIO 109
95 #define N810_KEYBOARD_GPIO 109
96 #define N800_BAT_COVER_GPIO 110
97 #define N810_SLIDE_GPIO 110
98 #define N8X0_TAHVO_GPIO 111
99 #define N800_UNKNOWN_GPIO4 112 /* out */
100 #define N810_SLEEPX_LED_GPIO 112
101 #define N800_TSC_RESET_GPIO 118 /* ? */
102 #define N810_AIC33_RESET_GPIO 118
103 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
104 #define N8X0_TMP105_GPIO 125
105
106 /* Config */
107 #define BT_UART 0
108 #define XLDR_LL_UART 1
109
110 /* Addresses on the I2C bus 0 */
111 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
112 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
113 #define N810_LP5521_ADDR 0x32 /* LEDs */
114 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
115 #define N810_LM8323_ADDR 0x45 /* Keyboard */
116 /* Addresses on the I2C bus 1 */
117 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
118 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
119
120 /* Chipselects on GPMC NOR interface */
121 #define N8X0_ONENAND_CS 0
122 #define N8X0_USB_ASYNC_CS 1
123 #define N8X0_USB_SYNC_CS 4
124
125 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
126
127 static void n800_mmc_cs_cb(void *opaque, int line, int level)
128 {
129 /* TODO: this seems to actually be connected to the menelaus, to
130 * which also both MMC slots connect. */
131 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
132
133 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
134 }
135
136 static void n8x0_gpio_setup(struct n800_s *s)
137 {
138 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
139 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
140
141 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
142 }
143
144 #define MAEMO_CAL_HEADER(...) \
145 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
146 __VA_ARGS__, \
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
148
149 static const uint8_t n8x0_cal_wlan_mac[] = {
150 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
151 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
152 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
154 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
155 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
156 };
157
158 static const uint8_t n8x0_cal_bt_id[] = {
159 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
160 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
161 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
162 N8X0_BD_ADDR,
163 };
164
165 static void n8x0_nand_setup(struct n800_s *s)
166 {
167 char *otp_region;
168 DriveInfo *dinfo;
169
170 dinfo = drive_get(IF_MTD, 0, 0);
171 /* Either 0x40 or 0x48 are OK for the device ID */
172 s->nand = onenand_init(dinfo ? dinfo->bdrv : 0,
173 NAND_MFR_SAMSUNG, 0x48, 0, 1,
174 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
175 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
176 onenand_base_unmap, s->nand);
177 otp_region = onenand_raw_otp(s->nand);
178
179 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
180 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
181 /* XXX: in theory should also update the OOB for both pages */
182 }
183
184 static void n8x0_i2c_setup(struct n800_s *s)
185 {
186 DeviceState *dev;
187 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
188
189 /* Attach the CPU on one end of our I2C bus. */
190 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
191
192 /* Attach a menelaus PM chip */
193 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
194 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
195
196 /* Attach a TMP105 PM chip (A0 wired to ground) */
197 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
198 qdev_connect_gpio_out(dev, 0, tmp_irq);
199 }
200
201 /* Touchscreen and keypad controller */
202 static MouseTransformInfo n800_pointercal = {
203 .x = 800,
204 .y = 480,
205 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
206 };
207
208 static MouseTransformInfo n810_pointercal = {
209 .x = 800,
210 .y = 480,
211 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
212 };
213
214 #define RETU_KEYCODE 61 /* F3 */
215
216 static void n800_key_event(void *opaque, int keycode)
217 {
218 struct n800_s *s = (struct n800_s *) opaque;
219 int code = s->keymap[keycode & 0x7f];
220
221 if (code == -1) {
222 if ((keycode & 0x7f) == RETU_KEYCODE)
223 retu_key_event(s->retu, !(keycode & 0x80));
224 return;
225 }
226
227 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
228 }
229
230 static const int n800_keys[16] = {
231 -1,
232 72, /* Up */
233 63, /* Home (F5) */
234 -1,
235 75, /* Left */
236 28, /* Enter */
237 77, /* Right */
238 -1,
239 1, /* Cycle (ESC) */
240 80, /* Down */
241 62, /* Menu (F4) */
242 -1,
243 66, /* Zoom- (F8) */
244 64, /* FullScreen (F6) */
245 65, /* Zoom+ (F7) */
246 -1,
247 };
248
249 static void n800_tsc_kbd_setup(struct n800_s *s)
250 {
251 int i;
252
253 /* XXX: are the three pins inverted inside the chip between the
254 * tsc and the cpu (N4111)? */
255 qemu_irq penirq = NULL; /* NC */
256 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
257 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
258
259 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
260 s->ts.opaque = s->ts.chip->opaque;
261 s->ts.txrx = tsc210x_txrx;
262
263 for (i = 0; i < 0x80; i ++)
264 s->keymap[i] = -1;
265 for (i = 0; i < 0x10; i ++)
266 if (n800_keys[i] >= 0)
267 s->keymap[n800_keys[i]] = i;
268
269 qemu_add_kbd_event_handler(n800_key_event, s);
270
271 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
272 }
273
274 static void n810_tsc_setup(struct n800_s *s)
275 {
276 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
277
278 s->ts.opaque = tsc2005_init(pintdav);
279 s->ts.txrx = tsc2005_txrx;
280
281 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
282 }
283
284 /* N810 Keyboard controller */
285 static void n810_key_event(void *opaque, int keycode)
286 {
287 struct n800_s *s = (struct n800_s *) opaque;
288 int code = s->keymap[keycode & 0x7f];
289
290 if (code == -1) {
291 if ((keycode & 0x7f) == RETU_KEYCODE)
292 retu_key_event(s->retu, !(keycode & 0x80));
293 return;
294 }
295
296 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
297 }
298
299 #define M 0
300
301 static int n810_keys[0x80] = {
302 [0x01] = 16, /* Q */
303 [0x02] = 37, /* K */
304 [0x03] = 24, /* O */
305 [0x04] = 25, /* P */
306 [0x05] = 14, /* Backspace */
307 [0x06] = 30, /* A */
308 [0x07] = 31, /* S */
309 [0x08] = 32, /* D */
310 [0x09] = 33, /* F */
311 [0x0a] = 34, /* G */
312 [0x0b] = 35, /* H */
313 [0x0c] = 36, /* J */
314
315 [0x11] = 17, /* W */
316 [0x12] = 62, /* Menu (F4) */
317 [0x13] = 38, /* L */
318 [0x14] = 40, /* ' (Apostrophe) */
319 [0x16] = 44, /* Z */
320 [0x17] = 45, /* X */
321 [0x18] = 46, /* C */
322 [0x19] = 47, /* V */
323 [0x1a] = 48, /* B */
324 [0x1b] = 49, /* N */
325 [0x1c] = 42, /* Shift (Left shift) */
326 [0x1f] = 65, /* Zoom+ (F7) */
327
328 [0x21] = 18, /* E */
329 [0x22] = 39, /* ; (Semicolon) */
330 [0x23] = 12, /* - (Minus) */
331 [0x24] = 13, /* = (Equal) */
332 [0x2b] = 56, /* Fn (Left Alt) */
333 [0x2c] = 50, /* M */
334 [0x2f] = 66, /* Zoom- (F8) */
335
336 [0x31] = 19, /* R */
337 [0x32] = 29 | M, /* Right Ctrl */
338 [0x34] = 57, /* Space */
339 [0x35] = 51, /* , (Comma) */
340 [0x37] = 72 | M, /* Up */
341 [0x3c] = 82 | M, /* Compose (Insert) */
342 [0x3f] = 64, /* FullScreen (F6) */
343
344 [0x41] = 20, /* T */
345 [0x44] = 52, /* . (Dot) */
346 [0x46] = 77 | M, /* Right */
347 [0x4f] = 63, /* Home (F5) */
348 [0x51] = 21, /* Y */
349 [0x53] = 80 | M, /* Down */
350 [0x55] = 28, /* Enter */
351 [0x5f] = 1, /* Cycle (ESC) */
352
353 [0x61] = 22, /* U */
354 [0x64] = 75 | M, /* Left */
355
356 [0x71] = 23, /* I */
357 #if 0
358 [0x75] = 28 | M, /* KP Enter (KP Enter) */
359 #else
360 [0x75] = 15, /* KP Enter (Tab) */
361 #endif
362 };
363
364 #undef M
365
366 static void n810_kbd_setup(struct n800_s *s)
367 {
368 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
369 int i;
370
371 for (i = 0; i < 0x80; i ++)
372 s->keymap[i] = -1;
373 for (i = 0; i < 0x80; i ++)
374 if (n810_keys[i] > 0)
375 s->keymap[n810_keys[i]] = i;
376
377 qemu_add_kbd_event_handler(n810_key_event, s);
378
379 /* Attach the LM8322 keyboard to the I2C bus,
380 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
381 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
382 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
383 }
384
385 /* LCD MIPI DBI-C controller (URAL) */
386 struct mipid_s {
387 int resp[4];
388 int param[4];
389 int p;
390 int pm;
391 int cmd;
392
393 int sleep;
394 int booster;
395 int te;
396 int selfcheck;
397 int partial;
398 int normal;
399 int vscr;
400 int invert;
401 int onoff;
402 int gamma;
403 uint32_t id;
404 };
405
406 static void mipid_reset(struct mipid_s *s)
407 {
408 if (!s->sleep)
409 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
410
411 s->pm = 0;
412 s->cmd = 0;
413
414 s->sleep = 1;
415 s->booster = 0;
416 s->selfcheck =
417 (1 << 7) | /* Register loading OK. */
418 (1 << 5) | /* The chip is attached. */
419 (1 << 4); /* Display glass still in one piece. */
420 s->te = 0;
421 s->partial = 0;
422 s->normal = 1;
423 s->vscr = 0;
424 s->invert = 0;
425 s->onoff = 1;
426 s->gamma = 0;
427 }
428
429 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
430 {
431 struct mipid_s *s = (struct mipid_s *) opaque;
432 uint8_t ret;
433
434 if (len > 9)
435 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
436
437 if (s->p >= ARRAY_SIZE(s->resp))
438 ret = 0;
439 else
440 ret = s->resp[s->p ++];
441 if (s->pm --> 0)
442 s->param[s->pm] = cmd;
443 else
444 s->cmd = cmd;
445
446 switch (s->cmd) {
447 case 0x00: /* NOP */
448 break;
449
450 case 0x01: /* SWRESET */
451 mipid_reset(s);
452 break;
453
454 case 0x02: /* BSTROFF */
455 s->booster = 0;
456 break;
457 case 0x03: /* BSTRON */
458 s->booster = 1;
459 break;
460
461 case 0x04: /* RDDID */
462 s->p = 0;
463 s->resp[0] = (s->id >> 16) & 0xff;
464 s->resp[1] = (s->id >> 8) & 0xff;
465 s->resp[2] = (s->id >> 0) & 0xff;
466 break;
467
468 case 0x06: /* RD_RED */
469 case 0x07: /* RD_GREEN */
470 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
471 * for the bootloader one needs to change this. */
472 case 0x08: /* RD_BLUE */
473 s->p = 0;
474 /* TODO: return first pixel components */
475 s->resp[0] = 0x01;
476 break;
477
478 case 0x09: /* RDDST */
479 s->p = 0;
480 s->resp[0] = s->booster << 7;
481 s->resp[1] = (5 << 4) | (s->partial << 2) |
482 (s->sleep << 1) | s->normal;
483 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
484 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
485 s->resp[3] = s->gamma << 6;
486 break;
487
488 case 0x0a: /* RDDPM */
489 s->p = 0;
490 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
491 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
492 break;
493 case 0x0b: /* RDDMADCTR */
494 s->p = 0;
495 s->resp[0] = 0;
496 break;
497 case 0x0c: /* RDDCOLMOD */
498 s->p = 0;
499 s->resp[0] = 5; /* 65K colours */
500 break;
501 case 0x0d: /* RDDIM */
502 s->p = 0;
503 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
504 break;
505 case 0x0e: /* RDDSM */
506 s->p = 0;
507 s->resp[0] = s->te << 7;
508 break;
509 case 0x0f: /* RDDSDR */
510 s->p = 0;
511 s->resp[0] = s->selfcheck;
512 break;
513
514 case 0x10: /* SLPIN */
515 s->sleep = 1;
516 break;
517 case 0x11: /* SLPOUT */
518 s->sleep = 0;
519 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
520 break;
521
522 case 0x12: /* PTLON */
523 s->partial = 1;
524 s->normal = 0;
525 s->vscr = 0;
526 break;
527 case 0x13: /* NORON */
528 s->partial = 0;
529 s->normal = 1;
530 s->vscr = 0;
531 break;
532
533 case 0x20: /* INVOFF */
534 s->invert = 0;
535 break;
536 case 0x21: /* INVON */
537 s->invert = 1;
538 break;
539
540 case 0x22: /* APOFF */
541 case 0x23: /* APON */
542 goto bad_cmd;
543
544 case 0x25: /* WRCNTR */
545 if (s->pm < 0)
546 s->pm = 1;
547 goto bad_cmd;
548
549 case 0x26: /* GAMSET */
550 if (!s->pm)
551 s->gamma = ffs(s->param[0] & 0xf) - 1;
552 else if (s->pm < 0)
553 s->pm = 1;
554 break;
555
556 case 0x28: /* DISPOFF */
557 s->onoff = 0;
558 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
559 break;
560 case 0x29: /* DISPON */
561 s->onoff = 1;
562 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
563 break;
564
565 case 0x2a: /* CASET */
566 case 0x2b: /* RASET */
567 case 0x2c: /* RAMWR */
568 case 0x2d: /* RGBSET */
569 case 0x2e: /* RAMRD */
570 case 0x30: /* PTLAR */
571 case 0x33: /* SCRLAR */
572 goto bad_cmd;
573
574 case 0x34: /* TEOFF */
575 s->te = 0;
576 break;
577 case 0x35: /* TEON */
578 if (!s->pm)
579 s->te = 1;
580 else if (s->pm < 0)
581 s->pm = 1;
582 break;
583
584 case 0x36: /* MADCTR */
585 goto bad_cmd;
586
587 case 0x37: /* VSCSAD */
588 s->partial = 0;
589 s->normal = 0;
590 s->vscr = 1;
591 break;
592
593 case 0x38: /* IDMOFF */
594 case 0x39: /* IDMON */
595 case 0x3a: /* COLMOD */
596 goto bad_cmd;
597
598 case 0xb0: /* CLKINT / DISCTL */
599 case 0xb1: /* CLKEXT */
600 if (s->pm < 0)
601 s->pm = 2;
602 break;
603
604 case 0xb4: /* FRMSEL */
605 break;
606
607 case 0xb5: /* FRM8SEL */
608 case 0xb6: /* TMPRNG / INIESC */
609 case 0xb7: /* TMPHIS / NOP2 */
610 case 0xb8: /* TMPREAD / MADCTL */
611 case 0xba: /* DISTCTR */
612 case 0xbb: /* EPVOL */
613 goto bad_cmd;
614
615 case 0xbd: /* Unknown */
616 s->p = 0;
617 s->resp[0] = 0;
618 s->resp[1] = 1;
619 break;
620
621 case 0xc2: /* IFMOD */
622 if (s->pm < 0)
623 s->pm = 2;
624 break;
625
626 case 0xc6: /* PWRCTL */
627 case 0xc7: /* PPWRCTL */
628 case 0xd0: /* EPWROUT */
629 case 0xd1: /* EPWRIN */
630 case 0xd4: /* RDEV */
631 case 0xd5: /* RDRR */
632 goto bad_cmd;
633
634 case 0xda: /* RDID1 */
635 s->p = 0;
636 s->resp[0] = (s->id >> 16) & 0xff;
637 break;
638 case 0xdb: /* RDID2 */
639 s->p = 0;
640 s->resp[0] = (s->id >> 8) & 0xff;
641 break;
642 case 0xdc: /* RDID3 */
643 s->p = 0;
644 s->resp[0] = (s->id >> 0) & 0xff;
645 break;
646
647 default:
648 bad_cmd:
649 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
650 break;
651 }
652
653 return ret;
654 }
655
656 static void *mipid_init(void)
657 {
658 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
659
660 s->id = 0x838f03;
661 mipid_reset(s);
662
663 return s;
664 }
665
666 static void n8x0_spi_setup(struct n800_s *s)
667 {
668 void *tsc = s->ts.opaque;
669 void *mipid = mipid_init();
670
671 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
672 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
673 }
674
675 /* This task is normally performed by the bootloader. If we're loading
676 * a kernel directly, we need to enable the Blizzard ourselves. */
677 static void n800_dss_init(struct rfbi_chip_s *chip)
678 {
679 uint8_t *fb_blank;
680
681 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
682 chip->write(chip->opaque, 1, 0x64);
683 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
684 chip->write(chip->opaque, 1, 0x1e);
685 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
686 chip->write(chip->opaque, 1, 0xe0);
687 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
688 chip->write(chip->opaque, 1, 0x01);
689 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
690 chip->write(chip->opaque, 1, 0x06);
691 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
692 chip->write(chip->opaque, 1, 1); /* Enable bit */
693
694 chip->write(chip->opaque, 0, 0x6c);
695 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
696 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
697 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
698 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
699 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
700 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
701 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
702 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
703 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
704 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
705 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
706 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
707 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
708 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
709 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
710 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
711 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
712 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
713
714 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
715 /* Display Memory Data Port */
716 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
717 g_free(fb_blank);
718 }
719
720 static void n8x0_dss_setup(struct n800_s *s)
721 {
722 s->blizzard.opaque = s1d13745_init(NULL);
723 s->blizzard.block = s1d13745_write_block;
724 s->blizzard.write = s1d13745_write;
725 s->blizzard.read = s1d13745_read;
726
727 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
728 }
729
730 static void n8x0_cbus_setup(struct n800_s *s)
731 {
732 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
733 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
734 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
735
736 CBus *cbus = cbus_init(dat_out);
737
738 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
739 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
740 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
741
742 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
743 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
744 }
745
746 static void n8x0_uart_setup(struct n800_s *s)
747 {
748 CharDriverState *radio = uart_hci_init(
749 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
750
751 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
752 csrhci_pins_get(radio)[csrhci_pin_reset]);
753 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
754 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
755
756 omap_uart_attach(s->cpu->uart[BT_UART], radio);
757 }
758
759 static void n8x0_usb_power_cb(void *opaque, int line, int level)
760 {
761 struct n800_s *s = opaque;
762
763 tusb6010_power(s->usb, level);
764 }
765
766 static void n8x0_usb_setup(struct n800_s *s)
767 {
768 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
769 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
770 TUSBState *tusb = tusb6010_init(tusb_irq);
771
772 /* Using the NOR interface */
773 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
774 tusb6010_async_io(tusb), NULL, NULL, tusb);
775 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
776 tusb6010_sync_io(tusb), NULL, NULL, tusb);
777
778 s->usb = tusb;
779 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
780 }
781
782 /* Setup done before the main bootloader starts by some early setup code
783 * - used when we want to run the main bootloader in emulation. This
784 * isn't documented. */
785 static uint32_t n800_pinout[104] = {
786 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
787 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
788 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
789 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
790 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
791 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
792 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
793 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
794 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
795 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
796 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
797 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
798 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
799 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
800 0x00000000, 0x00000038, 0x00340000, 0x00000000,
801 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
802 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
803 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
804 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
805 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
806 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
807 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
808 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
809 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
810 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
811 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
812 };
813
814 static void n800_setup_nolo_tags(void *sram_base)
815 {
816 int i;
817 uint32_t *p = sram_base + 0x8000;
818 uint32_t *v = sram_base + 0xa000;
819
820 memset(p, 0, 0x3000);
821
822 strcpy((void *) (p + 0), "QEMU N800");
823
824 strcpy((void *) (p + 8), "F5");
825
826 stl_raw(p + 10, 0x04f70000);
827 strcpy((void *) (p + 9), "RX-34");
828
829 /* RAM size in MB? */
830 stl_raw(p + 12, 0x80);
831
832 /* Pointer to the list of tags */
833 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
834
835 /* The NOLO tags start here */
836 p = sram_base + 0x9000;
837 #define ADD_TAG(tag, len) \
838 stw_raw((uint16_t *) p + 0, tag); \
839 stw_raw((uint16_t *) p + 1, len); p ++; \
840 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
841
842 /* OMAP STI console? Pin out settings? */
843 ADD_TAG(0x6e01, 414);
844 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
845 stl_raw(v ++, n800_pinout[i]);
846
847 /* Kernel memsize? */
848 ADD_TAG(0x6e05, 1);
849 stl_raw(v ++, 2);
850
851 /* NOLO serial console */
852 ADD_TAG(0x6e02, 4);
853 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
854
855 #if 0
856 /* CBUS settings (Retu/AVilma) */
857 ADD_TAG(0x6e03, 6);
858 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
859 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
860 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
861 v += 2;
862 #endif
863
864 /* Nokia ASIC BB5 (Retu/Tahvo) */
865 ADD_TAG(0x6e0a, 4);
866 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
867 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
868 v ++;
869
870 /* LCD console? */
871 ADD_TAG(0x6e04, 4);
872 stw_raw((uint16_t *) v + 0, 30); /* ??? */
873 stw_raw((uint16_t *) v + 1, 24); /* ??? */
874 v ++;
875
876 #if 0
877 /* LCD settings */
878 ADD_TAG(0x6e06, 2);
879 stw_raw((uint16_t *) (v ++), 15); /* ??? */
880 #endif
881
882 /* I^2C (Menelaus) */
883 ADD_TAG(0x6e07, 4);
884 stl_raw(v ++, 0x00720000); /* ??? */
885
886 /* Unknown */
887 ADD_TAG(0x6e0b, 6);
888 stw_raw((uint16_t *) v + 0, 94); /* ??? */
889 stw_raw((uint16_t *) v + 1, 23); /* ??? */
890 stw_raw((uint16_t *) v + 2, 0); /* ??? */
891 v += 2;
892
893 /* OMAP gpio switch info */
894 ADD_TAG(0x6e0c, 80);
895 strcpy((void *) v, "bat_cover"); v += 3;
896 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
897 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
898 v += 2;
899 strcpy((void *) v, "cam_act"); v += 3;
900 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
901 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
902 v += 2;
903 strcpy((void *) v, "cam_turn"); v += 3;
904 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
905 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
906 v += 2;
907 strcpy((void *) v, "headphone"); v += 3;
908 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
909 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
910 v += 2;
911
912 /* Bluetooth */
913 ADD_TAG(0x6e0e, 12);
914 stl_raw(v ++, 0x5c623d01); /* ??? */
915 stl_raw(v ++, 0x00000201); /* ??? */
916 stl_raw(v ++, 0x00000000); /* ??? */
917
918 /* CX3110x WLAN settings */
919 ADD_TAG(0x6e0f, 8);
920 stl_raw(v ++, 0x00610025); /* ??? */
921 stl_raw(v ++, 0xffff0057); /* ??? */
922
923 /* MMC host settings */
924 ADD_TAG(0x6e10, 12);
925 stl_raw(v ++, 0xffff000f); /* ??? */
926 stl_raw(v ++, 0xffffffff); /* ??? */
927 stl_raw(v ++, 0x00000060); /* ??? */
928
929 /* OneNAND chip select */
930 ADD_TAG(0x6e11, 10);
931 stl_raw(v ++, 0x00000401); /* ??? */
932 stl_raw(v ++, 0x0002003a); /* ??? */
933 stl_raw(v ++, 0x00000002); /* ??? */
934
935 /* TEA5761 sensor settings */
936 ADD_TAG(0x6e12, 2);
937 stl_raw(v ++, 93); /* GPIO num ??? */
938
939 #if 0
940 /* Unknown tag */
941 ADD_TAG(6e09, 0);
942
943 /* Kernel UART / console */
944 ADD_TAG(6e12, 0);
945 #endif
946
947 /* End of the list */
948 stl_raw(p ++, 0x00000000);
949 stl_raw(p ++, 0x00000000);
950 }
951
952 /* This task is normally performed by the bootloader. If we're loading
953 * a kernel directly, we need to set up GPMC mappings ourselves. */
954 static void n800_gpmc_init(struct n800_s *s)
955 {
956 uint32_t config7 =
957 (0xf << 8) | /* MASKADDRESS */
958 (1 << 6) | /* CSVALID */
959 (4 << 0); /* BASEADDRESS */
960
961 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
962 (void *) &config7, sizeof(config7));
963 }
964
965 /* Setup sequence done by the bootloader */
966 static void n8x0_boot_init(void *opaque)
967 {
968 struct n800_s *s = (struct n800_s *) opaque;
969 uint32_t buf;
970
971 /* PRCM setup */
972 #define omap_writel(addr, val) \
973 buf = (val); \
974 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
975
976 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
977 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
978 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
979 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
980 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
981 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
982 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
983 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
984 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
985 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
986 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
987 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
988 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
989 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
990 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
991 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
992 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
993 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
994 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
995 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
996 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
997 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
998 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
999 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1000 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1001 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1002 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1003 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1004 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1005 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1006 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1007 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1008 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1009 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1010 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1011 (0x78 << 12) | (6 << 8));
1012 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1013
1014 /* GPMC setup */
1015 n800_gpmc_init(s);
1016
1017 /* Video setup */
1018 n800_dss_init(&s->blizzard);
1019
1020 /* CPU setup */
1021 s->cpu->env->GE = 0x5;
1022
1023 /* If the machine has a slided keyboard, open it */
1024 if (s->kbd)
1025 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
1026 }
1027
1028 #define OMAP_TAG_NOKIA_BT 0x4e01
1029 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1030 #define OMAP_TAG_CBUS 0x4e03
1031 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1032
1033 static struct omap_gpiosw_info_s {
1034 const char *name;
1035 int line;
1036 int type;
1037 } n800_gpiosw_info[] = {
1038 {
1039 "bat_cover", N800_BAT_COVER_GPIO,
1040 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1041 }, {
1042 "cam_act", N800_CAM_ACT_GPIO,
1043 OMAP_GPIOSW_TYPE_ACTIVITY,
1044 }, {
1045 "cam_turn", N800_CAM_TURN_GPIO,
1046 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1047 }, {
1048 "headphone", N8X0_HEADPHONE_GPIO,
1049 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1050 },
1051 { NULL }
1052 }, n810_gpiosw_info[] = {
1053 {
1054 "gps_reset", N810_GPS_RESET_GPIO,
1055 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1056 }, {
1057 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1058 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1059 }, {
1060 "headphone", N8X0_HEADPHONE_GPIO,
1061 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1062 }, {
1063 "kb_lock", N810_KB_LOCK_GPIO,
1064 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1065 }, {
1066 "sleepx_led", N810_SLEEPX_LED_GPIO,
1067 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1068 }, {
1069 "slide", N810_SLIDE_GPIO,
1070 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1071 },
1072 { NULL }
1073 };
1074
1075 static struct omap_partition_info_s {
1076 uint32_t offset;
1077 uint32_t size;
1078 int mask;
1079 const char *name;
1080 } n800_part_info[] = {
1081 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1082 { 0x00020000, 0x00060000, 0x0, "config" },
1083 { 0x00080000, 0x00200000, 0x0, "kernel" },
1084 { 0x00280000, 0x00200000, 0x3, "initfs" },
1085 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1086
1087 { 0, 0, 0, NULL }
1088 }, n810_part_info[] = {
1089 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1090 { 0x00020000, 0x00060000, 0x0, "config" },
1091 { 0x00080000, 0x00220000, 0x0, "kernel" },
1092 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1093 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1094
1095 { 0, 0, 0, NULL }
1096 };
1097
1098 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1099
1100 static int n8x0_atag_setup(void *p, int model)
1101 {
1102 uint8_t *b;
1103 uint16_t *w;
1104 uint32_t *l;
1105 struct omap_gpiosw_info_s *gpiosw;
1106 struct omap_partition_info_s *partition;
1107 const char *tag;
1108
1109 w = p;
1110
1111 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1112 stw_raw(w ++, 4); /* u16 len */
1113 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1114 w ++;
1115
1116 #if 0
1117 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1118 stw_raw(w ++, 4); /* u16 len */
1119 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1120 stw_raw(w ++, 115200); /* u32 console_speed */
1121 #endif
1122
1123 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1124 stw_raw(w ++, 36); /* u16 len */
1125 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1126 w += 8;
1127 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1128 w += 8;
1129 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1130 stw_raw(w ++, 24); /* u8 data_lines */
1131
1132 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1133 stw_raw(w ++, 8); /* u16 len */
1134 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1135 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1136 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1137 w ++;
1138
1139 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1140 stw_raw(w ++, 4); /* u16 len */
1141 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1142 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1143
1144 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1145 for (; gpiosw->name; gpiosw ++) {
1146 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1147 stw_raw(w ++, 20); /* u16 len */
1148 strcpy((void *) w, gpiosw->name); /* char name[12] */
1149 w += 6;
1150 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1151 stw_raw(w ++, gpiosw->type);
1152 stw_raw(w ++, 0);
1153 stw_raw(w ++, 0);
1154 }
1155
1156 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1157 stw_raw(w ++, 12); /* u16 len */
1158 b = (void *) w;
1159 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1160 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1161 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1162 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1163 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1164 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1165 b += 6;
1166 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1167 w = (void *) b;
1168
1169 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1170 stw_raw(w ++, 8); /* u16 len */
1171 stw_raw(w ++, 0x25); /* u8 chip_type */
1172 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1173 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1174 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1175
1176 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1177 stw_raw(w ++, 16); /* u16 len */
1178 if (model == 810) {
1179 stw_raw(w ++, 0x23f); /* unsigned flags */
1180 stw_raw(w ++, -1); /* s16 power_pin */
1181 stw_raw(w ++, -1); /* s16 switch_pin */
1182 stw_raw(w ++, -1); /* s16 wp_pin */
1183 stw_raw(w ++, 0x240); /* unsigned flags */
1184 stw_raw(w ++, 0xc000); /* s16 power_pin */
1185 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1186 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1187 } else {
1188 stw_raw(w ++, 0xf); /* unsigned flags */
1189 stw_raw(w ++, -1); /* s16 power_pin */
1190 stw_raw(w ++, -1); /* s16 switch_pin */
1191 stw_raw(w ++, -1); /* s16 wp_pin */
1192 stw_raw(w ++, 0); /* unsigned flags */
1193 stw_raw(w ++, 0); /* s16 power_pin */
1194 stw_raw(w ++, 0); /* s16 switch_pin */
1195 stw_raw(w ++, 0); /* s16 wp_pin */
1196 }
1197
1198 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1199 stw_raw(w ++, 4); /* u16 len */
1200 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1201 w ++;
1202
1203 partition = (model == 810) ? n810_part_info : n800_part_info;
1204 for (; partition->name; partition ++) {
1205 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1206 stw_raw(w ++, 28); /* u16 len */
1207 strcpy((void *) w, partition->name); /* char name[16] */
1208 l = (void *) (w + 8);
1209 stl_raw(l ++, partition->size); /* unsigned int size */
1210 stl_raw(l ++, partition->offset); /* unsigned int offset */
1211 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1212 w = (void *) l;
1213 }
1214
1215 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1216 stw_raw(w ++, 12); /* u16 len */
1217 #if 0
1218 strcpy((void *) w, "por"); /* char reason_str[12] */
1219 strcpy((void *) w, "charger"); /* char reason_str[12] */
1220 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1221 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1222 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1223 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1224 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1225 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1226 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1227 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1228 #else
1229 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1230 #endif
1231 w += 6;
1232
1233 tag = (model == 810) ? "RX-44" : "RX-34";
1234 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1235 stw_raw(w ++, 24); /* u16 len */
1236 strcpy((void *) w, "product"); /* char component[12] */
1237 w += 6;
1238 strcpy((void *) w, tag); /* char version[12] */
1239 w += 6;
1240
1241 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1242 stw_raw(w ++, 24); /* u16 len */
1243 strcpy((void *) w, "hw-build"); /* char component[12] */
1244 w += 6;
1245 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1246 w += 6;
1247
1248 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1249 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1250 stw_raw(w ++, 24); /* u16 len */
1251 strcpy((void *) w, "nolo"); /* char component[12] */
1252 w += 6;
1253 strcpy((void *) w, tag); /* char version[12] */
1254 w += 6;
1255
1256 return (void *) w - p;
1257 }
1258
1259 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1260 {
1261 return n8x0_atag_setup(p, 800);
1262 }
1263
1264 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1265 {
1266 return n8x0_atag_setup(p, 810);
1267 }
1268
1269 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1270 const char *kernel_filename,
1271 const char *kernel_cmdline, const char *initrd_filename,
1272 const char *cpu_model, struct arm_boot_info *binfo, int model)
1273 {
1274 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1275 int sdram_size = binfo->ram_size;
1276 DisplayState *ds;
1277
1278 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1279
1280 /* Setup peripherals
1281 *
1282 * Believed external peripherals layout in the N810:
1283 * (spi bus 1)
1284 * tsc2005
1285 * lcd_mipid
1286 * (spi bus 2)
1287 * Conexant cx3110x (WLAN)
1288 * optional: pc2400m (WiMAX)
1289 * (i2c bus 0)
1290 * TLV320AIC33 (audio codec)
1291 * TCM825x (camera by Toshiba)
1292 * lp5521 (clever LEDs)
1293 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1294 * lm8323 (keypad, manf 00, rev 04)
1295 * (i2c bus 1)
1296 * tmp105 (temperature sensor, hwmon)
1297 * menelaus (pm)
1298 * (somewhere on i2c - maybe N800-only)
1299 * tea5761 (FM tuner)
1300 * (serial 0)
1301 * GPS
1302 * (some serial port)
1303 * csr41814 (Bluetooth)
1304 */
1305 n8x0_gpio_setup(s);
1306 n8x0_nand_setup(s);
1307 n8x0_i2c_setup(s);
1308 if (model == 800)
1309 n800_tsc_kbd_setup(s);
1310 else if (model == 810) {
1311 n810_tsc_setup(s);
1312 n810_kbd_setup(s);
1313 }
1314 n8x0_spi_setup(s);
1315 n8x0_dss_setup(s);
1316 n8x0_cbus_setup(s);
1317 n8x0_uart_setup(s);
1318 if (usb_enabled)
1319 n8x0_usb_setup(s);
1320
1321 if (kernel_filename) {
1322 /* Or at the linux loader. */
1323 binfo->kernel_filename = kernel_filename;
1324 binfo->kernel_cmdline = kernel_cmdline;
1325 binfo->initrd_filename = initrd_filename;
1326 arm_load_kernel(s->cpu->env, binfo);
1327
1328 qemu_register_reset(n8x0_boot_init, s);
1329 }
1330
1331 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
1332 int rom_size;
1333 uint8_t nolo_tags[0x10000];
1334 /* No, wait, better start at the ROM. */
1335 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1336
1337 /* This is intended for loading the `secondary.bin' program from
1338 * Nokia images (the NOLO bootloader). The entry point seems
1339 * to be at OMAP2_Q2_BASE + 0x400000.
1340 *
1341 * The `2nd.bin' files contain some kind of earlier boot code and
1342 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1343 *
1344 * The code above is for loading the `zImage' file from Nokia
1345 * images. */
1346 rom_size = load_image_targphys(option_rom[0].name,
1347 OMAP2_Q2_BASE + 0x400000,
1348 sdram_size - 0x400000);
1349 printf("%i bytes of image loaded\n", rom_size);
1350
1351 n800_setup_nolo_tags(nolo_tags);
1352 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1353 }
1354 /* FIXME: We shouldn't really be doing this here. The LCD controller
1355 will set the size once configured, so this just sets an initial
1356 size until the guest activates the display. */
1357 ds = get_displaystate();
1358 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1359 dpy_resize(ds);
1360 }
1361
1362 static struct arm_boot_info n800_binfo = {
1363 .loader_start = OMAP2_Q2_BASE,
1364 /* Actually two chips of 0x4000000 bytes each */
1365 .ram_size = 0x08000000,
1366 .board_id = 0x4f7,
1367 .atag_board = n800_atag_setup,
1368 };
1369
1370 static struct arm_boot_info n810_binfo = {
1371 .loader_start = OMAP2_Q2_BASE,
1372 /* Actually two chips of 0x4000000 bytes each */
1373 .ram_size = 0x08000000,
1374 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1375 * used by some older versions of the bootloader and 5555 is used
1376 * instead (including versions that shipped with many devices). */
1377 .board_id = 0x60c,
1378 .atag_board = n810_atag_setup,
1379 };
1380
1381 static void n800_init(ram_addr_t ram_size,
1382 const char *boot_device,
1383 const char *kernel_filename, const char *kernel_cmdline,
1384 const char *initrd_filename, const char *cpu_model)
1385 {
1386 return n8x0_init(ram_size, boot_device,
1387 kernel_filename, kernel_cmdline, initrd_filename,
1388 cpu_model, &n800_binfo, 800);
1389 }
1390
1391 static void n810_init(ram_addr_t ram_size,
1392 const char *boot_device,
1393 const char *kernel_filename, const char *kernel_cmdline,
1394 const char *initrd_filename, const char *cpu_model)
1395 {
1396 return n8x0_init(ram_size, boot_device,
1397 kernel_filename, kernel_cmdline, initrd_filename,
1398 cpu_model, &n810_binfo, 810);
1399 }
1400
1401 static QEMUMachine n800_machine = {
1402 .name = "n800",
1403 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1404 .init = n800_init,
1405 };
1406
1407 static QEMUMachine n810_machine = {
1408 .name = "n810",
1409 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1410 .init = n810_init,
1411 };
1412
1413 static void nseries_machine_init(void)
1414 {
1415 qemu_register_machine(&n800_machine);
1416 qemu_register_machine(&n810_machine);
1417 }
1418
1419 machine_init(nseries_machine_init);
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