2 * m68k virtual CPU header
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
37 #define EXCP_ACCESS 2 /* Access (MMU) error. */
38 #define EXCP_ADDRESS 3 /* Address error. */
39 #define EXCP_ILLEGAL 4 /* Illegal instruction. */
40 #define EXCP_DIV0 5 /* Divide by zero */
41 #define EXCP_CHK 6 /* CHK, CHK2 Instructions */
42 #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */
43 #define EXCP_PRIVILEGE 8 /* Privilege violation. */
45 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
46 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
47 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
48 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
49 #define EXCP_FORMAT 14 /* RTE format error. */
50 #define EXCP_UNINITIALIZED 15
51 #define EXCP_SPURIOUS 24 /* Spurious interrupt */
52 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */
53 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */
54 #define EXCP_TRAP0 32 /* User trap #0. */
55 #define EXCP_TRAP15 47 /* User trap #15. */
56 #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */
57 #define EXCP_FP_INEX 49 /* Inexact result */
58 #define EXCP_FP_DZ 50 /* Divide by Zero */
59 #define EXCP_FP_UNFL 51 /* Underflow */
60 #define EXCP_FP_OPERR 52 /* Operand Error */
61 #define EXCP_FP_OVFL 53 /* Overflow */
62 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
63 #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */
64 #define EXCP_MMU_CONF 56 /* MMU Configuration Error */
65 #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */
66 #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */
68 #define EXCP_RTE 0x100
69 #define EXCP_HALT_INSN 0x101
76 #define M68K_MAX_TTR 2
77 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
79 #define TARGET_INSN_START_EXTRA_WORDS 1
81 typedef CPU_LDoubleU FPReg
;
83 typedef struct CPUArchState
{
90 * The 68020/30/40 support two supervisor stacks, ISP and MSP.
91 * The 68000/10, Coldfire, and CPU32 only have USP/SSP.
93 * The current_sp is stored in aregs[7], the other here.
94 * The USP, SSP, and if used the additional ISP for 68020/30/40.
99 /* Condition flags. */
101 uint32_t cc_x
; /* always 0/1 */
102 uint32_t cc_n
; /* in bit 31 (i.e. negative) */
103 uint32_t cc_v
; /* in bit 31, unused, or computed from cc_n and cc_v */
104 uint32_t cc_c
; /* either 0/1, unused, or computed from cc_n and cc_v */
105 uint32_t cc_z
; /* == 0 or unused */
111 float_status fp_status
;
115 * EMAC Hardware deals with 48-bit values composed of one 32-bit and
116 * two 8-bit parts. We store a single 64-bit value and
117 * rearrange/extend this when changing modes.
126 * Holds the "address" value in between raising an exception
127 * and creation of the exception stack frame.
128 * Used for both Format 7 exceptions (Access, i.e. mmu)
129 * and Format 2 exceptions (chk, div0, trapcc, etc).
142 /* Control registers. */
153 /* Fields up to this point are cleared by a CPU reset */
154 struct {} end_reset_fields
;
156 /* Fields from here on are preserved across CPU reset. */
162 * @env: #CPUM68KState
164 * A Motorola 68k CPU.
175 #ifndef CONFIG_USER_ONLY
176 void m68k_cpu_do_interrupt(CPUState
*cpu
);
177 bool m68k_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
178 hwaddr
m68k_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
179 #endif /* !CONFIG_USER_ONLY */
180 void m68k_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
181 int m68k_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
182 int m68k_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
184 void m68k_tcg_init(void);
185 void m68k_cpu_init_gdb(M68kCPU
*cpu
);
186 uint32_t cpu_m68k_get_ccr(CPUM68KState
*env
);
187 void cpu_m68k_set_ccr(CPUM68KState
*env
, uint32_t);
188 void cpu_m68k_set_sr(CPUM68KState
*env
, uint32_t);
189 void cpu_m68k_restore_fp_status(CPUM68KState
*env
);
190 void cpu_m68k_set_fpcr(CPUM68KState
*env
, uint32_t val
);
194 * Instead of computing the condition codes after each m68k instruction,
195 * QEMU just stores one operand (called CC_SRC), the result
196 * (called CC_DEST) and the type of operation (called CC_OP). When the
197 * condition codes are needed, the condition codes can be calculated
198 * using this information. Condition codes are not generated if they
199 * are only needed for conditional branches.
202 /* Translator only -- use env->cc_op. */
205 /* Each flag bit computed into cc_[xcnvz]. */
208 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
209 CC_OP_ADDB
, CC_OP_ADDW
, CC_OP_ADDL
,
210 CC_OP_SUBB
, CC_OP_SUBW
, CC_OP_SUBL
,
212 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
213 CC_OP_CMPB
, CC_OP_CMPW
, CC_OP_CMPL
,
215 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
231 #define SR_T_SHIFT 14
234 #define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT)
235 #define M68K_SR_TRACE_ANY_INS 0x2
241 /* bits for 68040 special status word */
242 #define M68K_CP_040 0x8000
243 #define M68K_CU_040 0x4000
244 #define M68K_CT_040 0x2000
245 #define M68K_CM_040 0x1000
246 #define M68K_MA_040 0x0800
247 #define M68K_ATC_040 0x0400
248 #define M68K_LK_040 0x0200
249 #define M68K_RW_040 0x0100
250 #define M68K_SIZ_040 0x0060
251 #define M68K_TT_040 0x0018
252 #define M68K_TM_040 0x0007
254 #define M68K_TM_040_DATA 0x0001
255 #define M68K_TM_040_CODE 0x0002
256 #define M68K_TM_040_SUPER 0x0004
258 /* bits for 68040 write back status word */
259 #define M68K_WBV_040 0x80
260 #define M68K_WBSIZ_040 0x60
261 #define M68K_WBBYT_040 0x20
262 #define M68K_WBWRD_040 0x40
263 #define M68K_WBLNG_040 0x00
264 #define M68K_WBTT_040 0x18
265 #define M68K_WBTM_040 0x07
267 /* bus access size codes */
268 #define M68K_BA_SIZE_MASK 0x60
269 #define M68K_BA_SIZE_BYTE 0x20
270 #define M68K_BA_SIZE_WORD 0x40
271 #define M68K_BA_SIZE_LONG 0x00
272 #define M68K_BA_SIZE_LINE 0x60
274 /* bus access transfer type codes */
275 #define M68K_BA_TT_MOVE16 0x08
277 /* bits for 68040 MMU status register (mmusr) */
278 #define M68K_MMU_B_040 0x0800
279 #define M68K_MMU_G_040 0x0400
280 #define M68K_MMU_U1_040 0x0200
281 #define M68K_MMU_U0_040 0x0100
282 #define M68K_MMU_S_040 0x0080
283 #define M68K_MMU_CM_040 0x0060
284 #define M68K_MMU_M_040 0x0010
285 #define M68K_MMU_WP_040 0x0004
286 #define M68K_MMU_T_040 0x0002
287 #define M68K_MMU_R_040 0x0001
289 #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
290 M68K_MMU_U0_040 | M68K_MMU_S_040 | \
291 M68K_MMU_CM_040 | M68K_MMU_M_040 | \
294 /* bits for 68040 MMU Translation Control Register */
295 #define M68K_TCR_ENABLED 0x8000
296 #define M68K_TCR_PAGE_8K 0x4000
298 /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
299 #define M68K_DESC_WRITEPROT 0x00000004
300 #define M68K_DESC_USED 0x00000008
301 #define M68K_DESC_MODIFIED 0x00000010
302 #define M68K_DESC_CACHEMODE 0x00000060
303 #define M68K_DESC_CM_WRTHRU 0x00000000
304 #define M68K_DESC_CM_COPYBK 0x00000020
305 #define M68K_DESC_CM_SERIAL 0x00000040
306 #define M68K_DESC_CM_NCACHE 0x00000060
307 #define M68K_DESC_SUPERONLY 0x00000080
308 #define M68K_DESC_USERATTR 0x00000300
309 #define M68K_DESC_USERATTR_SHIFT 8
310 #define M68K_DESC_GLOBAL 0x00000400
311 #define M68K_DESC_URESERVED 0x00000800
313 #define M68K_ROOT_POINTER_ENTRIES 128
314 #define M68K_4K_PAGE_MASK (~0xff)
315 #define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
316 #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
317 #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
318 #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
319 #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
320 #define M68K_8K_PAGE_MASK (~0x7f)
321 #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
322 #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
323 #define M68K_UDT_VALID(entry) (entry & 2)
324 #define M68K_PDT_VALID(entry) (entry & 3)
325 #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
326 #define M68K_INDIRECT_POINTER(addr) (addr & ~3)
327 #define M68K_TTS_POINTER_SHIFT 18
328 #define M68K_TTS_ROOT_SHIFT 25
330 /* bits for 68040 MMU Transparent Translation Registers */
331 #define M68K_TTR_ADDR_BASE 0xff000000
332 #define M68K_TTR_ADDR_MASK 0x00ff0000
333 #define M68K_TTR_ADDR_MASK_SHIFT 8
334 #define M68K_TTR_ENABLED 0x00008000
335 #define M68K_TTR_SFIELD 0x00006000
336 #define M68K_TTR_SFIELD_USER 0x0000
337 #define M68K_TTR_SFIELD_SUPER 0x2000
339 /* m68k Control Registers */
342 /* Memory Management Control Registers */
343 #define M68K_CR_ASID 0x003
344 #define M68K_CR_ACR0 0x004
345 #define M68K_CR_ACR1 0x005
346 #define M68K_CR_ACR2 0x006
347 #define M68K_CR_ACR3 0x007
348 #define M68K_CR_MMUBAR 0x008
350 /* Processor Miscellaneous Registers */
351 #define M68K_CR_PC 0x80F
353 /* Local Memory and Module Control Registers */
354 #define M68K_CR_ROMBAR0 0xC00
355 #define M68K_CR_ROMBAR1 0xC01
356 #define M68K_CR_RAMBAR0 0xC04
357 #define M68K_CR_RAMBAR1 0xC05
358 #define M68K_CR_MPCR 0xC0C
359 #define M68K_CR_EDRAMBAR 0xC0D
360 #define M68K_CR_SECMBAR 0xC0E
361 #define M68K_CR_MBAR 0xC0F
363 /* Local Memory Address Permutation Control Registers */
364 #define M68K_CR_PCR1U0 0xD02
365 #define M68K_CR_PCR1L0 0xD03
366 #define M68K_CR_PCR2U0 0xD04
367 #define M68K_CR_PCR2L0 0xD05
368 #define M68K_CR_PCR3U0 0xD06
369 #define M68K_CR_PCR3L0 0xD07
370 #define M68K_CR_PCR1U1 0xD0A
371 #define M68K_CR_PCR1L1 0xD0B
372 #define M68K_CR_PCR2U1 0xD0C
373 #define M68K_CR_PCR2L1 0xD0D
374 #define M68K_CR_PCR3U1 0xD0E
375 #define M68K_CR_PCR3L1 0xD0F
378 /* MC680[1234]0/CPU32 */
379 #define M68K_CR_SFC 0x000
380 #define M68K_CR_DFC 0x001
381 #define M68K_CR_USP 0x800
382 #define M68K_CR_VBR 0x801 /* + Coldfire */
385 #define M68K_CR_CACR 0x002 /* + Coldfire */
386 #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */
387 #define M68K_CR_MSP 0x803
388 #define M68K_CR_ISP 0x804
390 /* MC68040/MC68LC040 */
391 #define M68K_CR_TC 0x003
392 #define M68K_CR_ITT0 0x004
393 #define M68K_CR_ITT1 0x005
394 #define M68K_CR_DTT0 0x006
395 #define M68K_CR_DTT1 0x007
396 #define M68K_CR_MMUSR 0x805
397 #define M68K_CR_URP 0x806
398 #define M68K_CR_SRP 0x807
401 #define M68K_CR_IACR0 0x004
402 #define M68K_CR_IACR1 0x005
403 #define M68K_CR_DACR0 0x006
404 #define M68K_CR_DACR1 0x007
407 #define M68K_CR_BUSCR 0x008
408 #define M68K_CR_PCR 0x808
410 #define M68K_FPIAR_SHIFT 0
411 #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
412 #define M68K_FPSR_SHIFT 1
413 #define M68K_FPSR (1 << M68K_FPSR_SHIFT)
414 #define M68K_FPCR_SHIFT 2
415 #define M68K_FPCR (1 << M68K_FPCR_SHIFT)
417 /* Floating-Point Status Register */
420 #define FPSR_CC_MASK 0x0f000000
421 #define FPSR_CC_A 0x01000000 /* Not-A-Number */
422 #define FPSR_CC_I 0x02000000 /* Infinity */
423 #define FPSR_CC_Z 0x04000000 /* Zero */
424 #define FPSR_CC_N 0x08000000 /* Negative */
428 #define FPSR_QT_MASK 0x00ff0000
429 #define FPSR_QT_SHIFT 16
431 /* Floating-Point Control Register */
433 #define FPCR_RND_MASK 0x0030
434 #define FPCR_RND_N 0x0000
435 #define FPCR_RND_Z 0x0010
436 #define FPCR_RND_M 0x0020
437 #define FPCR_RND_P 0x0030
439 /* Rounding precision */
440 #define FPCR_PREC_MASK 0x00c0
441 #define FPCR_PREC_X 0x0000
442 #define FPCR_PREC_S 0x0040
443 #define FPCR_PREC_D 0x0080
444 #define FPCR_PREC_U 0x00c0
446 #define FPCR_EXCP_MASK 0xff00
448 /* CACR fields are implementation defined, but some bits are common. */
449 #define M68K_CACR_EUSP 0x10
451 #define MACSR_PAV0 0x100
452 #define MACSR_OMC 0x080
453 #define MACSR_SU 0x040
454 #define MACSR_FI 0x020
455 #define MACSR_RT 0x010
456 #define MACSR_N 0x008
457 #define MACSR_Z 0x004
458 #define MACSR_V 0x002
459 #define MACSR_EV 0x001
461 void m68k_set_irq_level(M68kCPU
*cpu
, int level
, uint8_t vector
);
462 void m68k_switch_sp(CPUM68KState
*env
);
464 void do_m68k_semihosting(CPUM68KState
*env
, int nr
);
467 * The 68000 family is defined in six main CPU classes, the 680[012346]0.
468 * Generally each successive CPU adds enhanced data/stack/instructions.
469 * However, some features are only common to one, or a few classes.
470 * The features covers those subsets of instructons.
472 * CPU32/32+ are basically 680010 compatible with some 68020 class instructons,
473 * and some additional CPU32 instructions. Mostly Supervisor state differences.
475 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu.
476 * There are 4 ColdFire core ISA revisions: A, A+, B and C.
477 * Each feature covers the subset of instructions common to the
478 * ISA revisions mentioned.
482 /* Base Motorola CPU set (not set for Coldfire CPUs) */
484 /* Motorola CPU feature sets */
490 /* Base Coldfire set Rev A. */
491 M68K_FEATURE_CF_ISA_A
,
493 M68K_FEATURE_CF_ISA_B
,
494 /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
495 M68K_FEATURE_CF_ISA_APLUSC
,
496 /* BRA with Long branch. (680[2346]0, ISA A+ or B). */
500 M68K_FEATURE_CF_EMAC
,
501 /* Revision B EMAC (dual accumulate). */
502 M68K_FEATURE_CF_EMAC_B
,
503 /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */
505 /* Master Stack Pointer. (680[234]0) */
507 /* 68020+ full extension word. */
508 M68K_FEATURE_EXT_FULL
,
509 /* word sized address index registers. */
510 M68K_FEATURE_WORD_INDEX
,
511 /* scaled address index registers. */
512 M68K_FEATURE_SCALED_INDEX
,
513 /* 32 bit mul/div. (680[2346]0, and CPU32) */
514 M68K_FEATURE_LONG_MULDIV
,
515 /* 64 bit mul/div. (680[2346]0, and CPU32) */
516 M68K_FEATURE_QUAD_MULDIV
,
517 /* Bcc with Long branches. (680[2346]0, and CPU32) */
519 /* BFxxx Bit field insns. (680[2346]0) */
520 M68K_FEATURE_BITFIELD
,
521 /* fpu insn. (680[46]0) */
523 /* CAS/CAS2[WL] insns. (680[2346]0) */
525 /* BKPT insn. (680[12346]0, and CPU32) */
527 /* RTD insn. (680[12346]0, and CPU32) */
529 /* CHK2 insn. (680[2346]0, and CPU32) */
531 /* MOVEP insn. (680[01234]0, and CPU32) */
533 /* MOVEC insn. (from 68010) */
535 /* Unaligned data accesses (680[2346]0) */
536 M68K_FEATURE_UNALIGNED_DATA
,
537 /* TRAPcc insn. (680[2346]0, and CPU32) */
539 /* MOVE from SR privileged (from 68010) */
540 M68K_FEATURE_MOVEFROMSR_PRIV
,
543 static inline bool m68k_feature(CPUM68KState
*env
, int feature
)
545 return (env
->features
& BIT_ULL(feature
)) != 0;
548 void m68k_cpu_list(void);
550 void register_m68k_insns (CPUM68KState
*env
);
553 /* 1 bit to define user level / supervisor access */
555 /* 1 bit to indicate direction */
557 /* 1 bit to indicate debug access */
559 /* PTEST instruction */
561 /* Type of instruction that generated the access */
562 ACCESS_CODE
= 0x10, /* Code fetch access */
563 ACCESS_DATA
= 0x20, /* Data load/store access */
566 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
567 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
568 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU
570 #define cpu_list m68k_cpu_list
572 /* MMU modes definitions */
573 #define MMU_KERNEL_IDX 0
574 #define MMU_USER_IDX 1
575 static inline int cpu_mmu_index (CPUM68KState
*env
, bool ifetch
)
577 return (env
->sr
& SR_S
) == 0 ? 1 : 0;
580 bool m68k_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
581 MMUAccessType access_type
, int mmu_idx
,
582 bool probe
, uintptr_t retaddr
);
583 #ifndef CONFIG_USER_ONLY
584 void m68k_cpu_transaction_failed(CPUState
*cs
, hwaddr physaddr
, vaddr addr
,
585 unsigned size
, MMUAccessType access_type
,
586 int mmu_idx
, MemTxAttrs attrs
,
587 MemTxResult response
, uintptr_t retaddr
);
590 #include "exec/cpu-all.h"
593 #define TB_FLAGS_MACSR 0x0f
594 #define TB_FLAGS_MSR_S_BIT 13
595 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
596 #define TB_FLAGS_SFC_S_BIT 14
597 #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
598 #define TB_FLAGS_DFC_S_BIT 15
599 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
600 #define TB_FLAGS_TRACE 16
601 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
603 static inline void cpu_get_tb_cpu_state(CPUM68KState
*env
, vaddr
*pc
,
604 uint64_t *cs_base
, uint32_t *flags
)
608 *flags
= (env
->macsr
>> 4) & TB_FLAGS_MACSR
;
609 if (env
->sr
& SR_S
) {
610 *flags
|= TB_FLAGS_MSR_S
;
611 *flags
|= (env
->sfc
<< (TB_FLAGS_SFC_S_BIT
- 2)) & TB_FLAGS_SFC_S
;
612 *flags
|= (env
->dfc
<< (TB_FLAGS_DFC_S_BIT
- 2)) & TB_FLAGS_DFC_S
;
614 if (M68K_SR_TRACE(env
->sr
) == M68K_SR_TRACE_ANY_INS
) {
615 *flags
|= TB_FLAGS_TRACE
;
619 void dump_mmu(CPUM68KState
*env
);