4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "cpu_loop-common.h"
25 /***********************************************************/
26 /* CPUX86 core interface */
28 uint64_t cpu_get_tsc(CPUX86State
*env
)
30 return cpu_get_host_ticks();
33 static void write_dt(void *ptr
, unsigned long addr
, unsigned long limit
,
38 e1
= (addr
<< 16) | (limit
& 0xffff);
39 e2
= ((addr
>> 16) & 0xff) | (addr
& 0xff000000) | (limit
& 0x000f0000);
46 static uint64_t *idt_table
;
48 static void set_gate64(void *ptr
, unsigned int type
, unsigned int dpl
,
49 uint64_t addr
, unsigned int sel
)
52 e1
= (addr
& 0xffff) | (sel
<< 16);
53 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
57 p
[2] = tswap32(addr
>> 32);
60 /* only dpl matters as we do only user space emulation */
61 static void set_idt(int n
, unsigned int dpl
)
63 set_gate64(idt_table
+ n
* 2, 0, dpl
, 0, 0);
66 static void set_gate(void *ptr
, unsigned int type
, unsigned int dpl
,
67 uint32_t addr
, unsigned int sel
)
70 e1
= (addr
& 0xffff) | (sel
<< 16);
71 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
77 /* only dpl matters as we do only user space emulation */
78 static void set_idt(int n
, unsigned int dpl
)
80 set_gate(idt_table
+ n
, 0, dpl
, 0, 0);
84 static void gen_signal(CPUX86State
*env
, int sig
, int code
, abi_ptr addr
)
86 target_siginfo_t info
= {
89 ._sifields
._sigfault
._addr
= addr
92 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
96 static bool write_ok_or_segv(CPUX86State
*env
, abi_ptr addr
, size_t len
)
99 * For all the vsyscalls, NULL means "don't write anything" not
100 * "write it at address 0".
102 if (addr
== 0 || access_ok(env_cpu(env
), VERIFY_WRITE
, addr
, len
)) {
106 env
->error_code
= PG_ERROR_W_MASK
| PG_ERROR_U_MASK
;
107 gen_signal(env
, TARGET_SIGSEGV
, TARGET_SEGV_MAPERR
, addr
);
112 * Since v3.1, the kernel traps and emulates the vsyscall page.
113 * Entry points other than the official generate SIGSEGV.
115 static void emulate_vsyscall(CPUX86State
*env
)
122 * Validate the entry point. We have already validated the page
123 * during translation to get here; now verify the offset.
125 switch (env
->eip
& ~TARGET_PAGE_MASK
) {
127 syscall
= TARGET_NR_gettimeofday
;
130 syscall
= TARGET_NR_time
;
133 syscall
= TARGET_NR_getcpu
;
140 * Validate the return address.
141 * Note that the kernel treats this the same as an invalid entry point.
143 if (get_user_u64(caller
, env
->regs
[R_ESP
])) {
148 * Validate the the pointer arguments.
151 case TARGET_NR_gettimeofday
:
152 if (!write_ok_or_segv(env
, env
->regs
[R_EDI
],
153 sizeof(struct target_timeval
)) ||
154 !write_ok_or_segv(env
, env
->regs
[R_ESI
],
155 sizeof(struct target_timezone
))) {
160 if (!write_ok_or_segv(env
, env
->regs
[R_EDI
], sizeof(abi_long
))) {
164 case TARGET_NR_getcpu
:
165 if (!write_ok_or_segv(env
, env
->regs
[R_EDI
], sizeof(uint32_t)) ||
166 !write_ok_or_segv(env
, env
->regs
[R_ESI
], sizeof(uint32_t))) {
171 g_assert_not_reached();
175 * Perform the syscall. None of the vsyscalls should need restarting.
177 ret
= do_syscall(env
, syscall
, env
->regs
[R_EDI
], env
->regs
[R_ESI
],
178 env
->regs
[R_EDX
], env
->regs
[10], env
->regs
[8],
180 g_assert(ret
!= -TARGET_ERESTARTSYS
);
181 g_assert(ret
!= -TARGET_QEMU_ESIGRETURN
);
182 if (ret
== -TARGET_EFAULT
) {
185 env
->regs
[R_EAX
] = ret
;
187 /* Emulate a ret instruction to leave the vsyscall page. */
189 env
->regs
[R_ESP
] += 8;
193 /* Like force_sig(SIGSEGV). */
194 gen_signal(env
, TARGET_SIGSEGV
, TARGET_SI_KERNEL
, 0);
198 void cpu_loop(CPUX86State
*env
)
200 CPUState
*cs
= env_cpu(env
);
207 trapnr
= cpu_exec(cs
);
209 process_queued_cpu_work(cs
);
213 /* linux syscall from int $0x80 */
214 ret
= do_syscall(env
,
223 if (ret
== -TARGET_ERESTARTSYS
) {
225 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
226 env
->regs
[R_EAX
] = ret
;
231 /* linux syscall from syscall instruction */
232 ret
= do_syscall(env
,
241 if (ret
== -TARGET_ERESTARTSYS
) {
243 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
244 env
->regs
[R_EAX
] = ret
;
250 emulate_vsyscall(env
);
255 gen_signal(env
, TARGET_SIGBUS
, TARGET_SI_KERNEL
, 0);
258 /* XXX: potential problem if ABI32 */
259 #ifndef TARGET_X86_64
260 if (env
->eflags
& VM_MASK
) {
261 handle_vm86_fault(env
);
265 gen_signal(env
, TARGET_SIGSEGV
, TARGET_SI_KERNEL
, 0);
268 gen_signal(env
, TARGET_SIGSEGV
,
269 (env
->error_code
& 1 ?
270 TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
),
274 #ifndef TARGET_X86_64
275 if (env
->eflags
& VM_MASK
) {
276 handle_vm86_trap(env
, trapnr
);
280 gen_signal(env
, TARGET_SIGFPE
, TARGET_FPE_INTDIV
, env
->eip
);
284 #ifndef TARGET_X86_64
285 if (env
->eflags
& VM_MASK
) {
286 handle_vm86_trap(env
, trapnr
);
290 if (trapnr
== EXCP01_DB
) {
291 gen_signal(env
, TARGET_SIGTRAP
, TARGET_TRAP_BRKPT
, env
->eip
);
293 gen_signal(env
, TARGET_SIGTRAP
, TARGET_SI_KERNEL
, 0);
298 #ifndef TARGET_X86_64
299 if (env
->eflags
& VM_MASK
) {
300 handle_vm86_trap(env
, trapnr
);
304 gen_signal(env
, TARGET_SIGSEGV
, TARGET_SI_KERNEL
, 0);
307 gen_signal(env
, TARGET_SIGILL
, TARGET_ILL_ILLOPN
, env
->eip
);
310 /* just indicate that signals should be handled asap */
313 gen_signal(env
, TARGET_SIGTRAP
, TARGET_TRAP_BRKPT
, 0);
316 cpu_exec_step_atomic(cs
);
319 pc
= env
->segs
[R_CS
].base
+ env
->eip
;
320 EXCP_DUMP(env
, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
324 process_pending_signals(env
);
328 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
330 env
->cr
[0] = CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
;
331 env
->hflags
|= HF_PE_MASK
| HF_CPL_MASK
;
332 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
333 env
->cr
[4] |= CR4_OSFXSR_MASK
;
334 env
->hflags
|= HF_OSFXSR_MASK
;
337 /* enable 64 bit mode if possible */
338 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
)) {
339 fprintf(stderr
, "The selected x86 CPU does not support 64 bit mode\n");
342 env
->cr
[4] |= CR4_PAE_MASK
;
343 env
->efer
|= MSR_EFER_LMA
| MSR_EFER_LME
;
344 env
->hflags
|= HF_LMA_MASK
;
347 /* flags setup : we activate the IRQs by default as in user mode */
348 env
->eflags
|= IF_MASK
;
350 /* linux register setup */
352 env
->regs
[R_EAX
] = regs
->rax
;
353 env
->regs
[R_EBX
] = regs
->rbx
;
354 env
->regs
[R_ECX
] = regs
->rcx
;
355 env
->regs
[R_EDX
] = regs
->rdx
;
356 env
->regs
[R_ESI
] = regs
->rsi
;
357 env
->regs
[R_EDI
] = regs
->rdi
;
358 env
->regs
[R_EBP
] = regs
->rbp
;
359 env
->regs
[R_ESP
] = regs
->rsp
;
360 env
->eip
= regs
->rip
;
362 env
->regs
[R_EAX
] = regs
->eax
;
363 env
->regs
[R_EBX
] = regs
->ebx
;
364 env
->regs
[R_ECX
] = regs
->ecx
;
365 env
->regs
[R_EDX
] = regs
->edx
;
366 env
->regs
[R_ESI
] = regs
->esi
;
367 env
->regs
[R_EDI
] = regs
->edi
;
368 env
->regs
[R_EBP
] = regs
->ebp
;
369 env
->regs
[R_ESP
] = regs
->esp
;
370 env
->eip
= regs
->eip
;
373 /* linux interrupt setup */
375 env
->idt
.limit
= 511;
377 env
->idt
.limit
= 255;
379 env
->idt
.base
= target_mmap(0, sizeof(uint64_t) * (env
->idt
.limit
+ 1),
380 PROT_READ
|PROT_WRITE
,
381 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
382 idt_table
= g2h_untagged(env
->idt
.base
);
405 /* linux segment setup */
408 env
->gdt
.base
= target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES
,
409 PROT_READ
|PROT_WRITE
,
410 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
411 env
->gdt
.limit
= sizeof(uint64_t) * TARGET_GDT_ENTRIES
- 1;
412 gdt_table
= g2h_untagged(env
->gdt
.base
);
414 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
415 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
416 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
418 /* 64 bit code segment */
419 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
420 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
422 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
424 write_dt(&gdt_table
[__USER_DS
>> 3], 0, 0xfffff,
425 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
426 (3 << DESC_DPL_SHIFT
) | (0x2 << DESC_TYPE_SHIFT
));
428 cpu_x86_load_seg(env
, R_CS
, __USER_CS
);
429 cpu_x86_load_seg(env
, R_SS
, __USER_DS
);
431 cpu_x86_load_seg(env
, R_DS
, __USER_DS
);
432 cpu_x86_load_seg(env
, R_ES
, __USER_DS
);
433 cpu_x86_load_seg(env
, R_FS
, __USER_DS
);
434 cpu_x86_load_seg(env
, R_GS
, __USER_DS
);
435 /* This hack makes Wine work... */
436 env
->segs
[R_FS
].selector
= 0;
438 cpu_x86_load_seg(env
, R_DS
, 0);
439 cpu_x86_load_seg(env
, R_ES
, 0);
440 cpu_x86_load_seg(env
, R_FS
, 0);
441 cpu_x86_load_seg(env
, R_GS
, 0);