hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33
  34 #define BIOS_FILENAME "ppc405_rom.bin"
  35 #undef BIOS_SIZE
  36 #define BIOS_SIZE (2048 * 1024)
  37
  38 #define KERNEL_LOAD_ADDR 0x00000000
  39 #define INITRD_LOAD_ADDR 0x01800000
  40
  41 #define USE_FLASH_BIOS
  42
  43 #define DEBUG_BOARD_INIT
  44
  45 /*****************************************************************************/
  46 /* PPC405EP reference board (IBM) */
  47 /* Standalone board with:
  48  * - PowerPC 405EP CPU
  49  * - SDRAM (0x00000000)
  50  * - Flash (0xFFF80000)
  51  * - SRAM  (0xFFF00000)
  52  * - NVRAM (0xF0000000)
  53  * - FPGA  (0xF0300000)
  54  */
  55 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  56 struct ref405ep_fpga_t {
  57     uint8_t reg0;
  58     uint8_t reg1;
  59 };
  60
  61 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  62 {
  63     ref405ep_fpga_t *fpga;
  64     uint32_t ret;
  65
  66     fpga = opaque;
  67     switch (addr) {
  68     case 0x0:
  69         ret = fpga->reg0;
  70         break;
  71     case 0x1:
  72         ret = fpga->reg1;
  73         break;
  74     default:
  75         ret = 0;
  76         break;
  77     }
  78
  79     return ret;
  80 }
  81
  82 static void ref405ep_fpga_writeb (void *opaque,
  83                                   target_phys_addr_t addr, uint32_t value)
  84 {
  85     ref405ep_fpga_t *fpga;
  86
  87     fpga = opaque;
  88     switch (addr) {
  89     case 0x0:
  90         /* Read only */
  91         break;
  92     case 0x1:
  93         fpga->reg1 = value;
  94         break;
  95     default:
  96         break;
  97     }
  98 }
  99
 100 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 101 {
 102     uint32_t ret;
 103
 104     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 105     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 106
 107     return ret;
 108 }
 109
 110 static void ref405ep_fpga_writew (void *opaque,
 111                                   target_phys_addr_t addr, uint32_t value)
 112 {
 113     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 114     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 115 }
 116
 117 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 118 {
 119     uint32_t ret;
 120
 121     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 125
 126     return ret;
 127 }
 128
 129 static void ref405ep_fpga_writel (void *opaque,
 130                                   target_phys_addr_t addr, uint32_t value)
 131 {
 132     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 136 }
 137
 138 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
 139     &ref405ep_fpga_readb,
 140     &ref405ep_fpga_readw,
 141     &ref405ep_fpga_readl,
 142 };
 143
 144 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
 145     &ref405ep_fpga_writeb,
 146     &ref405ep_fpga_writew,
 147     &ref405ep_fpga_writel,
 148 };
 149
 150 static void ref405ep_fpga_reset (void *opaque)
 151 {
 152     ref405ep_fpga_t *fpga;
 153
 154     fpga = opaque;
 155     fpga->reg0 = 0x00;
 156     fpga->reg1 = 0x0F;
 157 }
 158
 159 static void ref405ep_fpga_init (uint32_t base)
 160 {
 161     ref405ep_fpga_t *fpga;
 162     int fpga_memory;
 163
 164     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 165     fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
 166                                          ref405ep_fpga_write, fpga);
 167     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 168     ref405ep_fpga_reset(fpga);
 169     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 170 }
 171
 172 static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
 173                            const char *boot_device,
 174                            const char *kernel_filename,
 175                            const char *kernel_cmdline,
 176                            const char *initrd_filename,
 177                            const char *cpu_model)
 178 {
 179     char buf[1024];
 180     ppc4xx_bd_info_t bd;
 181     CPUPPCState *env;
 182     qemu_irq *pic;
 183     ram_addr_t sram_offset, bios_offset, bdloc;
 184     target_phys_addr_t ram_bases[2], ram_sizes[2];
 185     target_ulong sram_size, bios_size;
 186     //int phy_addr = 0;
 187     //static int phy_addr = 1;
 188     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 189     int linux_boot;
 190     int fl_idx, fl_sectors, len;
 191     int ppc_boot_device = boot_device[0];
 192     int index;
 193
 194     /* XXX: fix this */
 195     ram_bases[0] = qemu_ram_alloc(0x08000000);
 196     ram_sizes[0] = 0x08000000;
 197     ram_bases[1] = 0x00000000;
 198     ram_sizes[1] = 0x00000000;
 199     ram_size = 128 * 1024 * 1024;
 200 #ifdef DEBUG_BOARD_INIT
 201     printf("%s: register cpu\n", __func__);
 202 #endif
 203     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 204                         kernel_filename == NULL ? 0 : 1);
 205     /* allocate SRAM */
 206     sram_size = 512 * 1024;
 207     sram_offset = qemu_ram_alloc(sram_size);
 208 #ifdef DEBUG_BOARD_INIT
 209     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 210 #endif
 211     cpu_register_physical_memory(0xFFF00000, sram_size,
 212                                  sram_offset | IO_MEM_RAM);
 213     /* allocate and load BIOS */
 214 #ifdef DEBUG_BOARD_INIT
 215     printf("%s: register BIOS\n", __func__);
 216 #endif
 217     fl_idx = 0;
 218 #ifdef USE_FLASH_BIOS
 219     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 220     if (index != -1) {
 221         bios_size = bdrv_getlength(drives_table[index].bdrv);
 222         bios_offset = qemu_ram_alloc(bios_size);
 223         fl_sectors = (bios_size + 65535) >> 16;
 224 #ifdef DEBUG_BOARD_INIT
 225         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 226                " addr " ADDRX " '%s' %d\n",
 227                fl_idx, bios_size, bios_offset, -bios_size,
 228                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 229 #endif
 230         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 231                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 232                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 233         fl_idx++;
 234     } else
 235 #endif
 236     {
 237 #ifdef DEBUG_BOARD_INIT
 238         printf("Load BIOS from file\n");
 239 #endif
 240         if (bios_name == NULL)
 241             bios_name = BIOS_FILENAME;
 242         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 243         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 244         bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset));
 245         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 246             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 247             exit(1);
 248         }
 249         bios_size = (bios_size + 0xfff) & ~0xfff;
 250         cpu_register_physical_memory((uint32_t)(-bios_size),
 251                                      bios_size, bios_offset | IO_MEM_ROM);
 252     }
 253     /* Register FPGA */
 254 #ifdef DEBUG_BOARD_INIT
 255     printf("%s: register FPGA\n", __func__);
 256 #endif
 257     ref405ep_fpga_init(0xF0300000);
 258     /* Register NVRAM */
 259 #ifdef DEBUG_BOARD_INIT
 260     printf("%s: register NVRAM\n", __func__);
 261 #endif
 262     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 263     /* Load kernel */
 264     linux_boot = (kernel_filename != NULL);
 265     if (linux_boot) {
 266 #ifdef DEBUG_BOARD_INIT
 267         printf("%s: load kernel\n", __func__);
 268 #endif
 269         memset(&bd, 0, sizeof(bd));
 270         bd.bi_memstart = 0x00000000;
 271         bd.bi_memsize = ram_size;
 272         bd.bi_flashstart = -bios_size;
 273         bd.bi_flashsize = -bios_size;
 274         bd.bi_flashoffset = 0;
 275         bd.bi_sramstart = 0xFFF00000;
 276         bd.bi_sramsize = sram_size;
 277         bd.bi_bootflags = 0;
 278         bd.bi_intfreq = 133333333;
 279         bd.bi_busfreq = 33333333;
 280         bd.bi_baudrate = 115200;
 281         bd.bi_s_version[0] = 'Q';
 282         bd.bi_s_version[1] = 'M';
 283         bd.bi_s_version[2] = 'U';
 284         bd.bi_s_version[3] = '\0';
 285         bd.bi_r_version[0] = 'Q';
 286         bd.bi_r_version[1] = 'E';
 287         bd.bi_r_version[2] = 'M';
 288         bd.bi_r_version[3] = 'U';
 289         bd.bi_r_version[4] = '\0';
 290         bd.bi_procfreq = 133333333;
 291         bd.bi_plb_busfreq = 33333333;
 292         bd.bi_pci_busfreq = 33333333;
 293         bd.bi_opbfreq = 33333333;
 294         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 295         env->gpr[3] = bdloc;
 296         kernel_base = KERNEL_LOAD_ADDR;
 297         /* now we can load the kernel */
 298         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 299                                           ram_size - kernel_base);
 300         if (kernel_size < 0) {
 301             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 302                     kernel_filename);
 303             exit(1);
 304         }
 305         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 306                kernel_size, kernel_base);
 307         /* load initrd */
 308         if (initrd_filename) {
 309             initrd_base = INITRD_LOAD_ADDR;
 310             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 311                                               ram_size - initrd_base);
 312             if (initrd_size < 0) {
 313                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 314                         initrd_filename);
 315                 exit(1);
 316             }
 317         } else {
 318             initrd_base = 0;
 319             initrd_size = 0;
 320         }
 321         env->gpr[4] = initrd_base;
 322         env->gpr[5] = initrd_size;
 323         ppc_boot_device = 'm';
 324         if (kernel_cmdline != NULL) {
 325             len = strlen(kernel_cmdline);
 326             bdloc -= ((len + 255) & ~255);
 327             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 328             env->gpr[6] = bdloc;
 329             env->gpr[7] = bdloc + len;
 330         } else {
 331             env->gpr[6] = 0;
 332             env->gpr[7] = 0;
 333         }
 334         env->nip = KERNEL_LOAD_ADDR;
 335     } else {
 336         kernel_base = 0;
 337         kernel_size = 0;
 338         initrd_base = 0;
 339         initrd_size = 0;
 340         bdloc = 0;
 341     }
 342 #ifdef DEBUG_BOARD_INIT
 343     printf("%s: Done\n", __func__);
 344 #endif
 345     printf("bdloc %016lx\n", (unsigned long)bdloc);
 346 }
 347
 348 QEMUMachine ref405ep_machine = {
 349     .name = "ref405ep",
 350     .desc = "ref405ep",
 351     .init = ref405ep_init,
 352 };
 353
 354 /*****************************************************************************/
 355 /* AMCC Taihu evaluation board */
 356 /* - PowerPC 405EP processor
 357  * - SDRAM               128 MB at 0x00000000
 358  * - Boot flash          2 MB   at 0xFFE00000
 359  * - Application flash   32 MB  at 0xFC000000
 360  * - 2 serial ports
 361  * - 2 ethernet PHY
 362  * - 1 USB 1.1 device    0x50000000
 363  * - 1 LCD display       0x50100000
 364  * - 1 CPLD              0x50100000
 365  * - 1 I2C EEPROM
 366  * - 1 I2C thermal sensor
 367  * - a set of LEDs
 368  * - bit-bang SPI port using GPIOs
 369  * - 1 EBC interface connector 0 0x50200000
 370  * - 1 cardbus controller + expansion slot.
 371  * - 1 PCI expansion slot.
 372  */
 373 typedef struct taihu_cpld_t taihu_cpld_t;
 374 struct taihu_cpld_t {
 375     uint8_t reg0;
 376     uint8_t reg1;
 377 };
 378
 379 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 380 {
 381     taihu_cpld_t *cpld;
 382     uint32_t ret;
 383
 384     cpld = opaque;
 385     switch (addr) {
 386     case 0x0:
 387         ret = cpld->reg0;
 388         break;
 389     case 0x1:
 390         ret = cpld->reg1;
 391         break;
 392     default:
 393         ret = 0;
 394         break;
 395     }
 396
 397     return ret;
 398 }
 399
 400 static void taihu_cpld_writeb (void *opaque,
 401                                target_phys_addr_t addr, uint32_t value)
 402 {
 403     taihu_cpld_t *cpld;
 404
 405     cpld = opaque;
 406     switch (addr) {
 407     case 0x0:
 408         /* Read only */
 409         break;
 410     case 0x1:
 411         cpld->reg1 = value;
 412         break;
 413     default:
 414         break;
 415     }
 416 }
 417
 418 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 419 {
 420     uint32_t ret;
 421
 422     ret = taihu_cpld_readb(opaque, addr) << 8;
 423     ret |= taihu_cpld_readb(opaque, addr + 1);
 424
 425     return ret;
 426 }
 427
 428 static void taihu_cpld_writew (void *opaque,
 429                                target_phys_addr_t addr, uint32_t value)
 430 {
 431     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 432     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 433 }
 434
 435 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 436 {
 437     uint32_t ret;
 438
 439     ret = taihu_cpld_readb(opaque, addr) << 24;
 440     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 441     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 442     ret |= taihu_cpld_readb(opaque, addr + 3);
 443
 444     return ret;
 445 }
 446
 447 static void taihu_cpld_writel (void *opaque,
 448                                target_phys_addr_t addr, uint32_t value)
 449 {
 450     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 451     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 452     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 453     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 454 }
 455
 456 static CPUReadMemoryFunc *taihu_cpld_read[] = {
 457     &taihu_cpld_readb,
 458     &taihu_cpld_readw,
 459     &taihu_cpld_readl,
 460 };
 461
 462 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
 463     &taihu_cpld_writeb,
 464     &taihu_cpld_writew,
 465     &taihu_cpld_writel,
 466 };
 467
 468 static void taihu_cpld_reset (void *opaque)
 469 {
 470     taihu_cpld_t *cpld;
 471
 472     cpld = opaque;
 473     cpld->reg0 = 0x01;
 474     cpld->reg1 = 0x80;
 475 }
 476
 477 static void taihu_cpld_init (uint32_t base)
 478 {
 479     taihu_cpld_t *cpld;
 480     int cpld_memory;
 481
 482     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 483     cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
 484                                          taihu_cpld_write, cpld);
 485     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 486     taihu_cpld_reset(cpld);
 487     qemu_register_reset(&taihu_cpld_reset, cpld);
 488 }
 489
 490 static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
 491                              const char *boot_device,
 492                              const char *kernel_filename,
 493                              const char *kernel_cmdline,
 494                              const char *initrd_filename,
 495                              const char *cpu_model)
 496 {
 497     char buf[1024];
 498     CPUPPCState *env;
 499     qemu_irq *pic;
 500     ram_addr_t bios_offset;
 501     target_phys_addr_t ram_bases[2], ram_sizes[2];
 502     target_ulong bios_size;
 503     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 504     int linux_boot;
 505     int fl_idx, fl_sectors;
 506     int ppc_boot_device = boot_device[0];
 507     int index;
 508
 509     /* RAM is soldered to the board so the size cannot be changed */
 510     ram_bases[0] = qemu_ram_alloc(0x04000000);
 511     ram_sizes[0] = 0x04000000;
 512     ram_bases[1] = qemu_ram_alloc(0x04000000);
 513     ram_sizes[1] = 0x04000000;
 514     ram_size = 0x08000000;
 515 #ifdef DEBUG_BOARD_INIT
 516     printf("%s: register cpu\n", __func__);
 517 #endif
 518     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 519                         kernel_filename == NULL ? 0 : 1);
 520     /* allocate and load BIOS */
 521 #ifdef DEBUG_BOARD_INIT
 522     printf("%s: register BIOS\n", __func__);
 523 #endif
 524     fl_idx = 0;
 525 #if defined(USE_FLASH_BIOS)
 526     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 527     if (index != -1) {
 528         bios_size = bdrv_getlength(drives_table[index].bdrv);
 529         /* XXX: should check that size is 2MB */
 530         //        bios_size = 2 * 1024 * 1024;
 531         fl_sectors = (bios_size + 65535) >> 16;
 532         bios_offset = qemu_ram_alloc(bios_size);
 533 #ifdef DEBUG_BOARD_INIT
 534         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 535                " addr " ADDRX " '%s' %d\n",
 536                fl_idx, bios_size, bios_offset, -bios_size,
 537                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 538 #endif
 539         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 540                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 541                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 542         fl_idx++;
 543     } else
 544 #endif
 545     {
 546 #ifdef DEBUG_BOARD_INIT
 547         printf("Load BIOS from file\n");
 548 #endif
 549         if (bios_name == NULL)
 550             bios_name = BIOS_FILENAME;
 551         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 552         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 553         bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset));
 554         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 555             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 556             exit(1);
 557         }
 558         bios_size = (bios_size + 0xfff) & ~0xfff;
 559         cpu_register_physical_memory((uint32_t)(-bios_size),
 560                                      bios_size, bios_offset | IO_MEM_ROM);
 561     }
 562     /* Register Linux flash */
 563     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 564     if (index != -1) {
 565         bios_size = bdrv_getlength(drives_table[index].bdrv);
 566         /* XXX: should check that size is 32MB */
 567         bios_size = 32 * 1024 * 1024;
 568         fl_sectors = (bios_size + 65535) >> 16;
 569 #ifdef DEBUG_BOARD_INIT
 570         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 571                " addr " ADDRX " '%s'\n",
 572                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 573                bdrv_get_device_name(drives_table[index].bdrv));
 574 #endif
 575         bios_offset = qemu_ram_alloc(bios_size);
 576         pflash_cfi02_register(0xfc000000, bios_offset,
 577                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 578                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 579         fl_idx++;
 580     }
 581     /* Register CLPD & LCD display */
 582 #ifdef DEBUG_BOARD_INIT
 583     printf("%s: register CPLD\n", __func__);
 584 #endif
 585     taihu_cpld_init(0x50100000);
 586     /* Load kernel */
 587     linux_boot = (kernel_filename != NULL);
 588     if (linux_boot) {
 589 #ifdef DEBUG_BOARD_INIT
 590         printf("%s: load kernel\n", __func__);
 591 #endif
 592         kernel_base = KERNEL_LOAD_ADDR;
 593         /* now we can load the kernel */
 594         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 595                                           ram_size - kernel_base);
 596         if (kernel_size < 0) {
 597             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 598                     kernel_filename);
 599             exit(1);
 600         }
 601         /* load initrd */
 602         if (initrd_filename) {
 603             initrd_base = INITRD_LOAD_ADDR;
 604             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 605                                               ram_size - initrd_base);
 606             if (initrd_size < 0) {
 607                 fprintf(stderr,
 608                         "qemu: could not load initial ram disk '%s'\n",
 609                         initrd_filename);
 610                 exit(1);
 611             }
 612         } else {
 613             initrd_base = 0;
 614             initrd_size = 0;
 615         }
 616         ppc_boot_device = 'm';
 617     } else {
 618         kernel_base = 0;
 619         kernel_size = 0;
 620         initrd_base = 0;
 621         initrd_size = 0;
 622     }
 623 #ifdef DEBUG_BOARD_INIT
 624     printf("%s: Done\n", __func__);
 625 #endif
 626 }
 627
 628 QEMUMachine taihu_machine = {
 629     .name = "taihu",
 630     .desc = "taihu",
 631     .init = taihu_405ep_init,
 632 };