hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU LGPL
   8  */
   9
  10 #include "hw.h"
  11 #include "primecell.h"
  12 #include "console.h"
  13 #include "framebuffer.h"
  14
  15 #define PL110_CR_EN   0x001
  16 #define PL110_CR_BGR  0x100
  17 #define PL110_CR_BEBO 0x200
  18 #define PL110_CR_BEPO 0x400
  19 #define PL110_CR_PWR  0x800
  20
  21 enum pl110_bppmode
  22 {
  23     BPP_1,
  24     BPP_2,
  25     BPP_4,
  26     BPP_8,
  27     BPP_16,
  28     BPP_32
  29 };
  30
  31 typedef struct {
  32     DisplayState *ds;
  33
  34     /* The Versatile/PB uses a slightly modified PL110 controller.  */
  35     int versatile;
  36     uint32_t timing[4];
  37     uint32_t cr;
  38     uint32_t upbase;
  39     uint32_t lpbase;
  40     uint32_t int_status;
  41     uint32_t int_mask;
  42     int cols;
  43     int rows;
  44     enum pl110_bppmode bpp;
  45     int invalidate;
  46     uint32_t pallette[256];
  47     uint32_t raw_pallette[128];
  48     qemu_irq irq;
  49 } pl110_state;
  50
  51 static const unsigned char pl110_id[] =
  52 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  53
  54 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  55    has a different ID.  However Linux only looks for the normal ID.  */
  56 #if 0
  57 static const unsigned char pl110_versatile_id[] =
  58 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  59 #else
  60 #define pl110_versatile_id pl110_id
  61 #endif
  62
  63 #include "pixel_ops.h"
  64
  65 #define BITS 8
  66 #include "pl110_template.h"
  67 #define BITS 15
  68 #include "pl110_template.h"
  69 #define BITS 16
  70 #include "pl110_template.h"
  71 #define BITS 24
  72 #include "pl110_template.h"
  73 #define BITS 32
  74 #include "pl110_template.h"
  75
  76 static int pl110_enabled(pl110_state *s)
  77 {
  78   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
  79 }
  80
  81 static void pl110_update_display(void *opaque)
  82 {
  83     pl110_state *s = (pl110_state *)opaque;
  84     drawfn* fntable;
  85     drawfn fn;
  86     int dest_width;
  87     int src_width;
  88     int bpp_offset;
  89     int first;
  90     int last;
  91
  92     if (!pl110_enabled(s))
  93         return;
  94
  95     switch (ds_get_bits_per_pixel(s->ds)) {
  96     case 0:
  97         return;
  98     case 8:
  99         fntable = pl110_draw_fn_8;
 100         dest_width = 1;
 101         break;
 102     case 15:
 103         fntable = pl110_draw_fn_15;
 104         dest_width = 2;
 105         break;
 106     case 16:
 107         fntable = pl110_draw_fn_16;
 108         dest_width = 2;
 109         break;
 110     case 24:
 111         fntable = pl110_draw_fn_24;
 112         dest_width = 3;
 113         break;
 114     case 32:
 115         fntable = pl110_draw_fn_32;
 116         dest_width = 4;
 117         break;
 118     default:
 119         fprintf(stderr, "pl110: Bad color depth\n");
 120         exit(1);
 121     }
 122     if (s->cr & PL110_CR_BGR)
 123         bpp_offset = 0;
 124     else
 125         bpp_offset = 18;
 126
 127     if (s->cr & PL110_CR_BEBO)
 128         fn = fntable[s->bpp + 6 + bpp_offset];
 129     else if (s->cr & PL110_CR_BEPO)
 130         fn = fntable[s->bpp + 12 + bpp_offset];
 131     else
 132         fn = fntable[s->bpp + bpp_offset];
 133
 134     src_width = s->cols;
 135     switch (s->bpp) {
 136     case BPP_1:
 137         src_width >>= 3;
 138         break;
 139     case BPP_2:
 140         src_width >>= 2;
 141         break;
 142     case BPP_4:
 143         src_width >>= 1;
 144         break;
 145     case BPP_8:
 146         break;
 147     case BPP_16:
 148         src_width <<= 1;
 149         break;
 150     case BPP_32:
 151         src_width <<= 2;
 152         break;
 153     }
 154     dest_width *= s->cols;
 155     first = 0;
 156     framebuffer_update_display(s->ds,
 157                                s->upbase, s->cols, s->rows,
 158                                src_width, dest_width, 0,
 159                                s->invalidate,
 160                                fn, s->pallette,
 161                                &first, &last);
 162     if (first >= 0) {
 163         dpy_update(s->ds, 0, first, s->cols, last - first + 1);
 164     }
 165     s->invalidate = 0;
 166 }
 167
 168 static void pl110_invalidate_display(void * opaque)
 169 {
 170     pl110_state *s = (pl110_state *)opaque;
 171     s->invalidate = 1;
 172 }
 173
 174 static void pl110_update_pallette(pl110_state *s, int n)
 175 {
 176     int i;
 177     uint32_t raw;
 178     unsigned int r, g, b;
 179
 180     raw = s->raw_pallette[n];
 181     n <<= 1;
 182     for (i = 0; i < 2; i++) {
 183         r = (raw & 0x1f) << 3;
 184         raw >>= 5;
 185         g = (raw & 0x1f) << 3;
 186         raw >>= 5;
 187         b = (raw & 0x1f) << 3;
 188         /* The I bit is ignored.  */
 189         raw >>= 6;
 190         switch (ds_get_bits_per_pixel(s->ds)) {
 191         case 8:
 192             s->pallette[n] = rgb_to_pixel8(r, g, b);
 193             break;
 194         case 15:
 195             s->pallette[n] = rgb_to_pixel15(r, g, b);
 196             break;
 197         case 16:
 198             s->pallette[n] = rgb_to_pixel16(r, g, b);
 199             break;
 200         case 24:
 201         case 32:
 202             s->pallette[n] = rgb_to_pixel32(r, g, b);
 203             break;
 204         }
 205         n++;
 206     }
 207 }
 208
 209 static void pl110_resize(pl110_state *s, int width, int height)
 210 {
 211     if (width != s->cols || height != s->rows) {
 212         if (pl110_enabled(s)) {
 213             qemu_console_resize(s->ds, width, height);
 214         }
 215     }
 216     s->cols = width;
 217     s->rows = height;
 218 }
 219
 220 /* Update interrupts.  */
 221 static void pl110_update(pl110_state *s)
 222 {
 223   /* TODO: Implement interrupts.  */
 224 }
 225
 226 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
 227 {
 228     pl110_state *s = (pl110_state *)opaque;
 229
 230     if (offset >= 0xfe0 && offset < 0x1000) {
 231         if (s->versatile)
 232             return pl110_versatile_id[(offset - 0xfe0) >> 2];
 233         else
 234             return pl110_id[(offset - 0xfe0) >> 2];
 235     }
 236     if (offset >= 0x200 && offset < 0x400) {
 237         return s->raw_pallette[(offset - 0x200) >> 2];
 238     }
 239     switch (offset >> 2) {
 240     case 0: /* LCDTiming0 */
 241         return s->timing[0];
 242     case 1: /* LCDTiming1 */
 243         return s->timing[1];
 244     case 2: /* LCDTiming2 */
 245         return s->timing[2];
 246     case 3: /* LCDTiming3 */
 247         return s->timing[3];
 248     case 4: /* LCDUPBASE */
 249         return s->upbase;
 250     case 5: /* LCDLPBASE */
 251         return s->lpbase;
 252     case 6: /* LCDIMSC */
 253         if (s->versatile)
 254           return s->cr;
 255         return s->int_mask;
 256     case 7: /* LCDControl */
 257         if (s->versatile)
 258           return s->int_mask;
 259         return s->cr;
 260     case 8: /* LCDRIS */
 261         return s->int_status;
 262     case 9: /* LCDMIS */
 263         return s->int_status & s->int_mask;
 264     case 11: /* LCDUPCURR */
 265         /* TODO: Implement vertical refresh.  */
 266         return s->upbase;
 267     case 12: /* LCDLPCURR */
 268         return s->lpbase;
 269     default:
 270         cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
 271         return 0;
 272     }
 273 }
 274
 275 static void pl110_write(void *opaque, target_phys_addr_t offset,
 276                         uint32_t val)
 277 {
 278     pl110_state *s = (pl110_state *)opaque;
 279     int n;
 280
 281     /* For simplicity invalidate the display whenever a control register
 282        is writen to.  */
 283     s->invalidate = 1;
 284     if (offset >= 0x200 && offset < 0x400) {
 285         /* Pallette.  */
 286         n = (offset - 0x200) >> 2;
 287         s->raw_pallette[(offset - 0x200) >> 2] = val;
 288         pl110_update_pallette(s, n);
 289         return;
 290     }
 291     switch (offset >> 2) {
 292     case 0: /* LCDTiming0 */
 293         s->timing[0] = val;
 294         n = ((val & 0xfc) + 4) * 4;
 295         pl110_resize(s, n, s->rows);
 296         break;
 297     case 1: /* LCDTiming1 */
 298         s->timing[1] = val;
 299         n = (val & 0x3ff) + 1;
 300         pl110_resize(s, s->cols, n);
 301         break;
 302     case 2: /* LCDTiming2 */
 303         s->timing[2] = val;
 304         break;
 305     case 3: /* LCDTiming3 */
 306         s->timing[3] = val;
 307         break;
 308     case 4: /* LCDUPBASE */
 309         s->upbase = val;
 310         break;
 311     case 5: /* LCDLPBASE */
 312         s->lpbase = val;
 313         break;
 314     case 6: /* LCDIMSC */
 315         if (s->versatile)
 316             goto control;
 317     imsc:
 318         s->int_mask = val;
 319         pl110_update(s);
 320         break;
 321     case 7: /* LCDControl */
 322         if (s->versatile)
 323             goto imsc;
 324     control:
 325         s->cr = val;
 326         s->bpp = (val >> 1) & 7;
 327         if (pl110_enabled(s)) {
 328             qemu_console_resize(s->ds, s->cols, s->rows);
 329         }
 330         break;
 331     case 10: /* LCDICR */
 332         s->int_status &= ~val;
 333         pl110_update(s);
 334         break;
 335     default:
 336         cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
 337     }
 338 }
 339
 340 static CPUReadMemoryFunc *pl110_readfn[] = {
 341    pl110_read,
 342    pl110_read,
 343    pl110_read
 344 };
 345
 346 static CPUWriteMemoryFunc *pl110_writefn[] = {
 347    pl110_write,
 348    pl110_write,
 349    pl110_write
 350 };
 351
 352 void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
 353 {
 354     pl110_state *s;
 355     int iomemtype;
 356
 357     s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
 358     iomemtype = cpu_register_io_memory(0, pl110_readfn,
 359                                        pl110_writefn, s);
 360     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 361     s->versatile = versatile;
 362     s->irq = irq;
 363     s->ds = graphic_console_init(pl110_update_display,
 364                                  pl110_invalidate_display,
 365                                  NULL, NULL, s);
 366     /* ??? Save/restore.  */
 367     return s;
 368 }