target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #include "config.h"
   5
   6 #if !defined(TARGET_SPARC64)
   7 #define TARGET_LONG_BITS 32
   8 #define TARGET_FPREGS 32
   9 #define TARGET_PAGE_BITS 12 /* 4k */
  10 #else
  11 #define TARGET_LONG_BITS 64
  12 #define TARGET_FPREGS 64
  13 #define TARGET_PAGE_BITS 13 /* 8k */
  14 #endif
  15
  16 #define TARGET_PHYS_ADDR_BITS 64
  17
  18 #define CPUState struct CPUSPARCState
  19
  20 #include "cpu-defs.h"
  21
  22 #include "softfloat.h"
  23
  24 #define TARGET_HAS_ICE 1
  25
  26 #if !defined(TARGET_SPARC64)
  27 #define ELF_MACHINE     EM_SPARC
  28 #else
  29 #define ELF_MACHINE     EM_SPARCV9
  30 #endif
  31
  32 /*#define EXCP_INTERRUPT 0x100*/
  33
  34 /* trap definitions */
  35 #ifndef TARGET_SPARC64
  36 #define TT_TFAULT   0x01
  37 #define TT_ILL_INSN 0x02
  38 #define TT_PRIV_INSN 0x03
  39 #define TT_NFPU_INSN 0x04
  40 #define TT_WIN_OVF  0x05
  41 #define TT_WIN_UNF  0x06
  42 #define TT_UNALIGNED 0x07
  43 #define TT_FP_EXCP  0x08
  44 #define TT_DFAULT   0x09
  45 #define TT_TOVF     0x0a
  46 #define TT_EXTINT   0x10
  47 #define TT_CODE_ACCESS 0x21
  48 #define TT_UNIMP_FLUSH 0x25
  49 #define TT_DATA_ACCESS 0x29
  50 #define TT_DIV_ZERO 0x2a
  51 #define TT_NCP_INSN 0x24
  52 #define TT_TRAP     0x80
  53 #else
  54 #define TT_TFAULT   0x08
  55 #define TT_CODE_ACCESS 0x0a
  56 #define TT_ILL_INSN 0x10
  57 #define TT_UNIMP_FLUSH TT_ILL_INSN
  58 #define TT_PRIV_INSN 0x11
  59 #define TT_NFPU_INSN 0x20
  60 #define TT_FP_EXCP  0x21
  61 #define TT_TOVF     0x23
  62 #define TT_CLRWIN   0x24
  63 #define TT_DIV_ZERO 0x28
  64 #define TT_DFAULT   0x30
  65 #define TT_DATA_ACCESS 0x32
  66 #define TT_UNALIGNED 0x34
  67 #define TT_PRIV_ACT 0x37
  68 #define TT_EXTINT   0x40
  69 #define TT_IVEC     0x60
  70 #define TT_TMISS    0x64
  71 #define TT_DMISS    0x68
  72 #define TT_DPROT    0x6c
  73 #define TT_SPILL    0x80
  74 #define TT_FILL     0xc0
  75 #define TT_WOTHER   0x10
  76 #define TT_TRAP     0x100
  77 #endif
  78
  79 #define PSR_NEG_SHIFT 23
  80 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
  81 #define PSR_ZERO_SHIFT 22
  82 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  83 #define PSR_OVF_SHIFT 21
  84 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
  85 #define PSR_CARRY_SHIFT 20
  86 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  87 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  88 #define PSR_EF    (1<<12)
  89 #define PSR_PIL   0xf00
  90 #define PSR_S     (1<<7)
  91 #define PSR_PS    (1<<6)
  92 #define PSR_ET    (1<<5)
  93 #define PSR_CWP   0x1f
  94
  95 /* Trap base register */
  96 #define TBR_BASE_MASK 0xfffff000
  97
  98 #if defined(TARGET_SPARC64)
  99 #define PS_IG    (1<<11)
 100 #define PS_MG    (1<<10)
 101 #define PS_RMO   (1<<7)
 102 #define PS_RED   (1<<5)
 103 #define PS_PEF   (1<<4)
 104 #define PS_AM    (1<<3)
 105 #define PS_PRIV  (1<<2)
 106 #define PS_IE    (1<<1)
 107 #define PS_AG    (1<<0)
 108
 109 #define FPRS_FEF (1<<2)
 110
 111 #define HS_PRIV  (1<<2)
 112 #endif
 113
 114 /* Fcc */
 115 #define FSR_RD1        (1ULL << 31)
 116 #define FSR_RD0        (1ULL << 30)
 117 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 118 #define FSR_RD_NEAREST 0
 119 #define FSR_RD_ZERO    FSR_RD0
 120 #define FSR_RD_POS     FSR_RD1
 121 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 122
 123 #define FSR_NVM   (1ULL << 27)
 124 #define FSR_OFM   (1ULL << 26)
 125 #define FSR_UFM   (1ULL << 25)
 126 #define FSR_DZM   (1ULL << 24)
 127 #define FSR_NXM   (1ULL << 23)
 128 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 129
 130 #define FSR_NVA   (1ULL << 9)
 131 #define FSR_OFA   (1ULL << 8)
 132 #define FSR_UFA   (1ULL << 7)
 133 #define FSR_DZA   (1ULL << 6)
 134 #define FSR_NXA   (1ULL << 5)
 135 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 136
 137 #define FSR_NVC   (1ULL << 4)
 138 #define FSR_OFC   (1ULL << 3)
 139 #define FSR_UFC   (1ULL << 2)
 140 #define FSR_DZC   (1ULL << 1)
 141 #define FSR_NXC   (1ULL << 0)
 142 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 143
 144 #define FSR_FTT2   (1ULL << 16)
 145 #define FSR_FTT1   (1ULL << 15)
 146 #define FSR_FTT0   (1ULL << 14)
 147 //gcc warns about constant overflow for ~FSR_FTT_MASK
 148 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 149 #ifdef TARGET_SPARC64
 150 #define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 151 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 152 #define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 153 #define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 154 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 155 #else
 156 #define FSR_FTT_NMASK      0xfffe3fffULL
 157 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 158 #define FSR_LDFSR_OLDMASK  0x000fc000ULL
 159 #endif
 160 #define FSR_LDFSR_MASK     0xcfc00fffULL
 161 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
 162 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
 163 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
 164 #define FSR_FTT_INVAL_FPR (6ULL << 14)
 165
 166 #define FSR_FCC1_SHIFT 11
 167 #define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 168 #define FSR_FCC0_SHIFT 10
 169 #define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 170
 171 /* MMU */
 172 #define MMU_E     (1<<0)
 173 #define MMU_NF    (1<<1)
 174
 175 #define PTE_ENTRYTYPE_MASK 3
 176 #define PTE_ACCESS_MASK    0x1c
 177 #define PTE_ACCESS_SHIFT   2
 178 #define PTE_PPN_SHIFT      7
 179 #define PTE_ADDR_MASK      0xffffff00
 180
 181 #define PG_ACCESSED_BIT 5
 182 #define PG_MODIFIED_BIT 6
 183 #define PG_CACHE_BIT    7
 184
 185 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 186 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 187 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 188
 189 /* 3 <= NWINDOWS <= 32. */
 190 #define MIN_NWINDOWS 3
 191 #define MAX_NWINDOWS 32
 192
 193 #if !defined(TARGET_SPARC64)
 194 #define NB_MMU_MODES 2
 195 #else
 196 #define NB_MMU_MODES 3
 197 typedef struct trap_state {
 198     uint64_t tpc;
 199     uint64_t tnpc;
 200     uint64_t tstate;
 201     uint32_t tt;
 202 } trap_state;
 203 #endif
 204
 205 typedef struct sparc_def_t {
 206     const char *name;
 207     target_ulong iu_version;
 208     uint32_t fpu_version;
 209     uint32_t mmu_version;
 210     uint32_t mmu_bm;
 211     uint32_t mmu_ctpr_mask;
 212     uint32_t mmu_cxr_mask;
 213     uint32_t mmu_sfsr_mask;
 214     uint32_t mmu_trcr_mask;
 215     uint32_t mxcc_version;
 216     uint32_t features;
 217     uint32_t nwindows;
 218     uint32_t maxtl;
 219 } sparc_def_t;
 220
 221 #define CPU_FEATURE_FLOAT    (1 << 0)
 222 #define CPU_FEATURE_FLOAT128 (1 << 1)
 223 #define CPU_FEATURE_SWAP     (1 << 2)
 224 #define CPU_FEATURE_MUL      (1 << 3)
 225 #define CPU_FEATURE_DIV      (1 << 4)
 226 #define CPU_FEATURE_FLUSH    (1 << 5)
 227 #define CPU_FEATURE_FSQRT    (1 << 6)
 228 #define CPU_FEATURE_FMUL     (1 << 7)
 229 #define CPU_FEATURE_VIS1     (1 << 8)
 230 #define CPU_FEATURE_VIS2     (1 << 9)
 231 #define CPU_FEATURE_FSMULD   (1 << 10)
 232 #define CPU_FEATURE_HYPV     (1 << 11)
 233 #define CPU_FEATURE_CMT      (1 << 12)
 234 #define CPU_FEATURE_GL       (1 << 13)
 235 #ifndef TARGET_SPARC64
 236 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 237                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 238                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 239                               CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 240 #else
 241 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 242                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 243                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 244                               CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 245                               CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
 246 enum {
 247     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 248     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 249     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 250     mmu_sun4v, // T1, T2
 251 };
 252 #endif
 253
 254 typedef struct CPUSPARCState {
 255     target_ulong gregs[8]; /* general registers */
 256     target_ulong *regwptr; /* pointer to current register window */
 257     target_ulong pc;       /* program counter */
 258     target_ulong npc;      /* next program counter */
 259     target_ulong y;        /* multiply/divide register */
 260
 261     /* emulator internal flags handling */
 262     target_ulong cc_src, cc_src2;
 263     target_ulong cc_dst;
 264
 265     target_ulong t0, t1; /* temporaries live across basic blocks */
 266     target_ulong cond; /* conditional branch result (XXX: save it in a
 267                           temporary register when possible) */
 268
 269     uint32_t psr;      /* processor state register */
 270     target_ulong fsr;      /* FPU state register */
 271     float32 fpr[TARGET_FPREGS];  /* floating point registers */
 272     uint32_t cwp;      /* index of current register window (extracted
 273                           from PSR) */
 274     uint32_t wim;      /* window invalid mask */
 275     target_ulong tbr;  /* trap base register */
 276     int      psrs;     /* supervisor mode (extracted from PSR) */
 277     int      psrps;    /* previous supervisor mode */
 278     int      psret;    /* enable traps */
 279     uint32_t psrpil;   /* interrupt blocking level */
 280     uint32_t pil_in;   /* incoming interrupt level bitmap */
 281     int      psref;    /* enable fpu */
 282     target_ulong version;
 283     int interrupt_index;
 284     uint32_t nwindows;
 285     /* NOTE: we allow 8 more registers to handle wrapping */
 286     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 287
 288     CPU_COMMON
 289
 290     /* MMU regs */
 291 #if defined(TARGET_SPARC64)
 292     uint64_t lsu;
 293 #define DMMU_E 0x8
 294 #define IMMU_E 0x4
 295     uint64_t immuregs[16];
 296     uint64_t dmmuregs[16];
 297     uint64_t itlb_tag[64];
 298     uint64_t itlb_tte[64];
 299     uint64_t dtlb_tag[64];
 300     uint64_t dtlb_tte[64];
 301     uint32_t mmu_version;
 302 #else
 303     uint32_t mmuregs[32];
 304     uint64_t mxccdata[4];
 305     uint64_t mxccregs[8];
 306     uint64_t mmubpregs[4];
 307     uint64_t prom_addr;
 308 #endif
 309     /* temporary float registers */
 310     float64 dt0, dt1;
 311     float128 qt0, qt1;
 312     float_status fp_status;
 313 #if defined(TARGET_SPARC64)
 314 #define MAXTL_MAX 8
 315 #define MAXTL_MASK (MAXTL_MAX - 1)
 316     trap_state *tsptr;
 317     trap_state ts[MAXTL_MAX];
 318     uint32_t xcc;               /* Extended integer condition codes */
 319     uint32_t asi;
 320     uint32_t pstate;
 321     uint32_t tl;
 322     uint32_t maxtl;
 323     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 324     uint64_t agregs[8]; /* alternate general registers */
 325     uint64_t bgregs[8]; /* backup for normal global registers */
 326     uint64_t igregs[8]; /* interrupt general registers */
 327     uint64_t mgregs[8]; /* mmu general registers */
 328     uint64_t fprs;
 329     uint64_t tick_cmpr, stick_cmpr;
 330     void *tick, *stick;
 331     uint64_t gsr;
 332     uint32_t gl; // UA2005
 333     /* UA 2005 hyperprivileged registers */
 334     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 335     void *hstick; // UA 2005
 336     uint32_t softint;
 337 #define SOFTINT_TIMER   1
 338 #define SOFTINT_STIMER  (1 << 16)
 339 #endif
 340     sparc_def_t *def;
 341 } CPUSPARCState;
 342
 343 /* helper.c */
 344 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
 345 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 346 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 347                                                  ...));
 348 void cpu_lock(void);
 349 void cpu_unlock(void);
 350 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
 351                                int mmu_idx, int is_softmmu);
 352 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 353 void dump_mmu(CPUSPARCState *env);
 354
 355 /* translate.c */
 356 void gen_intermediate_code_init(CPUSPARCState *env);
 357
 358 /* cpu-exec.c */
 359 int cpu_sparc_exec(CPUSPARCState *s);
 360
 361 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
 362                       (env->psref? PSR_EF : 0) |                        \
 363                       (env->psrpil << 8) |                              \
 364                       (env->psrs? PSR_S : 0) |                          \
 365                       (env->psrps? PSR_PS : 0) |                        \
 366                       (env->psret? PSR_ET : 0) | env->cwp)
 367
 368 #ifndef NO_CPU_IO_DEFS
 369 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
 370 {
 371     dst[0] = src[0];
 372     dst[1] = src[1];
 373     dst[2] = src[2];
 374     dst[3] = src[3];
 375     dst[4] = src[4];
 376     dst[5] = src[5];
 377     dst[6] = src[6];
 378     dst[7] = src[7];
 379 }
 380
 381 static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
 382 {
 383     /* put the modified wrap registers at their proper location */
 384     if (env1->cwp == env1->nwindows - 1)
 385         memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
 386     env1->cwp = new_cwp;
 387     /* put the wrap registers at their temporary location */
 388     if (new_cwp == env1->nwindows - 1)
 389         memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
 390     env1->regwptr = env1->regbase + (new_cwp * 16);
 391 }
 392
 393 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
 394 {
 395     if (unlikely(cwp >= env1->nwindows))
 396         cwp -= env1->nwindows;
 397     return cwp;
 398 }
 399
 400 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
 401 {
 402     if (unlikely(cwp < 0))
 403         cwp += env1->nwindows;
 404     return cwp;
 405 }
 406 #endif
 407
 408 #define PUT_PSR(env, val) do { int _tmp = val;                          \
 409         env->psr = _tmp & PSR_ICC;                                      \
 410         env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
 411         env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
 412         env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
 413         env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
 414         env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
 415         cpu_set_cwp(env, _tmp & PSR_CWP);                               \
 416     } while (0)
 417
 418 #ifdef TARGET_SPARC64
 419 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
 420 #define PUT_CCR(env, val) do { int _tmp = val;                          \
 421         env->xcc = (_tmp >> 4) << 20;                                   \
 422         env->psr = (_tmp & 0xf) << 20;                                  \
 423     } while (0)
 424 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
 425
 426 #ifndef NO_CPU_IO_DEFS
 427 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
 428 {
 429     if (unlikely(cwp >= env1->nwindows || cwp < 0))
 430         cwp = 0;
 431     cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
 432 }
 433 #endif
 434 #endif
 435
 436 /* cpu-exec.c */
 437 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 438                           int is_asi, int size);
 439 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 440
 441 #define cpu_init cpu_sparc_init
 442 #define cpu_exec cpu_sparc_exec
 443 #define cpu_gen_code cpu_sparc_gen_code
 444 #define cpu_signal_handler cpu_sparc_signal_handler
 445 #define cpu_list sparc_cpu_list
 446
 447 #define CPU_SAVE_VERSION 5
 448
 449 /* MMU modes definitions */
 450 #define MMU_MODE0_SUFFIX _user
 451 #define MMU_MODE1_SUFFIX _kernel
 452 #ifdef TARGET_SPARC64
 453 #define MMU_MODE2_SUFFIX _hypv
 454 #endif
 455 #define MMU_USER_IDX   0
 456 #define MMU_KERNEL_IDX 1
 457 #define MMU_HYPV_IDX   2
 458
 459 static inline int cpu_mmu_index(CPUState *env1)
 460 {
 461 #if defined(CONFIG_USER_ONLY)
 462     return MMU_USER_IDX;
 463 #elif !defined(TARGET_SPARC64)
 464     return env1->psrs;
 465 #else
 466     if (!env1->psrs)
 467         return MMU_USER_IDX;
 468     else if ((env1->hpstate & HS_PRIV) == 0)
 469         return MMU_KERNEL_IDX;
 470     else
 471         return MMU_HYPV_IDX;
 472 #endif
 473 }
 474
 475 static inline int cpu_fpu_enabled(CPUState *env1)
 476 {
 477 #if defined(CONFIG_USER_ONLY)
 478     return 1;
 479 #elif !defined(TARGET_SPARC64)
 480     return env1->psref;
 481 #else
 482     return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
 483 #endif
 484 }
 485
 486 #if defined(CONFIG_USER_ONLY)
 487 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 488 {
 489     if (newsp)
 490         env->regwptr[22] = newsp;
 491     env->regwptr[0] = 0;
 492     /* FIXME: Do we also need to clear CF?  */
 493     /* XXXXX */
 494     printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
 495 }
 496 #endif
 497
 498 #include "cpu-all.h"
 499 #include "exec-all.h"
 500
 501 /* sum4m.c, sun4u.c */
 502 void cpu_check_irqs(CPUSPARCState *env);
 503
 504 #ifdef TARGET_SPARC64
 505 /* sun4u.c */
 506 void cpu_tick_set_count(void *opaque, uint64_t count);
 507 uint64_t cpu_tick_get_count(void *opaque);
 508 void cpu_tick_set_limit(void *opaque, uint64_t limit);
 509 #endif
 510
 511 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 512 {
 513     env->pc = tb->pc;
 514     env->npc = tb->cs_base;
 515 }
 516
 517 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 518                                         target_ulong *cs_base, int *flags)
 519 {
 520     *pc = env->pc;
 521     *cs_base = env->npc;
 522 #ifdef TARGET_SPARC64
 523     // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 524     *flags = ((env->pstate & PS_AM) << 2)
 525         | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
 526         | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
 527 #else
 528     // FPU enable . Supervisor
 529     *flags = (env->psref << 4) | env->psrs;
 530 #endif
 531 }
 532
 533 #endif