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Update irqs on reset and device load
[qemu/hppa.git] / hw / sun4m.c
blobef9fa5e0b6a77bf6e88e59208f82ce222f18f0cf
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_gpio_in(dev, 0);
383 }
384
385 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
386 const char *boot_device,
387 const char *kernel_filename,
388 const char *kernel_cmdline,
389 const char *initrd_filename, const char *cpu_model)
390
391 {
392 CPUState *env, *envs[MAX_CPUS];
393 unsigned int i;
394 void *iommu, *espdma, *ledma, *nvram;
395 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
396 *espdma_irq, *ledma_irq;
397 qemu_irq *esp_reset, *le_reset;
398 qemu_irq *fdc_tc;
399 qemu_irq *cpu_halt;
400 ram_addr_t ram_offset, prom_offset, idreg_offset;
401 unsigned long kernel_size;
402 int ret;
403 char *filename;
404 BlockDriverState *fd[MAX_FD];
405 int drive_index;
406 void *fw_cfg;
407
408 /* init CPUs */
409 if (!cpu_model)
410 cpu_model = hwdef->default_cpu_model;
411
412 for(i = 0; i < smp_cpus; i++) {
413 env = cpu_init(cpu_model);
414 if (!env) {
415 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
416 exit(1);
417 }
418 cpu_sparc_set_id(env, i);
419 envs[i] = env;
420 if (i == 0) {
421 qemu_register_reset(main_cpu_reset, 0, env);
422 } else {
423 qemu_register_reset(secondary_cpu_reset, 0, env);
424 env->halted = 1;
425 }
426 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
427 env->prom_addr = hwdef->slavio_base;
428 }
429
430 for (i = smp_cpus; i < MAX_CPUS; i++)
431 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
432
433
434 /* allocate RAM */
435 if ((uint64_t)RAM_size > hwdef->max_mem) {
436 fprintf(stderr,
437 "qemu: Too much memory for this machine: %d, maximum %d\n",
438 (unsigned int)(RAM_size / (1024 * 1024)),
439 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
440 exit(1);
441 }
442 ram_offset = qemu_ram_alloc(RAM_size);
443 cpu_register_physical_memory(0, RAM_size, ram_offset);
444
445 /* load boot prom */
446 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
447 cpu_register_physical_memory(hwdef->slavio_base,
448 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
449 TARGET_PAGE_MASK,
450 prom_offset | IO_MEM_ROM);
451
452 if (bios_name == NULL)
453 bios_name = PROM_FILENAME;
454 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
455 if (filename) {
456 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
457 NULL, NULL, NULL);
458 if (ret < 0 || ret > PROM_SIZE_MAX)
459 ret = load_image_targphys(filename, hwdef->slavio_base,
460 PROM_SIZE_MAX);
461 qemu_free(filename);
462 } else {
463 ret = -1;
464 }
465 if (ret < 0 || ret > PROM_SIZE_MAX) {
466 fprintf(stderr, "qemu: could not load prom '%s'\n",
467 bios_name);
468 exit(1);
469 }
470
471 /* set up devices */
472 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
473 hwdef->intctl_base + 0x10000ULL,
474 &hwdef->intbit_to_level[0],
475 &slavio_irq, &slavio_cpu_irq,
476 cpu_irqs,
477 hwdef->clock_irq);
478
479 if (hwdef->idreg_base) {
480 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
481
482 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
483 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
484 idreg_offset | IO_MEM_ROM);
485 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
486 sizeof(idreg_data));
487 }
488
489 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
490 slavio_irq[hwdef->me_irq]);
491
492 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
493 iommu, &espdma_irq, &esp_reset);
494
495 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
496 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
497 &le_reset);
498
499 if (graphic_depth != 8 && graphic_depth != 24) {
500 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
501 exit (1);
502 }
503 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
504 graphic_depth);
505
506 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
507
508 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
509 hwdef->nvram_size, 8);
510
511 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
512 slavio_cpu_irq, smp_cpus);
513
514 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
515 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
516 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
517 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
518 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
519 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
520
521 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
522 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
523 hwdef->aux1_base, hwdef->aux2_base,
524 slavio_irq[hwdef->me_irq], cpu_halt[0],
525 &fdc_tc);
526
527 if (hwdef->fd_base) {
528 /* there is zero or one floppy drive */
529 memset(fd, 0, sizeof(fd));
530 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
531 if (drive_index != -1)
532 fd[0] = drives_table[drive_index].bdrv;
533
534 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
535 fdc_tc);
536 }
537
538 if (drive_get_max_bus(IF_SCSI) > 0) {
539 fprintf(stderr, "qemu: too many SCSI bus\n");
540 exit(1);
541 }
542
543 esp_init(hwdef->esp_base, 2,
544 espdma_memory_read, espdma_memory_write,
545 espdma, *espdma_irq, esp_reset);
546
547 if (hwdef->cs_base)
548 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
549
550 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
551 RAM_size);
552
553 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
554 boot_device, RAM_size, kernel_size, graphic_width,
555 graphic_height, graphic_depth, hwdef->nvram_machine_id,
556 "Sun4m");
557
558 if (hwdef->ecc_base)
559 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
560 hwdef->ecc_version);
561
562 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
563 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
564 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
565 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
566 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
567 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
568 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
569 if (kernel_cmdline) {
570 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
571 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
572 } else {
573 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
574 }
575 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
576 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
577 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
578 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
579 }
580
581 enum {
582 ss2_id = 0,
583 ss5_id = 32,
584 vger_id,
585 lx_id,
586 ss4_id,
587 scls_id,
588 sbook_id,
589 ss10_id = 64,
590 ss20_id,
591 ss600mp_id,
592 ss1000_id = 96,
593 ss2000_id,
594 };
595
596 static const struct sun4m_hwdef sun4m_hwdefs[] = {
597 /* SS-5 */
598 {
599 .iommu_base = 0x10000000,
600 .tcx_base = 0x50000000,
601 .cs_base = 0x6c000000,
602 .slavio_base = 0x70000000,
603 .ms_kb_base = 0x71000000,
604 .serial_base = 0x71100000,
605 .nvram_base = 0x71200000,
606 .fd_base = 0x71400000,
607 .counter_base = 0x71d00000,
608 .intctl_base = 0x71e00000,
609 .idreg_base = 0x78000000,
610 .dma_base = 0x78400000,
611 .esp_base = 0x78800000,
612 .le_base = 0x78c00000,
613 .apc_base = 0x6a000000,
614 .aux1_base = 0x71900000,
615 .aux2_base = 0x71910000,
616 .vram_size = 0x00100000,
617 .nvram_size = 0x2000,
618 .esp_irq = 18,
619 .le_irq = 16,
620 .clock_irq = 7,
621 .clock1_irq = 19,
622 .ms_kb_irq = 14,
623 .ser_irq = 15,
624 .fd_irq = 22,
625 .me_irq = 30,
626 .cs_irq = 5,
627 .nvram_machine_id = 0x80,
628 .machine_id = ss5_id,
629 .iommu_version = 0x05000000,
630 .intbit_to_level = {
631 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
632 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
633 },
634 .max_mem = 0x10000000,
635 .default_cpu_model = "Fujitsu MB86904",
636 },
637 /* SS-10 */
638 {
639 .iommu_base = 0xfe0000000ULL,
640 .tcx_base = 0xe20000000ULL,
641 .slavio_base = 0xff0000000ULL,
642 .ms_kb_base = 0xff1000000ULL,
643 .serial_base = 0xff1100000ULL,
644 .nvram_base = 0xff1200000ULL,
645 .fd_base = 0xff1700000ULL,
646 .counter_base = 0xff1300000ULL,
647 .intctl_base = 0xff1400000ULL,
648 .idreg_base = 0xef0000000ULL,
649 .dma_base = 0xef0400000ULL,
650 .esp_base = 0xef0800000ULL,
651 .le_base = 0xef0c00000ULL,
652 .apc_base = 0xefa000000ULL, // XXX should not exist
653 .aux1_base = 0xff1800000ULL,
654 .aux2_base = 0xff1a01000ULL,
655 .ecc_base = 0xf00000000ULL,
656 .ecc_version = 0x10000000, // version 0, implementation 1
657 .vram_size = 0x00100000,
658 .nvram_size = 0x2000,
659 .esp_irq = 18,
660 .le_irq = 16,
661 .clock_irq = 7,
662 .clock1_irq = 19,
663 .ms_kb_irq = 14,
664 .ser_irq = 15,
665 .fd_irq = 22,
666 .me_irq = 30,
667 .ecc_irq = 28,
668 .nvram_machine_id = 0x72,
669 .machine_id = ss10_id,
670 .iommu_version = 0x03000000,
671 .intbit_to_level = {
672 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
673 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
674 },
675 .max_mem = 0xf00000000ULL,
676 .default_cpu_model = "TI SuperSparc II",
677 },
678 /* SS-600MP */
679 {
680 .iommu_base = 0xfe0000000ULL,
681 .tcx_base = 0xe20000000ULL,
682 .slavio_base = 0xff0000000ULL,
683 .ms_kb_base = 0xff1000000ULL,
684 .serial_base = 0xff1100000ULL,
685 .nvram_base = 0xff1200000ULL,
686 .counter_base = 0xff1300000ULL,
687 .intctl_base = 0xff1400000ULL,
688 .dma_base = 0xef0081000ULL,
689 .esp_base = 0xef0080000ULL,
690 .le_base = 0xef0060000ULL,
691 .apc_base = 0xefa000000ULL, // XXX should not exist
692 .aux1_base = 0xff1800000ULL,
693 .aux2_base = 0xff1a01000ULL, // XXX should not exist
694 .ecc_base = 0xf00000000ULL,
695 .ecc_version = 0x00000000, // version 0, implementation 0
696 .vram_size = 0x00100000,
697 .nvram_size = 0x2000,
698 .esp_irq = 18,
699 .le_irq = 16,
700 .clock_irq = 7,
701 .clock1_irq = 19,
702 .ms_kb_irq = 14,
703 .ser_irq = 15,
704 .fd_irq = 22,
705 .me_irq = 30,
706 .ecc_irq = 28,
707 .nvram_machine_id = 0x71,
708 .machine_id = ss600mp_id,
709 .iommu_version = 0x01000000,
710 .intbit_to_level = {
711 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
712 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
713 },
714 .max_mem = 0xf00000000ULL,
715 .default_cpu_model = "TI SuperSparc II",
716 },
717 /* SS-20 */
718 {
719 .iommu_base = 0xfe0000000ULL,
720 .tcx_base = 0xe20000000ULL,
721 .slavio_base = 0xff0000000ULL,
722 .ms_kb_base = 0xff1000000ULL,
723 .serial_base = 0xff1100000ULL,
724 .nvram_base = 0xff1200000ULL,
725 .fd_base = 0xff1700000ULL,
726 .counter_base = 0xff1300000ULL,
727 .intctl_base = 0xff1400000ULL,
728 .idreg_base = 0xef0000000ULL,
729 .dma_base = 0xef0400000ULL,
730 .esp_base = 0xef0800000ULL,
731 .le_base = 0xef0c00000ULL,
732 .apc_base = 0xefa000000ULL, // XXX should not exist
733 .aux1_base = 0xff1800000ULL,
734 .aux2_base = 0xff1a01000ULL,
735 .ecc_base = 0xf00000000ULL,
736 .ecc_version = 0x20000000, // version 0, implementation 2
737 .vram_size = 0x00100000,
738 .nvram_size = 0x2000,
739 .esp_irq = 18,
740 .le_irq = 16,
741 .clock_irq = 7,
742 .clock1_irq = 19,
743 .ms_kb_irq = 14,
744 .ser_irq = 15,
745 .fd_irq = 22,
746 .me_irq = 30,
747 .ecc_irq = 28,
748 .nvram_machine_id = 0x72,
749 .machine_id = ss20_id,
750 .iommu_version = 0x13000000,
751 .intbit_to_level = {
752 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
753 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
754 },
755 .max_mem = 0xf00000000ULL,
756 .default_cpu_model = "TI SuperSparc II",
757 },
758 /* Voyager */
759 {
760 .iommu_base = 0x10000000,
761 .tcx_base = 0x50000000,
762 .slavio_base = 0x70000000,
763 .ms_kb_base = 0x71000000,
764 .serial_base = 0x71100000,
765 .nvram_base = 0x71200000,
766 .fd_base = 0x71400000,
767 .counter_base = 0x71d00000,
768 .intctl_base = 0x71e00000,
769 .idreg_base = 0x78000000,
770 .dma_base = 0x78400000,
771 .esp_base = 0x78800000,
772 .le_base = 0x78c00000,
773 .apc_base = 0x71300000, // pmc
774 .aux1_base = 0x71900000,
775 .aux2_base = 0x71910000,
776 .vram_size = 0x00100000,
777 .nvram_size = 0x2000,
778 .esp_irq = 18,
779 .le_irq = 16,
780 .clock_irq = 7,
781 .clock1_irq = 19,
782 .ms_kb_irq = 14,
783 .ser_irq = 15,
784 .fd_irq = 22,
785 .me_irq = 30,
786 .nvram_machine_id = 0x80,
787 .machine_id = vger_id,
788 .iommu_version = 0x05000000,
789 .intbit_to_level = {
790 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
791 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
792 },
793 .max_mem = 0x10000000,
794 .default_cpu_model = "Fujitsu MB86904",
795 },
796 /* LX */
797 {
798 .iommu_base = 0x10000000,
799 .tcx_base = 0x50000000,
800 .slavio_base = 0x70000000,
801 .ms_kb_base = 0x71000000,
802 .serial_base = 0x71100000,
803 .nvram_base = 0x71200000,
804 .fd_base = 0x71400000,
805 .counter_base = 0x71d00000,
806 .intctl_base = 0x71e00000,
807 .idreg_base = 0x78000000,
808 .dma_base = 0x78400000,
809 .esp_base = 0x78800000,
810 .le_base = 0x78c00000,
811 .aux1_base = 0x71900000,
812 .aux2_base = 0x71910000,
813 .vram_size = 0x00100000,
814 .nvram_size = 0x2000,
815 .esp_irq = 18,
816 .le_irq = 16,
817 .clock_irq = 7,
818 .clock1_irq = 19,
819 .ms_kb_irq = 14,
820 .ser_irq = 15,
821 .fd_irq = 22,
822 .me_irq = 30,
823 .nvram_machine_id = 0x80,
824 .machine_id = lx_id,
825 .iommu_version = 0x04000000,
826 .intbit_to_level = {
827 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
828 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
829 },
830 .max_mem = 0x10000000,
831 .default_cpu_model = "TI MicroSparc I",
832 },
833 /* SS-4 */
834 {
835 .iommu_base = 0x10000000,
836 .tcx_base = 0x50000000,
837 .cs_base = 0x6c000000,
838 .slavio_base = 0x70000000,
839 .ms_kb_base = 0x71000000,
840 .serial_base = 0x71100000,
841 .nvram_base = 0x71200000,
842 .fd_base = 0x71400000,
843 .counter_base = 0x71d00000,
844 .intctl_base = 0x71e00000,
845 .idreg_base = 0x78000000,
846 .dma_base = 0x78400000,
847 .esp_base = 0x78800000,
848 .le_base = 0x78c00000,
849 .apc_base = 0x6a000000,
850 .aux1_base = 0x71900000,
851 .aux2_base = 0x71910000,
852 .vram_size = 0x00100000,
853 .nvram_size = 0x2000,
854 .esp_irq = 18,
855 .le_irq = 16,
856 .clock_irq = 7,
857 .clock1_irq = 19,
858 .ms_kb_irq = 14,
859 .ser_irq = 15,
860 .fd_irq = 22,
861 .me_irq = 30,
862 .cs_irq = 5,
863 .nvram_machine_id = 0x80,
864 .machine_id = ss4_id,
865 .iommu_version = 0x05000000,
866 .intbit_to_level = {
867 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
868 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
869 },
870 .max_mem = 0x10000000,
871 .default_cpu_model = "Fujitsu MB86904",
872 },
873 /* SPARCClassic */
874 {
875 .iommu_base = 0x10000000,
876 .tcx_base = 0x50000000,
877 .slavio_base = 0x70000000,
878 .ms_kb_base = 0x71000000,
879 .serial_base = 0x71100000,
880 .nvram_base = 0x71200000,
881 .fd_base = 0x71400000,
882 .counter_base = 0x71d00000,
883 .intctl_base = 0x71e00000,
884 .idreg_base = 0x78000000,
885 .dma_base = 0x78400000,
886 .esp_base = 0x78800000,
887 .le_base = 0x78c00000,
888 .apc_base = 0x6a000000,
889 .aux1_base = 0x71900000,
890 .aux2_base = 0x71910000,
891 .vram_size = 0x00100000,
892 .nvram_size = 0x2000,
893 .esp_irq = 18,
894 .le_irq = 16,
895 .clock_irq = 7,
896 .clock1_irq = 19,
897 .ms_kb_irq = 14,
898 .ser_irq = 15,
899 .fd_irq = 22,
900 .me_irq = 30,
901 .nvram_machine_id = 0x80,
902 .machine_id = scls_id,
903 .iommu_version = 0x05000000,
904 .intbit_to_level = {
905 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
906 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
907 },
908 .max_mem = 0x10000000,
909 .default_cpu_model = "TI MicroSparc I",
910 },
911 /* SPARCbook */
912 {
913 .iommu_base = 0x10000000,
914 .tcx_base = 0x50000000, // XXX
915 .slavio_base = 0x70000000,
916 .ms_kb_base = 0x71000000,
917 .serial_base = 0x71100000,
918 .nvram_base = 0x71200000,
919 .fd_base = 0x71400000,
920 .counter_base = 0x71d00000,
921 .intctl_base = 0x71e00000,
922 .idreg_base = 0x78000000,
923 .dma_base = 0x78400000,
924 .esp_base = 0x78800000,
925 .le_base = 0x78c00000,
926 .apc_base = 0x6a000000,
927 .aux1_base = 0x71900000,
928 .aux2_base = 0x71910000,
929 .vram_size = 0x00100000,
930 .nvram_size = 0x2000,
931 .esp_irq = 18,
932 .le_irq = 16,
933 .clock_irq = 7,
934 .clock1_irq = 19,
935 .ms_kb_irq = 14,
936 .ser_irq = 15,
937 .fd_irq = 22,
938 .me_irq = 30,
939 .nvram_machine_id = 0x80,
940 .machine_id = sbook_id,
941 .iommu_version = 0x05000000,
942 .intbit_to_level = {
943 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
944 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
945 },
946 .max_mem = 0x10000000,
947 .default_cpu_model = "TI MicroSparc I",
948 },
949 };
950
951 /* SPARCstation 5 hardware initialisation */
952 static void ss5_init(ram_addr_t RAM_size,
953 const char *boot_device,
954 const char *kernel_filename, const char *kernel_cmdline,
955 const char *initrd_filename, const char *cpu_model)
956 {
957 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
958 kernel_cmdline, initrd_filename, cpu_model);
959 }
960
961 /* SPARCstation 10 hardware initialisation */
962 static void ss10_init(ram_addr_t RAM_size,
963 const char *boot_device,
964 const char *kernel_filename, const char *kernel_cmdline,
965 const char *initrd_filename, const char *cpu_model)
966 {
967 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
968 kernel_cmdline, initrd_filename, cpu_model);
969 }
970
971 /* SPARCserver 600MP hardware initialisation */
972 static void ss600mp_init(ram_addr_t RAM_size,
973 const char *boot_device,
974 const char *kernel_filename,
975 const char *kernel_cmdline,
976 const char *initrd_filename, const char *cpu_model)
977 {
978 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
979 kernel_cmdline, initrd_filename, cpu_model);
980 }
981
982 /* SPARCstation 20 hardware initialisation */
983 static void ss20_init(ram_addr_t RAM_size,
984 const char *boot_device,
985 const char *kernel_filename, const char *kernel_cmdline,
986 const char *initrd_filename, const char *cpu_model)
987 {
988 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
989 kernel_cmdline, initrd_filename, cpu_model);
990 }
991
992 /* SPARCstation Voyager hardware initialisation */
993 static void vger_init(ram_addr_t RAM_size,
994 const char *boot_device,
995 const char *kernel_filename, const char *kernel_cmdline,
996 const char *initrd_filename, const char *cpu_model)
997 {
998 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
999 kernel_cmdline, initrd_filename, cpu_model);
1000 }
1001
1002 /* SPARCstation LX hardware initialisation */
1003 static void ss_lx_init(ram_addr_t RAM_size,
1004 const char *boot_device,
1005 const char *kernel_filename, const char *kernel_cmdline,
1006 const char *initrd_filename, const char *cpu_model)
1007 {
1008 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1009 kernel_cmdline, initrd_filename, cpu_model);
1010 }
1011
1012 /* SPARCstation 4 hardware initialisation */
1013 static void ss4_init(ram_addr_t RAM_size,
1014 const char *boot_device,
1015 const char *kernel_filename, const char *kernel_cmdline,
1016 const char *initrd_filename, const char *cpu_model)
1017 {
1018 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1019 kernel_cmdline, initrd_filename, cpu_model);
1020 }
1021
1022 /* SPARCClassic hardware initialisation */
1023 static void scls_init(ram_addr_t RAM_size,
1024 const char *boot_device,
1025 const char *kernel_filename, const char *kernel_cmdline,
1026 const char *initrd_filename, const char *cpu_model)
1027 {
1028 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1029 kernel_cmdline, initrd_filename, cpu_model);
1030 }
1031
1032 /* SPARCbook hardware initialisation */
1033 static void sbook_init(ram_addr_t RAM_size,
1034 const char *boot_device,
1035 const char *kernel_filename, const char *kernel_cmdline,
1036 const char *initrd_filename, const char *cpu_model)
1037 {
1038 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1039 kernel_cmdline, initrd_filename, cpu_model);
1040 }
1041
1042 static QEMUMachine ss5_machine = {
1043 .name = "SS-5",
1044 .desc = "Sun4m platform, SPARCstation 5",
1045 .init = ss5_init,
1046 .use_scsi = 1,
1047 .is_default = 1,
1048 };
1049
1050 static QEMUMachine ss10_machine = {
1051 .name = "SS-10",
1052 .desc = "Sun4m platform, SPARCstation 10",
1053 .init = ss10_init,
1054 .use_scsi = 1,
1055 .max_cpus = 4,
1056 };
1057
1058 static QEMUMachine ss600mp_machine = {
1059 .name = "SS-600MP",
1060 .desc = "Sun4m platform, SPARCserver 600MP",
1061 .init = ss600mp_init,
1062 .use_scsi = 1,
1063 .max_cpus = 4,
1064 };
1065
1066 static QEMUMachine ss20_machine = {
1067 .name = "SS-20",
1068 .desc = "Sun4m platform, SPARCstation 20",
1069 .init = ss20_init,
1070 .use_scsi = 1,
1071 .max_cpus = 4,
1072 };
1073
1074 static QEMUMachine voyager_machine = {
1075 .name = "Voyager",
1076 .desc = "Sun4m platform, SPARCstation Voyager",
1077 .init = vger_init,
1078 .use_scsi = 1,
1079 };
1080
1081 static QEMUMachine ss_lx_machine = {
1082 .name = "LX",
1083 .desc = "Sun4m platform, SPARCstation LX",
1084 .init = ss_lx_init,
1085 .use_scsi = 1,
1086 };
1087
1088 static QEMUMachine ss4_machine = {
1089 .name = "SS-4",
1090 .desc = "Sun4m platform, SPARCstation 4",
1091 .init = ss4_init,
1092 .use_scsi = 1,
1093 };
1094
1095 static QEMUMachine scls_machine = {
1096 .name = "SPARCClassic",
1097 .desc = "Sun4m platform, SPARCClassic",
1098 .init = scls_init,
1099 .use_scsi = 1,
1100 };
1101
1102 static QEMUMachine sbook_machine = {
1103 .name = "SPARCbook",
1104 .desc = "Sun4m platform, SPARCbook",
1105 .init = sbook_init,
1106 .use_scsi = 1,
1107 };
1108
1109 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1110 /* SS-1000 */
1111 {
1112 .iounit_bases = {
1113 0xfe0200000ULL,
1114 0xfe1200000ULL,
1115 0xfe2200000ULL,
1116 0xfe3200000ULL,
1117 -1,
1118 },
1119 .tcx_base = 0x820000000ULL,
1120 .slavio_base = 0xf00000000ULL,
1121 .ms_kb_base = 0xf00240000ULL,
1122 .serial_base = 0xf00200000ULL,
1123 .nvram_base = 0xf00280000ULL,
1124 .counter_base = 0xf00300000ULL,
1125 .espdma_base = 0x800081000ULL,
1126 .esp_base = 0x800080000ULL,
1127 .ledma_base = 0x800040000ULL,
1128 .le_base = 0x800060000ULL,
1129 .sbi_base = 0xf02800000ULL,
1130 .vram_size = 0x00100000,
1131 .nvram_size = 0x2000,
1132 .esp_irq = 3,
1133 .le_irq = 4,
1134 .clock_irq = 14,
1135 .clock1_irq = 10,
1136 .ms_kb_irq = 12,
1137 .ser_irq = 12,
1138 .nvram_machine_id = 0x80,
1139 .machine_id = ss1000_id,
1140 .iounit_version = 0x03000000,
1141 .max_mem = 0xf00000000ULL,
1142 .default_cpu_model = "TI SuperSparc II",
1143 },
1144 /* SS-2000 */
1145 {
1146 .iounit_bases = {
1147 0xfe0200000ULL,
1148 0xfe1200000ULL,
1149 0xfe2200000ULL,
1150 0xfe3200000ULL,
1151 0xfe4200000ULL,
1152 },
1153 .tcx_base = 0x820000000ULL,
1154 .slavio_base = 0xf00000000ULL,
1155 .ms_kb_base = 0xf00240000ULL,
1156 .serial_base = 0xf00200000ULL,
1157 .nvram_base = 0xf00280000ULL,
1158 .counter_base = 0xf00300000ULL,
1159 .espdma_base = 0x800081000ULL,
1160 .esp_base = 0x800080000ULL,
1161 .ledma_base = 0x800040000ULL,
1162 .le_base = 0x800060000ULL,
1163 .sbi_base = 0xf02800000ULL,
1164 .vram_size = 0x00100000,
1165 .nvram_size = 0x2000,
1166 .esp_irq = 3,
1167 .le_irq = 4,
1168 .clock_irq = 14,
1169 .clock1_irq = 10,
1170 .ms_kb_irq = 12,
1171 .ser_irq = 12,
1172 .nvram_machine_id = 0x80,
1173 .machine_id = ss2000_id,
1174 .iounit_version = 0x03000000,
1175 .max_mem = 0xf00000000ULL,
1176 .default_cpu_model = "TI SuperSparc II",
1177 },
1178 };
1179
1180 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1181 const char *boot_device,
1182 const char *kernel_filename,
1183 const char *kernel_cmdline,
1184 const char *initrd_filename, const char *cpu_model)
1185 {
1186 CPUState *env, *envs[MAX_CPUS];
1187 unsigned int i;
1188 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1189 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1190 *espdma_irq, *ledma_irq;
1191 qemu_irq *esp_reset, *le_reset;
1192 ram_addr_t ram_offset, prom_offset;
1193 unsigned long kernel_size;
1194 int ret;
1195 char *filename;
1196 void *fw_cfg;
1197
1198 /* init CPUs */
1199 if (!cpu_model)
1200 cpu_model = hwdef->default_cpu_model;
1201
1202 for (i = 0; i < smp_cpus; i++) {
1203 env = cpu_init(cpu_model);
1204 if (!env) {
1205 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1206 exit(1);
1207 }
1208 cpu_sparc_set_id(env, i);
1209 envs[i] = env;
1210 if (i == 0) {
1211 qemu_register_reset(main_cpu_reset, 0, env);
1212 } else {
1213 qemu_register_reset(secondary_cpu_reset, 0, env);
1214 env->halted = 1;
1215 }
1216 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1217 env->prom_addr = hwdef->slavio_base;
1218 }
1219
1220 for (i = smp_cpus; i < MAX_CPUS; i++)
1221 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1222
1223 /* allocate RAM */
1224 if ((uint64_t)RAM_size > hwdef->max_mem) {
1225 fprintf(stderr,
1226 "qemu: Too much memory for this machine: %d, maximum %d\n",
1227 (unsigned int)(RAM_size / (1024 * 1024)),
1228 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1229 exit(1);
1230 }
1231 ram_offset = qemu_ram_alloc(RAM_size);
1232 cpu_register_physical_memory(0, RAM_size, ram_offset);
1233
1234 /* load boot prom */
1235 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1236 cpu_register_physical_memory(hwdef->slavio_base,
1237 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1238 TARGET_PAGE_MASK,
1239 prom_offset | IO_MEM_ROM);
1240
1241 if (bios_name == NULL)
1242 bios_name = PROM_FILENAME;
1243 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1244 if (filename) {
1245 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1246 NULL, NULL, NULL);
1247 if (ret < 0 || ret > PROM_SIZE_MAX)
1248 ret = load_image_targphys(filename, hwdef->slavio_base,
1249 PROM_SIZE_MAX);
1250 qemu_free(filename);
1251 } else {
1252 ret = -1;
1253 }
1254 if (ret < 0 || ret > PROM_SIZE_MAX) {
1255 fprintf(stderr, "qemu: could not load prom '%s'\n",
1256 bios_name);
1257 exit(1);
1258 }
1259
1260 /* set up devices */
1261 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1262
1263 for (i = 0; i < MAX_IOUNITS; i++)
1264 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1265 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1266 hwdef->iounit_version,
1267 sbi_irq[hwdef->me_irq]);
1268
1269 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1270 iounits[0], &espdma_irq, &esp_reset);
1271
1272 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1273 iounits[0], &ledma_irq, &le_reset);
1274
1275 if (graphic_depth != 8 && graphic_depth != 24) {
1276 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1277 exit (1);
1278 }
1279 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1280 graphic_depth);
1281
1282 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1283
1284 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1285 hwdef->nvram_size, 8);
1286
1287 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1288 sbi_cpu_irq, smp_cpus);
1289
1290 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1291 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1292 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1293 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1294 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1295 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1296
1297 if (drive_get_max_bus(IF_SCSI) > 0) {
1298 fprintf(stderr, "qemu: too many SCSI bus\n");
1299 exit(1);
1300 }
1301
1302 esp_init(hwdef->esp_base, 2,
1303 espdma_memory_read, espdma_memory_write,
1304 espdma, *espdma_irq, esp_reset);
1305
1306 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1307 RAM_size);
1308
1309 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1310 boot_device, RAM_size, kernel_size, graphic_width,
1311 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1312 "Sun4d");
1313
1314 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1315 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1316 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1317 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1318 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1319 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1320 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1321 if (kernel_cmdline) {
1322 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1323 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1324 } else {
1325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1326 }
1327 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1328 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1329 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1330 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1331 }
1332
1333 /* SPARCserver 1000 hardware initialisation */
1334 static void ss1000_init(ram_addr_t RAM_size,
1335 const char *boot_device,
1336 const char *kernel_filename, const char *kernel_cmdline,
1337 const char *initrd_filename, const char *cpu_model)
1338 {
1339 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1340 kernel_cmdline, initrd_filename, cpu_model);
1341 }
1342
1343 /* SPARCcenter 2000 hardware initialisation */
1344 static void ss2000_init(ram_addr_t RAM_size,
1345 const char *boot_device,
1346 const char *kernel_filename, const char *kernel_cmdline,
1347 const char *initrd_filename, const char *cpu_model)
1348 {
1349 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1350 kernel_cmdline, initrd_filename, cpu_model);
1351 }
1352
1353 static QEMUMachine ss1000_machine = {
1354 .name = "SS-1000",
1355 .desc = "Sun4d platform, SPARCserver 1000",
1356 .init = ss1000_init,
1357 .use_scsi = 1,
1358 .max_cpus = 8,
1359 };
1360
1361 static QEMUMachine ss2000_machine = {
1362 .name = "SS-2000",
1363 .desc = "Sun4d platform, SPARCcenter 2000",
1364 .init = ss2000_init,
1365 .use_scsi = 1,
1366 .max_cpus = 20,
1367 };
1368
1369 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1370 /* SS-2 */
1371 {
1372 .iommu_base = 0xf8000000,
1373 .tcx_base = 0xfe000000,
1374 .slavio_base = 0xf6000000,
1375 .intctl_base = 0xf5000000,
1376 .counter_base = 0xf3000000,
1377 .ms_kb_base = 0xf0000000,
1378 .serial_base = 0xf1000000,
1379 .nvram_base = 0xf2000000,
1380 .fd_base = 0xf7200000,
1381 .dma_base = 0xf8400000,
1382 .esp_base = 0xf8800000,
1383 .le_base = 0xf8c00000,
1384 .aux1_base = 0xf7400003,
1385 .vram_size = 0x00100000,
1386 .nvram_size = 0x800,
1387 .esp_irq = 2,
1388 .le_irq = 3,
1389 .clock_irq = 5,
1390 .clock1_irq = 7,
1391 .ms_kb_irq = 1,
1392 .ser_irq = 1,
1393 .fd_irq = 1,
1394 .me_irq = 1,
1395 .nvram_machine_id = 0x55,
1396 .machine_id = ss2_id,
1397 .max_mem = 0x10000000,
1398 .default_cpu_model = "Cypress CY7C601",
1399 },
1400 };
1401
1402 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1403 const char *boot_device,
1404 const char *kernel_filename,
1405 const char *kernel_cmdline,
1406 const char *initrd_filename, const char *cpu_model)
1407 {
1408 CPUState *env;
1409 void *iommu, *espdma, *ledma, *nvram;
1410 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1411 qemu_irq *esp_reset, *le_reset;
1412 qemu_irq *fdc_tc;
1413 ram_addr_t ram_offset, prom_offset;
1414 unsigned long kernel_size;
1415 int ret;
1416 char *filename;
1417 BlockDriverState *fd[MAX_FD];
1418 int drive_index;
1419 void *fw_cfg;
1420
1421 /* init CPU */
1422 if (!cpu_model)
1423 cpu_model = hwdef->default_cpu_model;
1424
1425 env = cpu_init(cpu_model);
1426 if (!env) {
1427 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1428 exit(1);
1429 }
1430
1431 cpu_sparc_set_id(env, 0);
1432
1433 qemu_register_reset(main_cpu_reset, 0, env);
1434 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1435 env->prom_addr = hwdef->slavio_base;
1436
1437 /* allocate RAM */
1438 if ((uint64_t)RAM_size > hwdef->max_mem) {
1439 fprintf(stderr,
1440 "qemu: Too much memory for this machine: %d, maximum %d\n",
1441 (unsigned int)(RAM_size / (1024 * 1024)),
1442 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1443 exit(1);
1444 }
1445 ram_offset = qemu_ram_alloc(RAM_size);
1446 cpu_register_physical_memory(0, RAM_size, ram_offset);
1447
1448 /* load boot prom */
1449 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1450 cpu_register_physical_memory(hwdef->slavio_base,
1451 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1452 TARGET_PAGE_MASK,
1453 prom_offset | IO_MEM_ROM);
1454
1455 if (bios_name == NULL)
1456 bios_name = PROM_FILENAME;
1457 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1458 if (filename) {
1459 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1460 NULL, NULL, NULL);
1461 if (ret < 0 || ret > PROM_SIZE_MAX)
1462 ret = load_image_targphys(filename, hwdef->slavio_base,
1463 PROM_SIZE_MAX);
1464 qemu_free(filename);
1465 } else {
1466 ret = -1;
1467 }
1468 if (ret < 0 || ret > PROM_SIZE_MAX) {
1469 fprintf(stderr, "qemu: could not load prom '%s'\n",
1470 filename);
1471 exit(1);
1472 }
1473
1474 /* set up devices */
1475 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1476 &slavio_irq, cpu_irqs);
1477
1478 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1479 slavio_irq[hwdef->me_irq]);
1480
1481 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1482 iommu, &espdma_irq, &esp_reset);
1483
1484 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1485 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1486 &le_reset);
1487
1488 if (graphic_depth != 8 && graphic_depth != 24) {
1489 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1490 exit (1);
1491 }
1492 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1493 graphic_depth);
1494
1495 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1496
1497 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1498 hwdef->nvram_size, 2);
1499
1500 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1501 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1502 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1503 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1504 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1505 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1506 ESCC_CLOCK, 1);
1507
1508 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1509 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1510
1511 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1512 /* there is zero or one floppy drive */
1513 memset(fd, 0, sizeof(fd));
1514 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1515 if (drive_index != -1)
1516 fd[0] = drives_table[drive_index].bdrv;
1517
1518 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1519 fdc_tc);
1520 }
1521
1522 if (drive_get_max_bus(IF_SCSI) > 0) {
1523 fprintf(stderr, "qemu: too many SCSI bus\n");
1524 exit(1);
1525 }
1526
1527 esp_init(hwdef->esp_base, 2,
1528 espdma_memory_read, espdma_memory_write,
1529 espdma, *espdma_irq, esp_reset);
1530
1531 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1532 RAM_size);
1533
1534 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1535 boot_device, RAM_size, kernel_size, graphic_width,
1536 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1537 "Sun4c");
1538
1539 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1540 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1541 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1542 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1543 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1544 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1545 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1546 if (kernel_cmdline) {
1547 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1548 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1549 } else {
1550 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1551 }
1552 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1553 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1554 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1555 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1556 }
1557
1558 /* SPARCstation 2 hardware initialisation */
1559 static void ss2_init(ram_addr_t RAM_size,
1560 const char *boot_device,
1561 const char *kernel_filename, const char *kernel_cmdline,
1562 const char *initrd_filename, const char *cpu_model)
1563 {
1564 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1565 kernel_cmdline, initrd_filename, cpu_model);
1566 }
1567
1568 static QEMUMachine ss2_machine = {
1569 .name = "SS-2",
1570 .desc = "Sun4c platform, SPARCstation 2",
1571 .init = ss2_init,
1572 .use_scsi = 1,
1573 };
1574
1575 static void ss2_machine_init(void)
1576 {
1577 qemu_register_machine(&ss5_machine);
1578 qemu_register_machine(&ss10_machine);
1579 qemu_register_machine(&ss600mp_machine);
1580 qemu_register_machine(&ss20_machine);
1581 qemu_register_machine(&voyager_machine);
1582 qemu_register_machine(&ss_lx_machine);
1583 qemu_register_machine(&ss4_machine);
1584 qemu_register_machine(&scls_machine);
1585 qemu_register_machine(&sbook_machine);
1586 qemu_register_machine(&ss1000_machine);
1587 qemu_register_machine(&ss2000_machine);
1588 qemu_register_machine(&ss2_machine);
1589 }
1590
1591 machine_init(ss2_machine_init);
HPPA (PA-RISC) target for QEMU