hw/versatile_pci.c

   1 /*
   2  * ARM Versatile/PB PCI host controller
   3  *
   4  * Copyright (c) 2006-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "pci.h"
  12
  13 typedef struct {
  14     SysBusDevice busdev;
  15     qemu_irq irq[4];
  16     int realview;
  17     int mem_config;
  18 } PCIVPBState;
  19
  20 static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
  21 {
  22     return addr & 0xffffff;
  23 }
  24
  25 static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
  26                                    uint32_t val)
  27 {
  28     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
  29 }
  30
  31 static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
  32                                    uint32_t val)
  33 {
  34 #ifdef TARGET_WORDS_BIGENDIAN
  35     val = bswap16(val);
  36 #endif
  37     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
  38 }
  39
  40 static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
  41                                    uint32_t val)
  42 {
  43 #ifdef TARGET_WORDS_BIGENDIAN
  44     val = bswap32(val);
  45 #endif
  46     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
  47 }
  48
  49 static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
  50 {
  51     uint32_t val;
  52     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
  53     return val;
  54 }
  55
  56 static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
  57 {
  58     uint32_t val;
  59     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
  60 #ifdef TARGET_WORDS_BIGENDIAN
  61     val = bswap16(val);
  62 #endif
  63     return val;
  64 }
  65
  66 static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
  67 {
  68     uint32_t val;
  69     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
  70 #ifdef TARGET_WORDS_BIGENDIAN
  71     val = bswap32(val);
  72 #endif
  73     return val;
  74 }
  75
  76 static CPUWriteMemoryFunc *pci_vpb_config_write[] = {
  77     &pci_vpb_config_writeb,
  78     &pci_vpb_config_writew,
  79     &pci_vpb_config_writel,
  80 };
  81
  82 static CPUReadMemoryFunc *pci_vpb_config_read[] = {
  83     &pci_vpb_config_readb,
  84     &pci_vpb_config_readw,
  85     &pci_vpb_config_readl,
  86 };
  87
  88 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
  89 {
  90     return irq_num;
  91 }
  92
  93 static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
  94 {
  95     qemu_set_irq(pic[irq_num], level);
  96 }
  97
  98 static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
  99 {
 100     PCIVPBState *s = (PCIVPBState *)dev;
 101     /* Selfconfig area.  */
 102     cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
 103     /* Normal config area.  */
 104     cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
 105
 106     if (s->realview) {
 107         /* IO memory area.  */
 108         isa_mmio_init(base + 0x03000000, 0x00100000);
 109     }
 110 }
 111
 112 static void pci_vpb_init(SysBusDevice *dev)
 113 {
 114     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 115     PCIBus *bus;
 116     int i;
 117
 118     for (i = 0; i < 4; i++) {
 119         sysbus_init_irq(dev, &s->irq[i]);
 120     }
 121     bus = pci_register_bus(&dev->qdev, "pci",
 122                            pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
 123                            11 << 3, 4);
 124
 125     /* ??? Register memory space.  */
 126
 127     s->mem_config = cpu_register_io_memory(0, pci_vpb_config_read,
 128                                            pci_vpb_config_write, bus);
 129     sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
 130
 131     pci_create_simple(bus, -1, "versatile_pci_host");
 132 }
 133
 134 static void pci_realview_init(SysBusDevice *dev)
 135 {
 136     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 137     s->realview = 1;
 138     pci_vpb_init(dev);
 139 }
 140
 141 static void versatile_pci_host_init(PCIDevice *d)
 142 {
 143     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX);
 144     /* Both boards have the same device ID.  Oh well.  */
 145     pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30);
 146     d->config[0x04] = 0x00;
 147     d->config[0x05] = 0x00;
 148     d->config[0x06] = 0x20;
 149     d->config[0x07] = 0x02;
 150     d->config[0x08] = 0x00; // revision
 151     d->config[0x09] = 0x00; // programming i/f
 152     pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
 153     d->config[0x0D] = 0x10; // latency_timer
 154 }
 155
 156 static void versatile_pci_register_devices(void)
 157 {
 158     sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
 159     sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
 160                         pci_realview_init);
 161     pci_qdev_register("versatile_pci_host", sizeof(PCIDevice),
 162                       versatile_pci_host_init);
 163 }
 164
 165 device_init(versatile_pci_register_devices)