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Cirrus transparent BITBLT (w/o color expand), by Hitoshi Osada.
[qemu/dscho.git] / vl.h
blob242b4bc3d2b383eefef8e12de7fa070c80ba5ff9
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef MIN
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
98 #endif
99 #ifndef MAX
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
101 #endif
102
103 /* cutils.c */
104 void pstrcpy(char *buf, int buf_size, const char *str);
105 char *pstrcat(char *buf, int buf_size, const char *s);
106 int strstart(const char *str, const char *val, const char **ptr);
107 int stristart(const char *str, const char *val, const char **ptr);
108
109 /* vl.c */
110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
111
112 void hw_error(const char *fmt, ...);
113
114 extern const char *bios_dir;
115
116 extern int vm_running;
117 extern const char *qemu_name;
118
119 typedef struct vm_change_state_entry VMChangeStateEntry;
120 typedef void VMChangeStateHandler(void *opaque, int running);
121 typedef void VMStopHandler(void *opaque, int reason);
122
123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130 void vm_start(void);
131 void vm_stop(int reason);
132
133 typedef void QEMUResetHandler(void *opaque);
134
135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
142 #else
143 void qemu_system_powerdown(void);
144 #endif
145
146 void main_loop_wait(int timeout);
147
148 extern int ram_size;
149 extern int bios_size;
150 extern int rtc_utc;
151 extern int cirrus_vga_enabled;
152 extern int vmsvga_enabled;
153 extern int graphic_width;
154 extern int graphic_height;
155 extern int graphic_depth;
156 extern const char *keyboard_layout;
157 extern int kqemu_allowed;
158 extern int win2k_install_hack;
159 extern int alt_grab;
160 extern int usb_enabled;
161 extern int smp_cpus;
162 extern int cursor_hide;
163 extern int graphic_rotate;
164 extern int no_quit;
165 extern int semihosting_enabled;
166 extern int autostart;
167 extern int old_param;
168 extern const char *bootp_filename;
169
170 #define MAX_OPTION_ROMS 16
171 extern const char *option_rom[MAX_OPTION_ROMS];
172 extern int nb_option_roms;
173
174 #ifdef TARGET_SPARC
175 #define MAX_PROM_ENVS 128
176 extern const char *prom_envs[MAX_PROM_ENVS];
177 extern unsigned int nb_prom_envs;
178 #endif
179
180 /* XXX: make it dynamic */
181 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
182 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
183 #define BIOS_SIZE ((512 + 32) * 1024)
184 #elif defined(TARGET_MIPS)
185 #define BIOS_SIZE (4 * 1024 * 1024)
186 #endif
187
188 /* keyboard/mouse support */
189
190 #define MOUSE_EVENT_LBUTTON 0x01
191 #define MOUSE_EVENT_RBUTTON 0x02
192 #define MOUSE_EVENT_MBUTTON 0x04
193
194 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
195 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
196
197 typedef struct QEMUPutMouseEntry {
198 QEMUPutMouseEvent *qemu_put_mouse_event;
199 void *qemu_put_mouse_event_opaque;
200 int qemu_put_mouse_event_absolute;
201 char *qemu_put_mouse_event_name;
202
203 /* used internally by qemu for handling mice */
204 struct QEMUPutMouseEntry *next;
205 } QEMUPutMouseEntry;
206
207 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
208 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
209 void *opaque, int absolute,
210 const char *name);
211 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
212
213 void kbd_put_keycode(int keycode);
214 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
215 int kbd_mouse_is_absolute(void);
216
217 void do_info_mice(void);
218 void do_mouse_set(int index);
219
220 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
221 constants) */
222 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
223 #define QEMU_KEY_BACKSPACE 0x007f
224 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
225 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
226 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
227 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
228 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
229 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
230 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
231 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
232 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
233
234 #define QEMU_KEY_CTRL_UP 0xe400
235 #define QEMU_KEY_CTRL_DOWN 0xe401
236 #define QEMU_KEY_CTRL_LEFT 0xe402
237 #define QEMU_KEY_CTRL_RIGHT 0xe403
238 #define QEMU_KEY_CTRL_HOME 0xe404
239 #define QEMU_KEY_CTRL_END 0xe405
240 #define QEMU_KEY_CTRL_PAGEUP 0xe406
241 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
242
243 void kbd_put_keysym(int keysym);
244
245 /* async I/O support */
246
247 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
248 typedef int IOCanRWHandler(void *opaque);
249 typedef void IOHandler(void *opaque);
250
251 int qemu_set_fd_handler2(int fd,
252 IOCanRWHandler *fd_read_poll,
253 IOHandler *fd_read,
254 IOHandler *fd_write,
255 void *opaque);
256 int qemu_set_fd_handler(int fd,
257 IOHandler *fd_read,
258 IOHandler *fd_write,
259 void *opaque);
260
261 /* Polling handling */
262
263 /* return TRUE if no sleep should be done afterwards */
264 typedef int PollingFunc(void *opaque);
265
266 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
267 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
268
269 #ifdef _WIN32
270 /* Wait objects handling */
271 typedef void WaitObjectFunc(void *opaque);
272
273 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
274 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
275 #endif
276
277 typedef struct QEMUBH QEMUBH;
278
279 /* character device */
280
281 #define CHR_EVENT_BREAK 0 /* serial break char */
282 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
283 #define CHR_EVENT_RESET 2 /* new connection established */
284
285
286 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
287 typedef struct {
288 int speed;
289 int parity;
290 int data_bits;
291 int stop_bits;
292 } QEMUSerialSetParams;
293
294 #define CHR_IOCTL_SERIAL_SET_BREAK 2
295
296 #define CHR_IOCTL_PP_READ_DATA 3
297 #define CHR_IOCTL_PP_WRITE_DATA 4
298 #define CHR_IOCTL_PP_READ_CONTROL 5
299 #define CHR_IOCTL_PP_WRITE_CONTROL 6
300 #define CHR_IOCTL_PP_READ_STATUS 7
301 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
302 #define CHR_IOCTL_PP_EPP_READ 9
303 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
304 #define CHR_IOCTL_PP_EPP_WRITE 11
305
306 typedef void IOEventHandler(void *opaque, int event);
307
308 typedef struct CharDriverState {
309 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
310 void (*chr_update_read_handler)(struct CharDriverState *s);
311 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
312 IOEventHandler *chr_event;
313 IOCanRWHandler *chr_can_read;
314 IOReadHandler *chr_read;
315 void *handler_opaque;
316 void (*chr_send_event)(struct CharDriverState *chr, int event);
317 void (*chr_close)(struct CharDriverState *chr);
318 void *opaque;
319 int focus;
320 QEMUBH *bh;
321 } CharDriverState;
322
323 CharDriverState *qemu_chr_open(const char *filename);
324 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
325 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
326 void qemu_chr_send_event(CharDriverState *s, int event);
327 void qemu_chr_add_handlers(CharDriverState *s,
328 IOCanRWHandler *fd_can_read,
329 IOReadHandler *fd_read,
330 IOEventHandler *fd_event,
331 void *opaque);
332 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
333 void qemu_chr_reset(CharDriverState *s);
334 int qemu_chr_can_read(CharDriverState *s);
335 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
336
337 /* consoles */
338
339 typedef struct DisplayState DisplayState;
340 typedef struct TextConsole TextConsole;
341
342 typedef void (*vga_hw_update_ptr)(void *);
343 typedef void (*vga_hw_invalidate_ptr)(void *);
344 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
345
346 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
347 vga_hw_invalidate_ptr invalidate,
348 vga_hw_screen_dump_ptr screen_dump,
349 void *opaque);
350 void vga_hw_update(void);
351 void vga_hw_invalidate(void);
352 void vga_hw_screen_dump(const char *filename);
353
354 int is_graphic_console(void);
355 CharDriverState *text_console_init(DisplayState *ds, const char *p);
356 void console_select(unsigned int index);
357
358 /* serial ports */
359
360 #define MAX_SERIAL_PORTS 4
361
362 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
363
364 /* parallel ports */
365
366 #define MAX_PARALLEL_PORTS 3
367
368 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
369
370 struct ParallelIOArg {
371 void *buffer;
372 int count;
373 };
374
375 /* VLANs support */
376
377 typedef struct VLANClientState VLANClientState;
378
379 struct VLANClientState {
380 IOReadHandler *fd_read;
381 /* Packets may still be sent if this returns zero. It's used to
382 rate-limit the slirp code. */
383 IOCanRWHandler *fd_can_read;
384 void *opaque;
385 struct VLANClientState *next;
386 struct VLANState *vlan;
387 char info_str[256];
388 };
389
390 typedef struct VLANState {
391 int id;
392 VLANClientState *first_client;
393 struct VLANState *next;
394 unsigned int nb_guest_devs, nb_host_devs;
395 } VLANState;
396
397 VLANState *qemu_find_vlan(int id);
398 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
399 IOReadHandler *fd_read,
400 IOCanRWHandler *fd_can_read,
401 void *opaque);
402 int qemu_can_send_packet(VLANClientState *vc);
403 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
404 void qemu_handler_true(void *opaque);
405
406 void do_info_network(void);
407
408 /* TAP win32 */
409 int tap_win32_init(VLANState *vlan, const char *ifname);
410
411 /* NIC info */
412
413 #define MAX_NICS 8
414
415 typedef struct NICInfo {
416 uint8_t macaddr[6];
417 const char *model;
418 VLANState *vlan;
419 } NICInfo;
420
421 extern int nb_nics;
422 extern NICInfo nd_table[MAX_NICS];
423
424 /* timers */
425
426 typedef struct QEMUClock QEMUClock;
427 typedef struct QEMUTimer QEMUTimer;
428 typedef void QEMUTimerCB(void *opaque);
429
430 /* The real time clock should be used only for stuff which does not
431 change the virtual machine state, as it is run even if the virtual
432 machine is stopped. The real time clock has a frequency of 1000
433 Hz. */
434 extern QEMUClock *rt_clock;
435
436 /* The virtual clock is only run during the emulation. It is stopped
437 when the virtual machine is stopped. Virtual timers use a high
438 precision clock, usually cpu cycles (use ticks_per_sec). */
439 extern QEMUClock *vm_clock;
440
441 int64_t qemu_get_clock(QEMUClock *clock);
442
443 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
444 void qemu_free_timer(QEMUTimer *ts);
445 void qemu_del_timer(QEMUTimer *ts);
446 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
447 int qemu_timer_pending(QEMUTimer *ts);
448
449 extern int64_t ticks_per_sec;
450 extern int pit_min_timer_count;
451
452 int64_t cpu_get_ticks(void);
453 void cpu_enable_ticks(void);
454 void cpu_disable_ticks(void);
455
456 /* VM Load/Save */
457
458 typedef struct QEMUFile QEMUFile;
459
460 QEMUFile *qemu_fopen(const char *filename, const char *mode);
461 void qemu_fflush(QEMUFile *f);
462 void qemu_fclose(QEMUFile *f);
463 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
464 void qemu_put_byte(QEMUFile *f, int v);
465 void qemu_put_be16(QEMUFile *f, unsigned int v);
466 void qemu_put_be32(QEMUFile *f, unsigned int v);
467 void qemu_put_be64(QEMUFile *f, uint64_t v);
468 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
469 int qemu_get_byte(QEMUFile *f);
470 unsigned int qemu_get_be16(QEMUFile *f);
471 unsigned int qemu_get_be32(QEMUFile *f);
472 uint64_t qemu_get_be64(QEMUFile *f);
473
474 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
475 {
476 qemu_put_be64(f, *pv);
477 }
478
479 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
480 {
481 qemu_put_be32(f, *pv);
482 }
483
484 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
485 {
486 qemu_put_be16(f, *pv);
487 }
488
489 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
490 {
491 qemu_put_byte(f, *pv);
492 }
493
494 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
495 {
496 *pv = qemu_get_be64(f);
497 }
498
499 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
500 {
501 *pv = qemu_get_be32(f);
502 }
503
504 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
505 {
506 *pv = qemu_get_be16(f);
507 }
508
509 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
510 {
511 *pv = qemu_get_byte(f);
512 }
513
514 #if TARGET_LONG_BITS == 64
515 #define qemu_put_betl qemu_put_be64
516 #define qemu_get_betl qemu_get_be64
517 #define qemu_put_betls qemu_put_be64s
518 #define qemu_get_betls qemu_get_be64s
519 #else
520 #define qemu_put_betl qemu_put_be32
521 #define qemu_get_betl qemu_get_be32
522 #define qemu_put_betls qemu_put_be32s
523 #define qemu_get_betls qemu_get_be32s
524 #endif
525
526 int64_t qemu_ftell(QEMUFile *f);
527 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
528
529 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
530 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
531
532 int register_savevm(const char *idstr,
533 int instance_id,
534 int version_id,
535 SaveStateHandler *save_state,
536 LoadStateHandler *load_state,
537 void *opaque);
538 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
539 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
540
541 void cpu_save(QEMUFile *f, void *opaque);
542 int cpu_load(QEMUFile *f, void *opaque, int version_id);
543
544 void do_savevm(const char *name);
545 void do_loadvm(const char *name);
546 void do_delvm(const char *name);
547 void do_info_snapshots(void);
548
549 /* bottom halves */
550 typedef void QEMUBHFunc(void *opaque);
551
552 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
553 void qemu_bh_schedule(QEMUBH *bh);
554 void qemu_bh_cancel(QEMUBH *bh);
555 void qemu_bh_delete(QEMUBH *bh);
556 int qemu_bh_poll(void);
557
558 /* block.c */
559 typedef struct BlockDriverState BlockDriverState;
560 typedef struct BlockDriver BlockDriver;
561
562 extern BlockDriver bdrv_raw;
563 extern BlockDriver bdrv_host_device;
564 extern BlockDriver bdrv_cow;
565 extern BlockDriver bdrv_qcow;
566 extern BlockDriver bdrv_vmdk;
567 extern BlockDriver bdrv_cloop;
568 extern BlockDriver bdrv_dmg;
569 extern BlockDriver bdrv_bochs;
570 extern BlockDriver bdrv_vpc;
571 extern BlockDriver bdrv_vvfat;
572 extern BlockDriver bdrv_qcow2;
573
574 typedef struct BlockDriverInfo {
575 /* in bytes, 0 if irrelevant */
576 int cluster_size;
577 /* offset at which the VM state can be saved (0 if not possible) */
578 int64_t vm_state_offset;
579 } BlockDriverInfo;
580
581 typedef struct QEMUSnapshotInfo {
582 char id_str[128]; /* unique snapshot id */
583 /* the following fields are informative. They are not needed for
584 the consistency of the snapshot */
585 char name[256]; /* user choosen name */
586 uint32_t vm_state_size; /* VM state info size */
587 uint32_t date_sec; /* UTC date of the snapshot */
588 uint32_t date_nsec;
589 uint64_t vm_clock_nsec; /* VM clock relative to boot */
590 } QEMUSnapshotInfo;
591
592 #define BDRV_O_RDONLY 0x0000
593 #define BDRV_O_RDWR 0x0002
594 #define BDRV_O_ACCESS 0x0003
595 #define BDRV_O_CREAT 0x0004 /* create an empty file */
596 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
597 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
598 use a disk image format on top of
599 it (default for
600 bdrv_file_open()) */
601
602 void bdrv_init(void);
603 BlockDriver *bdrv_find_format(const char *format_name);
604 int bdrv_create(BlockDriver *drv,
605 const char *filename, int64_t size_in_sectors,
606 const char *backing_file, int flags);
607 BlockDriverState *bdrv_new(const char *device_name);
608 void bdrv_delete(BlockDriverState *bs);
609 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
610 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
611 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
612 BlockDriver *drv);
613 void bdrv_close(BlockDriverState *bs);
614 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
615 uint8_t *buf, int nb_sectors);
616 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
617 const uint8_t *buf, int nb_sectors);
618 int bdrv_pread(BlockDriverState *bs, int64_t offset,
619 void *buf, int count);
620 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
621 const void *buf, int count);
622 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
623 int64_t bdrv_getlength(BlockDriverState *bs);
624 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
625 int bdrv_commit(BlockDriverState *bs);
626 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
627 /* async block I/O */
628 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
629 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
630
631 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
632 uint8_t *buf, int nb_sectors,
633 BlockDriverCompletionFunc *cb, void *opaque);
634 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
635 const uint8_t *buf, int nb_sectors,
636 BlockDriverCompletionFunc *cb, void *opaque);
637 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
638
639 void qemu_aio_init(void);
640 void qemu_aio_poll(void);
641 void qemu_aio_flush(void);
642 void qemu_aio_wait_start(void);
643 void qemu_aio_wait(void);
644 void qemu_aio_wait_end(void);
645
646 int qemu_key_check(BlockDriverState *bs, const char *name);
647
648 /* Ensure contents are flushed to disk. */
649 void bdrv_flush(BlockDriverState *bs);
650
651 #define BDRV_TYPE_HD 0
652 #define BDRV_TYPE_CDROM 1
653 #define BDRV_TYPE_FLOPPY 2
654 #define BIOS_ATA_TRANSLATION_AUTO 0
655 #define BIOS_ATA_TRANSLATION_NONE 1
656 #define BIOS_ATA_TRANSLATION_LBA 2
657 #define BIOS_ATA_TRANSLATION_LARGE 3
658 #define BIOS_ATA_TRANSLATION_RECHS 4
659
660 void bdrv_set_geometry_hint(BlockDriverState *bs,
661 int cyls, int heads, int secs);
662 void bdrv_set_type_hint(BlockDriverState *bs, int type);
663 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
664 void bdrv_get_geometry_hint(BlockDriverState *bs,
665 int *pcyls, int *pheads, int *psecs);
666 int bdrv_get_type_hint(BlockDriverState *bs);
667 int bdrv_get_translation_hint(BlockDriverState *bs);
668 int bdrv_is_removable(BlockDriverState *bs);
669 int bdrv_is_read_only(BlockDriverState *bs);
670 int bdrv_is_inserted(BlockDriverState *bs);
671 int bdrv_media_changed(BlockDriverState *bs);
672 int bdrv_is_locked(BlockDriverState *bs);
673 void bdrv_set_locked(BlockDriverState *bs, int locked);
674 void bdrv_eject(BlockDriverState *bs, int eject_flag);
675 void bdrv_set_change_cb(BlockDriverState *bs,
676 void (*change_cb)(void *opaque), void *opaque);
677 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
678 void bdrv_info(void);
679 BlockDriverState *bdrv_find(const char *name);
680 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
681 int bdrv_is_encrypted(BlockDriverState *bs);
682 int bdrv_set_key(BlockDriverState *bs, const char *key);
683 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
684 void *opaque);
685 const char *bdrv_get_device_name(BlockDriverState *bs);
686 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
687 const uint8_t *buf, int nb_sectors);
688 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
689
690 void bdrv_get_backing_filename(BlockDriverState *bs,
691 char *filename, int filename_size);
692 int bdrv_snapshot_create(BlockDriverState *bs,
693 QEMUSnapshotInfo *sn_info);
694 int bdrv_snapshot_goto(BlockDriverState *bs,
695 const char *snapshot_id);
696 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
697 int bdrv_snapshot_list(BlockDriverState *bs,
698 QEMUSnapshotInfo **psn_info);
699 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
700
701 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
702 int path_is_absolute(const char *path);
703 void path_combine(char *dest, int dest_size,
704 const char *base_path,
705 const char *filename);
706
707 #ifndef QEMU_TOOL
708
709 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
710 int boot_device,
711 DisplayState *ds, const char **fd_filename, int snapshot,
712 const char *kernel_filename, const char *kernel_cmdline,
713 const char *initrd_filename, const char *cpu_model);
714
715 typedef struct QEMUMachine {
716 const char *name;
717 const char *desc;
718 QEMUMachineInitFunc *init;
719 struct QEMUMachine *next;
720 } QEMUMachine;
721
722 int qemu_register_machine(QEMUMachine *m);
723
724 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
725
726 #if defined(TARGET_PPC)
727 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
728 #endif
729
730 #if defined(TARGET_MIPS)
731 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
732 #endif
733
734 #include "hw/irq.h"
735
736 /* ISA bus */
737
738 extern target_phys_addr_t isa_mem_base;
739
740 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
741 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
742
743 int register_ioport_read(int start, int length, int size,
744 IOPortReadFunc *func, void *opaque);
745 int register_ioport_write(int start, int length, int size,
746 IOPortWriteFunc *func, void *opaque);
747 void isa_unassign_ioport(int start, int length);
748
749 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
750
751 /* PCI bus */
752
753 extern target_phys_addr_t pci_mem_base;
754
755 typedef struct PCIBus PCIBus;
756 typedef struct PCIDevice PCIDevice;
757
758 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
759 uint32_t address, uint32_t data, int len);
760 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
761 uint32_t address, int len);
762 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
763 uint32_t addr, uint32_t size, int type);
764
765 #define PCI_ADDRESS_SPACE_MEM 0x00
766 #define PCI_ADDRESS_SPACE_IO 0x01
767 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
768
769 typedef struct PCIIORegion {
770 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
771 uint32_t size;
772 uint8_t type;
773 PCIMapIORegionFunc *map_func;
774 } PCIIORegion;
775
776 #define PCI_ROM_SLOT 6
777 #define PCI_NUM_REGIONS 7
778
779 #define PCI_DEVICES_MAX 64
780
781 #define PCI_VENDOR_ID 0x00 /* 16 bits */
782 #define PCI_DEVICE_ID 0x02 /* 16 bits */
783 #define PCI_COMMAND 0x04 /* 16 bits */
784 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
785 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
786 #define PCI_CLASS_DEVICE 0x0a /* Device class */
787 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
788 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
789 #define PCI_MIN_GNT 0x3e /* 8 bits */
790 #define PCI_MAX_LAT 0x3f /* 8 bits */
791
792 struct PCIDevice {
793 /* PCI config space */
794 uint8_t config[256];
795
796 /* the following fields are read only */
797 PCIBus *bus;
798 int devfn;
799 char name[64];
800 PCIIORegion io_regions[PCI_NUM_REGIONS];
801
802 /* do not access the following fields */
803 PCIConfigReadFunc *config_read;
804 PCIConfigWriteFunc *config_write;
805 /* ??? This is a PC-specific hack, and should be removed. */
806 int irq_index;
807
808 /* IRQ objects for the INTA-INTD pins. */
809 qemu_irq *irq;
810
811 /* Current IRQ levels. Used internally by the generic PCI code. */
812 int irq_state[4];
813 };
814
815 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
816 int instance_size, int devfn,
817 PCIConfigReadFunc *config_read,
818 PCIConfigWriteFunc *config_write);
819
820 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
821 uint32_t size, int type,
822 PCIMapIORegionFunc *map_func);
823
824 uint32_t pci_default_read_config(PCIDevice *d,
825 uint32_t address, int len);
826 void pci_default_write_config(PCIDevice *d,
827 uint32_t address, uint32_t val, int len);
828 void pci_device_save(PCIDevice *s, QEMUFile *f);
829 int pci_device_load(PCIDevice *s, QEMUFile *f);
830
831 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
832 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
833 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
834 qemu_irq *pic, int devfn_min, int nirq);
835
836 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
837 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
838 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
839 int pci_bus_num(PCIBus *s);
840 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
841
842 void pci_info(void);
843 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
844 pci_map_irq_fn map_irq, const char *name);
845
846 /* prep_pci.c */
847 PCIBus *pci_prep_init(qemu_irq *pic);
848
849 /* grackle_pci.c */
850 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
851
852 /* unin_pci.c */
853 PCIBus *pci_pmac_init(qemu_irq *pic);
854
855 /* apb_pci.c */
856 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
857 qemu_irq *pic);
858
859 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
860
861 /* piix_pci.c */
862 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
863 void i440fx_set_smm(PCIDevice *d, int val);
864 int piix3_init(PCIBus *bus, int devfn);
865 void i440fx_init_memory_mappings(PCIDevice *d);
866
867 int piix4_init(PCIBus *bus, int devfn);
868
869 /* openpic.c */
870 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
871 enum {
872 OPENPIC_OUTPUT_INT = 0, /* IRQ */
873 OPENPIC_OUTPUT_CINT, /* critical IRQ */
874 OPENPIC_OUTPUT_MCK, /* Machine check event */
875 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
876 OPENPIC_OUTPUT_RESET, /* Core reset event */
877 OPENPIC_OUTPUT_NB,
878 };
879 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
880 qemu_irq **irqs, qemu_irq irq_out);
881
882 /* heathrow_pic.c */
883 qemu_irq *heathrow_pic_init(int *pmem_index);
884
885 /* gt64xxx.c */
886 PCIBus *pci_gt64120_init(qemu_irq *pic);
887
888 #ifdef HAS_AUDIO
889 struct soundhw {
890 const char *name;
891 const char *descr;
892 int enabled;
893 int isa;
894 union {
895 int (*init_isa) (AudioState *s, qemu_irq *pic);
896 int (*init_pci) (PCIBus *bus, AudioState *s);
897 } init;
898 };
899
900 extern struct soundhw soundhw[];
901 #endif
902
903 /* vga.c */
904
905 #ifndef TARGET_SPARC
906 #define VGA_RAM_SIZE (8192 * 1024)
907 #else
908 #define VGA_RAM_SIZE (9 * 1024 * 1024)
909 #endif
910
911 struct DisplayState {
912 uint8_t *data;
913 int linesize;
914 int depth;
915 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
916 int width;
917 int height;
918 void *opaque;
919 QEMUTimer *gui_timer;
920
921 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
922 void (*dpy_resize)(struct DisplayState *s, int w, int h);
923 void (*dpy_refresh)(struct DisplayState *s);
924 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
925 int dst_x, int dst_y, int w, int h);
926 void (*dpy_fill)(struct DisplayState *s, int x, int y,
927 int w, int h, uint32_t c);
928 void (*mouse_set)(int x, int y, int on);
929 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
930 uint8_t *image, uint8_t *mask);
931 };
932
933 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
934 {
935 s->dpy_update(s, x, y, w, h);
936 }
937
938 static inline void dpy_resize(DisplayState *s, int w, int h)
939 {
940 s->dpy_resize(s, w, h);
941 }
942
943 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
944 unsigned long vga_ram_offset, int vga_ram_size);
945 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
946 unsigned long vga_ram_offset, int vga_ram_size,
947 unsigned long vga_bios_offset, int vga_bios_size);
948 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
949 unsigned long vga_ram_offset, int vga_ram_size,
950 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
951 int it_shift);
952
953 /* cirrus_vga.c */
954 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
955 unsigned long vga_ram_offset, int vga_ram_size);
956 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
957 unsigned long vga_ram_offset, int vga_ram_size);
958
959 /* vmware_vga.c */
960 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
961 unsigned long vga_ram_offset, int vga_ram_size);
962
963 /* sdl.c */
964 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
965
966 /* cocoa.m */
967 void cocoa_display_init(DisplayState *ds, int full_screen);
968
969 /* vnc.c */
970 void vnc_display_init(DisplayState *ds, const char *display);
971 void do_info_vnc(void);
972
973 /* x_keymap.c */
974 extern uint8_t _translate_keycode(const int key);
975
976 /* ide.c */
977 #define MAX_DISKS 4
978
979 extern BlockDriverState *bs_table[MAX_DISKS + 1];
980 extern BlockDriverState *sd_bdrv;
981 extern BlockDriverState *mtd_bdrv;
982
983 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
984 BlockDriverState *hd0, BlockDriverState *hd1);
985 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
986 int secondary_ide_enabled);
987 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
988 qemu_irq *pic);
989 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
990 qemu_irq *pic);
991 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
992
993 /* cdrom.c */
994 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
995 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
996
997 /* ds1225y.c */
998 typedef struct ds1225y_t ds1225y_t;
999 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1000
1001 /* es1370.c */
1002 int es1370_init (PCIBus *bus, AudioState *s);
1003
1004 /* sb16.c */
1005 int SB16_init (AudioState *s, qemu_irq *pic);
1006
1007 /* adlib.c */
1008 int Adlib_init (AudioState *s, qemu_irq *pic);
1009
1010 /* gus.c */
1011 int GUS_init (AudioState *s, qemu_irq *pic);
1012
1013 /* dma.c */
1014 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1015 int DMA_get_channel_mode (int nchan);
1016 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1017 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1018 void DMA_hold_DREQ (int nchan);
1019 void DMA_release_DREQ (int nchan);
1020 void DMA_schedule(int nchan);
1021 void DMA_run (void);
1022 void DMA_init (int high_page_enable);
1023 void DMA_register_channel (int nchan,
1024 DMA_transfer_handler transfer_handler,
1025 void *opaque);
1026 /* fdc.c */
1027 #define MAX_FD 2
1028 extern BlockDriverState *fd_table[MAX_FD];
1029
1030 typedef struct fdctrl_t fdctrl_t;
1031
1032 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1033 target_phys_addr_t io_base,
1034 BlockDriverState **fds);
1035 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1036
1037 /* eepro100.c */
1038
1039 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1040 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1041 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1042
1043 /* ne2000.c */
1044
1045 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1046 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1047
1048 /* rtl8139.c */
1049
1050 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1051
1052 /* pcnet.c */
1053
1054 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1055 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1056 qemu_irq irq);
1057
1058 /* vmmouse.c */
1059 void *vmmouse_init(void *m);
1060
1061 /* pckbd.c */
1062
1063 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1064 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1065 target_phys_addr_t base, int it_shift);
1066
1067 /* mc146818rtc.c */
1068
1069 typedef struct RTCState RTCState;
1070
1071 RTCState *rtc_init(int base, qemu_irq irq);
1072 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1073 void rtc_set_memory(RTCState *s, int addr, int val);
1074 void rtc_set_date(RTCState *s, const struct tm *tm);
1075
1076 /* serial.c */
1077
1078 typedef struct SerialState SerialState;
1079 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1080 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1081 qemu_irq irq, CharDriverState *chr,
1082 int ioregister);
1083 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1084 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1085 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1086 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1087 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1088 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1089
1090 /* parallel.c */
1091
1092 typedef struct ParallelState ParallelState;
1093 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1094 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1095
1096 /* i8259.c */
1097
1098 typedef struct PicState2 PicState2;
1099 extern PicState2 *isa_pic;
1100 void pic_set_irq(int irq, int level);
1101 void pic_set_irq_new(void *opaque, int irq, int level);
1102 qemu_irq *i8259_init(qemu_irq parent_irq);
1103 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1104 void *alt_irq_opaque);
1105 int pic_read_irq(PicState2 *s);
1106 void pic_update_irq(PicState2 *s);
1107 uint32_t pic_intack_read(PicState2 *s);
1108 void pic_info(void);
1109 void irq_info(void);
1110
1111 /* APIC */
1112 typedef struct IOAPICState IOAPICState;
1113
1114 int apic_init(CPUState *env);
1115 int apic_get_interrupt(CPUState *env);
1116 IOAPICState *ioapic_init(void);
1117 void ioapic_set_irq(void *opaque, int vector, int level);
1118
1119 /* i8254.c */
1120
1121 #define PIT_FREQ 1193182
1122
1123 typedef struct PITState PITState;
1124
1125 PITState *pit_init(int base, qemu_irq irq);
1126 void pit_set_gate(PITState *pit, int channel, int val);
1127 int pit_get_gate(PITState *pit, int channel);
1128 int pit_get_initial_count(PITState *pit, int channel);
1129 int pit_get_mode(PITState *pit, int channel);
1130 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1131
1132 /* jazz_led.c */
1133 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1134
1135 /* pcspk.c */
1136 void pcspk_init(PITState *);
1137 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1138
1139 #include "hw/i2c.h"
1140
1141 #include "hw/smbus.h"
1142
1143 /* acpi.c */
1144 extern int acpi_enabled;
1145 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1146 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1147 void acpi_bios_init(void);
1148
1149 /* pc.c */
1150 extern QEMUMachine pc_machine;
1151 extern QEMUMachine isapc_machine;
1152 extern int fd_bootchk;
1153
1154 void ioport_set_a20(int enable);
1155 int ioport_get_a20(void);
1156
1157 /* ppc.c */
1158 extern QEMUMachine prep_machine;
1159 extern QEMUMachine core99_machine;
1160 extern QEMUMachine heathrow_machine;
1161 extern QEMUMachine ref405ep_machine;
1162 extern QEMUMachine taihu_machine;
1163
1164 /* mips_r4k.c */
1165 extern QEMUMachine mips_machine;
1166
1167 /* mips_malta.c */
1168 extern QEMUMachine mips_malta_machine;
1169
1170 /* mips_int.c */
1171 extern void cpu_mips_irq_init_cpu(CPUState *env);
1172
1173 /* mips_pica61.c */
1174 extern QEMUMachine mips_pica61_machine;
1175
1176 /* mips_timer.c */
1177 extern void cpu_mips_clock_init(CPUState *);
1178 extern void cpu_mips_irqctrl_init (void);
1179
1180 /* shix.c */
1181 extern QEMUMachine shix_machine;
1182
1183 #ifdef TARGET_PPC
1184 /* PowerPC hardware exceptions management helpers */
1185 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1186 typedef struct clk_setup_t clk_setup_t;
1187 struct clk_setup_t {
1188 clk_setup_cb cb;
1189 void *opaque;
1190 };
1191 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1192 {
1193 if (clk->cb != NULL)
1194 (*clk->cb)(clk->opaque, freq);
1195 }
1196
1197 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1198 /* Embedded PowerPC DCR management */
1199 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1200 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1201 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1202 int (*dcr_write_error)(int dcrn));
1203 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1204 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1205 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1206 /* Embedded PowerPC reset */
1207 void ppc40x_core_reset (CPUState *env);
1208 void ppc40x_chip_reset (CPUState *env);
1209 void ppc40x_system_reset (CPUState *env);
1210 #endif
1211 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1212
1213 extern CPUWriteMemoryFunc *PPC_io_write[];
1214 extern CPUReadMemoryFunc *PPC_io_read[];
1215 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1216
1217 /* sun4m.c */
1218 extern QEMUMachine ss5_machine, ss10_machine;
1219
1220 /* iommu.c */
1221 void *iommu_init(target_phys_addr_t addr);
1222 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1223 uint8_t *buf, int len, int is_write);
1224 static inline void sparc_iommu_memory_read(void *opaque,
1225 target_phys_addr_t addr,
1226 uint8_t *buf, int len)
1227 {
1228 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1229 }
1230
1231 static inline void sparc_iommu_memory_write(void *opaque,
1232 target_phys_addr_t addr,
1233 uint8_t *buf, int len)
1234 {
1235 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1236 }
1237
1238 /* tcx.c */
1239 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1240 unsigned long vram_offset, int vram_size, int width, int height,
1241 int depth);
1242
1243 /* slavio_intctl.c */
1244 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1245 const uint32_t *intbit_to_level,
1246 qemu_irq **irq, qemu_irq **cpu_irq,
1247 qemu_irq **parent_irq, unsigned int cputimer);
1248 void slavio_pic_info(void *opaque);
1249 void slavio_irq_info(void *opaque);
1250
1251 /* loader.c */
1252 int get_image_size(const char *filename);
1253 int load_image(const char *filename, uint8_t *addr);
1254 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1255 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1256 int load_aout(const char *filename, uint8_t *addr);
1257 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1258
1259 /* slavio_timer.c */
1260 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1261
1262 /* slavio_serial.c */
1263 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1264 CharDriverState *chr1, CharDriverState *chr2);
1265 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1266
1267 /* slavio_misc.c */
1268 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1269 qemu_irq irq);
1270 void slavio_set_power_fail(void *opaque, int power_failing);
1271
1272 /* esp.c */
1273 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1274 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1275 void *dma_opaque, qemu_irq irq);
1276
1277 /* sparc32_dma.c */
1278 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1279 void *iommu, qemu_irq **dev_irq);
1280 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1281 uint8_t *buf, int len, int do_bswap);
1282 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1283 uint8_t *buf, int len, int do_bswap);
1284 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1285 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1286 void sparc32_dma_set_reset_data(void *opaque, void (*dev_reset)(void *opaque),
1287 void *dev_opaque);
1288
1289 /* cs4231.c */
1290 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1291
1292 /* sun4u.c */
1293 extern QEMUMachine sun4u_machine;
1294
1295 /* NVRAM helpers */
1296 #include "hw/m48t59.h"
1297
1298 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1299 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1300 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1301 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1302 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1303 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1304 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1305 const unsigned char *str, uint32_t max);
1306 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1307 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1308 uint32_t start, uint32_t count);
1309 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1310 const unsigned char *arch,
1311 uint32_t RAM_size, int boot_device,
1312 uint32_t kernel_image, uint32_t kernel_size,
1313 const char *cmdline,
1314 uint32_t initrd_image, uint32_t initrd_size,
1315 uint32_t NVRAM_image,
1316 int width, int height, int depth);
1317
1318 /* adb.c */
1319
1320 #define MAX_ADB_DEVICES 16
1321
1322 #define ADB_MAX_OUT_LEN 16
1323
1324 typedef struct ADBDevice ADBDevice;
1325
1326 /* buf = NULL means polling */
1327 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1328 const uint8_t *buf, int len);
1329 typedef int ADBDeviceReset(ADBDevice *d);
1330
1331 struct ADBDevice {
1332 struct ADBBusState *bus;
1333 int devaddr;
1334 int handler;
1335 ADBDeviceRequest *devreq;
1336 ADBDeviceReset *devreset;
1337 void *opaque;
1338 };
1339
1340 typedef struct ADBBusState {
1341 ADBDevice devices[MAX_ADB_DEVICES];
1342 int nb_devices;
1343 int poll_index;
1344 } ADBBusState;
1345
1346 int adb_request(ADBBusState *s, uint8_t *buf_out,
1347 const uint8_t *buf, int len);
1348 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1349
1350 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1351 ADBDeviceRequest *devreq,
1352 ADBDeviceReset *devreset,
1353 void *opaque);
1354 void adb_kbd_init(ADBBusState *bus);
1355 void adb_mouse_init(ADBBusState *bus);
1356
1357 /* cuda.c */
1358
1359 extern ADBBusState adb_bus;
1360 int cuda_init(qemu_irq irq);
1361
1362 #include "hw/usb.h"
1363
1364 /* usb ports of the VM */
1365
1366 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1367 usb_attachfn attach);
1368
1369 #define VM_USB_HUB_SIZE 8
1370
1371 void do_usb_add(const char *devname);
1372 void do_usb_del(const char *devname);
1373 void usb_info(void);
1374
1375 /* scsi-disk.c */
1376 enum scsi_reason {
1377 SCSI_REASON_DONE, /* Command complete. */
1378 SCSI_REASON_DATA /* Transfer complete, more data required. */
1379 };
1380
1381 typedef struct SCSIDevice SCSIDevice;
1382 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1383 uint32_t arg);
1384
1385 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1386 int tcq,
1387 scsi_completionfn completion,
1388 void *opaque);
1389 void scsi_disk_destroy(SCSIDevice *s);
1390
1391 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1392 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1393 layer the completion routine may be called directly by
1394 scsi_{read,write}_data. */
1395 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1396 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1397 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1398 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1399
1400 /* lsi53c895a.c */
1401 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1402 void *lsi_scsi_init(PCIBus *bus, int devfn);
1403
1404 /* integratorcp.c */
1405 extern QEMUMachine integratorcp_machine;
1406
1407 /* versatilepb.c */
1408 extern QEMUMachine versatilepb_machine;
1409 extern QEMUMachine versatileab_machine;
1410
1411 /* realview.c */
1412 extern QEMUMachine realview_machine;
1413
1414 /* spitz.c */
1415 extern QEMUMachine akitapda_machine;
1416 extern QEMUMachine spitzpda_machine;
1417 extern QEMUMachine borzoipda_machine;
1418 extern QEMUMachine terrierpda_machine;
1419
1420 /* palm.c */
1421 extern QEMUMachine palmte_machine;
1422
1423 /* ps2.c */
1424 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1425 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1426 void ps2_write_mouse(void *, int val);
1427 void ps2_write_keyboard(void *, int val);
1428 uint32_t ps2_read_data(void *);
1429 void ps2_queue(void *, int b);
1430 void ps2_keyboard_set_translation(void *opaque, int mode);
1431 void ps2_mouse_fake_event(void *opaque);
1432
1433 /* smc91c111.c */
1434 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1435
1436 /* pl031.c */
1437 void pl031_init(uint32_t base, qemu_irq irq);
1438
1439 /* pl110.c */
1440 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1441
1442 /* pl011.c */
1443 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1444
1445 /* pl050.c */
1446 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1447
1448 /* pl080.c */
1449 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1450
1451 /* pl181.c */
1452 void pl181_init(uint32_t base, BlockDriverState *bd,
1453 qemu_irq irq0, qemu_irq irq1);
1454
1455 /* pl190.c */
1456 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1457
1458 /* arm-timer.c */
1459 void sp804_init(uint32_t base, qemu_irq irq);
1460 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1461
1462 /* arm_sysctl.c */
1463 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1464
1465 /* arm_gic.c */
1466 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1467
1468 /* arm_boot.c */
1469
1470 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1471 const char *kernel_cmdline, const char *initrd_filename,
1472 int board_id, target_phys_addr_t loader_start);
1473
1474 /* sh7750.c */
1475 struct SH7750State;
1476
1477 struct SH7750State *sh7750_init(CPUState * cpu);
1478
1479 typedef struct {
1480 /* The callback will be triggered if any of the designated lines change */
1481 uint16_t portamask_trigger;
1482 uint16_t portbmask_trigger;
1483 /* Return 0 if no action was taken */
1484 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1485 uint16_t * periph_pdtra,
1486 uint16_t * periph_portdira,
1487 uint16_t * periph_pdtrb,
1488 uint16_t * periph_portdirb);
1489 } sh7750_io_device;
1490
1491 int sh7750_register_io_device(struct SH7750State *s,
1492 sh7750_io_device * device);
1493 /* tc58128.c */
1494 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1495
1496 /* NOR flash devices */
1497 #define MAX_PFLASH 4
1498 extern BlockDriverState *pflash_table[MAX_PFLASH];
1499 typedef struct pflash_t pflash_t;
1500
1501 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1502 BlockDriverState *bs,
1503 uint32_t sector_len, int nb_blocs, int width,
1504 uint16_t id0, uint16_t id1,
1505 uint16_t id2, uint16_t id3);
1506
1507 /* nand.c */
1508 struct nand_flash_s;
1509 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1510 void nand_done(struct nand_flash_s *s);
1511 void nand_setpins(struct nand_flash_s *s,
1512 int cle, int ale, int ce, int wp, int gnd);
1513 void nand_getpins(struct nand_flash_s *s, int *rb);
1514 void nand_setio(struct nand_flash_s *s, uint8_t value);
1515 uint8_t nand_getio(struct nand_flash_s *s);
1516
1517 #define NAND_MFR_TOSHIBA 0x98
1518 #define NAND_MFR_SAMSUNG 0xec
1519 #define NAND_MFR_FUJITSU 0x04
1520 #define NAND_MFR_NATIONAL 0x8f
1521 #define NAND_MFR_RENESAS 0x07
1522 #define NAND_MFR_STMICRO 0x20
1523 #define NAND_MFR_HYNIX 0xad
1524 #define NAND_MFR_MICRON 0x2c
1525
1526 #include "ecc.h"
1527
1528 /* GPIO */
1529 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1530
1531 /* ads7846.c */
1532 struct ads7846_state_s;
1533 uint32_t ads7846_read(void *opaque);
1534 void ads7846_write(void *opaque, uint32_t value);
1535 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1536
1537 /* max111x.c */
1538 struct max111x_s;
1539 uint32_t max111x_read(void *opaque);
1540 void max111x_write(void *opaque, uint32_t value);
1541 struct max111x_s *max1110_init(qemu_irq cb);
1542 struct max111x_s *max1111_init(qemu_irq cb);
1543 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1544
1545 /* PCMCIA/Cardbus */
1546
1547 struct pcmcia_socket_s {
1548 qemu_irq irq;
1549 int attached;
1550 const char *slot_string;
1551 const char *card_string;
1552 };
1553
1554 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1555 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1556 void pcmcia_info(void);
1557
1558 struct pcmcia_card_s {
1559 void *state;
1560 struct pcmcia_socket_s *slot;
1561 int (*attach)(void *state);
1562 int (*detach)(void *state);
1563 const uint8_t *cis;
1564 int cis_len;
1565
1566 /* Only valid if attached */
1567 uint8_t (*attr_read)(void *state, uint32_t address);
1568 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1569 uint16_t (*common_read)(void *state, uint32_t address);
1570 void (*common_write)(void *state, uint32_t address, uint16_t value);
1571 uint16_t (*io_read)(void *state, uint32_t address);
1572 void (*io_write)(void *state, uint32_t address, uint16_t value);
1573 };
1574
1575 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1576 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1577 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1578 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1579 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1580 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1581 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1582 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1583 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1584 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1585 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1586 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1587 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1588 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1589 #define CISTPL_END 0xff /* Tuple End */
1590 #define CISTPL_ENDMARK 0xff
1591
1592 /* dscm1xxxx.c */
1593 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1594
1595 /* ptimer.c */
1596 typedef struct ptimer_state ptimer_state;
1597 typedef void (*ptimer_cb)(void *opaque);
1598
1599 ptimer_state *ptimer_init(QEMUBH *bh);
1600 void ptimer_set_period(ptimer_state *s, int64_t period);
1601 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1602 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1603 uint64_t ptimer_get_count(ptimer_state *s);
1604 void ptimer_set_count(ptimer_state *s, uint64_t count);
1605 void ptimer_run(ptimer_state *s, int oneshot);
1606 void ptimer_stop(ptimer_state *s);
1607 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1608 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1609
1610 #include "hw/pxa.h"
1611
1612 #include "hw/omap.h"
1613
1614 /* mcf_uart.c */
1615 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1616 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1617 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1618 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1619 CharDriverState *chr);
1620
1621 /* mcf_intc.c */
1622 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1623
1624 /* mcf_fec.c */
1625 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1626
1627 /* mcf5206.c */
1628 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1629
1630 /* an5206.c */
1631 extern QEMUMachine an5206_machine;
1632
1633 /* mcf5208.c */
1634 extern QEMUMachine mcf5208evb_machine;
1635
1636 #include "gdbstub.h"
1637
1638 #endif /* defined(QEMU_TOOL) */
1639
1640 /* monitor.c */
1641 void monitor_init(CharDriverState *hd, int show_banner);
1642 void term_puts(const char *str);
1643 void term_vprintf(const char *fmt, va_list ap);
1644 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1645 void term_print_filename(const char *filename);
1646 void term_flush(void);
1647 void term_print_help(void);
1648 void monitor_readline(const char *prompt, int is_password,
1649 char *buf, int buf_size);
1650
1651 /* readline.c */
1652 typedef void ReadLineFunc(void *opaque, const char *str);
1653
1654 extern int completion_index;
1655 void add_completion(const char *str);
1656 void readline_handle_byte(int ch);
1657 void readline_find_completion(const char *cmdline);
1658 const char *readline_get_history(unsigned int index);
1659 void readline_start(const char *prompt, int is_password,
1660 ReadLineFunc *readline_func, void *opaque);
1661
1662 void kqemu_record_dump(void);
1663
1664 #endif /* VL_H */
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