4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* i82731AB (PIIX4) compatible power management function */
24 #define PM_FREQ 3579545
26 #define ACPI_DBG_IO_ADDR 0xb044
27 #define SMB_IO_BASE 0xb100
29 typedef struct PIIX4PMState
{
37 int64_t tmr_overflow_time
;
38 SMBusDevice
*smb_dev
[128];
49 #define RTC_EN (1 << 10)
50 #define PWRBTN_EN (1 << 8)
51 #define GBL_EN (1 << 5)
52 #define TMROF_EN (1 << 0)
54 #define SCI_EN (1 << 0)
56 #define SUS_EN (1 << 13)
58 #define SMBHSTSTS 0x00
59 #define SMBHSTCNT 0x02
60 #define SMBHSTCMD 0x03
61 #define SMBHSTADD 0x04
62 #define SMBHSTDAT0 0x05
63 #define SMBHSTDAT1 0x06
64 #define SMBBLKDAT 0x07
66 /* Note: only used for piix4_smbus_register_device */
67 static PIIX4PMState
*piix4_pm_state
;
69 static uint32_t get_pmtmr(PIIX4PMState
*s
)
72 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
76 static int get_pmsts(PIIX4PMState
*s
)
81 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
82 if (d
>= s
->tmr_overflow_time
)
87 static void pm_update_sci(PIIX4PMState
*s
)
93 sci_level
= (((pmsts
& s
->pmen
) &
94 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
95 qemu_set_irq(s
->dev
.irq
[0], sci_level
);
96 /* schedule a timer interruption if needed */
97 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
98 expire_time
= muldiv64(s
->tmr_overflow_time
, ticks_per_sec
, PM_FREQ
);
99 qemu_mod_timer(s
->tmr_timer
, expire_time
);
101 qemu_del_timer(s
->tmr_timer
);
105 static void pm_tmr_timer(void *opaque
)
107 PIIX4PMState
*s
= opaque
;
111 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
113 PIIX4PMState
*s
= opaque
;
120 pmsts
= get_pmsts(s
);
121 if (pmsts
& val
& TMROF_EN
) {
122 /* if TMRSTS is reset, then compute the new overflow time */
123 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
124 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
137 s
->pmcntrl
= val
& ~(SUS_EN
);
139 /* change suspend type */
140 sus_typ
= (val
>> 10) & 3;
142 case 0: /* soft power off */
143 qemu_system_shutdown_request();
155 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
159 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
161 PIIX4PMState
*s
= opaque
;
180 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
185 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
187 // PIIX4PMState *s = opaque;
190 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
194 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
196 PIIX4PMState
*s
= opaque
;
209 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
214 static void pm_smi_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
216 PIIX4PMState
*s
= opaque
;
219 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr
, val
);
223 if (s
->dev
.config
[0x5b] & (1 << 1)) {
224 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
231 static uint32_t pm_smi_readb(void *opaque
, uint32_t addr
)
233 PIIX4PMState
*s
= opaque
;
243 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr
, val
);
248 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
251 printf("ACPI: DBG: 0x%08x\n", val
);
255 static void smb_transaction(PIIX4PMState
*s
)
257 uint8_t prot
= (s
->smb_ctl
>> 2) & 0x07;
258 uint8_t read
= s
->smb_addr
& 0x01;
259 uint8_t cmd
= s
->smb_cmd
;
260 uint8_t addr
= s
->smb_addr
>> 1;
261 SMBusDevice
*dev
= s
->smb_dev
[addr
];
264 printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr
, prot
);
266 if (!dev
) goto error
;
270 if (!dev
->quick_cmd
) goto error
;
271 (*dev
->quick_cmd
)(dev
, read
);
275 if (!dev
->receive_byte
) goto error
;
276 s
->smb_data0
= (*dev
->receive_byte
)(dev
);
279 if (!dev
->send_byte
) goto error
;
280 (*dev
->send_byte
)(dev
, cmd
);
285 if (!dev
->read_byte
) goto error
;
286 s
->smb_data0
= (*dev
->read_byte
)(dev
, cmd
);
289 if (!dev
->write_byte
) goto error
;
290 (*dev
->write_byte
)(dev
, cmd
, s
->smb_data0
);
296 if (!dev
->read_word
) goto error
;
297 val
= (*dev
->read_word
)(dev
, cmd
);
299 s
->smb_data1
= val
>> 8;
302 if (!dev
->write_word
) goto error
;
303 (*dev
->write_word
)(dev
, cmd
, (s
->smb_data1
<< 8) | s
->smb_data0
);
308 if (!dev
->read_block
) goto error
;
309 s
->smb_data0
= (*dev
->read_block
)(dev
, cmd
, s
->smb_data
);
312 if (!dev
->write_block
) goto error
;
313 (*dev
->write_block
)(dev
, cmd
, s
->smb_data0
, s
->smb_data
);
325 static void smb_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
327 PIIX4PMState
*s
= opaque
;
330 printf("SMB writeb port=0x%04x val=0x%02x\n", addr
, val
);
355 s
->smb_data
[s
->smb_index
++] = val
;
356 if (s
->smb_index
> 31)
364 static uint32_t smb_ioport_readb(void *opaque
, uint32_t addr
)
366 PIIX4PMState
*s
= opaque
;
376 val
= s
->smb_ctl
& 0x1f;
391 val
= s
->smb_data
[s
->smb_index
++];
392 if (s
->smb_index
> 31)
400 printf("SMB readb port=0x%04x val=0x%02x\n", addr
, val
);
405 static void pm_io_space_update(PIIX4PMState
*s
)
409 if (s
->dev
.config
[0x80] & 1) {
410 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
411 pm_io_base
&= 0xfffe;
413 /* XXX: need to improve memory and ioport allocation */
415 printf("PM: mapping to 0x%x\n", pm_io_base
);
417 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
418 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
419 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
420 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
424 static void pm_write_config(PCIDevice
*d
,
425 uint32_t address
, uint32_t val
, int len
)
427 pci_default_write_config(d
, address
, val
, len
);
429 pm_io_space_update((PIIX4PMState
*)d
);
432 static void pm_save(QEMUFile
* f
,void *opaque
)
434 PIIX4PMState
*s
= opaque
;
436 pci_device_save(&s
->dev
, f
);
438 qemu_put_be16s(f
, &s
->pmsts
);
439 qemu_put_be16s(f
, &s
->pmen
);
440 qemu_put_be16s(f
, &s
->pmcntrl
);
441 qemu_put_8s(f
, &s
->apmc
);
442 qemu_put_8s(f
, &s
->apms
);
443 qemu_put_timer(f
, s
->tmr_timer
);
444 qemu_put_be64s(f
, &s
->tmr_overflow_time
);
447 static int pm_load(QEMUFile
* f
,void* opaque
,int version_id
)
449 PIIX4PMState
*s
= opaque
;
455 ret
= pci_device_load(&s
->dev
, f
);
459 qemu_get_be16s(f
, &s
->pmsts
);
460 qemu_get_be16s(f
, &s
->pmen
);
461 qemu_get_be16s(f
, &s
->pmcntrl
);
462 qemu_get_8s(f
, &s
->apmc
);
463 qemu_get_8s(f
, &s
->apms
);
464 qemu_get_timer(f
, s
->tmr_timer
);
465 qemu_get_be64s(f
, &s
->tmr_overflow_time
);
467 pm_io_space_update(s
);
472 void piix4_pm_init(PCIBus
*bus
, int devfn
)
476 uint32_t smb_io_base
;
478 s
= (PIIX4PMState
*)pci_register_device(bus
,
479 "PM", sizeof(PIIX4PMState
),
480 devfn
, NULL
, pm_write_config
);
481 pci_conf
= s
->dev
.config
;
482 pci_conf
[0x00] = 0x86;
483 pci_conf
[0x01] = 0x80;
484 pci_conf
[0x02] = 0x13;
485 pci_conf
[0x03] = 0x71;
486 pci_conf
[0x08] = 0x00; // revision number
487 pci_conf
[0x09] = 0x00;
488 pci_conf
[0x0a] = 0x80; // other bridge device
489 pci_conf
[0x0b] = 0x06; // bridge device
490 pci_conf
[0x0e] = 0x00; // header_type
491 pci_conf
[0x3d] = 0x01; // interrupt pin 1
493 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
495 register_ioport_write(0xb2, 2, 1, pm_smi_writeb
, s
);
496 register_ioport_read(0xb2, 2, 1, pm_smi_readb
, s
);
498 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
500 /* XXX: which specification is used ? The i82731AB has different
502 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
503 pci_conf
[0x63] = 0x60;
504 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
505 (serial_hds
[1] != NULL
? 0x90 : 0);
507 smb_io_base
= SMB_IO_BASE
;
508 pci_conf
[0x90] = smb_io_base
| 1;
509 pci_conf
[0x91] = smb_io_base
>> 8;
510 pci_conf
[0xd2] = 0x09;
511 register_ioport_write(smb_io_base
, 64, 1, smb_ioport_writeb
, s
);
512 register_ioport_read(smb_io_base
, 64, 1, smb_ioport_readb
, s
);
514 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
516 register_savevm("piix4_pm", 0, 1, pm_save
, pm_load
, s
);
520 void piix4_smbus_register_device(SMBusDevice
*dev
, uint8_t addr
)
522 piix4_pm_state
->smb_dev
[addr
] = dev
;