2 * QEMU System Emulator header
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 /* we put basic includes here to avoid repeating them in device drivers */
49 #define ENOMEDIUM ENODEV
55 #define lseek _lseeki64
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
61 static inline char *realpath(const char *path
, char *resolved_path
)
63 _fullpath(resolved_path
, path
, _MAX_PATH
);
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
84 #include "audio/audio.h"
87 #endif /* !defined(QEMU_TOOL) */
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
104 void pstrcpy(char *buf
, int buf_size
, const char *str
);
105 char *pstrcat(char *buf
, int buf_size
, const char *s
);
106 int strstart(const char *str
, const char *val
, const char **ptr
);
107 int stristart(const char *str
, const char *val
, const char **ptr
);
110 uint64_t muldiv64(uint64_t a
, uint32_t b
, uint32_t c
);
112 void hw_error(const char *fmt
, ...);
114 extern const char *bios_dir
;
116 extern int vm_running
;
117 extern const char *qemu_name
;
119 typedef struct vm_change_state_entry VMChangeStateEntry
;
120 typedef void VMChangeStateHandler(void *opaque
, int running
);
121 typedef void VMStopHandler(void *opaque
, int reason
);
123 VMChangeStateEntry
*qemu_add_vm_change_state_handler(VMChangeStateHandler
*cb
,
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry
*e
);
127 int qemu_add_vm_stop_handler(VMStopHandler
*cb
, void *opaque
);
128 void qemu_del_vm_stop_handler(VMStopHandler
*cb
, void *opaque
);
131 void vm_stop(int reason
);
133 typedef void QEMUResetHandler(void *opaque
);
135 void qemu_register_reset(QEMUResetHandler
*func
, void *opaque
);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
143 void qemu_system_powerdown(void);
146 void main_loop_wait(int timeout
);
149 extern int bios_size
;
151 extern int cirrus_vga_enabled
;
152 extern int vmsvga_enabled
;
153 extern int graphic_width
;
154 extern int graphic_height
;
155 extern int graphic_depth
;
156 extern const char *keyboard_layout
;
157 extern int kqemu_allowed
;
158 extern int win2k_install_hack
;
159 extern int usb_enabled
;
161 extern int cursor_hide
;
162 extern int graphic_rotate
;
164 extern int semihosting_enabled
;
165 extern int autostart
;
166 extern const char *bootp_filename
;
168 #define MAX_OPTION_ROMS 16
169 extern const char *option_rom
[MAX_OPTION_ROMS
];
170 extern int nb_option_roms
;
173 #define MAX_PROM_ENVS 128
174 extern const char *prom_envs
[MAX_PROM_ENVS
];
175 extern unsigned int nb_prom_envs
;
178 /* XXX: make it dynamic */
179 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
180 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
181 #define BIOS_SIZE ((512 + 32) * 1024)
182 #elif defined(TARGET_MIPS)
183 #define BIOS_SIZE (4 * 1024 * 1024)
186 /* keyboard/mouse support */
188 #define MOUSE_EVENT_LBUTTON 0x01
189 #define MOUSE_EVENT_RBUTTON 0x02
190 #define MOUSE_EVENT_MBUTTON 0x04
192 typedef void QEMUPutKBDEvent(void *opaque
, int keycode
);
193 typedef void QEMUPutMouseEvent(void *opaque
, int dx
, int dy
, int dz
, int buttons_state
);
195 typedef struct QEMUPutMouseEntry
{
196 QEMUPutMouseEvent
*qemu_put_mouse_event
;
197 void *qemu_put_mouse_event_opaque
;
198 int qemu_put_mouse_event_absolute
;
199 char *qemu_put_mouse_event_name
;
201 /* used internally by qemu for handling mice */
202 struct QEMUPutMouseEntry
*next
;
205 void qemu_add_kbd_event_handler(QEMUPutKBDEvent
*func
, void *opaque
);
206 QEMUPutMouseEntry
*qemu_add_mouse_event_handler(QEMUPutMouseEvent
*func
,
207 void *opaque
, int absolute
,
209 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry
*entry
);
211 void kbd_put_keycode(int keycode
);
212 void kbd_mouse_event(int dx
, int dy
, int dz
, int buttons_state
);
213 int kbd_mouse_is_absolute(void);
215 void do_info_mice(void);
216 void do_mouse_set(int index
);
218 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
220 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
221 #define QEMU_KEY_BACKSPACE 0x007f
222 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
223 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
224 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
225 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
226 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
227 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
228 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
229 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
230 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
232 #define QEMU_KEY_CTRL_UP 0xe400
233 #define QEMU_KEY_CTRL_DOWN 0xe401
234 #define QEMU_KEY_CTRL_LEFT 0xe402
235 #define QEMU_KEY_CTRL_RIGHT 0xe403
236 #define QEMU_KEY_CTRL_HOME 0xe404
237 #define QEMU_KEY_CTRL_END 0xe405
238 #define QEMU_KEY_CTRL_PAGEUP 0xe406
239 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
241 void kbd_put_keysym(int keysym
);
243 /* async I/O support */
245 typedef void IOReadHandler(void *opaque
, const uint8_t *buf
, int size
);
246 typedef int IOCanRWHandler(void *opaque
);
247 typedef void IOHandler(void *opaque
);
249 int qemu_set_fd_handler2(int fd
,
250 IOCanRWHandler
*fd_read_poll
,
254 int qemu_set_fd_handler(int fd
,
259 /* Polling handling */
261 /* return TRUE if no sleep should be done afterwards */
262 typedef int PollingFunc(void *opaque
);
264 int qemu_add_polling_cb(PollingFunc
*func
, void *opaque
);
265 void qemu_del_polling_cb(PollingFunc
*func
, void *opaque
);
268 /* Wait objects handling */
269 typedef void WaitObjectFunc(void *opaque
);
271 int qemu_add_wait_object(HANDLE handle
, WaitObjectFunc
*func
, void *opaque
);
272 void qemu_del_wait_object(HANDLE handle
, WaitObjectFunc
*func
, void *opaque
);
275 typedef struct QEMUBH QEMUBH
;
277 /* character device */
279 #define CHR_EVENT_BREAK 0 /* serial break char */
280 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
281 #define CHR_EVENT_RESET 2 /* new connection established */
284 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
290 } QEMUSerialSetParams
;
292 #define CHR_IOCTL_SERIAL_SET_BREAK 2
294 #define CHR_IOCTL_PP_READ_DATA 3
295 #define CHR_IOCTL_PP_WRITE_DATA 4
296 #define CHR_IOCTL_PP_READ_CONTROL 5
297 #define CHR_IOCTL_PP_WRITE_CONTROL 6
298 #define CHR_IOCTL_PP_READ_STATUS 7
299 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
300 #define CHR_IOCTL_PP_EPP_READ 9
301 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
302 #define CHR_IOCTL_PP_EPP_WRITE 11
304 typedef void IOEventHandler(void *opaque
, int event
);
306 typedef struct CharDriverState
{
307 int (*chr_write
)(struct CharDriverState
*s
, const uint8_t *buf
, int len
);
308 void (*chr_update_read_handler
)(struct CharDriverState
*s
);
309 int (*chr_ioctl
)(struct CharDriverState
*s
, int cmd
, void *arg
);
310 IOEventHandler
*chr_event
;
311 IOCanRWHandler
*chr_can_read
;
312 IOReadHandler
*chr_read
;
313 void *handler_opaque
;
314 void (*chr_send_event
)(struct CharDriverState
*chr
, int event
);
315 void (*chr_close
)(struct CharDriverState
*chr
);
321 CharDriverState
*qemu_chr_open(const char *filename
);
322 void qemu_chr_printf(CharDriverState
*s
, const char *fmt
, ...);
323 int qemu_chr_write(CharDriverState
*s
, const uint8_t *buf
, int len
);
324 void qemu_chr_send_event(CharDriverState
*s
, int event
);
325 void qemu_chr_add_handlers(CharDriverState
*s
,
326 IOCanRWHandler
*fd_can_read
,
327 IOReadHandler
*fd_read
,
328 IOEventHandler
*fd_event
,
330 int qemu_chr_ioctl(CharDriverState
*s
, int cmd
, void *arg
);
331 void qemu_chr_reset(CharDriverState
*s
);
332 int qemu_chr_can_read(CharDriverState
*s
);
333 void qemu_chr_read(CharDriverState
*s
, uint8_t *buf
, int len
);
337 typedef struct DisplayState DisplayState
;
338 typedef struct TextConsole TextConsole
;
340 typedef void (*vga_hw_update_ptr
)(void *);
341 typedef void (*vga_hw_invalidate_ptr
)(void *);
342 typedef void (*vga_hw_screen_dump_ptr
)(void *, const char *);
344 TextConsole
*graphic_console_init(DisplayState
*ds
, vga_hw_update_ptr update
,
345 vga_hw_invalidate_ptr invalidate
,
346 vga_hw_screen_dump_ptr screen_dump
,
348 void vga_hw_update(void);
349 void vga_hw_invalidate(void);
350 void vga_hw_screen_dump(const char *filename
);
352 int is_graphic_console(void);
353 CharDriverState
*text_console_init(DisplayState
*ds
);
354 void console_select(unsigned int index
);
358 #define MAX_SERIAL_PORTS 4
360 extern CharDriverState
*serial_hds
[MAX_SERIAL_PORTS
];
364 #define MAX_PARALLEL_PORTS 3
366 extern CharDriverState
*parallel_hds
[MAX_PARALLEL_PORTS
];
368 struct ParallelIOArg
{
375 typedef struct VLANClientState VLANClientState
;
377 struct VLANClientState
{
378 IOReadHandler
*fd_read
;
379 /* Packets may still be sent if this returns zero. It's used to
380 rate-limit the slirp code. */
381 IOCanRWHandler
*fd_can_read
;
383 struct VLANClientState
*next
;
384 struct VLANState
*vlan
;
388 typedef struct VLANState
{
390 VLANClientState
*first_client
;
391 struct VLANState
*next
;
392 unsigned int nb_guest_devs
, nb_host_devs
;
395 VLANState
*qemu_find_vlan(int id
);
396 VLANClientState
*qemu_new_vlan_client(VLANState
*vlan
,
397 IOReadHandler
*fd_read
,
398 IOCanRWHandler
*fd_can_read
,
400 int qemu_can_send_packet(VLANClientState
*vc
);
401 void qemu_send_packet(VLANClientState
*vc
, const uint8_t *buf
, int size
);
402 void qemu_handler_true(void *opaque
);
404 void do_info_network(void);
407 int tap_win32_init(VLANState
*vlan
, const char *ifname
);
413 typedef struct NICInfo
{
420 extern NICInfo nd_table
[MAX_NICS
];
424 typedef struct QEMUClock QEMUClock
;
425 typedef struct QEMUTimer QEMUTimer
;
426 typedef void QEMUTimerCB(void *opaque
);
428 /* The real time clock should be used only for stuff which does not
429 change the virtual machine state, as it is run even if the virtual
430 machine is stopped. The real time clock has a frequency of 1000
432 extern QEMUClock
*rt_clock
;
434 /* The virtual clock is only run during the emulation. It is stopped
435 when the virtual machine is stopped. Virtual timers use a high
436 precision clock, usually cpu cycles (use ticks_per_sec). */
437 extern QEMUClock
*vm_clock
;
439 int64_t qemu_get_clock(QEMUClock
*clock
);
441 QEMUTimer
*qemu_new_timer(QEMUClock
*clock
, QEMUTimerCB
*cb
, void *opaque
);
442 void qemu_free_timer(QEMUTimer
*ts
);
443 void qemu_del_timer(QEMUTimer
*ts
);
444 void qemu_mod_timer(QEMUTimer
*ts
, int64_t expire_time
);
445 int qemu_timer_pending(QEMUTimer
*ts
);
447 extern int64_t ticks_per_sec
;
448 extern int pit_min_timer_count
;
450 int64_t cpu_get_ticks(void);
451 void cpu_enable_ticks(void);
452 void cpu_disable_ticks(void);
456 typedef struct QEMUFile QEMUFile
;
458 QEMUFile
*qemu_fopen(const char *filename
, const char *mode
);
459 void qemu_fflush(QEMUFile
*f
);
460 void qemu_fclose(QEMUFile
*f
);
461 void qemu_put_buffer(QEMUFile
*f
, const uint8_t *buf
, int size
);
462 void qemu_put_byte(QEMUFile
*f
, int v
);
463 void qemu_put_be16(QEMUFile
*f
, unsigned int v
);
464 void qemu_put_be32(QEMUFile
*f
, unsigned int v
);
465 void qemu_put_be64(QEMUFile
*f
, uint64_t v
);
466 int qemu_get_buffer(QEMUFile
*f
, uint8_t *buf
, int size
);
467 int qemu_get_byte(QEMUFile
*f
);
468 unsigned int qemu_get_be16(QEMUFile
*f
);
469 unsigned int qemu_get_be32(QEMUFile
*f
);
470 uint64_t qemu_get_be64(QEMUFile
*f
);
472 static inline void qemu_put_be64s(QEMUFile
*f
, const uint64_t *pv
)
474 qemu_put_be64(f
, *pv
);
477 static inline void qemu_put_be32s(QEMUFile
*f
, const uint32_t *pv
)
479 qemu_put_be32(f
, *pv
);
482 static inline void qemu_put_be16s(QEMUFile
*f
, const uint16_t *pv
)
484 qemu_put_be16(f
, *pv
);
487 static inline void qemu_put_8s(QEMUFile
*f
, const uint8_t *pv
)
489 qemu_put_byte(f
, *pv
);
492 static inline void qemu_get_be64s(QEMUFile
*f
, uint64_t *pv
)
494 *pv
= qemu_get_be64(f
);
497 static inline void qemu_get_be32s(QEMUFile
*f
, uint32_t *pv
)
499 *pv
= qemu_get_be32(f
);
502 static inline void qemu_get_be16s(QEMUFile
*f
, uint16_t *pv
)
504 *pv
= qemu_get_be16(f
);
507 static inline void qemu_get_8s(QEMUFile
*f
, uint8_t *pv
)
509 *pv
= qemu_get_byte(f
);
512 #if TARGET_LONG_BITS == 64
513 #define qemu_put_betl qemu_put_be64
514 #define qemu_get_betl qemu_get_be64
515 #define qemu_put_betls qemu_put_be64s
516 #define qemu_get_betls qemu_get_be64s
518 #define qemu_put_betl qemu_put_be32
519 #define qemu_get_betl qemu_get_be32
520 #define qemu_put_betls qemu_put_be32s
521 #define qemu_get_betls qemu_get_be32s
524 int64_t qemu_ftell(QEMUFile
*f
);
525 int64_t qemu_fseek(QEMUFile
*f
, int64_t pos
, int whence
);
527 typedef void SaveStateHandler(QEMUFile
*f
, void *opaque
);
528 typedef int LoadStateHandler(QEMUFile
*f
, void *opaque
, int version_id
);
530 int register_savevm(const char *idstr
,
533 SaveStateHandler
*save_state
,
534 LoadStateHandler
*load_state
,
536 void qemu_get_timer(QEMUFile
*f
, QEMUTimer
*ts
);
537 void qemu_put_timer(QEMUFile
*f
, QEMUTimer
*ts
);
539 void cpu_save(QEMUFile
*f
, void *opaque
);
540 int cpu_load(QEMUFile
*f
, void *opaque
, int version_id
);
542 void do_savevm(const char *name
);
543 void do_loadvm(const char *name
);
544 void do_delvm(const char *name
);
545 void do_info_snapshots(void);
548 typedef void QEMUBHFunc(void *opaque
);
550 QEMUBH
*qemu_bh_new(QEMUBHFunc
*cb
, void *opaque
);
551 void qemu_bh_schedule(QEMUBH
*bh
);
552 void qemu_bh_cancel(QEMUBH
*bh
);
553 void qemu_bh_delete(QEMUBH
*bh
);
554 int qemu_bh_poll(void);
557 typedef struct BlockDriverState BlockDriverState
;
558 typedef struct BlockDriver BlockDriver
;
560 extern BlockDriver bdrv_raw
;
561 extern BlockDriver bdrv_host_device
;
562 extern BlockDriver bdrv_cow
;
563 extern BlockDriver bdrv_qcow
;
564 extern BlockDriver bdrv_vmdk
;
565 extern BlockDriver bdrv_cloop
;
566 extern BlockDriver bdrv_dmg
;
567 extern BlockDriver bdrv_bochs
;
568 extern BlockDriver bdrv_vpc
;
569 extern BlockDriver bdrv_vvfat
;
570 extern BlockDriver bdrv_qcow2
;
572 typedef struct BlockDriverInfo
{
573 /* in bytes, 0 if irrelevant */
575 /* offset at which the VM state can be saved (0 if not possible) */
576 int64_t vm_state_offset
;
579 typedef struct QEMUSnapshotInfo
{
580 char id_str
[128]; /* unique snapshot id */
581 /* the following fields are informative. They are not needed for
582 the consistency of the snapshot */
583 char name
[256]; /* user choosen name */
584 uint32_t vm_state_size
; /* VM state info size */
585 uint32_t date_sec
; /* UTC date of the snapshot */
587 uint64_t vm_clock_nsec
; /* VM clock relative to boot */
590 #define BDRV_O_RDONLY 0x0000
591 #define BDRV_O_RDWR 0x0002
592 #define BDRV_O_ACCESS 0x0003
593 #define BDRV_O_CREAT 0x0004 /* create an empty file */
594 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
595 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
596 use a disk image format on top of
600 void bdrv_init(void);
601 BlockDriver
*bdrv_find_format(const char *format_name
);
602 int bdrv_create(BlockDriver
*drv
,
603 const char *filename
, int64_t size_in_sectors
,
604 const char *backing_file
, int flags
);
605 BlockDriverState
*bdrv_new(const char *device_name
);
606 void bdrv_delete(BlockDriverState
*bs
);
607 int bdrv_file_open(BlockDriverState
**pbs
, const char *filename
, int flags
);
608 int bdrv_open(BlockDriverState
*bs
, const char *filename
, int flags
);
609 int bdrv_open2(BlockDriverState
*bs
, const char *filename
, int flags
,
611 void bdrv_close(BlockDriverState
*bs
);
612 int bdrv_read(BlockDriverState
*bs
, int64_t sector_num
,
613 uint8_t *buf
, int nb_sectors
);
614 int bdrv_write(BlockDriverState
*bs
, int64_t sector_num
,
615 const uint8_t *buf
, int nb_sectors
);
616 int bdrv_pread(BlockDriverState
*bs
, int64_t offset
,
617 void *buf
, int count
);
618 int bdrv_pwrite(BlockDriverState
*bs
, int64_t offset
,
619 const void *buf
, int count
);
620 int bdrv_truncate(BlockDriverState
*bs
, int64_t offset
);
621 int64_t bdrv_getlength(BlockDriverState
*bs
);
622 void bdrv_get_geometry(BlockDriverState
*bs
, int64_t *nb_sectors_ptr
);
623 int bdrv_commit(BlockDriverState
*bs
);
624 void bdrv_set_boot_sector(BlockDriverState
*bs
, const uint8_t *data
, int size
);
625 /* async block I/O */
626 typedef struct BlockDriverAIOCB BlockDriverAIOCB
;
627 typedef void BlockDriverCompletionFunc(void *opaque
, int ret
);
629 BlockDriverAIOCB
*bdrv_aio_read(BlockDriverState
*bs
, int64_t sector_num
,
630 uint8_t *buf
, int nb_sectors
,
631 BlockDriverCompletionFunc
*cb
, void *opaque
);
632 BlockDriverAIOCB
*bdrv_aio_write(BlockDriverState
*bs
, int64_t sector_num
,
633 const uint8_t *buf
, int nb_sectors
,
634 BlockDriverCompletionFunc
*cb
, void *opaque
);
635 void bdrv_aio_cancel(BlockDriverAIOCB
*acb
);
637 void qemu_aio_init(void);
638 void qemu_aio_poll(void);
639 void qemu_aio_flush(void);
640 void qemu_aio_wait_start(void);
641 void qemu_aio_wait(void);
642 void qemu_aio_wait_end(void);
644 int qemu_key_check(BlockDriverState
*bs
, const char *name
);
646 /* Ensure contents are flushed to disk. */
647 void bdrv_flush(BlockDriverState
*bs
);
649 #define BDRV_TYPE_HD 0
650 #define BDRV_TYPE_CDROM 1
651 #define BDRV_TYPE_FLOPPY 2
652 #define BIOS_ATA_TRANSLATION_AUTO 0
653 #define BIOS_ATA_TRANSLATION_NONE 1
654 #define BIOS_ATA_TRANSLATION_LBA 2
655 #define BIOS_ATA_TRANSLATION_LARGE 3
656 #define BIOS_ATA_TRANSLATION_RECHS 4
658 void bdrv_set_geometry_hint(BlockDriverState
*bs
,
659 int cyls
, int heads
, int secs
);
660 void bdrv_set_type_hint(BlockDriverState
*bs
, int type
);
661 void bdrv_set_translation_hint(BlockDriverState
*bs
, int translation
);
662 void bdrv_get_geometry_hint(BlockDriverState
*bs
,
663 int *pcyls
, int *pheads
, int *psecs
);
664 int bdrv_get_type_hint(BlockDriverState
*bs
);
665 int bdrv_get_translation_hint(BlockDriverState
*bs
);
666 int bdrv_is_removable(BlockDriverState
*bs
);
667 int bdrv_is_read_only(BlockDriverState
*bs
);
668 int bdrv_is_inserted(BlockDriverState
*bs
);
669 int bdrv_media_changed(BlockDriverState
*bs
);
670 int bdrv_is_locked(BlockDriverState
*bs
);
671 void bdrv_set_locked(BlockDriverState
*bs
, int locked
);
672 void bdrv_eject(BlockDriverState
*bs
, int eject_flag
);
673 void bdrv_set_change_cb(BlockDriverState
*bs
,
674 void (*change_cb
)(void *opaque
), void *opaque
);
675 void bdrv_get_format(BlockDriverState
*bs
, char *buf
, int buf_size
);
676 void bdrv_info(void);
677 BlockDriverState
*bdrv_find(const char *name
);
678 void bdrv_iterate(void (*it
)(void *opaque
, const char *name
), void *opaque
);
679 int bdrv_is_encrypted(BlockDriverState
*bs
);
680 int bdrv_set_key(BlockDriverState
*bs
, const char *key
);
681 void bdrv_iterate_format(void (*it
)(void *opaque
, const char *name
),
683 const char *bdrv_get_device_name(BlockDriverState
*bs
);
684 int bdrv_write_compressed(BlockDriverState
*bs
, int64_t sector_num
,
685 const uint8_t *buf
, int nb_sectors
);
686 int bdrv_get_info(BlockDriverState
*bs
, BlockDriverInfo
*bdi
);
688 void bdrv_get_backing_filename(BlockDriverState
*bs
,
689 char *filename
, int filename_size
);
690 int bdrv_snapshot_create(BlockDriverState
*bs
,
691 QEMUSnapshotInfo
*sn_info
);
692 int bdrv_snapshot_goto(BlockDriverState
*bs
,
693 const char *snapshot_id
);
694 int bdrv_snapshot_delete(BlockDriverState
*bs
, const char *snapshot_id
);
695 int bdrv_snapshot_list(BlockDriverState
*bs
,
696 QEMUSnapshotInfo
**psn_info
);
697 char *bdrv_snapshot_dump(char *buf
, int buf_size
, QEMUSnapshotInfo
*sn
);
699 char *get_human_readable_size(char *buf
, int buf_size
, int64_t size
);
700 int path_is_absolute(const char *path
);
701 void path_combine(char *dest
, int dest_size
,
702 const char *base_path
,
703 const char *filename
);
707 typedef void QEMUMachineInitFunc(int ram_size
, int vga_ram_size
,
709 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
710 const char *kernel_filename
, const char *kernel_cmdline
,
711 const char *initrd_filename
, const char *cpu_model
);
713 typedef struct QEMUMachine
{
716 QEMUMachineInitFunc
*init
;
717 struct QEMUMachine
*next
;
720 int qemu_register_machine(QEMUMachine
*m
);
722 typedef void SetIRQFunc(void *opaque
, int irq_num
, int level
);
724 #if defined(TARGET_PPC)
725 void ppc_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
728 #if defined(TARGET_MIPS)
729 void mips_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
736 extern target_phys_addr_t isa_mem_base
;
738 typedef void (IOPortWriteFunc
)(void *opaque
, uint32_t address
, uint32_t data
);
739 typedef uint32_t (IOPortReadFunc
)(void *opaque
, uint32_t address
);
741 int register_ioport_read(int start
, int length
, int size
,
742 IOPortReadFunc
*func
, void *opaque
);
743 int register_ioport_write(int start
, int length
, int size
,
744 IOPortWriteFunc
*func
, void *opaque
);
745 void isa_unassign_ioport(int start
, int length
);
747 void isa_mmio_init(target_phys_addr_t base
, target_phys_addr_t size
);
751 extern target_phys_addr_t pci_mem_base
;
753 typedef struct PCIBus PCIBus
;
754 typedef struct PCIDevice PCIDevice
;
756 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
757 uint32_t address
, uint32_t data
, int len
);
758 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
759 uint32_t address
, int len
);
760 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
761 uint32_t addr
, uint32_t size
, int type
);
763 #define PCI_ADDRESS_SPACE_MEM 0x00
764 #define PCI_ADDRESS_SPACE_IO 0x01
765 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
767 typedef struct PCIIORegion
{
768 uint32_t addr
; /* current PCI mapping address. -1 means not mapped */
771 PCIMapIORegionFunc
*map_func
;
774 #define PCI_ROM_SLOT 6
775 #define PCI_NUM_REGIONS 7
777 #define PCI_DEVICES_MAX 64
779 #define PCI_VENDOR_ID 0x00 /* 16 bits */
780 #define PCI_DEVICE_ID 0x02 /* 16 bits */
781 #define PCI_COMMAND 0x04 /* 16 bits */
782 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
783 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
784 #define PCI_CLASS_DEVICE 0x0a /* Device class */
785 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
786 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
787 #define PCI_MIN_GNT 0x3e /* 8 bits */
788 #define PCI_MAX_LAT 0x3f /* 8 bits */
791 /* PCI config space */
794 /* the following fields are read only */
798 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
800 /* do not access the following fields */
801 PCIConfigReadFunc
*config_read
;
802 PCIConfigWriteFunc
*config_write
;
803 /* ??? This is a PC-specific hack, and should be removed. */
806 /* IRQ objects for the INTA-INTD pins. */
809 /* Current IRQ levels. Used internally by the generic PCI code. */
813 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
814 int instance_size
, int devfn
,
815 PCIConfigReadFunc
*config_read
,
816 PCIConfigWriteFunc
*config_write
);
818 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
819 uint32_t size
, int type
,
820 PCIMapIORegionFunc
*map_func
);
822 uint32_t pci_default_read_config(PCIDevice
*d
,
823 uint32_t address
, int len
);
824 void pci_default_write_config(PCIDevice
*d
,
825 uint32_t address
, uint32_t val
, int len
);
826 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
827 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
829 typedef void (*pci_set_irq_fn
)(qemu_irq
*pic
, int irq_num
, int level
);
830 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
831 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
832 qemu_irq
*pic
, int devfn_min
, int nirq
);
834 void pci_nic_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
835 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
);
836 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
);
837 int pci_bus_num(PCIBus
*s
);
838 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
));
841 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint32_t id
,
842 pci_map_irq_fn map_irq
, const char *name
);
845 PCIBus
*pci_prep_init(qemu_irq
*pic
);
848 PCIBus
*pci_grackle_init(uint32_t base
, qemu_irq
*pic
);
851 PCIBus
*pci_pmac_init(qemu_irq
*pic
);
854 PCIBus
*pci_apb_init(target_phys_addr_t special_base
, target_phys_addr_t mem_base
,
857 PCIBus
*pci_vpb_init(qemu_irq
*pic
, int irq
, int realview
);
860 PCIBus
*i440fx_init(PCIDevice
**pi440fx_state
, qemu_irq
*pic
);
861 void i440fx_set_smm(PCIDevice
*d
, int val
);
862 int piix3_init(PCIBus
*bus
, int devfn
);
863 void i440fx_init_memory_mappings(PCIDevice
*d
);
865 int piix4_init(PCIBus
*bus
, int devfn
);
868 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
870 OPENPIC_OUTPUT_INT
= 0, /* IRQ */
871 OPENPIC_OUTPUT_CINT
, /* critical IRQ */
872 OPENPIC_OUTPUT_MCK
, /* Machine check event */
873 OPENPIC_OUTPUT_DEBUG
, /* Inconditional debug event */
874 OPENPIC_OUTPUT_RESET
, /* Core reset event */
877 qemu_irq
*openpic_init (PCIBus
*bus
, int *pmem_index
, int nb_cpus
,
878 qemu_irq
**irqs
, qemu_irq irq_out
);
881 qemu_irq
*heathrow_pic_init(int *pmem_index
);
884 PCIBus
*pci_gt64120_init(qemu_irq
*pic
);
893 int (*init_isa
) (AudioState
*s
, qemu_irq
*pic
);
894 int (*init_pci
) (PCIBus
*bus
, AudioState
*s
);
898 extern struct soundhw soundhw
[];
904 #define VGA_RAM_SIZE (8192 * 1024)
906 #define VGA_RAM_SIZE (9 * 1024 * 1024)
909 struct DisplayState
{
913 int bgr
; /* BGR color order instead of RGB. Only valid for depth == 32 */
918 void (*dpy_update
)(struct DisplayState
*s
, int x
, int y
, int w
, int h
);
919 void (*dpy_resize
)(struct DisplayState
*s
, int w
, int h
);
920 void (*dpy_refresh
)(struct DisplayState
*s
);
921 void (*dpy_copy
)(struct DisplayState
*s
, int src_x
, int src_y
,
922 int dst_x
, int dst_y
, int w
, int h
);
923 void (*dpy_fill
)(struct DisplayState
*s
, int x
, int y
,
924 int w
, int h
, uint32_t c
);
925 void (*mouse_set
)(int x
, int y
, int on
);
926 void (*cursor_define
)(int width
, int height
, int bpp
, int hot_x
, int hot_y
,
927 uint8_t *image
, uint8_t *mask
);
930 static inline void dpy_update(DisplayState
*s
, int x
, int y
, int w
, int h
)
932 s
->dpy_update(s
, x
, y
, w
, h
);
935 static inline void dpy_resize(DisplayState
*s
, int w
, int h
)
937 s
->dpy_resize(s
, w
, h
);
940 int isa_vga_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
941 unsigned long vga_ram_offset
, int vga_ram_size
);
942 int pci_vga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
943 unsigned long vga_ram_offset
, int vga_ram_size
,
944 unsigned long vga_bios_offset
, int vga_bios_size
);
945 int isa_vga_mm_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
946 unsigned long vga_ram_offset
, int vga_ram_size
,
947 target_phys_addr_t vram_base
, target_phys_addr_t ctrl_base
,
951 void pci_cirrus_vga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
952 unsigned long vga_ram_offset
, int vga_ram_size
);
953 void isa_cirrus_vga_init(DisplayState
*ds
, uint8_t *vga_ram_base
,
954 unsigned long vga_ram_offset
, int vga_ram_size
);
957 void pci_vmsvga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
958 unsigned long vga_ram_offset
, int vga_ram_size
);
961 void sdl_display_init(DisplayState
*ds
, int full_screen
, int no_frame
);
964 void cocoa_display_init(DisplayState
*ds
, int full_screen
);
967 void vnc_display_init(DisplayState
*ds
, const char *display
);
968 void do_info_vnc(void);
971 extern uint8_t _translate_keycode(const int key
);
976 extern BlockDriverState
*bs_table
[MAX_DISKS
+ 1];
977 extern BlockDriverState
*sd_bdrv
;
978 extern BlockDriverState
*mtd_bdrv
;
980 void isa_ide_init(int iobase
, int iobase2
, qemu_irq irq
,
981 BlockDriverState
*hd0
, BlockDriverState
*hd1
);
982 void pci_cmd646_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
,
983 int secondary_ide_enabled
);
984 void pci_piix3_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
, int devfn
,
986 void pci_piix4_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
, int devfn
,
988 int pmac_ide_init (BlockDriverState
**hd_table
, qemu_irq irq
);
991 int cdrom_read_toc(int nb_sectors
, uint8_t *buf
, int msf
, int start_track
);
992 int cdrom_read_toc_raw(int nb_sectors
, uint8_t *buf
, int msf
, int session_num
);
995 typedef struct ds1225y_t ds1225y_t
;
996 ds1225y_t
*ds1225y_init(target_ulong mem_base
, const char *filename
);
999 int es1370_init (PCIBus
*bus
, AudioState
*s
);
1002 int SB16_init (AudioState
*s
, qemu_irq
*pic
);
1005 int Adlib_init (AudioState
*s
, qemu_irq
*pic
);
1008 int GUS_init (AudioState
*s
, qemu_irq
*pic
);
1011 typedef int (*DMA_transfer_handler
) (void *opaque
, int nchan
, int pos
, int size
);
1012 int DMA_get_channel_mode (int nchan
);
1013 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
);
1014 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
);
1015 void DMA_hold_DREQ (int nchan
);
1016 void DMA_release_DREQ (int nchan
);
1017 void DMA_schedule(int nchan
);
1018 void DMA_run (void);
1019 void DMA_init (int high_page_enable
);
1020 void DMA_register_channel (int nchan
,
1021 DMA_transfer_handler transfer_handler
,
1025 extern BlockDriverState
*fd_table
[MAX_FD
];
1027 typedef struct fdctrl_t fdctrl_t
;
1029 fdctrl_t
*fdctrl_init (qemu_irq irq
, int dma_chann
, int mem_mapped
,
1030 target_phys_addr_t io_base
,
1031 BlockDriverState
**fds
);
1032 int fdctrl_get_drive_type(fdctrl_t
*fdctrl
, int drive_num
);
1036 void pci_i82551_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1037 void pci_i82557b_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1038 void pci_i82559er_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1042 void isa_ne2000_init(int base
, qemu_irq irq
, NICInfo
*nd
);
1043 void pci_ne2000_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1047 void pci_rtl8139_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1051 void pci_pcnet_init(PCIBus
*bus
, NICInfo
*nd
, int devfn
);
1052 void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
, void *dma_opaque
,
1056 void *vmmouse_init(void *m
);
1060 void i8042_init(qemu_irq kbd_irq
, qemu_irq mouse_irq
, uint32_t io_base
);
1061 void i8042_mm_init(qemu_irq kbd_irq
, qemu_irq mouse_irq
, target_ulong base
, int it_shift
);
1065 typedef struct RTCState RTCState
;
1067 RTCState
*rtc_init(int base
, qemu_irq irq
);
1068 RTCState
*rtc_mm_init(target_phys_addr_t base
, int it_shift
, qemu_irq irq
);
1069 void rtc_set_memory(RTCState
*s
, int addr
, int val
);
1070 void rtc_set_date(RTCState
*s
, const struct tm
*tm
);
1074 typedef struct SerialState SerialState
;
1075 SerialState
*serial_init(int base
, qemu_irq irq
, CharDriverState
*chr
);
1076 SerialState
*serial_mm_init (target_ulong base
, int it_shift
,
1077 qemu_irq irq
, CharDriverState
*chr
,
1079 uint32_t serial_mm_readb (void *opaque
, target_phys_addr_t addr
);
1080 void serial_mm_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
1081 uint32_t serial_mm_readw (void *opaque
, target_phys_addr_t addr
);
1082 void serial_mm_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
1083 uint32_t serial_mm_readl (void *opaque
, target_phys_addr_t addr
);
1084 void serial_mm_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
);
1088 typedef struct ParallelState ParallelState
;
1089 ParallelState
*parallel_init(int base
, qemu_irq irq
, CharDriverState
*chr
);
1093 typedef struct PicState2 PicState2
;
1094 extern PicState2
*isa_pic
;
1095 void pic_set_irq(int irq
, int level
);
1096 void pic_set_irq_new(void *opaque
, int irq
, int level
);
1097 qemu_irq
*i8259_init(qemu_irq parent_irq
);
1098 void pic_set_alt_irq_func(PicState2
*s
, SetIRQFunc
*alt_irq_func
,
1099 void *alt_irq_opaque
);
1100 int pic_read_irq(PicState2
*s
);
1101 void pic_update_irq(PicState2
*s
);
1102 uint32_t pic_intack_read(PicState2
*s
);
1103 void pic_info(void);
1104 void irq_info(void);
1107 typedef struct IOAPICState IOAPICState
;
1109 int apic_init(CPUState
*env
);
1110 int apic_get_interrupt(CPUState
*env
);
1111 IOAPICState
*ioapic_init(void);
1112 void ioapic_set_irq(void *opaque
, int vector
, int level
);
1116 #define PIT_FREQ 1193182
1118 typedef struct PITState PITState
;
1120 PITState
*pit_init(int base
, qemu_irq irq
);
1121 void pit_set_gate(PITState
*pit
, int channel
, int val
);
1122 int pit_get_gate(PITState
*pit
, int channel
);
1123 int pit_get_initial_count(PITState
*pit
, int channel
);
1124 int pit_get_mode(PITState
*pit
, int channel
);
1125 int pit_get_out(PITState
*pit
, int channel
, int64_t current_time
);
1128 void pcspk_init(PITState
*);
1129 int pcspk_audio_init(AudioState
*, qemu_irq
*pic
);
1133 #include "hw/smbus.h"
1136 extern int acpi_enabled
;
1137 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
);
1138 void piix4_smbus_register_device(SMBusDevice
*dev
, uint8_t addr
);
1139 void acpi_bios_init(void);
1142 extern QEMUMachine pc_machine
;
1143 extern QEMUMachine isapc_machine
;
1144 extern int fd_bootchk
;
1146 void ioport_set_a20(int enable
);
1147 int ioport_get_a20(void);
1150 extern QEMUMachine prep_machine
;
1151 extern QEMUMachine core99_machine
;
1152 extern QEMUMachine heathrow_machine
;
1153 extern QEMUMachine ref405ep_machine
;
1154 extern QEMUMachine taihu_machine
;
1157 extern QEMUMachine mips_machine
;
1160 extern QEMUMachine mips_malta_machine
;
1163 extern void cpu_mips_irq_init_cpu(CPUState
*env
);
1166 extern QEMUMachine mips_pica61_machine
;
1169 extern void cpu_mips_clock_init(CPUState
*);
1170 extern void cpu_mips_irqctrl_init (void);
1173 extern QEMUMachine shix_machine
;
1176 /* PowerPC hardware exceptions management helpers */
1177 typedef void (*clk_setup_cb
)(void *opaque
, uint32_t freq
);
1178 typedef struct clk_setup_t clk_setup_t
;
1179 struct clk_setup_t
{
1183 static inline void clk_setup (clk_setup_t
*clk
, uint32_t freq
)
1185 if (clk
->cb
!= NULL
)
1186 (*clk
->cb
)(clk
->opaque
, freq
);
1189 clk_setup_cb
cpu_ppc_tb_init (CPUState
*env
, uint32_t freq
);
1190 /* Embedded PowerPC DCR management */
1191 typedef target_ulong (*dcr_read_cb
)(void *opaque
, int dcrn
);
1192 typedef void (*dcr_write_cb
)(void *opaque
, int dcrn
, target_ulong val
);
1193 int ppc_dcr_init (CPUState
*env
, int (*dcr_read_error
)(int dcrn
),
1194 int (*dcr_write_error
)(int dcrn
));
1195 int ppc_dcr_register (CPUState
*env
, int dcrn
, void *opaque
,
1196 dcr_read_cb drc_read
, dcr_write_cb dcr_write
);
1197 clk_setup_cb
ppc_emb_timers_init (CPUState
*env
, uint32_t freq
);
1198 /* Embedded PowerPC reset */
1199 void ppc40x_core_reset (CPUState
*env
);
1200 void ppc40x_chip_reset (CPUState
*env
);
1201 void ppc40x_system_reset (CPUState
*env
);
1203 void PREP_debug_write (void *opaque
, uint32_t addr
, uint32_t val
);
1205 extern CPUWriteMemoryFunc
*PPC_io_write
[];
1206 extern CPUReadMemoryFunc
*PPC_io_read
[];
1207 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
);
1210 extern QEMUMachine ss5_machine
, ss10_machine
;
1213 void *iommu_init(target_phys_addr_t addr
);
1214 void sparc_iommu_memory_rw(void *opaque
, target_phys_addr_t addr
,
1215 uint8_t *buf
, int len
, int is_write
);
1216 static inline void sparc_iommu_memory_read(void *opaque
,
1217 target_phys_addr_t addr
,
1218 uint8_t *buf
, int len
)
1220 sparc_iommu_memory_rw(opaque
, addr
, buf
, len
, 0);
1223 static inline void sparc_iommu_memory_write(void *opaque
,
1224 target_phys_addr_t addr
,
1225 uint8_t *buf
, int len
)
1227 sparc_iommu_memory_rw(opaque
, addr
, buf
, len
, 1);
1231 void tcx_init(DisplayState
*ds
, target_phys_addr_t addr
, uint8_t *vram_base
,
1232 unsigned long vram_offset
, int vram_size
, int width
, int height
,
1235 /* slavio_intctl.c */
1236 void *slavio_intctl_init(target_phys_addr_t addr
, target_phys_addr_t addrg
,
1237 const uint32_t *intbit_to_level
,
1238 qemu_irq
**irq
, qemu_irq
**cpu_irq
,
1239 qemu_irq
**parent_irq
, unsigned int cputimer
);
1240 void slavio_pic_info(void *opaque
);
1241 void slavio_irq_info(void *opaque
);
1244 int get_image_size(const char *filename
);
1245 int load_image(const char *filename
, uint8_t *addr
);
1246 int load_elf(const char *filename
, int64_t virt_to_phys_addend
,
1247 uint64_t *pentry
, uint64_t *lowaddr
, uint64_t *highaddr
);
1248 int load_aout(const char *filename
, uint8_t *addr
);
1249 int load_uboot(const char *filename
, target_ulong
*ep
, int *is_linux
);
1251 /* slavio_timer.c */
1252 void slavio_timer_init(target_phys_addr_t addr
, qemu_irq irq
, int mode
);
1254 /* slavio_serial.c */
1255 SerialState
*slavio_serial_init(target_phys_addr_t base
, qemu_irq irq
,
1256 CharDriverState
*chr1
, CharDriverState
*chr2
);
1257 void slavio_serial_ms_kbd_init(target_phys_addr_t base
, qemu_irq irq
);
1260 void *slavio_misc_init(target_phys_addr_t base
, target_phys_addr_t power_base
,
1262 void slavio_set_power_fail(void *opaque
, int power_failing
);
1265 void esp_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
);
1266 void *esp_init(BlockDriverState
**bd
, target_phys_addr_t espaddr
,
1267 void *dma_opaque
, qemu_irq irq
);
1270 void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
1271 void *iommu
, qemu_irq
**dev_irq
);
1272 void ledma_memory_read(void *opaque
, target_phys_addr_t addr
,
1273 uint8_t *buf
, int len
, int do_bswap
);
1274 void ledma_memory_write(void *opaque
, target_phys_addr_t addr
,
1275 uint8_t *buf
, int len
, int do_bswap
);
1276 void espdma_memory_read(void *opaque
, uint8_t *buf
, int len
);
1277 void espdma_memory_write(void *opaque
, uint8_t *buf
, int len
);
1278 void sparc32_dma_set_reset_data(void *opaque
, void (*dev_reset
)(void *opaque
),
1282 void cs_init(target_phys_addr_t base
, int irq
, void *intctl
);
1285 extern QEMUMachine sun4u_machine
;
1288 #include "hw/m48t59.h"
1290 void NVRAM_set_byte (m48t59_t
*nvram
, uint32_t addr
, uint8_t value
);
1291 uint8_t NVRAM_get_byte (m48t59_t
*nvram
, uint32_t addr
);
1292 void NVRAM_set_word (m48t59_t
*nvram
, uint32_t addr
, uint16_t value
);
1293 uint16_t NVRAM_get_word (m48t59_t
*nvram
, uint32_t addr
);
1294 void NVRAM_set_lword (m48t59_t
*nvram
, uint32_t addr
, uint32_t value
);
1295 uint32_t NVRAM_get_lword (m48t59_t
*nvram
, uint32_t addr
);
1296 void NVRAM_set_string (m48t59_t
*nvram
, uint32_t addr
,
1297 const unsigned char *str
, uint32_t max
);
1298 int NVRAM_get_string (m48t59_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
);
1299 void NVRAM_set_crc (m48t59_t
*nvram
, uint32_t addr
,
1300 uint32_t start
, uint32_t count
);
1301 int PPC_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
1302 const unsigned char *arch
,
1303 uint32_t RAM_size
, int boot_device
,
1304 uint32_t kernel_image
, uint32_t kernel_size
,
1305 const char *cmdline
,
1306 uint32_t initrd_image
, uint32_t initrd_size
,
1307 uint32_t NVRAM_image
,
1308 int width
, int height
, int depth
);
1312 #define MAX_ADB_DEVICES 16
1314 #define ADB_MAX_OUT_LEN 16
1316 typedef struct ADBDevice ADBDevice
;
1318 /* buf = NULL means polling */
1319 typedef int ADBDeviceRequest(ADBDevice
*d
, uint8_t *buf_out
,
1320 const uint8_t *buf
, int len
);
1321 typedef int ADBDeviceReset(ADBDevice
*d
);
1324 struct ADBBusState
*bus
;
1327 ADBDeviceRequest
*devreq
;
1328 ADBDeviceReset
*devreset
;
1332 typedef struct ADBBusState
{
1333 ADBDevice devices
[MAX_ADB_DEVICES
];
1338 int adb_request(ADBBusState
*s
, uint8_t *buf_out
,
1339 const uint8_t *buf
, int len
);
1340 int adb_poll(ADBBusState
*s
, uint8_t *buf_out
);
1342 ADBDevice
*adb_register_device(ADBBusState
*s
, int devaddr
,
1343 ADBDeviceRequest
*devreq
,
1344 ADBDeviceReset
*devreset
,
1346 void adb_kbd_init(ADBBusState
*bus
);
1347 void adb_mouse_init(ADBBusState
*bus
);
1351 extern ADBBusState adb_bus
;
1352 int cuda_init(qemu_irq irq
);
1356 /* usb ports of the VM */
1358 void qemu_register_usb_port(USBPort
*port
, void *opaque
, int index
,
1359 usb_attachfn attach
);
1361 #define VM_USB_HUB_SIZE 8
1363 void do_usb_add(const char *devname
);
1364 void do_usb_del(const char *devname
);
1365 void usb_info(void);
1369 SCSI_REASON_DONE
, /* Command complete. */
1370 SCSI_REASON_DATA
/* Transfer complete, more data required. */
1373 typedef struct SCSIDevice SCSIDevice
;
1374 typedef void (*scsi_completionfn
)(void *opaque
, int reason
, uint32_t tag
,
1377 SCSIDevice
*scsi_disk_init(BlockDriverState
*bdrv
,
1379 scsi_completionfn completion
,
1381 void scsi_disk_destroy(SCSIDevice
*s
);
1383 int32_t scsi_send_command(SCSIDevice
*s
, uint32_t tag
, uint8_t *buf
, int lun
);
1384 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1385 layer the completion routine may be called directly by
1386 scsi_{read,write}_data. */
1387 void scsi_read_data(SCSIDevice
*s
, uint32_t tag
);
1388 int scsi_write_data(SCSIDevice
*s
, uint32_t tag
);
1389 void scsi_cancel_io(SCSIDevice
*s
, uint32_t tag
);
1390 uint8_t *scsi_get_buf(SCSIDevice
*s
, uint32_t tag
);
1393 void lsi_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
);
1394 void *lsi_scsi_init(PCIBus
*bus
, int devfn
);
1396 /* integratorcp.c */
1397 extern QEMUMachine integratorcp_machine
;
1400 extern QEMUMachine versatilepb_machine
;
1401 extern QEMUMachine versatileab_machine
;
1404 extern QEMUMachine realview_machine
;
1407 extern QEMUMachine akitapda_machine
;
1408 extern QEMUMachine spitzpda_machine
;
1409 extern QEMUMachine borzoipda_machine
;
1410 extern QEMUMachine terrierpda_machine
;
1413 void *ps2_kbd_init(void (*update_irq
)(void *, int), void *update_arg
);
1414 void *ps2_mouse_init(void (*update_irq
)(void *, int), void *update_arg
);
1415 void ps2_write_mouse(void *, int val
);
1416 void ps2_write_keyboard(void *, int val
);
1417 uint32_t ps2_read_data(void *);
1418 void ps2_queue(void *, int b
);
1419 void ps2_keyboard_set_translation(void *opaque
, int mode
);
1420 void ps2_mouse_fake_event(void *opaque
);
1423 void smc91c111_init(NICInfo
*, uint32_t, qemu_irq
);
1426 void *pl110_init(DisplayState
*ds
, uint32_t base
, qemu_irq irq
, int);
1429 void pl011_init(uint32_t base
, qemu_irq irq
, CharDriverState
*chr
);
1432 void pl050_init(uint32_t base
, qemu_irq irq
, int is_mouse
);
1435 void *pl080_init(uint32_t base
, qemu_irq irq
, int nchannels
);
1438 void pl181_init(uint32_t base
, BlockDriverState
*bd
,
1439 qemu_irq irq0
, qemu_irq irq1
);
1442 qemu_irq
*pl190_init(uint32_t base
, qemu_irq irq
, qemu_irq fiq
);
1445 void sp804_init(uint32_t base
, qemu_irq irq
);
1446 void icp_pit_init(uint32_t base
, qemu_irq
*pic
, int irq
);
1449 void arm_sysctl_init(uint32_t base
, uint32_t sys_id
);
1452 qemu_irq
*arm_gic_init(uint32_t base
, qemu_irq parent_irq
);
1456 void arm_load_kernel(CPUState
*env
, int ram_size
, const char *kernel_filename
,
1457 const char *kernel_cmdline
, const char *initrd_filename
,
1458 int board_id
, target_phys_addr_t loader_start
);
1463 struct SH7750State
*sh7750_init(CPUState
* cpu
);
1466 /* The callback will be triggered if any of the designated lines change */
1467 uint16_t portamask_trigger
;
1468 uint16_t portbmask_trigger
;
1469 /* Return 0 if no action was taken */
1470 int (*port_change_cb
) (uint16_t porta
, uint16_t portb
,
1471 uint16_t * periph_pdtra
,
1472 uint16_t * periph_portdira
,
1473 uint16_t * periph_pdtrb
,
1474 uint16_t * periph_portdirb
);
1477 int sh7750_register_io_device(struct SH7750State
*s
,
1478 sh7750_io_device
* device
);
1480 int tc58128_init(struct SH7750State
*s
, char *zone1
, char *zone2
);
1482 /* NOR flash devices */
1483 #define MAX_PFLASH 4
1484 extern BlockDriverState
*pflash_table
[MAX_PFLASH
];
1485 typedef struct pflash_t pflash_t
;
1487 pflash_t
*pflash_register (target_ulong base
, ram_addr_t off
,
1488 BlockDriverState
*bs
,
1489 target_ulong sector_len
, int nb_blocs
, int width
,
1490 uint16_t id0
, uint16_t id1
,
1491 uint16_t id2
, uint16_t id3
);
1494 struct nand_flash_s
;
1495 struct nand_flash_s
*nand_init(int manf_id
, int chip_id
);
1496 void nand_done(struct nand_flash_s
*s
);
1497 void nand_setpins(struct nand_flash_s
*s
,
1498 int cle
, int ale
, int ce
, int wp
, int gnd
);
1499 void nand_getpins(struct nand_flash_s
*s
, int *rb
);
1500 void nand_setio(struct nand_flash_s
*s
, uint8_t value
);
1501 uint8_t nand_getio(struct nand_flash_s
*s
);
1503 #define NAND_MFR_TOSHIBA 0x98
1504 #define NAND_MFR_SAMSUNG 0xec
1505 #define NAND_MFR_FUJITSU 0x04
1506 #define NAND_MFR_NATIONAL 0x8f
1507 #define NAND_MFR_RENESAS 0x07
1508 #define NAND_MFR_STMICRO 0x20
1509 #define NAND_MFR_HYNIX 0xad
1510 #define NAND_MFR_MICRON 0x2c
1515 typedef void (*gpio_handler_t
)(int line
, int level
, void *opaque
);
1518 struct ads7846_state_s
;
1519 uint32_t ads7846_read(void *opaque
);
1520 void ads7846_write(void *opaque
, uint32_t value
);
1521 struct ads7846_state_s
*ads7846_init(qemu_irq penirq
);
1525 uint32_t max111x_read(void *opaque
);
1526 void max111x_write(void *opaque
, uint32_t value
);
1527 struct max111x_s
*max1110_init(qemu_irq cb
);
1528 struct max111x_s
*max1111_init(qemu_irq cb
);
1529 void max111x_set_input(struct max111x_s
*s
, int line
, uint8_t value
);
1531 /* PCMCIA/Cardbus */
1533 struct pcmcia_socket_s
{
1536 const char *slot_string
;
1537 const char *card_string
;
1540 void pcmcia_socket_register(struct pcmcia_socket_s
*socket
);
1541 void pcmcia_socket_unregister(struct pcmcia_socket_s
*socket
);
1542 void pcmcia_info(void);
1544 struct pcmcia_card_s
{
1546 struct pcmcia_socket_s
*slot
;
1547 int (*attach
)(void *state
);
1548 int (*detach
)(void *state
);
1552 /* Only valid if attached */
1553 uint8_t (*attr_read
)(void *state
, uint32_t address
);
1554 void (*attr_write
)(void *state
, uint32_t address
, uint8_t value
);
1555 uint16_t (*common_read
)(void *state
, uint32_t address
);
1556 void (*common_write
)(void *state
, uint32_t address
, uint16_t value
);
1557 uint16_t (*io_read
)(void *state
, uint32_t address
);
1558 void (*io_write
)(void *state
, uint32_t address
, uint16_t value
);
1561 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1562 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1563 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1564 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1565 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1566 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1567 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1568 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1569 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1570 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1571 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1572 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1573 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1574 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1575 #define CISTPL_END 0xff /* Tuple End */
1576 #define CISTPL_ENDMARK 0xff
1579 struct pcmcia_card_s
*dscm1xxxx_init(BlockDriverState
*bdrv
);
1582 typedef struct ptimer_state ptimer_state
;
1583 typedef void (*ptimer_cb
)(void *opaque
);
1585 ptimer_state
*ptimer_init(QEMUBH
*bh
);
1586 void ptimer_set_period(ptimer_state
*s
, int64_t period
);
1587 void ptimer_set_freq(ptimer_state
*s
, uint32_t freq
);
1588 void ptimer_set_limit(ptimer_state
*s
, uint64_t limit
, int reload
);
1589 uint64_t ptimer_get_count(ptimer_state
*s
);
1590 void ptimer_set_count(ptimer_state
*s
, uint64_t count
);
1591 void ptimer_run(ptimer_state
*s
, int oneshot
);
1592 void ptimer_stop(ptimer_state
*s
);
1593 void qemu_put_ptimer(QEMUFile
*f
, ptimer_state
*s
);
1594 void qemu_get_ptimer(QEMUFile
*f
, ptimer_state
*s
);
1599 uint32_t mcf_uart_read(void *opaque
, target_phys_addr_t addr
);
1600 void mcf_uart_write(void *opaque
, target_phys_addr_t addr
, uint32_t val
);
1601 void *mcf_uart_init(qemu_irq irq
, CharDriverState
*chr
);
1602 void mcf_uart_mm_init(target_phys_addr_t base
, qemu_irq irq
,
1603 CharDriverState
*chr
);
1606 qemu_irq
*mcf_intc_init(target_phys_addr_t base
, CPUState
*env
);
1609 void mcf_fec_init(NICInfo
*nd
, target_phys_addr_t base
, qemu_irq
*irq
);
1612 qemu_irq
*mcf5206_init(uint32_t base
, CPUState
*env
);
1615 extern QEMUMachine an5206_machine
;
1618 extern QEMUMachine mcf5208evb_machine
;
1620 #include "gdbstub.h"
1622 #endif /* defined(QEMU_TOOL) */
1625 void monitor_init(CharDriverState
*hd
, int show_banner
);
1626 void term_puts(const char *str
);
1627 void term_vprintf(const char *fmt
, va_list ap
);
1628 void term_printf(const char *fmt
, ...) __attribute__ ((__format__ (__printf__
, 1, 2)));
1629 void term_print_filename(const char *filename
);
1630 void term_flush(void);
1631 void term_print_help(void);
1632 void monitor_readline(const char *prompt
, int is_password
,
1633 char *buf
, int buf_size
);
1636 typedef void ReadLineFunc(void *opaque
, const char *str
);
1638 extern int completion_index
;
1639 void add_completion(const char *str
);
1640 void readline_handle_byte(int ch
);
1641 void readline_find_completion(const char *cmdline
);
1642 const char *readline_get_history(unsigned int index
);
1643 void readline_start(const char *prompt
, int is_password
,
1644 ReadLineFunc
*readline_func
, void *opaque
);
1646 void kqemu_record_dump(void);