Impement Galilleo ISD register.
[qemu/dscho.git] / target-mips / op_mem.c
blob602c071c5b10307fc6ebda4d9274750de3974bde
1 /*
2 * MIPS emulation memory micro-operations for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* Standard loads and stores */
22 void glue(op_lb, MEMSUFFIX) (void)
24 T0 = glue(ldsb, MEMSUFFIX)(T0);
25 RETURN();
28 void glue(op_lbu, MEMSUFFIX) (void)
30 T0 = glue(ldub, MEMSUFFIX)(T0);
31 RETURN();
34 void glue(op_sb, MEMSUFFIX) (void)
36 glue(stb, MEMSUFFIX)(T0, T1);
37 RETURN();
40 void glue(op_lh, MEMSUFFIX) (void)
42 T0 = glue(ldsw, MEMSUFFIX)(T0);
43 RETURN();
46 void glue(op_lhu, MEMSUFFIX) (void)
48 T0 = glue(lduw, MEMSUFFIX)(T0);
49 RETURN();
52 void glue(op_sh, MEMSUFFIX) (void)
54 glue(stw, MEMSUFFIX)(T0, T1);
55 RETURN();
58 void glue(op_lw, MEMSUFFIX) (void)
60 T0 = glue(ldl, MEMSUFFIX)(T0);
61 RETURN();
64 void glue(op_lwu, MEMSUFFIX) (void)
66 T0 = (uint32_t)glue(ldl, MEMSUFFIX)(T0);
67 RETURN();
70 void glue(op_sw, MEMSUFFIX) (void)
72 glue(stl, MEMSUFFIX)(T0, T1);
73 RETURN();
76 /* "half" load and stores. We must do the memory access inline,
77 or fault handling won't work. */
78 /* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */
79 void glue(op_lwl, MEMSUFFIX) (void)
81 uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
82 CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp);
83 RETURN();
86 void glue(op_lwr, MEMSUFFIX) (void)
88 uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
89 CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp);
90 RETURN();
93 void glue(op_swl, MEMSUFFIX) (void)
95 uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
96 tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp);
97 glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
98 RETURN();
101 void glue(op_swr, MEMSUFFIX) (void)
103 uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
104 tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp);
105 glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
106 RETURN();
109 void glue(op_ll, MEMSUFFIX) (void)
111 T1 = T0;
112 T0 = glue(ldl, MEMSUFFIX)(T0);
113 env->CP0_LLAddr = T1;
114 RETURN();
117 void glue(op_sc, MEMSUFFIX) (void)
119 CALL_FROM_TB0(dump_sc);
120 if (T0 & 0x3) {
121 env->CP0_BadVAddr = T0;
122 CALL_FROM_TB1(do_raise_exception, EXCP_AdES);
124 if (T0 == env->CP0_LLAddr) {
125 glue(stl, MEMSUFFIX)(T0, T1);
126 T0 = 1;
127 } else {
128 T0 = 0;
130 RETURN();
133 #ifdef TARGET_MIPS64
134 void glue(op_ld, MEMSUFFIX) (void)
136 T0 = glue(ldq, MEMSUFFIX)(T0);
137 RETURN();
140 void glue(op_sd, MEMSUFFIX) (void)
142 glue(stq, MEMSUFFIX)(T0, T1);
143 RETURN();
146 /* "half" load and stores. We must do the memory access inline,
147 or fault handling won't work. */
148 void glue(op_ldl, MEMSUFFIX) (void)
150 target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
151 CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp);
152 RETURN();
155 void glue(op_ldr, MEMSUFFIX) (void)
157 target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
158 CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp);
159 RETURN();
162 void glue(op_sdl, MEMSUFFIX) (void)
164 target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
165 tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp);
166 glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
167 RETURN();
170 void glue(op_sdr, MEMSUFFIX) (void)
172 target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
173 tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp);
174 glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
175 RETURN();
178 void glue(op_lld, MEMSUFFIX) (void)
180 T1 = T0;
181 T0 = glue(ldq, MEMSUFFIX)(T0);
182 env->CP0_LLAddr = T1;
183 RETURN();
186 void glue(op_scd, MEMSUFFIX) (void)
188 CALL_FROM_TB0(dump_sc);
189 if (T0 & 0x7) {
190 env->CP0_BadVAddr = T0;
191 CALL_FROM_TB1(do_raise_exception, EXCP_AdES);
193 if (T0 == env->CP0_LLAddr) {
194 glue(stq, MEMSUFFIX)(T0, T1);
195 T0 = 1;
196 } else {
197 T0 = 0;
199 RETURN();
201 #endif /* TARGET_MIPS64 */
203 void glue(op_lwc1, MEMSUFFIX) (void)
205 WT0 = glue(ldl, MEMSUFFIX)(T0);
206 RETURN();
208 void glue(op_swc1, MEMSUFFIX) (void)
210 glue(stl, MEMSUFFIX)(T0, WT0);
211 RETURN();
213 void glue(op_ldc1, MEMSUFFIX) (void)
215 DT0 = glue(ldq, MEMSUFFIX)(T0);
216 RETURN();
218 void glue(op_sdc1, MEMSUFFIX) (void)
220 glue(stq, MEMSUFFIX)(T0, DT0);
221 RETURN();
223 void glue(op_luxc1, MEMSUFFIX) (void)
225 DT0 = glue(ldq, MEMSUFFIX)(T0 & ~0x7);
226 RETURN();
228 void glue(op_suxc1, MEMSUFFIX) (void)
230 glue(stq, MEMSUFFIX)(T0 & ~0x7, DT0);
231 RETURN();