2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL
18 uint32_t flash_offset
;
32 static uint8_t integrator_spd
[128] = {
33 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
34 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
37 static uint32_t integratorcm_read(void *opaque
, target_phys_addr_t offset
)
39 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
41 if (offset
>= 0x100 && offset
< 0x200) {
45 return integrator_spd
[offset
>> 2];
47 switch (offset
>> 2) {
59 if (s
->cm_lock
== 0xa05f) {
64 case 6: /* CM_LMBUSCNT */
65 /* ??? High frequency timer. */
66 cpu_abort(cpu_single_env
, "integratorcm_read: CM_LMBUSCNT");
67 case 7: /* CM_AUXOSC */
69 case 8: /* CM_SDRAM */
73 case 10: /* CM_REFCT */
74 /* ??? High frequency timer. */
75 cpu_abort(cpu_single_env
, "integratorcm_read: CM_REFCT");
76 case 12: /* CM_FLAGS */
78 case 14: /* CM_NVFLAGS */
80 case 16: /* CM_IRQ_STAT */
81 return s
->int_level
& s
->irq_enabled
;
82 case 17: /* CM_IRQ_RSTAT */
84 case 18: /* CM_IRQ_ENSET */
85 return s
->irq_enabled
;
86 case 20: /* CM_SOFT_INTSET */
87 return s
->int_level
& 1;
88 case 24: /* CM_FIQ_STAT */
89 return s
->int_level
& s
->fiq_enabled
;
90 case 25: /* CM_FIQ_RSTAT */
92 case 26: /* CM_FIQ_ENSET */
93 return s
->fiq_enabled
;
94 case 32: /* CM_VOLTAGE_CTL0 */
95 case 33: /* CM_VOLTAGE_CTL1 */
96 case 34: /* CM_VOLTAGE_CTL2 */
97 case 35: /* CM_VOLTAGE_CTL3 */
98 /* ??? Voltage control unimplemented. */
101 cpu_abort (cpu_single_env
,
102 "integratorcm_read: Unimplemented offset 0x%x\n", offset
);
107 static void integratorcm_do_remap(integratorcm_state
*s
, int flash
)
110 cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM
);
112 cpu_register_physical_memory(0, 0x100000, s
->flash_offset
| IO_MEM_RAM
);
114 //??? tlb_flush (cpu_single_env, 1);
117 static void integratorcm_set_ctrl(integratorcm_state
*s
, uint32_t value
)
120 cpu_abort(cpu_single_env
, "Board reset\n");
122 if ((s
->cm_init
^ value
) & 4) {
123 integratorcm_do_remap(s
, (value
& 4) == 0);
125 if ((s
->cm_init
^ value
) & 1) {
126 printf("Green LED %s\n", (value
& 1) ? "on" : "off");
128 s
->cm_init
= (s
->cm_init
& ~ 5) | (value
^ 5);
131 static void integratorcm_update(integratorcm_state
*s
)
133 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
135 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
136 cpu_abort(cpu_single_env
, "Core module interrupt\n");
139 static void integratorcm_write(void *opaque
, target_phys_addr_t offset
,
142 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
143 offset
-= 0x10000000;
144 switch (offset
>> 2) {
146 if (s
->cm_lock
== 0xa05f)
149 case 3: /* CM_CTRL */
150 integratorcm_set_ctrl(s
, value
);
152 case 5: /* CM_LOCK */
153 s
->cm_lock
= value
& 0xffff;
155 case 7: /* CM_AUXOSC */
156 if (s
->cm_lock
== 0xa05f)
157 s
->cm_auxosc
= value
;
159 case 8: /* CM_SDRAM */
162 case 9: /* CM_INIT */
163 /* ??? This can change the memory bus frequency. */
166 case 12: /* CM_FLAGSS */
167 s
->cm_flags
|= value
;
169 case 13: /* CM_FLAGSC */
170 s
->cm_flags
&= ~value
;
172 case 14: /* CM_NVFLAGSS */
173 s
->cm_nvflags
|= value
;
175 case 15: /* CM_NVFLAGSS */
176 s
->cm_nvflags
&= ~value
;
178 case 18: /* CM_IRQ_ENSET */
179 s
->irq_enabled
|= value
;
180 integratorcm_update(s
);
182 case 19: /* CM_IRQ_ENCLR */
183 s
->irq_enabled
&= ~value
;
184 integratorcm_update(s
);
186 case 20: /* CM_SOFT_INTSET */
187 s
->int_level
|= (value
& 1);
188 integratorcm_update(s
);
190 case 21: /* CM_SOFT_INTCLR */
191 s
->int_level
&= ~(value
& 1);
192 integratorcm_update(s
);
194 case 26: /* CM_FIQ_ENSET */
195 s
->fiq_enabled
|= value
;
196 integratorcm_update(s
);
198 case 27: /* CM_FIQ_ENCLR */
199 s
->fiq_enabled
&= ~value
;
200 integratorcm_update(s
);
202 case 32: /* CM_VOLTAGE_CTL0 */
203 case 33: /* CM_VOLTAGE_CTL1 */
204 case 34: /* CM_VOLTAGE_CTL2 */
205 case 35: /* CM_VOLTAGE_CTL3 */
206 /* ??? Voltage control unimplemented. */
209 cpu_abort (cpu_single_env
,
210 "integratorcm_write: Unimplemented offset 0x%x\n", offset
);
215 /* Integrator/CM control registers. */
217 static CPUReadMemoryFunc
*integratorcm_readfn
[] = {
223 static CPUWriteMemoryFunc
*integratorcm_writefn
[] = {
229 static void integratorcm_init(int memsz
, uint32_t flash_offset
)
232 integratorcm_state
*s
;
234 s
= (integratorcm_state
*)qemu_mallocz(sizeof(integratorcm_state
));
235 s
->cm_osc
= 0x01000048;
236 /* ??? What should the high bits of this value be? */
237 s
->cm_auxosc
= 0x0007feff;
238 s
->cm_sdram
= 0x00011122;
240 integrator_spd
[31] = 64;
242 } else if (memsz
>= 128) {
243 integrator_spd
[31] = 32;
245 } else if (memsz
>= 64) {
246 integrator_spd
[31] = 16;
248 } else if (memsz
>= 32) {
249 integrator_spd
[31] = 4;
252 integrator_spd
[31] = 2;
254 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
255 s
->cm_init
= 0x00000112;
256 s
->flash_offset
= flash_offset
;
258 iomemtype
= cpu_register_io_memory(0, integratorcm_readfn
,
259 integratorcm_writefn
, s
);
260 cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype
);
261 integratorcm_do_remap(s
, 1);
262 /* ??? Save/restore. */
265 /* Integrator/CP hardware emulation. */
266 /* Primary interrupt controller. */
268 typedef struct icp_pic_state
272 uint32_t irq_enabled
;
273 uint32_t fiq_enabled
;
278 static void icp_pic_update(icp_pic_state
*s
)
282 flags
= (s
->level
& s
->irq_enabled
);
283 qemu_set_irq(s
->parent_irq
, flags
!= 0);
284 flags
= (s
->level
& s
->fiq_enabled
);
285 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
288 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
290 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
292 s
->level
|= 1 << irq
;
294 s
->level
&= ~(1 << irq
);
298 static uint32_t icp_pic_read(void *opaque
, target_phys_addr_t offset
)
300 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
303 switch (offset
>> 2) {
304 case 0: /* IRQ_STATUS */
305 return s
->level
& s
->irq_enabled
;
306 case 1: /* IRQ_RAWSTAT */
308 case 2: /* IRQ_ENABLESET */
309 return s
->irq_enabled
;
310 case 4: /* INT_SOFTSET */
312 case 8: /* FRQ_STATUS */
313 return s
->level
& s
->fiq_enabled
;
314 case 9: /* FRQ_RAWSTAT */
316 case 10: /* FRQ_ENABLESET */
317 return s
->fiq_enabled
;
318 case 3: /* IRQ_ENABLECLR */
319 case 5: /* INT_SOFTCLR */
320 case 11: /* FRQ_ENABLECLR */
322 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
327 static void icp_pic_write(void *opaque
, target_phys_addr_t offset
,
330 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
333 switch (offset
>> 2) {
334 case 2: /* IRQ_ENABLESET */
335 s
->irq_enabled
|= value
;
337 case 3: /* IRQ_ENABLECLR */
338 s
->irq_enabled
&= ~value
;
340 case 4: /* INT_SOFTSET */
342 icp_pic_set_irq(s
, 0, 1);
344 case 5: /* INT_SOFTCLR */
346 icp_pic_set_irq(s
, 0, 0);
348 case 10: /* FRQ_ENABLESET */
349 s
->fiq_enabled
|= value
;
351 case 11: /* FRQ_ENABLECLR */
352 s
->fiq_enabled
&= ~value
;
354 case 0: /* IRQ_STATUS */
355 case 1: /* IRQ_RAWSTAT */
356 case 8: /* FRQ_STATUS */
357 case 9: /* FRQ_RAWSTAT */
359 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
365 static CPUReadMemoryFunc
*icp_pic_readfn
[] = {
371 static CPUWriteMemoryFunc
*icp_pic_writefn
[] = {
377 static qemu_irq
*icp_pic_init(uint32_t base
,
378 qemu_irq parent_irq
, qemu_irq parent_fiq
)
384 s
= (icp_pic_state
*)qemu_mallocz(sizeof(icp_pic_state
));
387 qi
= qemu_allocate_irqs(icp_pic_set_irq
, s
, 32);
389 s
->parent_irq
= parent_irq
;
390 s
->parent_fiq
= parent_fiq
;
391 iomemtype
= cpu_register_io_memory(0, icp_pic_readfn
,
393 cpu_register_physical_memory(base
, 0x00800000, iomemtype
);
394 /* ??? Save/restore. */
398 /* CP control registers. */
403 static uint32_t icp_control_read(void *opaque
, target_phys_addr_t offset
)
405 icp_control_state
*s
= (icp_control_state
*)opaque
;
407 switch (offset
>> 2) {
408 case 0: /* CP_IDFIELD */
410 case 1: /* CP_FLASHPROG */
412 case 2: /* CP_INTREG */
414 case 3: /* CP_DECODE */
417 cpu_abort (cpu_single_env
, "icp_control_read: Bad offset %x\n", offset
);
422 static void icp_control_write(void *opaque
, target_phys_addr_t offset
,
425 icp_control_state
*s
= (icp_control_state
*)opaque
;
427 switch (offset
>> 2) {
428 case 1: /* CP_FLASHPROG */
429 case 2: /* CP_INTREG */
430 case 3: /* CP_DECODE */
431 /* Nothing interesting implemented yet. */
434 cpu_abort (cpu_single_env
, "icp_control_write: Bad offset %x\n", offset
);
437 static CPUReadMemoryFunc
*icp_control_readfn
[] = {
443 static CPUWriteMemoryFunc
*icp_control_writefn
[] = {
449 static void icp_control_init(uint32_t base
)
452 icp_control_state
*s
;
454 s
= (icp_control_state
*)qemu_mallocz(sizeof(icp_control_state
));
455 iomemtype
= cpu_register_io_memory(0, icp_control_readfn
,
456 icp_control_writefn
, s
);
457 cpu_register_physical_memory(base
, 0x00800000, iomemtype
);
459 /* ??? Save/restore. */
465 static void integratorcp_init(int ram_size
, int vga_ram_size
, int boot_device
,
466 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
467 const char *kernel_filename
, const char *kernel_cmdline
,
468 const char *initrd_filename
, const char *cpu_model
)
471 uint32_t bios_offset
;
477 cpu_model
= "arm926";
478 cpu_arm_set_model(env
, cpu_model
);
479 bios_offset
= ram_size
+ vga_ram_size
;
480 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
481 /* ??? RAM shoud repeat to fill physical memory space. */
482 /* SDRAM at address zero*/
483 cpu_register_physical_memory(0, ram_size
, IO_MEM_RAM
);
484 /* And again at address 0x80000000 */
485 cpu_register_physical_memory(0x80000000, ram_size
, IO_MEM_RAM
);
487 integratorcm_init(ram_size
>> 20, bios_offset
);
488 cpu_pic
= arm_pic_init_cpu(env
);
489 pic
= icp_pic_init(0x14000000, cpu_pic
[ARM_PIC_CPU_IRQ
],
490 cpu_pic
[ARM_PIC_CPU_FIQ
]);
491 icp_pic_init(0xca000000, pic
[26], NULL
);
492 icp_pit_init(0x13000000, pic
, 5);
493 pl031_init(0x15000000, pic
[8]);
494 pl011_init(0x16000000, pic
[1], serial_hds
[0]);
495 pl011_init(0x17000000, pic
[2], serial_hds
[1]);
496 icp_control_init(0xcb000000);
497 pl050_init(0x18000000, pic
[3], 0);
498 pl050_init(0x19000000, pic
[4], 1);
499 pl181_init(0x1c000000, sd_bdrv
, pic
[23], pic
[24]);
500 if (nd_table
[0].vlan
) {
501 if (nd_table
[0].model
== NULL
502 || strcmp(nd_table
[0].model
, "smc91c111") == 0) {
503 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
504 } else if (strcmp(nd_table
[0].model
, "?") == 0) {
505 fprintf(stderr
, "qemu: Supported NICs: smc91c111\n");
508 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd_table
[0].model
);
512 pl110_init(ds
, 0xc0000000, pic
[22], 0);
514 arm_load_kernel(env
, ram_size
, kernel_filename
, kernel_cmdline
,
515 initrd_filename
, 0x113, 0x0);
518 QEMUMachine integratorcp_machine
= {
520 "ARM Integrator/CP (ARM926EJ-S)",