hw/pxa.h

   1 /*
   2  * Intel XScale PXA255/270 processor support.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9 #ifndef PXA_H
  10 # define PXA_H                  "pxa.h"
  11
  12 /* Interrupt numbers */
  13 # define PXA2XX_PIC_SSP3        0
  14 # define PXA2XX_PIC_USBH2       2
  15 # define PXA2XX_PIC_USBH1       3
  16 # define PXA2XX_PIC_PWRI2C      6
  17 # define PXA25X_PIC_HWUART      7
  18 # define PXA27X_PIC_OST_4_11    7
  19 # define PXA2XX_PIC_GPIO_0      8
  20 # define PXA2XX_PIC_GPIO_1      9
  21 # define PXA2XX_PIC_GPIO_X      10
  22 # define PXA2XX_PIC_I2S         13
  23 # define PXA26X_PIC_ASSP        15
  24 # define PXA25X_PIC_NSSP        16
  25 # define PXA27X_PIC_SSP2        16
  26 # define PXA2XX_PIC_LCD         17
  27 # define PXA2XX_PIC_I2C         18
  28 # define PXA2XX_PIC_ICP         19
  29 # define PXA2XX_PIC_STUART      20
  30 # define PXA2XX_PIC_BTUART      21
  31 # define PXA2XX_PIC_FFUART      22
  32 # define PXA2XX_PIC_MMC         23
  33 # define PXA2XX_PIC_SSP         24
  34 # define PXA2XX_PIC_DMA         25
  35 # define PXA2XX_PIC_OST_0       26
  36 # define PXA2XX_PIC_RTC1HZ      30
  37 # define PXA2XX_PIC_RTCALARM    31
  38
  39 /* DMA requests */
  40 # define PXA2XX_RX_RQ_I2S       2
  41 # define PXA2XX_TX_RQ_I2S       3
  42 # define PXA2XX_RX_RQ_BTUART    4
  43 # define PXA2XX_TX_RQ_BTUART    5
  44 # define PXA2XX_RX_RQ_FFUART    6
  45 # define PXA2XX_TX_RQ_FFUART    7
  46 # define PXA2XX_RX_RQ_SSP1      13
  47 # define PXA2XX_TX_RQ_SSP1      14
  48 # define PXA2XX_RX_RQ_SSP2      15
  49 # define PXA2XX_TX_RQ_SSP2      16
  50 # define PXA2XX_RX_RQ_ICP       17
  51 # define PXA2XX_TX_RQ_ICP       18
  52 # define PXA2XX_RX_RQ_STUART    19
  53 # define PXA2XX_TX_RQ_STUART    20
  54 # define PXA2XX_RX_RQ_MMCI      21
  55 # define PXA2XX_TX_RQ_MMCI      22
  56 # define PXA2XX_USB_RQ(x)       ((x) + 24)
  57 # define PXA2XX_RX_RQ_SSP3      66
  58 # define PXA2XX_TX_RQ_SSP3      67
  59
  60 # define PXA2XX_RAM_BASE        0xa0000000
  61
  62 /* pxa2xx_pic.c */
  63 struct pxa2xx_pic_state_s;
  64 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
  65
  66 /* pxa2xx_timer.c */
  67 void pxa25x_timer_init(target_phys_addr_t base,
  68                 qemu_irq *irqs, CPUState *cpustate);
  69 void pxa27x_timer_init(target_phys_addr_t base,
  70                 qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate);
  71
  72 /* pxa2xx_gpio.c */
  73 struct pxa2xx_gpio_info_s;
  74 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
  75                 CPUState *env, qemu_irq *pic, int lines);
  76 void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
  77 void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
  78                 gpio_handler_t handler, void *opaque);
  79 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
  80                 void (*handler)(void *opaque), void *opaque);
  81
  82 /* pxa2xx_dma.c */
  83 struct pxa2xx_dma_state_s;
  84 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
  85                 qemu_irq irq);
  86 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
  87                 qemu_irq irq);
  88 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
  89
  90 /* pxa2xx_lcd.c */
  91 struct pxa2xx_lcdc_s;
  92 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
  93                 qemu_irq irq, DisplayState *ds);
  94 void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
  95                 void (*cb)(void *opaque), void *opaque);
  96 void pxa2xx_lcdc_oritentation(void *opaque, int angle);
  97
  98 /* pxa2xx_mmci.c */
  99 struct pxa2xx_mmci_s;
 100 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
 101                 qemu_irq irq, void *dma);
 102 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
 103                 void (*readonly_cb)(void *, int),
 104                 void (*coverswitch_cb)(void *, int));
 105
 106 /* pxa2xx_pcmcia.c */
 107 struct pxa2xx_pcmcia_s;
 108 struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
 109 int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
 110 int pxa2xx_pcmcia_dettach(void *opaque);
 111 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
 112
 113 /* pxa2xx.c */
 114 struct pxa2xx_ssp_s;
 115 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
 116                 uint32_t (*readfn)(void *opaque),
 117                 void (*writefn)(void *opaque, uint32_t value), void *opaque);
 118
 119 struct pxa2xx_i2s_s;
 120 struct pxa2xx_fir_s;
 121
 122 struct pxa2xx_state_s {
 123     CPUState *env;
 124     qemu_irq *pic;
 125     struct pxa2xx_dma_state_s *dma;
 126     struct pxa2xx_gpio_info_s *gpio;
 127     struct pxa2xx_lcdc_s *lcd;
 128     struct pxa2xx_ssp_s **ssp;
 129     struct pxa2xx_mmci_s *mmc;
 130     struct pxa2xx_pcmcia_s *pcmcia[2];
 131     struct pxa2xx_i2s_s *i2s;
 132     struct pxa2xx_fir_s *fir;
 133
 134     /* Power management */
 135     target_phys_addr_t pm_base;
 136     uint32_t pm_regs[0x40];
 137
 138     /* Clock management */
 139     target_phys_addr_t cm_base;
 140     uint32_t cm_regs[4];
 141     uint32_t clkcfg;
 142
 143     /* Memory management */
 144     target_phys_addr_t mm_base;
 145     uint32_t mm_regs[0x1a];
 146
 147     /* Performance monitoring */
 148     uint32_t pmnc;
 149
 150     /* Real-Time clock */
 151     target_phys_addr_t rtc_base;
 152     uint32_t rttr;
 153     uint32_t rtsr;
 154     uint32_t rtar;
 155     uint32_t rdar1;
 156     uint32_t rdar2;
 157     uint32_t ryar1;
 158     uint32_t ryar2;
 159     uint32_t swar1;
 160     uint32_t swar2;
 161     uint32_t piar;
 162     uint32_t last_rcnr;
 163     uint32_t last_rdcr;
 164     uint32_t last_rycr;
 165     uint32_t last_swcr;
 166     uint32_t last_rtcpicr;
 167     int64_t last_hz;
 168     int64_t last_sw;
 169     int64_t last_pi;
 170     QEMUTimer *rtc_hz;
 171     QEMUTimer *rtc_rdal1;
 172     QEMUTimer *rtc_rdal2;
 173     QEMUTimer *rtc_swal1;
 174     QEMUTimer *rtc_swal2;
 175     QEMUTimer *rtc_pi;
 176 };
 177
 178 struct pxa2xx_i2s_s {
 179     target_phys_addr_t base;
 180     qemu_irq irq;
 181     struct pxa2xx_dma_state_s *dma;
 182     void (*data_req)(void *, int, int);
 183
 184     uint32_t control[2];
 185     uint32_t status;
 186     uint32_t mask;
 187     uint32_t clk;
 188
 189     int enable;
 190     int rx_len;
 191     int tx_len;
 192     void (*codec_out)(void *, uint32_t);
 193     uint32_t (*codec_in)(void *);
 194     void *opaque;
 195
 196     int fifo_len;
 197     uint32_t fifo[16];
 198 };
 199
 200 # define PA_FMT                 "0x%08lx"
 201 # define REG_FMT                "0x%lx"
 202
 203 struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision);
 204 struct pxa2xx_state_s *pxa255_init(DisplayState *ds);
 205
 206 void pxa2xx_reset(int line, int level, void *opaque);
 207
 208 #endif  /* PXA_H */