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Clear BD slot on next exception if appropriate.
[qemu/dscho.git] / hw / ppc405_uc.c
blobe06165d52984e81e486a70c30aefb1a4bee18958
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "ppc405.h"
26
27 extern int loglevel;
28 extern FILE *logfile;
29
30 //#define DEBUG_MMIO
31 #define DEBUG_OPBA
32 #define DEBUG_SDRAM
33 #define DEBUG_GPIO
34 #define DEBUG_SERIAL
35 #define DEBUG_OCM
36 //#define DEBUG_I2C
37 #define DEBUG_GPT
38 #define DEBUG_MAL
39 #define DEBUG_UIC
40 #define DEBUG_CLOCKS
41 //#define DEBUG_UNASSIGNED
42
43 /*****************************************************************************/
44 /* Generic PowerPC 405 processor instanciation */
45 CPUState *ppc405_init (const unsigned char *cpu_model,
46 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
47 uint32_t sysclk)
48 {
49 CPUState *env;
50 ppc_def_t *def;
51
52 /* init CPUs */
53 env = cpu_init();
54 qemu_register_reset(&cpu_ppc_reset, env);
55 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
56 ppc_find_by_name(cpu_model, &def);
57 if (def == NULL) {
58 cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",
59 cpu_model);
60 }
61 cpu_ppc_register(env, def);
62 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
63 cpu_clk->opaque = env;
64 /* Set time-base frequency to sysclk */
65 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
66 tb_clk->opaque = env;
67 ppc_dcr_init(env, NULL, NULL);
68
69 return env;
70 }
71
72 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
73 {
74 ram_addr_t bdloc;
75 int i, n;
76
77 /* We put the bd structure at the top of memory */
78 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
79 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
80 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
81 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
82 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
83 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
84 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
85 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
86 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
87 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
88 for (i = 0; i < 6; i++)
89 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
90 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
91 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
92 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
93 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
94 for (i = 0; i < 4; i++)
95 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
96 for (i = 0; i < 32; i++)
97 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
98 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
99 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
100 for (i = 0; i < 6; i++)
101 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
102 n = 0x6A;
103 if (env->spr[SPR_PVR] == CPU_PPC_405EP) {
104 for (i = 0; i < 6; i++)
105 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
106 }
107 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
108 n += 4;
109 for (i = 0; i < 2; i++) {
110 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
111 n += 4;
112 }
113
114 return bdloc;
115 }
116
117 /*****************************************************************************/
118 /* Shared peripherals */
119
120 /*****************************************************************************/
121 /* Fake device used to map multiple devices in a single memory page */
122 #define MMIO_AREA_BITS 8
123 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
124 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
125 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
126 struct ppc4xx_mmio_t {
127 target_phys_addr_t base;
128 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
129 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
130 void *opaque[MMIO_AREA_NB];
131 };
132
133 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
134 {
135 #ifdef DEBUG_UNASSIGNED
136 ppc4xx_mmio_t *mmio;
137
138 mmio = opaque;
139 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
140 addr, mmio->base);
141 #endif
142
143 return 0;
144 }
145
146 static void unassigned_mmio_writeb (void *opaque,
147 target_phys_addr_t addr, uint32_t val)
148 {
149 #ifdef DEBUG_UNASSIGNED
150 ppc4xx_mmio_t *mmio;
151
152 mmio = opaque;
153 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
154 addr, val, mmio->base);
155 #endif
156 }
157
158 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
159 unassigned_mmio_readb,
160 unassigned_mmio_readb,
161 unassigned_mmio_readb,
162 };
163
164 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
165 unassigned_mmio_writeb,
166 unassigned_mmio_writeb,
167 unassigned_mmio_writeb,
168 };
169
170 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
171 target_phys_addr_t addr, int len)
172 {
173 CPUReadMemoryFunc **mem_read;
174 uint32_t ret;
175 int idx;
176
177 idx = MMIO_IDX(addr - mmio->base);
178 #if defined(DEBUG_MMIO)
179 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
180 mmio, len, addr, idx);
181 #endif
182 mem_read = mmio->mem_read[idx];
183 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
184
185 return ret;
186 }
187
188 static void mmio_writelen (ppc4xx_mmio_t *mmio,
189 target_phys_addr_t addr, uint32_t value, int len)
190 {
191 CPUWriteMemoryFunc **mem_write;
192 int idx;
193
194 idx = MMIO_IDX(addr - mmio->base);
195 #if defined(DEBUG_MMIO)
196 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
197 mmio, len, addr, idx, value);
198 #endif
199 mem_write = mmio->mem_write[idx];
200 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
201 }
202
203 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
204 {
205 #if defined(DEBUG_MMIO)
206 printf("%s: addr " PADDRX "\n", __func__, addr);
207 #endif
208
209 return mmio_readlen(opaque, addr, 0);
210 }
211
212 static void mmio_writeb (void *opaque,
213 target_phys_addr_t addr, uint32_t value)
214 {
215 #if defined(DEBUG_MMIO)
216 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
217 #endif
218 mmio_writelen(opaque, addr, value, 0);
219 }
220
221 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
222 {
223 #if defined(DEBUG_MMIO)
224 printf("%s: addr " PADDRX "\n", __func__, addr);
225 #endif
226
227 return mmio_readlen(opaque, addr, 1);
228 }
229
230 static void mmio_writew (void *opaque,
231 target_phys_addr_t addr, uint32_t value)
232 {
233 #if defined(DEBUG_MMIO)
234 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
235 #endif
236 mmio_writelen(opaque, addr, value, 1);
237 }
238
239 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
240 {
241 #if defined(DEBUG_MMIO)
242 printf("%s: addr " PADDRX "\n", __func__, addr);
243 #endif
244
245 return mmio_readlen(opaque, addr, 2);
246 }
247
248 static void mmio_writel (void *opaque,
249 target_phys_addr_t addr, uint32_t value)
250 {
251 #if defined(DEBUG_MMIO)
252 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
253 #endif
254 mmio_writelen(opaque, addr, value, 2);
255 }
256
257 static CPUReadMemoryFunc *mmio_read[] = {
258 &mmio_readb,
259 &mmio_readw,
260 &mmio_readl,
261 };
262
263 static CPUWriteMemoryFunc *mmio_write[] = {
264 &mmio_writeb,
265 &mmio_writew,
266 &mmio_writel,
267 };
268
269 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
270 target_phys_addr_t offset, uint32_t len,
271 CPUReadMemoryFunc **mem_read,
272 CPUWriteMemoryFunc **mem_write, void *opaque)
273 {
274 uint32_t end;
275 int idx, eidx;
276
277 if ((offset + len) > TARGET_PAGE_SIZE)
278 return -1;
279 idx = MMIO_IDX(offset);
280 end = offset + len - 1;
281 eidx = MMIO_IDX(end);
282 #if defined(DEBUG_MMIO)
283 printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
284 end, idx, eidx);
285 #endif
286 for (; idx <= eidx; idx++) {
287 mmio->mem_read[idx] = mem_read;
288 mmio->mem_write[idx] = mem_write;
289 mmio->opaque[idx] = opaque;
290 }
291
292 return 0;
293 }
294
295 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
296 {
297 ppc4xx_mmio_t *mmio;
298 int mmio_memory;
299
300 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
301 if (mmio != NULL) {
302 mmio->base = base;
303 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
304 #if defined(DEBUG_MMIO)
305 printf("%s: %p base %08x len %08x %d\n", __func__,
306 mmio, base, TARGET_PAGE_SIZE, mmio_memory);
307 #endif
308 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
309 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
310 unassigned_mmio_read, unassigned_mmio_write,
311 mmio);
312 }
313
314 return mmio;
315 }
316
317 /*****************************************************************************/
318 /* Peripheral local bus arbitrer */
319 enum {
320 PLB0_BESR = 0x084,
321 PLB0_BEAR = 0x086,
322 PLB0_ACR = 0x087,
323 };
324
325 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
326 struct ppc4xx_plb_t {
327 uint32_t acr;
328 uint32_t bear;
329 uint32_t besr;
330 };
331
332 static target_ulong dcr_read_plb (void *opaque, int dcrn)
333 {
334 ppc4xx_plb_t *plb;
335 target_ulong ret;
336
337 plb = opaque;
338 switch (dcrn) {
339 case PLB0_ACR:
340 ret = plb->acr;
341 break;
342 case PLB0_BEAR:
343 ret = plb->bear;
344 break;
345 case PLB0_BESR:
346 ret = plb->besr;
347 break;
348 default:
349 /* Avoid gcc warning */
350 ret = 0;
351 break;
352 }
353
354 return ret;
355 }
356
357 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
358 {
359 ppc4xx_plb_t *plb;
360
361 plb = opaque;
362 switch (dcrn) {
363 case PLB0_ACR:
364 /* We don't care about the actual parameters written as
365 * we don't manage any priorities on the bus
366 */
367 plb->acr = val & 0xF8000000;
368 break;
369 case PLB0_BEAR:
370 /* Read only */
371 break;
372 case PLB0_BESR:
373 /* Write-clear */
374 plb->besr &= ~val;
375 break;
376 }
377 }
378
379 static void ppc4xx_plb_reset (void *opaque)
380 {
381 ppc4xx_plb_t *plb;
382
383 plb = opaque;
384 plb->acr = 0x00000000;
385 plb->bear = 0x00000000;
386 plb->besr = 0x00000000;
387 }
388
389 void ppc4xx_plb_init (CPUState *env)
390 {
391 ppc4xx_plb_t *plb;
392
393 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
394 if (plb != NULL) {
395 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
396 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
397 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
398 ppc4xx_plb_reset(plb);
399 qemu_register_reset(ppc4xx_plb_reset, plb);
400 }
401 }
402
403 /*****************************************************************************/
404 /* PLB to OPB bridge */
405 enum {
406 POB0_BESR0 = 0x0A0,
407 POB0_BESR1 = 0x0A2,
408 POB0_BEAR = 0x0A4,
409 };
410
411 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
412 struct ppc4xx_pob_t {
413 uint32_t bear;
414 uint32_t besr[2];
415 };
416
417 static target_ulong dcr_read_pob (void *opaque, int dcrn)
418 {
419 ppc4xx_pob_t *pob;
420 target_ulong ret;
421
422 pob = opaque;
423 switch (dcrn) {
424 case POB0_BEAR:
425 ret = pob->bear;
426 break;
427 case POB0_BESR0:
428 case POB0_BESR1:
429 ret = pob->besr[dcrn - POB0_BESR0];
430 break;
431 default:
432 /* Avoid gcc warning */
433 ret = 0;
434 break;
435 }
436
437 return ret;
438 }
439
440 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
441 {
442 ppc4xx_pob_t *pob;
443
444 pob = opaque;
445 switch (dcrn) {
446 case POB0_BEAR:
447 /* Read only */
448 break;
449 case POB0_BESR0:
450 case POB0_BESR1:
451 /* Write-clear */
452 pob->besr[dcrn - POB0_BESR0] &= ~val;
453 break;
454 }
455 }
456
457 static void ppc4xx_pob_reset (void *opaque)
458 {
459 ppc4xx_pob_t *pob;
460
461 pob = opaque;
462 /* No error */
463 pob->bear = 0x00000000;
464 pob->besr[0] = 0x0000000;
465 pob->besr[1] = 0x0000000;
466 }
467
468 void ppc4xx_pob_init (CPUState *env)
469 {
470 ppc4xx_pob_t *pob;
471
472 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
473 if (pob != NULL) {
474 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
475 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
476 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
477 qemu_register_reset(ppc4xx_pob_reset, pob);
478 ppc4xx_pob_reset(env);
479 }
480 }
481
482 /*****************************************************************************/
483 /* OPB arbitrer */
484 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
485 struct ppc4xx_opba_t {
486 target_phys_addr_t base;
487 uint8_t cr;
488 uint8_t pr;
489 };
490
491 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
492 {
493 ppc4xx_opba_t *opba;
494 uint32_t ret;
495
496 #ifdef DEBUG_OPBA
497 printf("%s: addr " PADDRX "\n", __func__, addr);
498 #endif
499 opba = opaque;
500 switch (addr - opba->base) {
501 case 0x00:
502 ret = opba->cr;
503 break;
504 case 0x01:
505 ret = opba->pr;
506 break;
507 default:
508 ret = 0x00;
509 break;
510 }
511
512 return ret;
513 }
514
515 static void opba_writeb (void *opaque,
516 target_phys_addr_t addr, uint32_t value)
517 {
518 ppc4xx_opba_t *opba;
519
520 #ifdef DEBUG_OPBA
521 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
522 #endif
523 opba = opaque;
524 switch (addr - opba->base) {
525 case 0x00:
526 opba->cr = value & 0xF8;
527 break;
528 case 0x01:
529 opba->pr = value & 0xFF;
530 break;
531 default:
532 break;
533 }
534 }
535
536 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
537 {
538 uint32_t ret;
539
540 #ifdef DEBUG_OPBA
541 printf("%s: addr " PADDRX "\n", __func__, addr);
542 #endif
543 ret = opba_readb(opaque, addr) << 8;
544 ret |= opba_readb(opaque, addr + 1);
545
546 return ret;
547 }
548
549 static void opba_writew (void *opaque,
550 target_phys_addr_t addr, uint32_t value)
551 {
552 #ifdef DEBUG_OPBA
553 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
554 #endif
555 opba_writeb(opaque, addr, value >> 8);
556 opba_writeb(opaque, addr + 1, value);
557 }
558
559 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
560 {
561 uint32_t ret;
562
563 #ifdef DEBUG_OPBA
564 printf("%s: addr " PADDRX "\n", __func__, addr);
565 #endif
566 ret = opba_readb(opaque, addr) << 24;
567 ret |= opba_readb(opaque, addr + 1) << 16;
568
569 return ret;
570 }
571
572 static void opba_writel (void *opaque,
573 target_phys_addr_t addr, uint32_t value)
574 {
575 #ifdef DEBUG_OPBA
576 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
577 #endif
578 opba_writeb(opaque, addr, value >> 24);
579 opba_writeb(opaque, addr + 1, value >> 16);
580 }
581
582 static CPUReadMemoryFunc *opba_read[] = {
583 &opba_readb,
584 &opba_readw,
585 &opba_readl,
586 };
587
588 static CPUWriteMemoryFunc *opba_write[] = {
589 &opba_writeb,
590 &opba_writew,
591 &opba_writel,
592 };
593
594 static void ppc4xx_opba_reset (void *opaque)
595 {
596 ppc4xx_opba_t *opba;
597
598 opba = opaque;
599 opba->cr = 0x00; /* No dynamic priorities - park disabled */
600 opba->pr = 0x11;
601 }
602
603 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
604 target_phys_addr_t offset)
605 {
606 ppc4xx_opba_t *opba;
607
608 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
609 if (opba != NULL) {
610 opba->base = offset;
611 #ifdef DEBUG_OPBA
612 printf("%s: offset=" PADDRX "\n", __func__, offset);
613 #endif
614 ppc4xx_mmio_register(env, mmio, offset, 0x002,
615 opba_read, opba_write, opba);
616 qemu_register_reset(ppc4xx_opba_reset, opba);
617 ppc4xx_opba_reset(opba);
618 }
619 }
620
621 /*****************************************************************************/
622 /* "Universal" Interrupt controller */
623 enum {
624 DCR_UICSR = 0x000,
625 DCR_UICSRS = 0x001,
626 DCR_UICER = 0x002,
627 DCR_UICCR = 0x003,
628 DCR_UICPR = 0x004,
629 DCR_UICTR = 0x005,
630 DCR_UICMSR = 0x006,
631 DCR_UICVR = 0x007,
632 DCR_UICVCR = 0x008,
633 DCR_UICMAX = 0x009,
634 };
635
636 #define UIC_MAX_IRQ 32
637 typedef struct ppcuic_t ppcuic_t;
638 struct ppcuic_t {
639 uint32_t dcr_base;
640 int use_vectors;
641 uint32_t uicsr; /* Status register */
642 uint32_t uicer; /* Enable register */
643 uint32_t uiccr; /* Critical register */
644 uint32_t uicpr; /* Polarity register */
645 uint32_t uictr; /* Triggering register */
646 uint32_t uicvcr; /* Vector configuration register */
647 uint32_t uicvr;
648 qemu_irq *irqs;
649 };
650
651 static void ppcuic_trigger_irq (ppcuic_t *uic)
652 {
653 uint32_t ir, cr;
654 int start, end, inc, i;
655
656 /* Trigger interrupt if any is pending */
657 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
658 cr = uic->uicsr & uic->uicer & uic->uiccr;
659 #ifdef DEBUG_UIC
660 if (loglevel & CPU_LOG_INT) {
661 fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"
662 " %08x ir %08x cr %08x\n", __func__,
663 uic->uicsr, uic->uicer, uic->uiccr,
664 uic->uicsr & uic->uicer, ir, cr);
665 }
666 #endif
667 if (ir != 0x0000000) {
668 #ifdef DEBUG_UIC
669 if (loglevel & CPU_LOG_INT) {
670 fprintf(logfile, "Raise UIC interrupt\n");
671 }
672 #endif
673 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
674 } else {
675 #ifdef DEBUG_UIC
676 if (loglevel & CPU_LOG_INT) {
677 fprintf(logfile, "Lower UIC interrupt\n");
678 }
679 #endif
680 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
681 }
682 /* Trigger critical interrupt if any is pending and update vector */
683 if (cr != 0x0000000) {
684 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
685 if (uic->use_vectors) {
686 /* Compute critical IRQ vector */
687 if (uic->uicvcr & 1) {
688 start = 31;
689 end = 0;
690 inc = -1;
691 } else {
692 start = 0;
693 end = 31;
694 inc = 1;
695 }
696 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
697 for (i = start; i <= end; i += inc) {
698 if (cr & (1 << i)) {
699 uic->uicvr += (i - start) * 512 * inc;
700 break;
701 }
702 }
703 }
704 #ifdef DEBUG_UIC
705 if (loglevel & CPU_LOG_INT) {
706 fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",
707 uic->uicvr);
708 }
709 #endif
710 } else {
711 #ifdef DEBUG_UIC
712 if (loglevel & CPU_LOG_INT) {
713 fprintf(logfile, "Lower UIC critical interrupt\n");
714 }
715 #endif
716 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
717 uic->uicvr = 0x00000000;
718 }
719 }
720
721 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
722 {
723 ppcuic_t *uic;
724 uint32_t mask, sr;
725
726 uic = opaque;
727 mask = 1 << irq_num;
728 #ifdef DEBUG_UIC
729 if (loglevel & CPU_LOG_INT) {
730 fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "
731 "%08x\n", __func__, irq_num, level,
732 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
733 }
734 #endif
735 if (irq_num < 0 || irq_num > 31)
736 return;
737 sr = uic->uicsr;
738 if (!(uic->uicpr & mask)) {
739 /* Negatively asserted IRQ */
740 level = level == 0 ? 1 : 0;
741 }
742 /* Update status register */
743 if (uic->uictr & mask) {
744 /* Edge sensitive interrupt */
745 if (level == 1)
746 uic->uicsr |= mask;
747 } else {
748 /* Level sensitive interrupt */
749 if (level == 1)
750 uic->uicsr |= mask;
751 else
752 uic->uicsr &= ~mask;
753 }
754 #ifdef DEBUG_UIC
755 if (loglevel & CPU_LOG_INT) {
756 fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,
757 irq_num, level, uic->uicsr, sr);
758 }
759 #endif
760 if (sr != uic->uicsr)
761 ppcuic_trigger_irq(uic);
762 }
763
764 static target_ulong dcr_read_uic (void *opaque, int dcrn)
765 {
766 ppcuic_t *uic;
767 target_ulong ret;
768
769 uic = opaque;
770 dcrn -= uic->dcr_base;
771 switch (dcrn) {
772 case DCR_UICSR:
773 case DCR_UICSRS:
774 ret = uic->uicsr;
775 break;
776 case DCR_UICER:
777 ret = uic->uicer;
778 break;
779 case DCR_UICCR:
780 ret = uic->uiccr;
781 break;
782 case DCR_UICPR:
783 ret = uic->uicpr;
784 break;
785 case DCR_UICTR:
786 ret = uic->uictr;
787 break;
788 case DCR_UICMSR:
789 ret = uic->uicsr & uic->uicer;
790 break;
791 case DCR_UICVR:
792 if (!uic->use_vectors)
793 goto no_read;
794 ret = uic->uicvr;
795 break;
796 case DCR_UICVCR:
797 if (!uic->use_vectors)
798 goto no_read;
799 ret = uic->uicvcr;
800 break;
801 default:
802 no_read:
803 ret = 0x00000000;
804 break;
805 }
806
807 return ret;
808 }
809
810 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
811 {
812 ppcuic_t *uic;
813
814 uic = opaque;
815 dcrn -= uic->dcr_base;
816 #ifdef DEBUG_UIC
817 if (loglevel & CPU_LOG_INT) {
818 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
819 }
820 #endif
821 switch (dcrn) {
822 case DCR_UICSR:
823 uic->uicsr &= ~val;
824 ppcuic_trigger_irq(uic);
825 break;
826 case DCR_UICSRS:
827 uic->uicsr |= val;
828 ppcuic_trigger_irq(uic);
829 break;
830 case DCR_UICER:
831 uic->uicer = val;
832 ppcuic_trigger_irq(uic);
833 break;
834 case DCR_UICCR:
835 uic->uiccr = val;
836 ppcuic_trigger_irq(uic);
837 break;
838 case DCR_UICPR:
839 uic->uicpr = val;
840 ppcuic_trigger_irq(uic);
841 break;
842 case DCR_UICTR:
843 uic->uictr = val;
844 ppcuic_trigger_irq(uic);
845 break;
846 case DCR_UICMSR:
847 break;
848 case DCR_UICVR:
849 break;
850 case DCR_UICVCR:
851 uic->uicvcr = val & 0xFFFFFFFD;
852 ppcuic_trigger_irq(uic);
853 break;
854 }
855 }
856
857 static void ppcuic_reset (void *opaque)
858 {
859 ppcuic_t *uic;
860
861 uic = opaque;
862 uic->uiccr = 0x00000000;
863 uic->uicer = 0x00000000;
864 uic->uicpr = 0x00000000;
865 uic->uicsr = 0x00000000;
866 uic->uictr = 0x00000000;
867 if (uic->use_vectors) {
868 uic->uicvcr = 0x00000000;
869 uic->uicvr = 0x0000000;
870 }
871 }
872
873 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
874 uint32_t dcr_base, int has_ssr, int has_vr)
875 {
876 ppcuic_t *uic;
877 int i;
878
879 uic = qemu_mallocz(sizeof(ppcuic_t));
880 if (uic != NULL) {
881 uic->dcr_base = dcr_base;
882 uic->irqs = irqs;
883 if (has_vr)
884 uic->use_vectors = 1;
885 for (i = 0; i < DCR_UICMAX; i++) {
886 ppc_dcr_register(env, dcr_base + i, uic,
887 &dcr_read_uic, &dcr_write_uic);
888 }
889 qemu_register_reset(ppcuic_reset, uic);
890 ppcuic_reset(uic);
891 }
892
893 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
894 }
895
896 /*****************************************************************************/
897 /* Code decompression controller */
898 /* XXX: TODO */
899
900 /*****************************************************************************/
901 /* SDRAM controller */
902 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
903 struct ppc4xx_sdram_t {
904 uint32_t addr;
905 int nbanks;
906 target_ulong ram_bases[4];
907 target_ulong ram_sizes[4];
908 uint32_t besr0;
909 uint32_t besr1;
910 uint32_t bear;
911 uint32_t cfg;
912 uint32_t status;
913 uint32_t rtr;
914 uint32_t pmit;
915 uint32_t bcr[4];
916 uint32_t tr;
917 uint32_t ecccfg;
918 uint32_t eccesr;
919 qemu_irq irq;
920 };
921
922 enum {
923 SDRAM0_CFGADDR = 0x010,
924 SDRAM0_CFGDATA = 0x011,
925 };
926
927 static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size)
928 {
929 uint32_t bcr;
930
931 switch (ram_size) {
932 case (4 * 1024 * 1024):
933 bcr = 0x00000000;
934 break;
935 case (8 * 1024 * 1024):
936 bcr = 0x00020000;
937 break;
938 case (16 * 1024 * 1024):
939 bcr = 0x00040000;
940 break;
941 case (32 * 1024 * 1024):
942 bcr = 0x00060000;
943 break;
944 case (64 * 1024 * 1024):
945 bcr = 0x00080000;
946 break;
947 case (128 * 1024 * 1024):
948 bcr = 0x000A0000;
949 break;
950 case (256 * 1024 * 1024):
951 bcr = 0x000C0000;
952 break;
953 default:
954 printf("%s: invalid RAM size " TARGET_FMT_ld "\n", __func__, ram_size);
955 return 0x00000000;
956 }
957 bcr |= ram_base & 0xFF800000;
958 bcr |= 1;
959
960 return bcr;
961 }
962
963 static inline target_ulong sdram_base (uint32_t bcr)
964 {
965 return bcr & 0xFF800000;
966 }
967
968 static target_ulong sdram_size (uint32_t bcr)
969 {
970 target_ulong size;
971 int sh;
972
973 sh = (bcr >> 17) & 0x7;
974 if (sh == 7)
975 size = -1;
976 else
977 size = (4 * 1024 * 1024) << sh;
978
979 return size;
980 }
981
982 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
983 {
984 if (*bcrp & 0x00000001) {
985 /* Unmap RAM */
986 #ifdef DEBUG_SDRAM
987 printf("%s: unmap RAM area " ADDRX " " ADDRX "\n", __func__,
988 sdram_base(*bcrp), sdram_size(*bcrp));
989 #endif
990 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
991 IO_MEM_UNASSIGNED);
992 }
993 *bcrp = bcr & 0xFFDEE001;
994 if (enabled && (bcr & 0x00000001)) {
995 #ifdef DEBUG_SDRAM
996 printf("%s: Map RAM area " ADDRX " " ADDRX "\n", __func__,
997 sdram_base(bcr), sdram_size(bcr));
998 #endif
999 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
1000 sdram_base(bcr) | IO_MEM_RAM);
1001 }
1002 }
1003
1004 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
1005 {
1006 int i;
1007
1008 for (i = 0; i < sdram->nbanks; i++) {
1009 if (sdram->ram_sizes[i] != 0) {
1010 sdram_set_bcr(&sdram->bcr[i],
1011 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
1012 1);
1013 } else {
1014 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
1015 }
1016 }
1017 }
1018
1019 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
1020 {
1021 int i;
1022
1023 for (i = 0; i < sdram->nbanks; i++) {
1024 #ifdef DEBUG_SDRAM
1025 printf("%s: Unmap RAM area " ADDRX " " ADDRX "\n", __func__,
1026 sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
1027 #endif
1028 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
1029 sdram_size(sdram->bcr[i]),
1030 IO_MEM_UNASSIGNED);
1031 }
1032 }
1033
1034 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
1035 {
1036 ppc4xx_sdram_t *sdram;
1037 target_ulong ret;
1038
1039 sdram = opaque;
1040 switch (dcrn) {
1041 case SDRAM0_CFGADDR:
1042 ret = sdram->addr;
1043 break;
1044 case SDRAM0_CFGDATA:
1045 switch (sdram->addr) {
1046 case 0x00: /* SDRAM_BESR0 */
1047 ret = sdram->besr0;
1048 break;
1049 case 0x08: /* SDRAM_BESR1 */
1050 ret = sdram->besr1;
1051 break;
1052 case 0x10: /* SDRAM_BEAR */
1053 ret = sdram->bear;
1054 break;
1055 case 0x20: /* SDRAM_CFG */
1056 ret = sdram->cfg;
1057 break;
1058 case 0x24: /* SDRAM_STATUS */
1059 ret = sdram->status;
1060 break;
1061 case 0x30: /* SDRAM_RTR */
1062 ret = sdram->rtr;
1063 break;
1064 case 0x34: /* SDRAM_PMIT */
1065 ret = sdram->pmit;
1066 break;
1067 case 0x40: /* SDRAM_B0CR */
1068 ret = sdram->bcr[0];
1069 break;
1070 case 0x44: /* SDRAM_B1CR */
1071 ret = sdram->bcr[1];
1072 break;
1073 case 0x48: /* SDRAM_B2CR */
1074 ret = sdram->bcr[2];
1075 break;
1076 case 0x4C: /* SDRAM_B3CR */
1077 ret = sdram->bcr[3];
1078 break;
1079 case 0x80: /* SDRAM_TR */
1080 ret = -1; /* ? */
1081 break;
1082 case 0x94: /* SDRAM_ECCCFG */
1083 ret = sdram->ecccfg;
1084 break;
1085 case 0x98: /* SDRAM_ECCESR */
1086 ret = sdram->eccesr;
1087 break;
1088 default: /* Error */
1089 ret = -1;
1090 break;
1091 }
1092 break;
1093 default:
1094 /* Avoid gcc warning */
1095 ret = 0x00000000;
1096 break;
1097 }
1098
1099 return ret;
1100 }
1101
1102 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
1103 {
1104 ppc4xx_sdram_t *sdram;
1105
1106 sdram = opaque;
1107 switch (dcrn) {
1108 case SDRAM0_CFGADDR:
1109 sdram->addr = val;
1110 break;
1111 case SDRAM0_CFGDATA:
1112 switch (sdram->addr) {
1113 case 0x00: /* SDRAM_BESR0 */
1114 sdram->besr0 &= ~val;
1115 break;
1116 case 0x08: /* SDRAM_BESR1 */
1117 sdram->besr1 &= ~val;
1118 break;
1119 case 0x10: /* SDRAM_BEAR */
1120 sdram->bear = val;
1121 break;
1122 case 0x20: /* SDRAM_CFG */
1123 val &= 0xFFE00000;
1124 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
1125 #ifdef DEBUG_SDRAM
1126 printf("%s: enable SDRAM controller\n", __func__);
1127 #endif
1128 /* validate all RAM mappings */
1129 sdram_map_bcr(sdram);
1130 sdram->status &= ~0x80000000;
1131 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
1132 #ifdef DEBUG_SDRAM
1133 printf("%s: disable SDRAM controller\n", __func__);
1134 #endif
1135 /* invalidate all RAM mappings */
1136 sdram_unmap_bcr(sdram);
1137 sdram->status |= 0x80000000;
1138 }
1139 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
1140 sdram->status |= 0x40000000;
1141 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
1142 sdram->status &= ~0x40000000;
1143 sdram->cfg = val;
1144 break;
1145 case 0x24: /* SDRAM_STATUS */
1146 /* Read-only register */
1147 break;
1148 case 0x30: /* SDRAM_RTR */
1149 sdram->rtr = val & 0x3FF80000;
1150 break;
1151 case 0x34: /* SDRAM_PMIT */
1152 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
1153 break;
1154 case 0x40: /* SDRAM_B0CR */
1155 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
1156 break;
1157 case 0x44: /* SDRAM_B1CR */
1158 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
1159 break;
1160 case 0x48: /* SDRAM_B2CR */
1161 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
1162 break;
1163 case 0x4C: /* SDRAM_B3CR */
1164 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
1165 break;
1166 case 0x80: /* SDRAM_TR */
1167 sdram->tr = val & 0x018FC01F;
1168 break;
1169 case 0x94: /* SDRAM_ECCCFG */
1170 sdram->ecccfg = val & 0x00F00000;
1171 break;
1172 case 0x98: /* SDRAM_ECCESR */
1173 val &= 0xFFF0F000;
1174 if (sdram->eccesr == 0 && val != 0)
1175 qemu_irq_raise(sdram->irq);
1176 else if (sdram->eccesr != 0 && val == 0)
1177 qemu_irq_lower(sdram->irq);
1178 sdram->eccesr = val;
1179 break;
1180 default: /* Error */
1181 break;
1182 }
1183 break;
1184 }
1185 }
1186
1187 static void sdram_reset (void *opaque)
1188 {
1189 ppc4xx_sdram_t *sdram;
1190
1191 sdram = opaque;
1192 sdram->addr = 0x00000000;
1193 sdram->bear = 0x00000000;
1194 sdram->besr0 = 0x00000000; /* No error */
1195 sdram->besr1 = 0x00000000; /* No error */
1196 sdram->cfg = 0x00000000;
1197 sdram->ecccfg = 0x00000000; /* No ECC */
1198 sdram->eccesr = 0x00000000; /* No error */
1199 sdram->pmit = 0x07C00000;
1200 sdram->rtr = 0x05F00000;
1201 sdram->tr = 0x00854009;
1202 /* We pre-initialize RAM banks */
1203 sdram->status = 0x00000000;
1204 sdram->cfg = 0x00800000;
1205 sdram_unmap_bcr(sdram);
1206 }
1207
1208 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1209 target_ulong *ram_bases, target_ulong *ram_sizes,
1210 int do_init)
1211 {
1212 ppc4xx_sdram_t *sdram;
1213
1214 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
1215 if (sdram != NULL) {
1216 sdram->irq = irq;
1217 sdram->nbanks = nbanks;
1218 memset(sdram->ram_bases, 0, 4 * sizeof(target_ulong));
1219 memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_ulong));
1220 memset(sdram->ram_sizes, 0, 4 * sizeof(target_ulong));
1221 memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_ulong));
1222 sdram_reset(sdram);
1223 qemu_register_reset(&sdram_reset, sdram);
1224 ppc_dcr_register(env, SDRAM0_CFGADDR,
1225 sdram, &dcr_read_sdram, &dcr_write_sdram);
1226 ppc_dcr_register(env, SDRAM0_CFGDATA,
1227 sdram, &dcr_read_sdram, &dcr_write_sdram);
1228 if (do_init)
1229 sdram_map_bcr(sdram);
1230 }
1231 }
1232
1233 /*****************************************************************************/
1234 /* Peripheral controller */
1235 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
1236 struct ppc4xx_ebc_t {
1237 uint32_t addr;
1238 uint32_t bcr[8];
1239 uint32_t bap[8];
1240 uint32_t bear;
1241 uint32_t besr0;
1242 uint32_t besr1;
1243 uint32_t cfg;
1244 };
1245
1246 enum {
1247 EBC0_CFGADDR = 0x012,
1248 EBC0_CFGDATA = 0x013,
1249 };
1250
1251 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
1252 {
1253 ppc4xx_ebc_t *ebc;
1254 target_ulong ret;
1255
1256 ebc = opaque;
1257 switch (dcrn) {
1258 case EBC0_CFGADDR:
1259 ret = ebc->addr;
1260 break;
1261 case EBC0_CFGDATA:
1262 switch (ebc->addr) {
1263 case 0x00: /* B0CR */
1264 ret = ebc->bcr[0];
1265 break;
1266 case 0x01: /* B1CR */
1267 ret = ebc->bcr[1];
1268 break;
1269 case 0x02: /* B2CR */
1270 ret = ebc->bcr[2];
1271 break;
1272 case 0x03: /* B3CR */
1273 ret = ebc->bcr[3];
1274 break;
1275 case 0x04: /* B4CR */
1276 ret = ebc->bcr[4];
1277 break;
1278 case 0x05: /* B5CR */
1279 ret = ebc->bcr[5];
1280 break;
1281 case 0x06: /* B6CR */
1282 ret = ebc->bcr[6];
1283 break;
1284 case 0x07: /* B7CR */
1285 ret = ebc->bcr[7];
1286 break;
1287 case 0x10: /* B0AP */
1288 ret = ebc->bap[0];
1289 break;
1290 case 0x11: /* B1AP */
1291 ret = ebc->bap[1];
1292 break;
1293 case 0x12: /* B2AP */
1294 ret = ebc->bap[2];
1295 break;
1296 case 0x13: /* B3AP */
1297 ret = ebc->bap[3];
1298 break;
1299 case 0x14: /* B4AP */
1300 ret = ebc->bap[4];
1301 break;
1302 case 0x15: /* B5AP */
1303 ret = ebc->bap[5];
1304 break;
1305 case 0x16: /* B6AP */
1306 ret = ebc->bap[6];
1307 break;
1308 case 0x17: /* B7AP */
1309 ret = ebc->bap[7];
1310 break;
1311 case 0x20: /* BEAR */
1312 ret = ebc->bear;
1313 break;
1314 case 0x21: /* BESR0 */
1315 ret = ebc->besr0;
1316 break;
1317 case 0x22: /* BESR1 */
1318 ret = ebc->besr1;
1319 break;
1320 case 0x23: /* CFG */
1321 ret = ebc->cfg;
1322 break;
1323 default:
1324 ret = 0x00000000;
1325 break;
1326 }
1327 default:
1328 ret = 0x00000000;
1329 break;
1330 }
1331
1332 return ret;
1333 }
1334
1335 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
1336 {
1337 ppc4xx_ebc_t *ebc;
1338
1339 ebc = opaque;
1340 switch (dcrn) {
1341 case EBC0_CFGADDR:
1342 ebc->addr = val;
1343 break;
1344 case EBC0_CFGDATA:
1345 switch (ebc->addr) {
1346 case 0x00: /* B0CR */
1347 break;
1348 case 0x01: /* B1CR */
1349 break;
1350 case 0x02: /* B2CR */
1351 break;
1352 case 0x03: /* B3CR */
1353 break;
1354 case 0x04: /* B4CR */
1355 break;
1356 case 0x05: /* B5CR */
1357 break;
1358 case 0x06: /* B6CR */
1359 break;
1360 case 0x07: /* B7CR */
1361 break;
1362 case 0x10: /* B0AP */
1363 break;
1364 case 0x11: /* B1AP */
1365 break;
1366 case 0x12: /* B2AP */
1367 break;
1368 case 0x13: /* B3AP */
1369 break;
1370 case 0x14: /* B4AP */
1371 break;
1372 case 0x15: /* B5AP */
1373 break;
1374 case 0x16: /* B6AP */
1375 break;
1376 case 0x17: /* B7AP */
1377 break;
1378 case 0x20: /* BEAR */
1379 break;
1380 case 0x21: /* BESR0 */
1381 break;
1382 case 0x22: /* BESR1 */
1383 break;
1384 case 0x23: /* CFG */
1385 break;
1386 default:
1387 break;
1388 }
1389 break;
1390 default:
1391 break;
1392 }
1393 }
1394
1395 static void ebc_reset (void *opaque)
1396 {
1397 ppc4xx_ebc_t *ebc;
1398 int i;
1399
1400 ebc = opaque;
1401 ebc->addr = 0x00000000;
1402 ebc->bap[0] = 0x7F8FFE80;
1403 ebc->bcr[0] = 0xFFE28000;
1404 for (i = 0; i < 8; i++) {
1405 ebc->bap[i] = 0x00000000;
1406 ebc->bcr[i] = 0x00000000;
1407 }
1408 ebc->besr0 = 0x00000000;
1409 ebc->besr1 = 0x00000000;
1410 ebc->cfg = 0x80400000;
1411 }
1412
1413 void ppc405_ebc_init (CPUState *env)
1414 {
1415 ppc4xx_ebc_t *ebc;
1416
1417 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
1418 if (ebc != NULL) {
1419 ebc_reset(ebc);
1420 qemu_register_reset(&ebc_reset, ebc);
1421 ppc_dcr_register(env, EBC0_CFGADDR,
1422 ebc, &dcr_read_ebc, &dcr_write_ebc);
1423 ppc_dcr_register(env, EBC0_CFGDATA,
1424 ebc, &dcr_read_ebc, &dcr_write_ebc);
1425 }
1426 }
1427
1428 /*****************************************************************************/
1429 /* DMA controller */
1430 enum {
1431 DMA0_CR0 = 0x100,
1432 DMA0_CT0 = 0x101,
1433 DMA0_DA0 = 0x102,
1434 DMA0_SA0 = 0x103,
1435 DMA0_SG0 = 0x104,
1436 DMA0_CR1 = 0x108,
1437 DMA0_CT1 = 0x109,
1438 DMA0_DA1 = 0x10A,
1439 DMA0_SA1 = 0x10B,
1440 DMA0_SG1 = 0x10C,
1441 DMA0_CR2 = 0x110,
1442 DMA0_CT2 = 0x111,
1443 DMA0_DA2 = 0x112,
1444 DMA0_SA2 = 0x113,
1445 DMA0_SG2 = 0x114,
1446 DMA0_CR3 = 0x118,
1447 DMA0_CT3 = 0x119,
1448 DMA0_DA3 = 0x11A,
1449 DMA0_SA3 = 0x11B,
1450 DMA0_SG3 = 0x11C,
1451 DMA0_SR = 0x120,
1452 DMA0_SGC = 0x123,
1453 DMA0_SLP = 0x125,
1454 DMA0_POL = 0x126,
1455 };
1456
1457 typedef struct ppc405_dma_t ppc405_dma_t;
1458 struct ppc405_dma_t {
1459 qemu_irq irqs[4];
1460 uint32_t cr[4];
1461 uint32_t ct[4];
1462 uint32_t da[4];
1463 uint32_t sa[4];
1464 uint32_t sg[4];
1465 uint32_t sr;
1466 uint32_t sgc;
1467 uint32_t slp;
1468 uint32_t pol;
1469 };
1470
1471 static target_ulong dcr_read_dma (void *opaque, int dcrn)
1472 {
1473 ppc405_dma_t *dma;
1474
1475 dma = opaque;
1476
1477 return 0;
1478 }
1479
1480 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
1481 {
1482 ppc405_dma_t *dma;
1483
1484 dma = opaque;
1485 }
1486
1487 static void ppc405_dma_reset (void *opaque)
1488 {
1489 ppc405_dma_t *dma;
1490 int i;
1491
1492 dma = opaque;
1493 for (i = 0; i < 4; i++) {
1494 dma->cr[i] = 0x00000000;
1495 dma->ct[i] = 0x00000000;
1496 dma->da[i] = 0x00000000;
1497 dma->sa[i] = 0x00000000;
1498 dma->sg[i] = 0x00000000;
1499 }
1500 dma->sr = 0x00000000;
1501 dma->sgc = 0x00000000;
1502 dma->slp = 0x7C000000;
1503 dma->pol = 0x00000000;
1504 }
1505
1506 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1507 {
1508 ppc405_dma_t *dma;
1509
1510 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1511 if (dma != NULL) {
1512 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1513 ppc405_dma_reset(dma);
1514 qemu_register_reset(&ppc405_dma_reset, dma);
1515 ppc_dcr_register(env, DMA0_CR0,
1516 dma, &dcr_read_dma, &dcr_write_dma);
1517 ppc_dcr_register(env, DMA0_CT0,
1518 dma, &dcr_read_dma, &dcr_write_dma);
1519 ppc_dcr_register(env, DMA0_DA0,
1520 dma, &dcr_read_dma, &dcr_write_dma);
1521 ppc_dcr_register(env, DMA0_SA0,
1522 dma, &dcr_read_dma, &dcr_write_dma);
1523 ppc_dcr_register(env, DMA0_SG0,
1524 dma, &dcr_read_dma, &dcr_write_dma);
1525 ppc_dcr_register(env, DMA0_CR1,
1526 dma, &dcr_read_dma, &dcr_write_dma);
1527 ppc_dcr_register(env, DMA0_CT1,
1528 dma, &dcr_read_dma, &dcr_write_dma);
1529 ppc_dcr_register(env, DMA0_DA1,
1530 dma, &dcr_read_dma, &dcr_write_dma);
1531 ppc_dcr_register(env, DMA0_SA1,
1532 dma, &dcr_read_dma, &dcr_write_dma);
1533 ppc_dcr_register(env, DMA0_SG1,
1534 dma, &dcr_read_dma, &dcr_write_dma);
1535 ppc_dcr_register(env, DMA0_CR2,
1536 dma, &dcr_read_dma, &dcr_write_dma);
1537 ppc_dcr_register(env, DMA0_CT2,
1538 dma, &dcr_read_dma, &dcr_write_dma);
1539 ppc_dcr_register(env, DMA0_DA2,
1540 dma, &dcr_read_dma, &dcr_write_dma);
1541 ppc_dcr_register(env, DMA0_SA2,
1542 dma, &dcr_read_dma, &dcr_write_dma);
1543 ppc_dcr_register(env, DMA0_SG2,
1544 dma, &dcr_read_dma, &dcr_write_dma);
1545 ppc_dcr_register(env, DMA0_CR3,
1546 dma, &dcr_read_dma, &dcr_write_dma);
1547 ppc_dcr_register(env, DMA0_CT3,
1548 dma, &dcr_read_dma, &dcr_write_dma);
1549 ppc_dcr_register(env, DMA0_DA3,
1550 dma, &dcr_read_dma, &dcr_write_dma);
1551 ppc_dcr_register(env, DMA0_SA3,
1552 dma, &dcr_read_dma, &dcr_write_dma);
1553 ppc_dcr_register(env, DMA0_SG3,
1554 dma, &dcr_read_dma, &dcr_write_dma);
1555 ppc_dcr_register(env, DMA0_SR,
1556 dma, &dcr_read_dma, &dcr_write_dma);
1557 ppc_dcr_register(env, DMA0_SGC,
1558 dma, &dcr_read_dma, &dcr_write_dma);
1559 ppc_dcr_register(env, DMA0_SLP,
1560 dma, &dcr_read_dma, &dcr_write_dma);
1561 ppc_dcr_register(env, DMA0_POL,
1562 dma, &dcr_read_dma, &dcr_write_dma);
1563 }
1564 }
1565
1566 /*****************************************************************************/
1567 /* GPIO */
1568 typedef struct ppc405_gpio_t ppc405_gpio_t;
1569 struct ppc405_gpio_t {
1570 target_phys_addr_t base;
1571 uint32_t or;
1572 uint32_t tcr;
1573 uint32_t osrh;
1574 uint32_t osrl;
1575 uint32_t tsrh;
1576 uint32_t tsrl;
1577 uint32_t odr;
1578 uint32_t ir;
1579 uint32_t rr1;
1580 uint32_t isr1h;
1581 uint32_t isr1l;
1582 };
1583
1584 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1585 {
1586 ppc405_gpio_t *gpio;
1587
1588 gpio = opaque;
1589 #ifdef DEBUG_GPIO
1590 printf("%s: addr " PADDRX "\n", __func__, addr);
1591 #endif
1592
1593 return 0;
1594 }
1595
1596 static void ppc405_gpio_writeb (void *opaque,
1597 target_phys_addr_t addr, uint32_t value)
1598 {
1599 ppc405_gpio_t *gpio;
1600
1601 gpio = opaque;
1602 #ifdef DEBUG_GPIO
1603 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1604 #endif
1605 }
1606
1607 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1608 {
1609 ppc405_gpio_t *gpio;
1610
1611 gpio = opaque;
1612 #ifdef DEBUG_GPIO
1613 printf("%s: addr " PADDRX "\n", __func__, addr);
1614 #endif
1615
1616 return 0;
1617 }
1618
1619 static void ppc405_gpio_writew (void *opaque,
1620 target_phys_addr_t addr, uint32_t value)
1621 {
1622 ppc405_gpio_t *gpio;
1623
1624 gpio = opaque;
1625 #ifdef DEBUG_GPIO
1626 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1627 #endif
1628 }
1629
1630 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1631 {
1632 ppc405_gpio_t *gpio;
1633
1634 gpio = opaque;
1635 #ifdef DEBUG_GPIO
1636 printf("%s: addr " PADDRX "\n", __func__, addr);
1637 #endif
1638
1639 return 0;
1640 }
1641
1642 static void ppc405_gpio_writel (void *opaque,
1643 target_phys_addr_t addr, uint32_t value)
1644 {
1645 ppc405_gpio_t *gpio;
1646
1647 gpio = opaque;
1648 #ifdef DEBUG_GPIO
1649 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1650 #endif
1651 }
1652
1653 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1654 &ppc405_gpio_readb,
1655 &ppc405_gpio_readw,
1656 &ppc405_gpio_readl,
1657 };
1658
1659 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1660 &ppc405_gpio_writeb,
1661 &ppc405_gpio_writew,
1662 &ppc405_gpio_writel,
1663 };
1664
1665 static void ppc405_gpio_reset (void *opaque)
1666 {
1667 ppc405_gpio_t *gpio;
1668
1669 gpio = opaque;
1670 }
1671
1672 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1673 target_phys_addr_t offset)
1674 {
1675 ppc405_gpio_t *gpio;
1676
1677 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1678 if (gpio != NULL) {
1679 gpio->base = offset;
1680 ppc405_gpio_reset(gpio);
1681 qemu_register_reset(&ppc405_gpio_reset, gpio);
1682 #ifdef DEBUG_GPIO
1683 printf("%s: offset=" PADDRX "\n", __func__, offset);
1684 #endif
1685 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1686 ppc405_gpio_read, ppc405_gpio_write, gpio);
1687 }
1688 }
1689
1690 /*****************************************************************************/
1691 /* Serial ports */
1692 static CPUReadMemoryFunc *serial_mm_read[] = {
1693 &serial_mm_readb,
1694 &serial_mm_readw,
1695 &serial_mm_readl,
1696 };
1697
1698 static CPUWriteMemoryFunc *serial_mm_write[] = {
1699 &serial_mm_writeb,
1700 &serial_mm_writew,
1701 &serial_mm_writel,
1702 };
1703
1704 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1705 target_phys_addr_t offset, qemu_irq irq,
1706 CharDriverState *chr)
1707 {
1708 void *serial;
1709
1710 #ifdef DEBUG_SERIAL
1711 printf("%s: offset=" PADDRX "\n", __func__, offset);
1712 #endif
1713 serial = serial_mm_init(offset, 0, irq, chr, 0);
1714 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1715 serial_mm_read, serial_mm_write, serial);
1716 }
1717
1718 /*****************************************************************************/
1719 /* On Chip Memory */
1720 enum {
1721 OCM0_ISARC = 0x018,
1722 OCM0_ISACNTL = 0x019,
1723 OCM0_DSARC = 0x01A,
1724 OCM0_DSACNTL = 0x01B,
1725 };
1726
1727 typedef struct ppc405_ocm_t ppc405_ocm_t;
1728 struct ppc405_ocm_t {
1729 target_ulong offset;
1730 uint32_t isarc;
1731 uint32_t isacntl;
1732 uint32_t dsarc;
1733 uint32_t dsacntl;
1734 };
1735
1736 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1737 uint32_t isarc, uint32_t isacntl,
1738 uint32_t dsarc, uint32_t dsacntl)
1739 {
1740 #ifdef DEBUG_OCM
1741 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1742 isarc, isacntl, dsarc, dsacntl,
1743 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1744 #endif
1745 if (ocm->isarc != isarc ||
1746 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1747 if (ocm->isacntl & 0x80000000) {
1748 /* Unmap previously assigned memory region */
1749 printf("OCM unmap ISA %08x\n", ocm->isarc);
1750 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1751 IO_MEM_UNASSIGNED);
1752 }
1753 if (isacntl & 0x80000000) {
1754 /* Map new instruction memory region */
1755 #ifdef DEBUG_OCM
1756 printf("OCM map ISA %08x\n", isarc);
1757 #endif
1758 cpu_register_physical_memory(isarc, 0x04000000,
1759 ocm->offset | IO_MEM_RAM);
1760 }
1761 }
1762 if (ocm->dsarc != dsarc ||
1763 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1764 if (ocm->dsacntl & 0x80000000) {
1765 /* Beware not to unmap the region we just mapped */
1766 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1767 /* Unmap previously assigned memory region */
1768 #ifdef DEBUG_OCM
1769 printf("OCM unmap DSA %08x\n", ocm->dsarc);
1770 #endif
1771 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1772 IO_MEM_UNASSIGNED);
1773 }
1774 }
1775 if (dsacntl & 0x80000000) {
1776 /* Beware not to remap the region we just mapped */
1777 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1778 /* Map new data memory region */
1779 #ifdef DEBUG_OCM
1780 printf("OCM map DSA %08x\n", dsarc);
1781 #endif
1782 cpu_register_physical_memory(dsarc, 0x04000000,
1783 ocm->offset | IO_MEM_RAM);
1784 }
1785 }
1786 }
1787 }
1788
1789 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1790 {
1791 ppc405_ocm_t *ocm;
1792 target_ulong ret;
1793
1794 ocm = opaque;
1795 switch (dcrn) {
1796 case OCM0_ISARC:
1797 ret = ocm->isarc;
1798 break;
1799 case OCM0_ISACNTL:
1800 ret = ocm->isacntl;
1801 break;
1802 case OCM0_DSARC:
1803 ret = ocm->dsarc;
1804 break;
1805 case OCM0_DSACNTL:
1806 ret = ocm->dsacntl;
1807 break;
1808 default:
1809 ret = 0;
1810 break;
1811 }
1812
1813 return ret;
1814 }
1815
1816 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1817 {
1818 ppc405_ocm_t *ocm;
1819 uint32_t isarc, dsarc, isacntl, dsacntl;
1820
1821 ocm = opaque;
1822 isarc = ocm->isarc;
1823 dsarc = ocm->dsarc;
1824 isacntl = ocm->isacntl;
1825 dsacntl = ocm->dsacntl;
1826 switch (dcrn) {
1827 case OCM0_ISARC:
1828 isarc = val & 0xFC000000;
1829 break;
1830 case OCM0_ISACNTL:
1831 isacntl = val & 0xC0000000;
1832 break;
1833 case OCM0_DSARC:
1834 isarc = val & 0xFC000000;
1835 break;
1836 case OCM0_DSACNTL:
1837 isacntl = val & 0xC0000000;
1838 break;
1839 }
1840 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1841 ocm->isarc = isarc;
1842 ocm->dsarc = dsarc;
1843 ocm->isacntl = isacntl;
1844 ocm->dsacntl = dsacntl;
1845 }
1846
1847 static void ocm_reset (void *opaque)
1848 {
1849 ppc405_ocm_t *ocm;
1850 uint32_t isarc, dsarc, isacntl, dsacntl;
1851
1852 ocm = opaque;
1853 isarc = 0x00000000;
1854 isacntl = 0x00000000;
1855 dsarc = 0x00000000;
1856 dsacntl = 0x00000000;
1857 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1858 ocm->isarc = isarc;
1859 ocm->dsarc = dsarc;
1860 ocm->isacntl = isacntl;
1861 ocm->dsacntl = dsacntl;
1862 }
1863
1864 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1865 {
1866 ppc405_ocm_t *ocm;
1867
1868 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1869 if (ocm != NULL) {
1870 ocm->offset = offset;
1871 ocm_reset(ocm);
1872 qemu_register_reset(&ocm_reset, ocm);
1873 ppc_dcr_register(env, OCM0_ISARC,
1874 ocm, &dcr_read_ocm, &dcr_write_ocm);
1875 ppc_dcr_register(env, OCM0_ISACNTL,
1876 ocm, &dcr_read_ocm, &dcr_write_ocm);
1877 ppc_dcr_register(env, OCM0_DSARC,
1878 ocm, &dcr_read_ocm, &dcr_write_ocm);
1879 ppc_dcr_register(env, OCM0_DSACNTL,
1880 ocm, &dcr_read_ocm, &dcr_write_ocm);
1881 }
1882 }
1883
1884 /*****************************************************************************/
1885 /* I2C controller */
1886 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1887 struct ppc4xx_i2c_t {
1888 target_phys_addr_t base;
1889 qemu_irq irq;
1890 uint8_t mdata;
1891 uint8_t lmadr;
1892 uint8_t hmadr;
1893 uint8_t cntl;
1894 uint8_t mdcntl;
1895 uint8_t sts;
1896 uint8_t extsts;
1897 uint8_t sdata;
1898 uint8_t lsadr;
1899 uint8_t hsadr;
1900 uint8_t clkdiv;
1901 uint8_t intrmsk;
1902 uint8_t xfrcnt;
1903 uint8_t xtcntlss;
1904 uint8_t directcntl;
1905 };
1906
1907 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1908 {
1909 ppc4xx_i2c_t *i2c;
1910 uint32_t ret;
1911
1912 #ifdef DEBUG_I2C
1913 printf("%s: addr " PADDRX "\n", __func__, addr);
1914 #endif
1915 i2c = opaque;
1916 switch (addr - i2c->base) {
1917 case 0x00:
1918 // i2c_readbyte(&i2c->mdata);
1919 ret = i2c->mdata;
1920 break;
1921 case 0x02:
1922 ret = i2c->sdata;
1923 break;
1924 case 0x04:
1925 ret = i2c->lmadr;
1926 break;
1927 case 0x05:
1928 ret = i2c->hmadr;
1929 break;
1930 case 0x06:
1931 ret = i2c->cntl;
1932 break;
1933 case 0x07:
1934 ret = i2c->mdcntl;
1935 break;
1936 case 0x08:
1937 ret = i2c->sts;
1938 break;
1939 case 0x09:
1940 ret = i2c->extsts;
1941 break;
1942 case 0x0A:
1943 ret = i2c->lsadr;
1944 break;
1945 case 0x0B:
1946 ret = i2c->hsadr;
1947 break;
1948 case 0x0C:
1949 ret = i2c->clkdiv;
1950 break;
1951 case 0x0D:
1952 ret = i2c->intrmsk;
1953 break;
1954 case 0x0E:
1955 ret = i2c->xfrcnt;
1956 break;
1957 case 0x0F:
1958 ret = i2c->xtcntlss;
1959 break;
1960 case 0x10:
1961 ret = i2c->directcntl;
1962 break;
1963 default:
1964 ret = 0x00;
1965 break;
1966 }
1967 #ifdef DEBUG_I2C
1968 printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret);
1969 #endif
1970
1971 return ret;
1972 }
1973
1974 static void ppc4xx_i2c_writeb (void *opaque,
1975 target_phys_addr_t addr, uint32_t value)
1976 {
1977 ppc4xx_i2c_t *i2c;
1978
1979 #ifdef DEBUG_I2C
1980 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
1981 #endif
1982 i2c = opaque;
1983 switch (addr - i2c->base) {
1984 case 0x00:
1985 i2c->mdata = value;
1986 // i2c_sendbyte(&i2c->mdata);
1987 break;
1988 case 0x02:
1989 i2c->sdata = value;
1990 break;
1991 case 0x04:
1992 i2c->lmadr = value;
1993 break;
1994 case 0x05:
1995 i2c->hmadr = value;
1996 break;
1997 case 0x06:
1998 i2c->cntl = value;
1999 break;
2000 case 0x07:
2001 i2c->mdcntl = value & 0xDF;
2002 break;
2003 case 0x08:
2004 i2c->sts &= ~(value & 0x0A);
2005 break;
2006 case 0x09:
2007 i2c->extsts &= ~(value & 0x8F);
2008 break;
2009 case 0x0A:
2010 i2c->lsadr = value;
2011 break;
2012 case 0x0B:
2013 i2c->hsadr = value;
2014 break;
2015 case 0x0C:
2016 i2c->clkdiv = value;
2017 break;
2018 case 0x0D:
2019 i2c->intrmsk = value;
2020 break;
2021 case 0x0E:
2022 i2c->xfrcnt = value & 0x77;
2023 break;
2024 case 0x0F:
2025 i2c->xtcntlss = value;
2026 break;
2027 case 0x10:
2028 i2c->directcntl = value & 0x7;
2029 break;
2030 }
2031 }
2032
2033 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
2034 {
2035 uint32_t ret;
2036
2037 #ifdef DEBUG_I2C
2038 printf("%s: addr " PADDRX "\n", __func__, addr);
2039 #endif
2040 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
2041 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
2042
2043 return ret;
2044 }
2045
2046 static void ppc4xx_i2c_writew (void *opaque,
2047 target_phys_addr_t addr, uint32_t value)
2048 {
2049 #ifdef DEBUG_I2C
2050 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2051 #endif
2052 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
2053 ppc4xx_i2c_writeb(opaque, addr + 1, value);
2054 }
2055
2056 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
2057 {
2058 uint32_t ret;
2059
2060 #ifdef DEBUG_I2C
2061 printf("%s: addr " PADDRX "\n", __func__, addr);
2062 #endif
2063 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
2064 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
2065 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
2066 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
2067
2068 return ret;
2069 }
2070
2071 static void ppc4xx_i2c_writel (void *opaque,
2072 target_phys_addr_t addr, uint32_t value)
2073 {
2074 #ifdef DEBUG_I2C
2075 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2076 #endif
2077 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
2078 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
2079 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
2080 ppc4xx_i2c_writeb(opaque, addr + 3, value);
2081 }
2082
2083 static CPUReadMemoryFunc *i2c_read[] = {
2084 &ppc4xx_i2c_readb,
2085 &ppc4xx_i2c_readw,
2086 &ppc4xx_i2c_readl,
2087 };
2088
2089 static CPUWriteMemoryFunc *i2c_write[] = {
2090 &ppc4xx_i2c_writeb,
2091 &ppc4xx_i2c_writew,
2092 &ppc4xx_i2c_writel,
2093 };
2094
2095 static void ppc4xx_i2c_reset (void *opaque)
2096 {
2097 ppc4xx_i2c_t *i2c;
2098
2099 i2c = opaque;
2100 i2c->mdata = 0x00;
2101 i2c->sdata = 0x00;
2102 i2c->cntl = 0x00;
2103 i2c->mdcntl = 0x00;
2104 i2c->sts = 0x00;
2105 i2c->extsts = 0x00;
2106 i2c->clkdiv = 0x00;
2107 i2c->xfrcnt = 0x00;
2108 i2c->directcntl = 0x0F;
2109 }
2110
2111 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
2112 target_phys_addr_t offset, qemu_irq irq)
2113 {
2114 ppc4xx_i2c_t *i2c;
2115
2116 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
2117 if (i2c != NULL) {
2118 i2c->base = offset;
2119 i2c->irq = irq;
2120 ppc4xx_i2c_reset(i2c);
2121 #ifdef DEBUG_I2C
2122 printf("%s: offset=" PADDRX "\n", __func__, offset);
2123 #endif
2124 ppc4xx_mmio_register(env, mmio, offset, 0x011,
2125 i2c_read, i2c_write, i2c);
2126 qemu_register_reset(ppc4xx_i2c_reset, i2c);
2127 }
2128 }
2129
2130 /*****************************************************************************/
2131 /* General purpose timers */
2132 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
2133 struct ppc4xx_gpt_t {
2134 target_phys_addr_t base;
2135 int64_t tb_offset;
2136 uint32_t tb_freq;
2137 struct QEMUTimer *timer;
2138 qemu_irq irqs[5];
2139 uint32_t oe;
2140 uint32_t ol;
2141 uint32_t im;
2142 uint32_t is;
2143 uint32_t ie;
2144 uint32_t comp[5];
2145 uint32_t mask[5];
2146 };
2147
2148 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
2149 {
2150 #ifdef DEBUG_GPT
2151 printf("%s: addr " PADDRX "\n", __func__, addr);
2152 #endif
2153 /* XXX: generate a bus fault */
2154 return -1;
2155 }
2156
2157 static void ppc4xx_gpt_writeb (void *opaque,
2158 target_phys_addr_t addr, uint32_t value)
2159 {
2160 #ifdef DEBUG_I2C
2161 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2162 #endif
2163 /* XXX: generate a bus fault */
2164 }
2165
2166 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
2167 {
2168 #ifdef DEBUG_GPT
2169 printf("%s: addr " PADDRX "\n", __func__, addr);
2170 #endif
2171 /* XXX: generate a bus fault */
2172 return -1;
2173 }
2174
2175 static void ppc4xx_gpt_writew (void *opaque,
2176 target_phys_addr_t addr, uint32_t value)
2177 {
2178 #ifdef DEBUG_I2C
2179 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2180 #endif
2181 /* XXX: generate a bus fault */
2182 }
2183
2184 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
2185 {
2186 /* XXX: TODO */
2187 return 0;
2188 }
2189
2190 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
2191 {
2192 /* XXX: TODO */
2193 }
2194
2195 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
2196 {
2197 uint32_t mask;
2198 int i;
2199
2200 mask = 0x80000000;
2201 for (i = 0; i < 5; i++) {
2202 if (gpt->oe & mask) {
2203 /* Output is enabled */
2204 if (ppc4xx_gpt_compare(gpt, i)) {
2205 /* Comparison is OK */
2206 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
2207 } else {
2208 /* Comparison is KO */
2209 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
2210 }
2211 }
2212 mask = mask >> 1;
2213 }
2214
2215 }
2216
2217 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
2218 {
2219 uint32_t mask;
2220 int i;
2221
2222 mask = 0x00008000;
2223 for (i = 0; i < 5; i++) {
2224 if (gpt->is & gpt->im & mask)
2225 qemu_irq_raise(gpt->irqs[i]);
2226 else
2227 qemu_irq_lower(gpt->irqs[i]);
2228 mask = mask >> 1;
2229 }
2230
2231 }
2232
2233 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
2234 {
2235 /* XXX: TODO */
2236 }
2237
2238 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
2239 {
2240 ppc4xx_gpt_t *gpt;
2241 uint32_t ret;
2242 int idx;
2243
2244 #ifdef DEBUG_GPT
2245 printf("%s: addr " PADDRX "\n", __func__, addr);
2246 #endif
2247 gpt = opaque;
2248 switch (addr - gpt->base) {
2249 case 0x00:
2250 /* Time base counter */
2251 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
2252 gpt->tb_freq, ticks_per_sec);
2253 break;
2254 case 0x10:
2255 /* Output enable */
2256 ret = gpt->oe;
2257 break;
2258 case 0x14:
2259 /* Output level */
2260 ret = gpt->ol;
2261 break;
2262 case 0x18:
2263 /* Interrupt mask */
2264 ret = gpt->im;
2265 break;
2266 case 0x1C:
2267 case 0x20:
2268 /* Interrupt status */
2269 ret = gpt->is;
2270 break;
2271 case 0x24:
2272 /* Interrupt enable */
2273 ret = gpt->ie;
2274 break;
2275 case 0x80 ... 0x90:
2276 /* Compare timer */
2277 idx = ((addr - gpt->base) - 0x80) >> 2;
2278 ret = gpt->comp[idx];
2279 break;
2280 case 0xC0 ... 0xD0:
2281 /* Compare mask */
2282 idx = ((addr - gpt->base) - 0xC0) >> 2;
2283 ret = gpt->mask[idx];
2284 break;
2285 default:
2286 ret = -1;
2287 break;
2288 }
2289
2290 return ret;
2291 }
2292
2293 static void ppc4xx_gpt_writel (void *opaque,
2294 target_phys_addr_t addr, uint32_t value)
2295 {
2296 ppc4xx_gpt_t *gpt;
2297 int idx;
2298
2299 #ifdef DEBUG_I2C
2300 printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
2301 #endif
2302 gpt = opaque;
2303 switch (addr - gpt->base) {
2304 case 0x00:
2305 /* Time base counter */
2306 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
2307 - qemu_get_clock(vm_clock);
2308 ppc4xx_gpt_compute_timer(gpt);
2309 break;
2310 case 0x10:
2311 /* Output enable */
2312 gpt->oe = value & 0xF8000000;
2313 ppc4xx_gpt_set_outputs(gpt);
2314 break;
2315 case 0x14:
2316 /* Output level */
2317 gpt->ol = value & 0xF8000000;
2318 ppc4xx_gpt_set_outputs(gpt);
2319 break;
2320 case 0x18:
2321 /* Interrupt mask */
2322 gpt->im = value & 0x0000F800;
2323 break;
2324 case 0x1C:
2325 /* Interrupt status set */
2326 gpt->is |= value & 0x0000F800;
2327 ppc4xx_gpt_set_irqs(gpt);
2328 break;
2329 case 0x20:
2330 /* Interrupt status clear */
2331 gpt->is &= ~(value & 0x0000F800);
2332 ppc4xx_gpt_set_irqs(gpt);
2333 break;
2334 case 0x24:
2335 /* Interrupt enable */
2336 gpt->ie = value & 0x0000F800;
2337 ppc4xx_gpt_set_irqs(gpt);
2338 break;
2339 case 0x80 ... 0x90:
2340 /* Compare timer */
2341 idx = ((addr - gpt->base) - 0x80) >> 2;
2342 gpt->comp[idx] = value & 0xF8000000;
2343 ppc4xx_gpt_compute_timer(gpt);
2344 break;
2345 case 0xC0 ... 0xD0:
2346 /* Compare mask */
2347 idx = ((addr - gpt->base) - 0xC0) >> 2;
2348 gpt->mask[idx] = value & 0xF8000000;
2349 ppc4xx_gpt_compute_timer(gpt);
2350 break;
2351 }
2352 }
2353
2354 static CPUReadMemoryFunc *gpt_read[] = {
2355 &ppc4xx_gpt_readb,
2356 &ppc4xx_gpt_readw,
2357 &ppc4xx_gpt_readl,
2358 };
2359
2360 static CPUWriteMemoryFunc *gpt_write[] = {
2361 &ppc4xx_gpt_writeb,
2362 &ppc4xx_gpt_writew,
2363 &ppc4xx_gpt_writel,
2364 };
2365
2366 static void ppc4xx_gpt_cb (void *opaque)
2367 {
2368 ppc4xx_gpt_t *gpt;
2369
2370 gpt = opaque;
2371 ppc4xx_gpt_set_irqs(gpt);
2372 ppc4xx_gpt_set_outputs(gpt);
2373 ppc4xx_gpt_compute_timer(gpt);
2374 }
2375
2376 static void ppc4xx_gpt_reset (void *opaque)
2377 {
2378 ppc4xx_gpt_t *gpt;
2379 int i;
2380
2381 gpt = opaque;
2382 qemu_del_timer(gpt->timer);
2383 gpt->oe = 0x00000000;
2384 gpt->ol = 0x00000000;
2385 gpt->im = 0x00000000;
2386 gpt->is = 0x00000000;
2387 gpt->ie = 0x00000000;
2388 for (i = 0; i < 5; i++) {
2389 gpt->comp[i] = 0x00000000;
2390 gpt->mask[i] = 0x00000000;
2391 }
2392 }
2393
2394 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
2395 target_phys_addr_t offset, qemu_irq irqs[5])
2396 {
2397 ppc4xx_gpt_t *gpt;
2398 int i;
2399
2400 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
2401 if (gpt != NULL) {
2402 gpt->base = offset;
2403 for (i = 0; i < 5; i++)
2404 gpt->irqs[i] = irqs[i];
2405 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
2406 ppc4xx_gpt_reset(gpt);
2407 #ifdef DEBUG_GPT
2408 printf("%s: offset=" PADDRX "\n", __func__, offset);
2409 #endif
2410 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
2411 gpt_read, gpt_write, gpt);
2412 qemu_register_reset(ppc4xx_gpt_reset, gpt);
2413 }
2414 }
2415
2416 /*****************************************************************************/
2417 /* MAL */
2418 enum {
2419 MAL0_CFG = 0x180,
2420 MAL0_ESR = 0x181,
2421 MAL0_IER = 0x182,
2422 MAL0_TXCASR = 0x184,
2423 MAL0_TXCARR = 0x185,
2424 MAL0_TXEOBISR = 0x186,
2425 MAL0_TXDEIR = 0x187,
2426 MAL0_RXCASR = 0x190,
2427 MAL0_RXCARR = 0x191,
2428 MAL0_RXEOBISR = 0x192,
2429 MAL0_RXDEIR = 0x193,
2430 MAL0_TXCTP0R = 0x1A0,
2431 MAL0_TXCTP1R = 0x1A1,
2432 MAL0_TXCTP2R = 0x1A2,
2433 MAL0_TXCTP3R = 0x1A3,
2434 MAL0_RXCTP0R = 0x1C0,
2435 MAL0_RXCTP1R = 0x1C1,
2436 MAL0_RCBS0 = 0x1E0,
2437 MAL0_RCBS1 = 0x1E1,
2438 };
2439
2440 typedef struct ppc40x_mal_t ppc40x_mal_t;
2441 struct ppc40x_mal_t {
2442 qemu_irq irqs[4];
2443 uint32_t cfg;
2444 uint32_t esr;
2445 uint32_t ier;
2446 uint32_t txcasr;
2447 uint32_t txcarr;
2448 uint32_t txeobisr;
2449 uint32_t txdeir;
2450 uint32_t rxcasr;
2451 uint32_t rxcarr;
2452 uint32_t rxeobisr;
2453 uint32_t rxdeir;
2454 uint32_t txctpr[4];
2455 uint32_t rxctpr[2];
2456 uint32_t rcbs[2];
2457 };
2458
2459 static void ppc40x_mal_reset (void *opaque);
2460
2461 static target_ulong dcr_read_mal (void *opaque, int dcrn)
2462 {
2463 ppc40x_mal_t *mal;
2464 target_ulong ret;
2465
2466 mal = opaque;
2467 switch (dcrn) {
2468 case MAL0_CFG:
2469 ret = mal->cfg;
2470 break;
2471 case MAL0_ESR:
2472 ret = mal->esr;
2473 break;
2474 case MAL0_IER:
2475 ret = mal->ier;
2476 break;
2477 case MAL0_TXCASR:
2478 ret = mal->txcasr;
2479 break;
2480 case MAL0_TXCARR:
2481 ret = mal->txcarr;
2482 break;
2483 case MAL0_TXEOBISR:
2484 ret = mal->txeobisr;
2485 break;
2486 case MAL0_TXDEIR:
2487 ret = mal->txdeir;
2488 break;
2489 case MAL0_RXCASR:
2490 ret = mal->rxcasr;
2491 break;
2492 case MAL0_RXCARR:
2493 ret = mal->rxcarr;
2494 break;
2495 case MAL0_RXEOBISR:
2496 ret = mal->rxeobisr;
2497 break;
2498 case MAL0_RXDEIR:
2499 ret = mal->rxdeir;
2500 break;
2501 case MAL0_TXCTP0R:
2502 ret = mal->txctpr[0];
2503 break;
2504 case MAL0_TXCTP1R:
2505 ret = mal->txctpr[1];
2506 break;
2507 case MAL0_TXCTP2R:
2508 ret = mal->txctpr[2];
2509 break;
2510 case MAL0_TXCTP3R:
2511 ret = mal->txctpr[3];
2512 break;
2513 case MAL0_RXCTP0R:
2514 ret = mal->rxctpr[0];
2515 break;
2516 case MAL0_RXCTP1R:
2517 ret = mal->rxctpr[1];
2518 break;
2519 case MAL0_RCBS0:
2520 ret = mal->rcbs[0];
2521 break;
2522 case MAL0_RCBS1:
2523 ret = mal->rcbs[1];
2524 break;
2525 default:
2526 ret = 0;
2527 break;
2528 }
2529
2530 return ret;
2531 }
2532
2533 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2534 {
2535 ppc40x_mal_t *mal;
2536 int idx;
2537
2538 mal = opaque;
2539 switch (dcrn) {
2540 case MAL0_CFG:
2541 if (val & 0x80000000)
2542 ppc40x_mal_reset(mal);
2543 mal->cfg = val & 0x00FFC087;
2544 break;
2545 case MAL0_ESR:
2546 /* Read/clear */
2547 mal->esr &= ~val;
2548 break;
2549 case MAL0_IER:
2550 mal->ier = val & 0x0000001F;
2551 break;
2552 case MAL0_TXCASR:
2553 mal->txcasr = val & 0xF0000000;
2554 break;
2555 case MAL0_TXCARR:
2556 mal->txcarr = val & 0xF0000000;
2557 break;
2558 case MAL0_TXEOBISR:
2559 /* Read/clear */
2560 mal->txeobisr &= ~val;
2561 break;
2562 case MAL0_TXDEIR:
2563 /* Read/clear */
2564 mal->txdeir &= ~val;
2565 break;
2566 case MAL0_RXCASR:
2567 mal->rxcasr = val & 0xC0000000;
2568 break;
2569 case MAL0_RXCARR:
2570 mal->rxcarr = val & 0xC0000000;
2571 break;
2572 case MAL0_RXEOBISR:
2573 /* Read/clear */
2574 mal->rxeobisr &= ~val;
2575 break;
2576 case MAL0_RXDEIR:
2577 /* Read/clear */
2578 mal->rxdeir &= ~val;
2579 break;
2580 case MAL0_TXCTP0R:
2581 idx = 0;
2582 goto update_tx_ptr;
2583 case MAL0_TXCTP1R:
2584 idx = 1;
2585 goto update_tx_ptr;
2586 case MAL0_TXCTP2R:
2587 idx = 2;
2588 goto update_tx_ptr;
2589 case MAL0_TXCTP3R:
2590 idx = 3;
2591 update_tx_ptr:
2592 mal->txctpr[idx] = val;
2593 break;
2594 case MAL0_RXCTP0R:
2595 idx = 0;
2596 goto update_rx_ptr;
2597 case MAL0_RXCTP1R:
2598 idx = 1;
2599 update_rx_ptr:
2600 mal->rxctpr[idx] = val;
2601 break;
2602 case MAL0_RCBS0:
2603 idx = 0;
2604 goto update_rx_size;
2605 case MAL0_RCBS1:
2606 idx = 1;
2607 update_rx_size:
2608 mal->rcbs[idx] = val & 0x000000FF;
2609 break;
2610 }
2611 }
2612
2613 static void ppc40x_mal_reset (void *opaque)
2614 {
2615 ppc40x_mal_t *mal;
2616
2617 mal = opaque;
2618 mal->cfg = 0x0007C000;
2619 mal->esr = 0x00000000;
2620 mal->ier = 0x00000000;
2621 mal->rxcasr = 0x00000000;
2622 mal->rxdeir = 0x00000000;
2623 mal->rxeobisr = 0x00000000;
2624 mal->txcasr = 0x00000000;
2625 mal->txdeir = 0x00000000;
2626 mal->txeobisr = 0x00000000;
2627 }
2628
2629 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2630 {
2631 ppc40x_mal_t *mal;
2632 int i;
2633
2634 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2635 if (mal != NULL) {
2636 for (i = 0; i < 4; i++)
2637 mal->irqs[i] = irqs[i];
2638 ppc40x_mal_reset(mal);
2639 qemu_register_reset(&ppc40x_mal_reset, mal);
2640 ppc_dcr_register(env, MAL0_CFG,
2641 mal, &dcr_read_mal, &dcr_write_mal);
2642 ppc_dcr_register(env, MAL0_ESR,
2643 mal, &dcr_read_mal, &dcr_write_mal);
2644 ppc_dcr_register(env, MAL0_IER,
2645 mal, &dcr_read_mal, &dcr_write_mal);
2646 ppc_dcr_register(env, MAL0_TXCASR,
2647 mal, &dcr_read_mal, &dcr_write_mal);
2648 ppc_dcr_register(env, MAL0_TXCARR,
2649 mal, &dcr_read_mal, &dcr_write_mal);
2650 ppc_dcr_register(env, MAL0_TXEOBISR,
2651 mal, &dcr_read_mal, &dcr_write_mal);
2652 ppc_dcr_register(env, MAL0_TXDEIR,
2653 mal, &dcr_read_mal, &dcr_write_mal);
2654 ppc_dcr_register(env, MAL0_RXCASR,
2655 mal, &dcr_read_mal, &dcr_write_mal);
2656 ppc_dcr_register(env, MAL0_RXCARR,
2657 mal, &dcr_read_mal, &dcr_write_mal);
2658 ppc_dcr_register(env, MAL0_RXEOBISR,
2659 mal, &dcr_read_mal, &dcr_write_mal);
2660 ppc_dcr_register(env, MAL0_RXDEIR,
2661 mal, &dcr_read_mal, &dcr_write_mal);
2662 ppc_dcr_register(env, MAL0_TXCTP0R,
2663 mal, &dcr_read_mal, &dcr_write_mal);
2664 ppc_dcr_register(env, MAL0_TXCTP1R,
2665 mal, &dcr_read_mal, &dcr_write_mal);
2666 ppc_dcr_register(env, MAL0_TXCTP2R,
2667 mal, &dcr_read_mal, &dcr_write_mal);
2668 ppc_dcr_register(env, MAL0_TXCTP3R,
2669 mal, &dcr_read_mal, &dcr_write_mal);
2670 ppc_dcr_register(env, MAL0_RXCTP0R,
2671 mal, &dcr_read_mal, &dcr_write_mal);
2672 ppc_dcr_register(env, MAL0_RXCTP1R,
2673 mal, &dcr_read_mal, &dcr_write_mal);
2674 ppc_dcr_register(env, MAL0_RCBS0,
2675 mal, &dcr_read_mal, &dcr_write_mal);
2676 ppc_dcr_register(env, MAL0_RCBS1,
2677 mal, &dcr_read_mal, &dcr_write_mal);
2678 }
2679 }
2680
2681 /*****************************************************************************/
2682 /* SPR */
2683 void ppc40x_core_reset (CPUState *env)
2684 {
2685 target_ulong dbsr;
2686
2687 printf("Reset PowerPC core\n");
2688 cpu_ppc_reset(env);
2689 dbsr = env->spr[SPR_40x_DBSR];
2690 dbsr &= ~0x00000300;
2691 dbsr |= 0x00000100;
2692 env->spr[SPR_40x_DBSR] = dbsr;
2693 cpu_loop_exit();
2694 }
2695
2696 void ppc40x_chip_reset (CPUState *env)
2697 {
2698 target_ulong dbsr;
2699
2700 printf("Reset PowerPC chip\n");
2701 cpu_ppc_reset(env);
2702 /* XXX: TODO reset all internal peripherals */
2703 dbsr = env->spr[SPR_40x_DBSR];
2704 dbsr &= ~0x00000300;
2705 dbsr |= 0x00000200;
2706 env->spr[SPR_40x_DBSR] = dbsr;
2707 cpu_loop_exit();
2708 }
2709
2710 void ppc40x_system_reset (CPUState *env)
2711 {
2712 printf("Reset PowerPC system\n");
2713 qemu_system_reset_request();
2714 }
2715
2716 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2717 {
2718 switch ((val >> 28) & 0x3) {
2719 case 0x0:
2720 /* No action */
2721 break;
2722 case 0x1:
2723 /* Core reset */
2724 ppc40x_core_reset(env);
2725 break;
2726 case 0x2:
2727 /* Chip reset */
2728 ppc40x_chip_reset(env);
2729 break;
2730 case 0x3:
2731 /* System reset */
2732 ppc40x_system_reset(env);
2733 break;
2734 }
2735 }
2736
2737 /*****************************************************************************/
2738 /* PowerPC 405CR */
2739 enum {
2740 PPC405CR_CPC0_PLLMR = 0x0B0,
2741 PPC405CR_CPC0_CR0 = 0x0B1,
2742 PPC405CR_CPC0_CR1 = 0x0B2,
2743 PPC405CR_CPC0_PSR = 0x0B4,
2744 PPC405CR_CPC0_JTAGID = 0x0B5,
2745 PPC405CR_CPC0_ER = 0x0B9,
2746 PPC405CR_CPC0_FR = 0x0BA,
2747 PPC405CR_CPC0_SR = 0x0BB,
2748 };
2749
2750 enum {
2751 PPC405CR_CPU_CLK = 0,
2752 PPC405CR_TMR_CLK = 1,
2753 PPC405CR_PLB_CLK = 2,
2754 PPC405CR_SDRAM_CLK = 3,
2755 PPC405CR_OPB_CLK = 4,
2756 PPC405CR_EXT_CLK = 5,
2757 PPC405CR_UART_CLK = 6,
2758 PPC405CR_CLK_NB = 7,
2759 };
2760
2761 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2762 struct ppc405cr_cpc_t {
2763 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2764 uint32_t sysclk;
2765 uint32_t psr;
2766 uint32_t cr0;
2767 uint32_t cr1;
2768 uint32_t jtagid;
2769 uint32_t pllmr;
2770 uint32_t er;
2771 uint32_t fr;
2772 };
2773
2774 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2775 {
2776 uint64_t VCO_out, PLL_out;
2777 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2778 int M, D0, D1, D2;
2779
2780 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2781 if (cpc->pllmr & 0x80000000) {
2782 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2783 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2784 M = D0 * D1 * D2;
2785 VCO_out = cpc->sysclk * M;
2786 if (VCO_out < 400000000 || VCO_out > 800000000) {
2787 /* PLL cannot lock */
2788 cpc->pllmr &= ~0x80000000;
2789 goto bypass_pll;
2790 }
2791 PLL_out = VCO_out / D2;
2792 } else {
2793 /* Bypass PLL */
2794 bypass_pll:
2795 M = D0;
2796 PLL_out = cpc->sysclk * M;
2797 }
2798 CPU_clk = PLL_out;
2799 if (cpc->cr1 & 0x00800000)
2800 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2801 else
2802 TMR_clk = CPU_clk;
2803 PLB_clk = CPU_clk / D0;
2804 SDRAM_clk = PLB_clk;
2805 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2806 OPB_clk = PLB_clk / D0;
2807 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2808 EXT_clk = PLB_clk / D0;
2809 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2810 UART_clk = CPU_clk / D0;
2811 /* Setup CPU clocks */
2812 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2813 /* Setup time-base clock */
2814 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2815 /* Setup PLB clock */
2816 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2817 /* Setup SDRAM clock */
2818 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2819 /* Setup OPB clock */
2820 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2821 /* Setup external clock */
2822 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2823 /* Setup UART clock */
2824 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2825 }
2826
2827 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2828 {
2829 ppc405cr_cpc_t *cpc;
2830 target_ulong ret;
2831
2832 cpc = opaque;
2833 switch (dcrn) {
2834 case PPC405CR_CPC0_PLLMR:
2835 ret = cpc->pllmr;
2836 break;
2837 case PPC405CR_CPC0_CR0:
2838 ret = cpc->cr0;
2839 break;
2840 case PPC405CR_CPC0_CR1:
2841 ret = cpc->cr1;
2842 break;
2843 case PPC405CR_CPC0_PSR:
2844 ret = cpc->psr;
2845 break;
2846 case PPC405CR_CPC0_JTAGID:
2847 ret = cpc->jtagid;
2848 break;
2849 case PPC405CR_CPC0_ER:
2850 ret = cpc->er;
2851 break;
2852 case PPC405CR_CPC0_FR:
2853 ret = cpc->fr;
2854 break;
2855 case PPC405CR_CPC0_SR:
2856 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2857 break;
2858 default:
2859 /* Avoid gcc warning */
2860 ret = 0;
2861 break;
2862 }
2863
2864 return ret;
2865 }
2866
2867 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2868 {
2869 ppc405cr_cpc_t *cpc;
2870
2871 cpc = opaque;
2872 switch (dcrn) {
2873 case PPC405CR_CPC0_PLLMR:
2874 cpc->pllmr = val & 0xFFF77C3F;
2875 break;
2876 case PPC405CR_CPC0_CR0:
2877 cpc->cr0 = val & 0x0FFFFFFE;
2878 break;
2879 case PPC405CR_CPC0_CR1:
2880 cpc->cr1 = val & 0x00800000;
2881 break;
2882 case PPC405CR_CPC0_PSR:
2883 /* Read-only */
2884 break;
2885 case PPC405CR_CPC0_JTAGID:
2886 /* Read-only */
2887 break;
2888 case PPC405CR_CPC0_ER:
2889 cpc->er = val & 0xBFFC0000;
2890 break;
2891 case PPC405CR_CPC0_FR:
2892 cpc->fr = val & 0xBFFC0000;
2893 break;
2894 case PPC405CR_CPC0_SR:
2895 /* Read-only */
2896 break;
2897 }
2898 }
2899
2900 static void ppc405cr_cpc_reset (void *opaque)
2901 {
2902 ppc405cr_cpc_t *cpc;
2903 int D;
2904
2905 cpc = opaque;
2906 /* Compute PLLMR value from PSR settings */
2907 cpc->pllmr = 0x80000000;
2908 /* PFWD */
2909 switch ((cpc->psr >> 30) & 3) {
2910 case 0:
2911 /* Bypass */
2912 cpc->pllmr &= ~0x80000000;
2913 break;
2914 case 1:
2915 /* Divide by 3 */
2916 cpc->pllmr |= 5 << 16;
2917 break;
2918 case 2:
2919 /* Divide by 4 */
2920 cpc->pllmr |= 4 << 16;
2921 break;
2922 case 3:
2923 /* Divide by 6 */
2924 cpc->pllmr |= 2 << 16;
2925 break;
2926 }
2927 /* PFBD */
2928 D = (cpc->psr >> 28) & 3;
2929 cpc->pllmr |= (D + 1) << 20;
2930 /* PT */
2931 D = (cpc->psr >> 25) & 7;
2932 switch (D) {
2933 case 0x2:
2934 cpc->pllmr |= 0x13;
2935 break;
2936 case 0x4:
2937 cpc->pllmr |= 0x15;
2938 break;
2939 case 0x5:
2940 cpc->pllmr |= 0x16;
2941 break;
2942 default:
2943 break;
2944 }
2945 /* PDC */
2946 D = (cpc->psr >> 23) & 3;
2947 cpc->pllmr |= D << 26;
2948 /* ODP */
2949 D = (cpc->psr >> 21) & 3;
2950 cpc->pllmr |= D << 10;
2951 /* EBPD */
2952 D = (cpc->psr >> 17) & 3;
2953 cpc->pllmr |= D << 24;
2954 cpc->cr0 = 0x0000003C;
2955 cpc->cr1 = 0x2B0D8800;
2956 cpc->er = 0x00000000;
2957 cpc->fr = 0x00000000;
2958 ppc405cr_clk_setup(cpc);
2959 }
2960
2961 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2962 {
2963 int D;
2964
2965 /* XXX: this should be read from IO pins */
2966 cpc->psr = 0x00000000; /* 8 bits ROM */
2967 /* PFWD */
2968 D = 0x2; /* Divide by 4 */
2969 cpc->psr |= D << 30;
2970 /* PFBD */
2971 D = 0x1; /* Divide by 2 */
2972 cpc->psr |= D << 28;
2973 /* PDC */
2974 D = 0x1; /* Divide by 2 */
2975 cpc->psr |= D << 23;
2976 /* PT */
2977 D = 0x5; /* M = 16 */
2978 cpc->psr |= D << 25;
2979 /* ODP */
2980 D = 0x1; /* Divide by 2 */
2981 cpc->psr |= D << 21;
2982 /* EBDP */
2983 D = 0x2; /* Divide by 4 */
2984 cpc->psr |= D << 17;
2985 }
2986
2987 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2988 uint32_t sysclk)
2989 {
2990 ppc405cr_cpc_t *cpc;
2991
2992 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2993 if (cpc != NULL) {
2994 memcpy(cpc->clk_setup, clk_setup,
2995 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2996 cpc->sysclk = sysclk;
2997 cpc->jtagid = 0x42051049;
2998 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2999 &dcr_read_crcpc, &dcr_write_crcpc);
3000 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
3001 &dcr_read_crcpc, &dcr_write_crcpc);
3002 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
3003 &dcr_read_crcpc, &dcr_write_crcpc);
3004 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
3005 &dcr_read_crcpc, &dcr_write_crcpc);
3006 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
3007 &dcr_read_crcpc, &dcr_write_crcpc);
3008 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
3009 &dcr_read_crcpc, &dcr_write_crcpc);
3010 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
3011 &dcr_read_crcpc, &dcr_write_crcpc);
3012 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
3013 &dcr_read_crcpc, &dcr_write_crcpc);
3014 ppc405cr_clk_init(cpc);
3015 qemu_register_reset(ppc405cr_cpc_reset, cpc);
3016 ppc405cr_cpc_reset(cpc);
3017 }
3018 }
3019
3020 CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
3021 uint32_t sysclk, qemu_irq **picp,
3022 ram_addr_t *offsetp, int do_init)
3023 {
3024 clk_setup_t clk_setup[PPC405CR_CLK_NB];
3025 qemu_irq dma_irqs[4];
3026 CPUState *env;
3027 ppc4xx_mmio_t *mmio;
3028 qemu_irq *pic, *irqs;
3029 ram_addr_t offset;
3030 int i;
3031
3032 memset(clk_setup, 0, sizeof(clk_setup));
3033 env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
3034 &clk_setup[PPC405CR_TMR_CLK], sysclk);
3035 /* Memory mapped devices registers */
3036 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3037 /* PLB arbitrer */
3038 ppc4xx_plb_init(env);
3039 /* PLB to OPB bridge */
3040 ppc4xx_pob_init(env);
3041 /* OBP arbitrer */
3042 ppc4xx_opba_init(env, mmio, 0x600);
3043 /* Universal interrupt controller */
3044 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3045 irqs[PPCUIC_OUTPUT_INT] =
3046 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3047 irqs[PPCUIC_OUTPUT_CINT] =
3048 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3049 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3050 *picp = pic;
3051 /* SDRAM controller */
3052 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
3053 offset = 0;
3054 for (i = 0; i < 4; i++)
3055 offset += ram_sizes[i];
3056 /* External bus controller */
3057 ppc405_ebc_init(env);
3058 /* DMA controller */
3059 dma_irqs[0] = pic[26];
3060 dma_irqs[1] = pic[25];
3061 dma_irqs[2] = pic[24];
3062 dma_irqs[3] = pic[23];
3063 ppc405_dma_init(env, dma_irqs);
3064 /* Serial ports */
3065 if (serial_hds[0] != NULL) {
3066 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3067 }
3068 if (serial_hds[1] != NULL) {
3069 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3070 }
3071 /* IIC controller */
3072 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3073 /* GPIO */
3074 ppc405_gpio_init(env, mmio, 0x700);
3075 /* CPU control */
3076 ppc405cr_cpc_init(env, clk_setup, sysclk);
3077 *offsetp = offset;
3078
3079 return env;
3080 }
3081
3082 /*****************************************************************************/
3083 /* PowerPC 405EP */
3084 /* CPU control */
3085 enum {
3086 PPC405EP_CPC0_PLLMR0 = 0x0F0,
3087 PPC405EP_CPC0_BOOT = 0x0F1,
3088 PPC405EP_CPC0_EPCTL = 0x0F3,
3089 PPC405EP_CPC0_PLLMR1 = 0x0F4,
3090 PPC405EP_CPC0_UCR = 0x0F5,
3091 PPC405EP_CPC0_SRR = 0x0F6,
3092 PPC405EP_CPC0_JTAGID = 0x0F7,
3093 PPC405EP_CPC0_PCI = 0x0F9,
3094 #if 0
3095 PPC405EP_CPC0_ER = xxx,
3096 PPC405EP_CPC0_FR = xxx,
3097 PPC405EP_CPC0_SR = xxx,
3098 #endif
3099 };
3100
3101 enum {
3102 PPC405EP_CPU_CLK = 0,
3103 PPC405EP_PLB_CLK = 1,
3104 PPC405EP_OPB_CLK = 2,
3105 PPC405EP_EBC_CLK = 3,
3106 PPC405EP_MAL_CLK = 4,
3107 PPC405EP_PCI_CLK = 5,
3108 PPC405EP_UART0_CLK = 6,
3109 PPC405EP_UART1_CLK = 7,
3110 PPC405EP_CLK_NB = 8,
3111 };
3112
3113 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
3114 struct ppc405ep_cpc_t {
3115 uint32_t sysclk;
3116 clk_setup_t clk_setup[PPC405EP_CLK_NB];
3117 uint32_t boot;
3118 uint32_t epctl;
3119 uint32_t pllmr[2];
3120 uint32_t ucr;
3121 uint32_t srr;
3122 uint32_t jtagid;
3123 uint32_t pci;
3124 /* Clock and power management */
3125 uint32_t er;
3126 uint32_t fr;
3127 uint32_t sr;
3128 };
3129
3130 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
3131 {
3132 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
3133 uint32_t UART0_clk, UART1_clk;
3134 uint64_t VCO_out, PLL_out;
3135 int M, D;
3136
3137 VCO_out = 0;
3138 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
3139 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
3140 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
3141 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
3142 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
3143 VCO_out = cpc->sysclk * M * D;
3144 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
3145 /* Error - unlock the PLL */
3146 printf("VCO out of range %" PRIu64 "\n", VCO_out);
3147 #if 0
3148 cpc->pllmr[1] &= ~0x80000000;
3149 goto pll_bypass;
3150 #endif
3151 }
3152 PLL_out = VCO_out / D;
3153 /* Pretend the PLL is locked */
3154 cpc->boot |= 0x00000001;
3155 } else {
3156 #if 0
3157 pll_bypass:
3158 #endif
3159 PLL_out = cpc->sysclk;
3160 if (cpc->pllmr[1] & 0x40000000) {
3161 /* Pretend the PLL is not locked */
3162 cpc->boot &= ~0x00000001;
3163 }
3164 }
3165 /* Now, compute all other clocks */
3166 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
3167 #ifdef DEBUG_CLOCKS
3168 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
3169 #endif
3170 CPU_clk = PLL_out / D;
3171 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
3172 #ifdef DEBUG_CLOCKS
3173 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
3174 #endif
3175 PLB_clk = CPU_clk / D;
3176 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
3177 #ifdef DEBUG_CLOCKS
3178 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
3179 #endif
3180 OPB_clk = PLB_clk / D;
3181 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
3182 #ifdef DEBUG_CLOCKS
3183 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
3184 #endif
3185 EBC_clk = PLB_clk / D;
3186 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
3187 #ifdef DEBUG_CLOCKS
3188 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
3189 #endif
3190 MAL_clk = PLB_clk / D;
3191 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
3192 #ifdef DEBUG_CLOCKS
3193 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
3194 #endif
3195 PCI_clk = PLB_clk / D;
3196 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
3197 #ifdef DEBUG_CLOCKS
3198 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
3199 #endif
3200 UART0_clk = PLL_out / D;
3201 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
3202 #ifdef DEBUG_CLOCKS
3203 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
3204 #endif
3205 UART1_clk = PLL_out / D;
3206 #ifdef DEBUG_CLOCKS
3207 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
3208 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
3209 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
3210 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
3211 UART0_clk, UART1_clk);
3212 printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
3213 cpc->clk_setup[PPC405EP_CPU_CLK].opaque);
3214 #endif
3215 /* Setup CPU clocks */
3216 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
3217 /* Setup PLB clock */
3218 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
3219 /* Setup OPB clock */
3220 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
3221 /* Setup external clock */
3222 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
3223 /* Setup MAL clock */
3224 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
3225 /* Setup PCI clock */
3226 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
3227 /* Setup UART0 clock */
3228 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
3229 /* Setup UART1 clock */
3230 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
3231 }
3232
3233 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
3234 {
3235 ppc405ep_cpc_t *cpc;
3236 target_ulong ret;
3237
3238 cpc = opaque;
3239 switch (dcrn) {
3240 case PPC405EP_CPC0_BOOT:
3241 ret = cpc->boot;
3242 break;
3243 case PPC405EP_CPC0_EPCTL:
3244 ret = cpc->epctl;
3245 break;
3246 case PPC405EP_CPC0_PLLMR0:
3247 ret = cpc->pllmr[0];
3248 break;
3249 case PPC405EP_CPC0_PLLMR1:
3250 ret = cpc->pllmr[1];
3251 break;
3252 case PPC405EP_CPC0_UCR:
3253 ret = cpc->ucr;
3254 break;
3255 case PPC405EP_CPC0_SRR:
3256 ret = cpc->srr;
3257 break;
3258 case PPC405EP_CPC0_JTAGID:
3259 ret = cpc->jtagid;
3260 break;
3261 case PPC405EP_CPC0_PCI:
3262 ret = cpc->pci;
3263 break;
3264 default:
3265 /* Avoid gcc warning */
3266 ret = 0;
3267 break;
3268 }
3269
3270 return ret;
3271 }
3272
3273 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
3274 {
3275 ppc405ep_cpc_t *cpc;
3276
3277 cpc = opaque;
3278 switch (dcrn) {
3279 case PPC405EP_CPC0_BOOT:
3280 /* Read-only register */
3281 break;
3282 case PPC405EP_CPC0_EPCTL:
3283 /* Don't care for now */
3284 cpc->epctl = val & 0xC00000F3;
3285 break;
3286 case PPC405EP_CPC0_PLLMR0:
3287 cpc->pllmr[0] = val & 0x00633333;
3288 ppc405ep_compute_clocks(cpc);
3289 break;
3290 case PPC405EP_CPC0_PLLMR1:
3291 cpc->pllmr[1] = val & 0xC0F73FFF;
3292 ppc405ep_compute_clocks(cpc);
3293 break;
3294 case PPC405EP_CPC0_UCR:
3295 /* UART control - don't care for now */
3296 cpc->ucr = val & 0x003F7F7F;
3297 break;
3298 case PPC405EP_CPC0_SRR:
3299 cpc->srr = val;
3300 break;
3301 case PPC405EP_CPC0_JTAGID:
3302 /* Read-only */
3303 break;
3304 case PPC405EP_CPC0_PCI:
3305 cpc->pci = val;
3306 break;
3307 }
3308 }
3309
3310 static void ppc405ep_cpc_reset (void *opaque)
3311 {
3312 ppc405ep_cpc_t *cpc = opaque;
3313
3314 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
3315 cpc->epctl = 0x00000000;
3316 cpc->pllmr[0] = 0x00011010;
3317 cpc->pllmr[1] = 0x40000000;
3318 cpc->ucr = 0x00000000;
3319 cpc->srr = 0x00040000;
3320 cpc->pci = 0x00000000;
3321 cpc->er = 0x00000000;
3322 cpc->fr = 0x00000000;
3323 cpc->sr = 0x00000000;
3324 ppc405ep_compute_clocks(cpc);
3325 }
3326
3327 /* XXX: sysclk should be between 25 and 100 MHz */
3328 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
3329 uint32_t sysclk)
3330 {
3331 ppc405ep_cpc_t *cpc;
3332
3333 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
3334 if (cpc != NULL) {
3335 memcpy(cpc->clk_setup, clk_setup,
3336 PPC405EP_CLK_NB * sizeof(clk_setup_t));
3337 cpc->jtagid = 0x20267049;
3338 cpc->sysclk = sysclk;
3339 ppc405ep_cpc_reset(cpc);
3340 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
3341 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
3342 &dcr_read_epcpc, &dcr_write_epcpc);
3343 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
3344 &dcr_read_epcpc, &dcr_write_epcpc);
3345 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
3346 &dcr_read_epcpc, &dcr_write_epcpc);
3347 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
3348 &dcr_read_epcpc, &dcr_write_epcpc);
3349 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
3350 &dcr_read_epcpc, &dcr_write_epcpc);
3351 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
3352 &dcr_read_epcpc, &dcr_write_epcpc);
3353 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
3354 &dcr_read_epcpc, &dcr_write_epcpc);
3355 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
3356 &dcr_read_epcpc, &dcr_write_epcpc);
3357 #if 0
3358 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
3359 &dcr_read_epcpc, &dcr_write_epcpc);
3360 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
3361 &dcr_read_epcpc, &dcr_write_epcpc);
3362 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
3363 &dcr_read_epcpc, &dcr_write_epcpc);
3364 #endif
3365 }
3366 }
3367
3368 CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
3369 uint32_t sysclk, qemu_irq **picp,
3370 ram_addr_t *offsetp, int do_init)
3371 {
3372 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
3373 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
3374 CPUState *env;
3375 ppc4xx_mmio_t *mmio;
3376 qemu_irq *pic, *irqs;
3377 ram_addr_t offset;
3378 int i;
3379
3380 memset(clk_setup, 0, sizeof(clk_setup));
3381 /* init CPUs */
3382 env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
3383 &tlb_clk_setup, sysclk);
3384 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
3385 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
3386 /* Internal devices init */
3387 /* Memory mapped devices registers */
3388 mmio = ppc4xx_mmio_init(env, 0xEF600000);
3389 /* PLB arbitrer */
3390 ppc4xx_plb_init(env);
3391 /* PLB to OPB bridge */
3392 ppc4xx_pob_init(env);
3393 /* OBP arbitrer */
3394 ppc4xx_opba_init(env, mmio, 0x600);
3395 /* Universal interrupt controller */
3396 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
3397 irqs[PPCUIC_OUTPUT_INT] =
3398 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_INT];
3399 irqs[PPCUIC_OUTPUT_CINT] =
3400 ((qemu_irq *)env->irq_inputs)[PPC405_INPUT_CINT];
3401 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
3402 *picp = pic;
3403 /* SDRAM controller */
3404 ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
3405 offset = 0;
3406 for (i = 0; i < 2; i++)
3407 offset += ram_sizes[i];
3408 /* External bus controller */
3409 ppc405_ebc_init(env);
3410 /* DMA controller */
3411 dma_irqs[0] = pic[26];
3412 dma_irqs[1] = pic[25];
3413 dma_irqs[2] = pic[24];
3414 dma_irqs[3] = pic[23];
3415 ppc405_dma_init(env, dma_irqs);
3416 /* IIC controller */
3417 ppc405_i2c_init(env, mmio, 0x500, pic[29]);
3418 /* GPIO */
3419 ppc405_gpio_init(env, mmio, 0x700);
3420 /* Serial ports */
3421 if (serial_hds[0] != NULL) {
3422 ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
3423 }
3424 if (serial_hds[1] != NULL) {
3425 ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
3426 }
3427 /* OCM */
3428 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
3429 offset += 4096;
3430 /* GPT */
3431 gpt_irqs[0] = pic[12];
3432 gpt_irqs[1] = pic[11];
3433 gpt_irqs[2] = pic[10];
3434 gpt_irqs[3] = pic[9];
3435 gpt_irqs[4] = pic[8];
3436 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
3437 /* PCI */
3438 /* Uses pic[28], pic[15], pic[13] */
3439 /* MAL */
3440 mal_irqs[0] = pic[20];
3441 mal_irqs[1] = pic[19];
3442 mal_irqs[2] = pic[18];
3443 mal_irqs[3] = pic[17];
3444 ppc405_mal_init(env, mal_irqs);
3445 /* Ethernet */
3446 /* Uses pic[22], pic[16], pic[14] */
3447 /* CPU control */
3448 ppc405ep_cpc_init(env, clk_setup, sysclk);
3449 *offsetp = offset;
3450
3451 return env;
3452 }
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