2 * QEMU IDE disk and CD-ROM Emulator
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 /* debug IDE devices */
29 //#define DEBUG_IDE_ATAPI
33 /* Bits of HD_STATUS */
35 #define INDEX_STAT 0x02
36 #define ECC_STAT 0x04 /* Corrected error */
38 #define SEEK_STAT 0x10
40 #define WRERR_STAT 0x20
41 #define READY_STAT 0x40
42 #define BUSY_STAT 0x80
44 /* Bits for HD_ERROR */
45 #define MARK_ERR 0x01 /* Bad address mark */
46 #define TRK0_ERR 0x02 /* couldn't find track 0 */
47 #define ABRT_ERR 0x04 /* Command aborted */
48 #define MCR_ERR 0x08 /* media change request */
49 #define ID_ERR 0x10 /* ID field not found */
50 #define MC_ERR 0x20 /* media changed */
51 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
52 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
53 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
55 /* Bits of HD_NSECTOR */
61 #define IDE_CMD_RESET 0x04
62 #define IDE_CMD_DISABLE_IRQ 0x02
64 /* ATA/ATAPI Commands pre T13 Spec */
69 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
73 #define WIN_SRST 0x08 /* ATAPI soft reset command */
74 #define WIN_DEVICE_RESET 0x08
78 #define WIN_RECAL 0x10
79 #define WIN_RESTORE WIN_RECAL
83 #define WIN_READ 0x20 /* 28-Bit */
84 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
85 #define WIN_READ_LONG 0x22 /* 28-Bit */
86 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
87 #define WIN_READ_EXT 0x24 /* 48-Bit */
88 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
89 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
90 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
94 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
98 #define WIN_WRITE 0x30 /* 28-Bit */
99 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
100 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
101 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
102 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
103 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
104 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
105 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
106 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
107 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
109 * 0x3A->0x3B Reserved
111 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
113 * 0x3D->0x3F Reserved
115 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
116 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
117 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
119 * 0x43->0x4F Reserved
121 #define WIN_FORMAT 0x50
123 * 0x51->0x5F Reserved
125 #define WIN_INIT 0x60
127 * 0x61->0x5F Reserved
129 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
130 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
131 #define WIN_DIAGNOSE 0x90
132 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
133 #define WIN_DOWNLOAD_MICROCODE 0x92
134 #define WIN_STANDBYNOW2 0x94
135 #define CFA_IDLEIMMEDIATE 0x95 /* force drive to become "ready" */
136 #define WIN_STANDBY2 0x96
137 #define WIN_SETIDLE2 0x97
138 #define WIN_CHECKPOWERMODE2 0x98
139 #define WIN_SLEEPNOW2 0x99
143 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
144 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
145 #define WIN_QUEUED_SERVICE 0xA2
146 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
147 #define CFA_ACCESS_METADATA_STORAGE 0xB8
148 #define CFA_ERASE_SECTORS 0xC0 /* microdrives implement as NOP */
149 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
150 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
151 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
152 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
153 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
154 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
155 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
156 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
157 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
158 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
159 #define WIN_GETMEDIASTATUS 0xDA
160 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
161 #define WIN_POSTBOOT 0xDC
162 #define WIN_PREBOOT 0xDD
163 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
164 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
165 #define WIN_STANDBYNOW1 0xE0
166 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
167 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
168 #define WIN_SETIDLE1 0xE3
169 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
170 #define WIN_CHECKPOWERMODE1 0xE5
171 #define WIN_SLEEPNOW1 0xE6
172 #define WIN_FLUSH_CACHE 0xE7
173 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
174 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
175 /* SET_FEATURES 0x22 or 0xDD */
176 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
177 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
178 #define WIN_MEDIAEJECT 0xED
179 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
180 #define WIN_SETFEATURES 0xEF /* set special drive features */
181 #define EXABYTE_ENABLE_NEST 0xF0
182 #define IBM_SENSE_CONDITION 0xF0 /* measure disk temperature */
183 #define WIN_SECURITY_SET_PASS 0xF1
184 #define WIN_SECURITY_UNLOCK 0xF2
185 #define WIN_SECURITY_ERASE_PREPARE 0xF3
186 #define WIN_SECURITY_ERASE_UNIT 0xF4
187 #define WIN_SECURITY_FREEZE_LOCK 0xF5
188 #define CFA_WEAR_LEVEL 0xF5 /* microdrives implement as NOP */
189 #define WIN_SECURITY_DISABLE 0xF6
190 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
191 #define WIN_SET_MAX 0xF9
192 #define DISABLE_SEAGATE 0xFB
194 /* set to 1 set disable mult support */
195 #define MAX_MULT_SECTORS 16
199 #define ATAPI_PACKET_SIZE 12
201 /* The generic packet command opcodes for CD/DVD Logical Units,
202 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
203 #define GPCMD_BLANK 0xa1
204 #define GPCMD_CLOSE_TRACK 0x5b
205 #define GPCMD_FLUSH_CACHE 0x35
206 #define GPCMD_FORMAT_UNIT 0x04
207 #define GPCMD_GET_CONFIGURATION 0x46
208 #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
209 #define GPCMD_GET_PERFORMANCE 0xac
210 #define GPCMD_INQUIRY 0x12
211 #define GPCMD_LOAD_UNLOAD 0xa6
212 #define GPCMD_MECHANISM_STATUS 0xbd
213 #define GPCMD_MODE_SELECT_10 0x55
214 #define GPCMD_MODE_SENSE_10 0x5a
215 #define GPCMD_PAUSE_RESUME 0x4b
216 #define GPCMD_PLAY_AUDIO_10 0x45
217 #define GPCMD_PLAY_AUDIO_MSF 0x47
218 #define GPCMD_PLAY_AUDIO_TI 0x48
219 #define GPCMD_PLAY_CD 0xbc
220 #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
221 #define GPCMD_READ_10 0x28
222 #define GPCMD_READ_12 0xa8
223 #define GPCMD_READ_CDVD_CAPACITY 0x25
224 #define GPCMD_READ_CD 0xbe
225 #define GPCMD_READ_CD_MSF 0xb9
226 #define GPCMD_READ_DISC_INFO 0x51
227 #define GPCMD_READ_DVD_STRUCTURE 0xad
228 #define GPCMD_READ_FORMAT_CAPACITIES 0x23
229 #define GPCMD_READ_HEADER 0x44
230 #define GPCMD_READ_TRACK_RZONE_INFO 0x52
231 #define GPCMD_READ_SUBCHANNEL 0x42
232 #define GPCMD_READ_TOC_PMA_ATIP 0x43
233 #define GPCMD_REPAIR_RZONE_TRACK 0x58
234 #define GPCMD_REPORT_KEY 0xa4
235 #define GPCMD_REQUEST_SENSE 0x03
236 #define GPCMD_RESERVE_RZONE_TRACK 0x53
237 #define GPCMD_SCAN 0xba
238 #define GPCMD_SEEK 0x2b
239 #define GPCMD_SEND_DVD_STRUCTURE 0xad
240 #define GPCMD_SEND_EVENT 0xa2
241 #define GPCMD_SEND_KEY 0xa3
242 #define GPCMD_SEND_OPC 0x54
243 #define GPCMD_SET_READ_AHEAD 0xa7
244 #define GPCMD_SET_STREAMING 0xb6
245 #define GPCMD_START_STOP_UNIT 0x1b
246 #define GPCMD_STOP_PLAY_SCAN 0x4e
247 #define GPCMD_TEST_UNIT_READY 0x00
248 #define GPCMD_VERIFY_10 0x2f
249 #define GPCMD_WRITE_10 0x2a
250 #define GPCMD_WRITE_AND_VERIFY_10 0x2e
251 /* This is listed as optional in ATAPI 2.6, but is (curiously)
252 * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
253 * Table 377 as an MMC command for SCSi devices though... Most ATAPI
254 * drives support it. */
255 #define GPCMD_SET_SPEED 0xbb
256 /* This seems to be a SCSI specific CD-ROM opcode
257 * to play data at track/index */
258 #define GPCMD_PLAYAUDIO_TI 0x48
260 * From MS Media Status Notification Support Specification. For
263 #define GPCMD_GET_MEDIA_STATUS 0xda
265 /* Mode page codes for mode sense/set */
266 #define GPMODE_R_W_ERROR_PAGE 0x01
267 #define GPMODE_WRITE_PARMS_PAGE 0x05
268 #define GPMODE_AUDIO_CTL_PAGE 0x0e
269 #define GPMODE_POWER_PAGE 0x1a
270 #define GPMODE_FAULT_FAIL_PAGE 0x1c
271 #define GPMODE_TO_PROTECT_PAGE 0x1d
272 #define GPMODE_CAPABILITIES_PAGE 0x2a
273 #define GPMODE_ALL_PAGES 0x3f
274 /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
275 * of MODE_SENSE_POWER_PAGE */
276 #define GPMODE_CDROM_PAGE 0x0d
278 #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
279 #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
280 #define ATAPI_INT_REASON_REL 0x04
281 #define ATAPI_INT_REASON_TAG 0xf8
283 /* same constants as bochs */
284 #define ASC_ILLEGAL_OPCODE 0x20
285 #define ASC_LOGICAL_BLOCK_OOR 0x21
286 #define ASC_INV_FIELD_IN_CMD_PACKET 0x24
287 #define ASC_MEDIUM_NOT_PRESENT 0x3a
288 #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
290 #define CFA_NO_ERROR 0x00
291 #define CFA_MISC_ERROR 0x09
292 #define CFA_INVALID_COMMAND 0x20
293 #define CFA_INVALID_ADDRESS 0x21
294 #define CFA_ADDRESS_OVERFLOW 0x2f
297 #define SENSE_NOT_READY 2
298 #define SENSE_ILLEGAL_REQUEST 5
299 #define SENSE_UNIT_ATTENTION 6
303 typedef void EndTransferFunc(struct IDEState
*);
305 /* NOTE: IDEState represents in fact one drive */
306 typedef struct IDEState
{
310 int cylinders
, heads
, sectors
;
314 uint16_t identify_data
[256];
317 struct BMDMAState
*bmdma
;
326 /* other part of tf for lba48 support */
336 /* 0x3f6 command, only meaningful for drive 0 */
338 /* set for lba48 access */
340 /* depends on bit 4 in select, only meaningful for drive 0 */
341 struct IDEState
*cur_drive
;
342 BlockDriverState
*bs
;
346 int packet_transfer_size
;
347 int elementary_transfer_size
;
351 int atapi_dma
; /* true if dma is requested for the packet cmd */
354 /* PIO transfer handling */
355 int req_nb_sectors
; /* number of sectors per interrupt */
356 EndTransferFunc
*end_transfer_func
;
359 uint8_t io_buffer
[MAX_MULT_SECTORS
*512 + 4];
360 QEMUTimer
*sector_write_timer
; /* only used for win2k instal hack */
361 uint32_t irq_count
; /* counts IRQs when using win2k install hack */
362 /* CF-ATA extended error */
364 /* CF-ATA metadata storage */
366 uint8_t *mdata_storage
;
370 #define BM_STATUS_DMAING 0x01
371 #define BM_STATUS_ERROR 0x02
372 #define BM_STATUS_INT 0x04
374 #define BM_CMD_START 0x01
375 #define BM_CMD_READ 0x08
377 #define IDE_TYPE_PIIX3 0
378 #define IDE_TYPE_CMD646 1
380 /* CMD646 specific */
382 #define MRDMODE_INTR_CH0 0x04
383 #define MRDMODE_INTR_CH1 0x08
384 #define MRDMODE_BLK_CH0 0x10
385 #define MRDMODE_BLK_CH1 0x20
386 #define UDIDETCR0 0x73
387 #define UDIDETCR1 0x7B
389 typedef struct BMDMAState
{
394 struct PCIIDEState
*pci_dev
;
395 /* current transfer state */
397 uint32_t cur_prd_last
;
398 uint32_t cur_prd_addr
;
399 uint32_t cur_prd_len
;
401 BlockDriverCompletionFunc
*dma_cb
;
402 BlockDriverAIOCB
*aiocb
;
405 typedef struct PCIIDEState
{
409 int type
; /* see IDE_TYPE_xxx */
412 static void ide_dma_start(IDEState
*s
, BlockDriverCompletionFunc
*dma_cb
);
413 static void ide_atapi_cmd_read_dma_cb(void *opaque
, int ret
);
415 static void padstr(char *str
, const char *src
, int len
)
418 for(i
= 0; i
< len
; i
++) {
423 *(char *)((long)str
^ 1) = v
;
428 static void padstr8(uint8_t *buf
, int buf_size
, const char *src
)
431 for(i
= 0; i
< buf_size
; i
++) {
439 static void put_le16(uint16_t *p
, unsigned int v
)
444 static void ide_identify(IDEState
*s
)
447 unsigned int oldsize
;
450 if (s
->identify_set
) {
451 memcpy(s
->io_buffer
, s
->identify_data
, sizeof(s
->identify_data
));
455 memset(s
->io_buffer
, 0, 512);
456 p
= (uint16_t *)s
->io_buffer
;
457 put_le16(p
+ 0, 0x0040);
458 put_le16(p
+ 1, s
->cylinders
);
459 put_le16(p
+ 3, s
->heads
);
460 put_le16(p
+ 4, 512 * s
->sectors
); /* XXX: retired, remove ? */
461 put_le16(p
+ 5, 512); /* XXX: retired, remove ? */
462 put_le16(p
+ 6, s
->sectors
);
463 snprintf(buf
, sizeof(buf
), "QM%05d", s
->drive_serial
);
464 padstr((uint8_t *)(p
+ 10), buf
, 20); /* serial number */
465 put_le16(p
+ 20, 3); /* XXX: retired, remove ? */
466 put_le16(p
+ 21, 512); /* cache size in sectors */
467 put_le16(p
+ 22, 4); /* ecc bytes */
468 padstr((uint8_t *)(p
+ 23), QEMU_VERSION
, 8); /* firmware version */
469 padstr((uint8_t *)(p
+ 27), "QEMU HARDDISK", 40); /* model */
470 #if MAX_MULT_SECTORS > 1
471 put_le16(p
+ 47, 0x8000 | MAX_MULT_SECTORS
);
473 put_le16(p
+ 48, 1); /* dword I/O */
474 put_le16(p
+ 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
475 put_le16(p
+ 51, 0x200); /* PIO transfer cycle */
476 put_le16(p
+ 52, 0x200); /* DMA transfer cycle */
477 put_le16(p
+ 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
478 put_le16(p
+ 54, s
->cylinders
);
479 put_le16(p
+ 55, s
->heads
);
480 put_le16(p
+ 56, s
->sectors
);
481 oldsize
= s
->cylinders
* s
->heads
* s
->sectors
;
482 put_le16(p
+ 57, oldsize
);
483 put_le16(p
+ 58, oldsize
>> 16);
485 put_le16(p
+ 59, 0x100 | s
->mult_sectors
);
486 put_le16(p
+ 60, s
->nb_sectors
);
487 put_le16(p
+ 61, s
->nb_sectors
>> 16);
488 put_le16(p
+ 63, 0x07); /* mdma0-2 supported */
489 put_le16(p
+ 65, 120);
490 put_le16(p
+ 66, 120);
491 put_le16(p
+ 67, 120);
492 put_le16(p
+ 68, 120);
493 put_le16(p
+ 80, 0xf0); /* ata3 -> ata6 supported */
494 put_le16(p
+ 81, 0x16); /* conforms to ata5 */
495 put_le16(p
+ 82, (1 << 14));
496 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
497 put_le16(p
+ 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
498 put_le16(p
+ 84, (1 << 14));
499 put_le16(p
+ 85, (1 << 14));
500 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
501 put_le16(p
+ 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
502 put_le16(p
+ 87, (1 << 14));
503 put_le16(p
+ 88, 0x3f | (1 << 13)); /* udma5 set and supported */
504 put_le16(p
+ 93, 1 | (1 << 14) | 0x2000);
505 put_le16(p
+ 100, s
->nb_sectors
);
506 put_le16(p
+ 101, s
->nb_sectors
>> 16);
507 put_le16(p
+ 102, s
->nb_sectors
>> 32);
508 put_le16(p
+ 103, s
->nb_sectors
>> 48);
510 memcpy(s
->identify_data
, p
, sizeof(s
->identify_data
));
514 static void ide_atapi_identify(IDEState
*s
)
519 if (s
->identify_set
) {
520 memcpy(s
->io_buffer
, s
->identify_data
, sizeof(s
->identify_data
));
524 memset(s
->io_buffer
, 0, 512);
525 p
= (uint16_t *)s
->io_buffer
;
526 /* Removable CDROM, 50us response, 12 byte packets */
527 put_le16(p
+ 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
528 snprintf(buf
, sizeof(buf
), "QM%05d", s
->drive_serial
);
529 padstr((uint8_t *)(p
+ 10), buf
, 20); /* serial number */
530 put_le16(p
+ 20, 3); /* buffer type */
531 put_le16(p
+ 21, 512); /* cache size in sectors */
532 put_le16(p
+ 22, 4); /* ecc bytes */
533 padstr((uint8_t *)(p
+ 23), QEMU_VERSION
, 8); /* firmware version */
534 padstr((uint8_t *)(p
+ 27), "QEMU CD-ROM", 40); /* model */
535 put_le16(p
+ 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
537 put_le16(p
+ 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
538 put_le16(p
+ 53, 7); /* words 64-70, 54-58, 88 valid */
539 put_le16(p
+ 63, 7); /* mdma0-2 supported */
540 put_le16(p
+ 64, 0x3f); /* PIO modes supported */
542 put_le16(p
+ 49, 1 << 9); /* LBA supported, no DMA */
543 put_le16(p
+ 53, 3); /* words 64-70, 54-58 valid */
544 put_le16(p
+ 63, 0x103); /* DMA modes XXX: may be incorrect */
545 put_le16(p
+ 64, 1); /* PIO modes */
547 put_le16(p
+ 65, 0xb4); /* minimum DMA multiword tx cycle time */
548 put_le16(p
+ 66, 0xb4); /* recommended DMA multiword tx cycle time */
549 put_le16(p
+ 67, 0x12c); /* minimum PIO cycle time without flow control */
550 put_le16(p
+ 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
552 put_le16(p
+ 71, 30); /* in ns */
553 put_le16(p
+ 72, 30); /* in ns */
555 put_le16(p
+ 80, 0x1e); /* support up to ATA/ATAPI-4 */
557 put_le16(p
+ 88, 0x3f | (1 << 13)); /* udma5 set and supported */
559 memcpy(s
->identify_data
, p
, sizeof(s
->identify_data
));
563 static void ide_cfata_identify(IDEState
*s
)
569 p
= (uint16_t *) s
->identify_data
;
573 memset(p
, 0, sizeof(s
->identify_data
));
575 cur_sec
= s
->cylinders
* s
->heads
* s
->sectors
;
577 put_le16(p
+ 0, 0x848a); /* CF Storage Card signature */
578 put_le16(p
+ 1, s
->cylinders
); /* Default cylinders */
579 put_le16(p
+ 3, s
->heads
); /* Default heads */
580 put_le16(p
+ 6, s
->sectors
); /* Default sectors per track */
581 put_le16(p
+ 7, s
->nb_sectors
>> 16); /* Sectors per card */
582 put_le16(p
+ 8, s
->nb_sectors
); /* Sectors per card */
583 snprintf(buf
, sizeof(buf
), "QM%05d", s
->drive_serial
);
584 padstr((uint8_t *)(p
+ 10), buf
, 20); /* Serial number in ASCII */
585 put_le16(p
+ 22, 0x0004); /* ECC bytes */
586 padstr((uint8_t *) (p
+ 23), QEMU_VERSION
, 8); /* Firmware Revision */
587 padstr((uint8_t *) (p
+ 27), "QEMU MICRODRIVE", 40);/* Model number */
588 #if MAX_MULT_SECTORS > 1
589 put_le16(p
+ 47, 0x8000 | MAX_MULT_SECTORS
);
591 put_le16(p
+ 47, 0x0000);
593 put_le16(p
+ 49, 0x0f00); /* Capabilities */
594 put_le16(p
+ 51, 0x0002); /* PIO cycle timing mode */
595 put_le16(p
+ 52, 0x0001); /* DMA cycle timing mode */
596 put_le16(p
+ 53, 0x0003); /* Translation params valid */
597 put_le16(p
+ 54, s
->cylinders
); /* Current cylinders */
598 put_le16(p
+ 55, s
->heads
); /* Current heads */
599 put_le16(p
+ 56, s
->sectors
); /* Current sectors */
600 put_le16(p
+ 57, cur_sec
); /* Current capacity */
601 put_le16(p
+ 58, cur_sec
>> 16); /* Current capacity */
602 if (s
->mult_sectors
) /* Multiple sector setting */
603 put_le16(p
+ 59, 0x100 | s
->mult_sectors
);
604 put_le16(p
+ 60, s
->nb_sectors
); /* Total LBA sectors */
605 put_le16(p
+ 61, s
->nb_sectors
>> 16); /* Total LBA sectors */
606 put_le16(p
+ 63, 0x0203); /* Multiword DMA capability */
607 put_le16(p
+ 64, 0x0001); /* Flow Control PIO support */
608 put_le16(p
+ 65, 0x0096); /* Min. Multiword DMA cycle */
609 put_le16(p
+ 66, 0x0096); /* Rec. Multiword DMA cycle */
610 put_le16(p
+ 68, 0x00b4); /* Min. PIO cycle time */
611 put_le16(p
+ 82, 0x400c); /* Command Set supported */
612 put_le16(p
+ 83, 0x7068); /* Command Set supported */
613 put_le16(p
+ 84, 0x4000); /* Features supported */
614 put_le16(p
+ 85, 0x000c); /* Command Set enabled */
615 put_le16(p
+ 86, 0x7044); /* Command Set enabled */
616 put_le16(p
+ 87, 0x4000); /* Features enabled */
617 put_le16(p
+ 91, 0x4060); /* Current APM level */
618 put_le16(p
+ 129, 0x0002); /* Current features option */
619 put_le16(p
+ 130, 0x0005); /* Reassigned sectors */
620 put_le16(p
+ 131, 0x0001); /* Initial power mode */
621 put_le16(p
+ 132, 0x0000); /* User signature */
622 put_le16(p
+ 160, 0x8100); /* Power requirement */
623 put_le16(p
+ 161, 0x8001); /* CF command set */
628 memcpy(s
->io_buffer
, p
, sizeof(s
->identify_data
));
631 static void ide_set_signature(IDEState
*s
)
633 s
->select
&= 0xf0; /* clear head */
649 static inline void ide_abort_command(IDEState
*s
)
651 s
->status
= READY_STAT
| ERR_STAT
;
655 static inline void ide_set_irq(IDEState
*s
)
657 BMDMAState
*bm
= s
->bmdma
;
658 if (!(s
->cmd
& IDE_CMD_DISABLE_IRQ
)) {
660 bm
->status
|= BM_STATUS_INT
;
662 qemu_irq_raise(s
->irq
);
666 /* prepare data transfer and tell what to do after */
667 static void ide_transfer_start(IDEState
*s
, uint8_t *buf
, int size
,
668 EndTransferFunc
*end_transfer_func
)
670 s
->end_transfer_func
= end_transfer_func
;
672 s
->data_end
= buf
+ size
;
673 s
->status
|= DRQ_STAT
;
676 static void ide_transfer_stop(IDEState
*s
)
678 s
->end_transfer_func
= ide_transfer_stop
;
679 s
->data_ptr
= s
->io_buffer
;
680 s
->data_end
= s
->io_buffer
;
681 s
->status
&= ~DRQ_STAT
;
684 static int64_t ide_get_sector(IDEState
*s
)
687 if (s
->select
& 0x40) {
690 sector_num
= ((s
->select
& 0x0f) << 24) | (s
->hcyl
<< 16) |
691 (s
->lcyl
<< 8) | s
->sector
;
693 sector_num
= ((int64_t)s
->hob_hcyl
<< 40) |
694 ((int64_t) s
->hob_lcyl
<< 32) |
695 ((int64_t) s
->hob_sector
<< 24) |
696 ((int64_t) s
->hcyl
<< 16) |
697 ((int64_t) s
->lcyl
<< 8) | s
->sector
;
700 sector_num
= ((s
->hcyl
<< 8) | s
->lcyl
) * s
->heads
* s
->sectors
+
701 (s
->select
& 0x0f) * s
->sectors
+ (s
->sector
- 1);
706 static void ide_set_sector(IDEState
*s
, int64_t sector_num
)
709 if (s
->select
& 0x40) {
711 s
->select
= (s
->select
& 0xf0) | (sector_num
>> 24);
712 s
->hcyl
= (sector_num
>> 16);
713 s
->lcyl
= (sector_num
>> 8);
714 s
->sector
= (sector_num
);
716 s
->sector
= sector_num
;
717 s
->lcyl
= sector_num
>> 8;
718 s
->hcyl
= sector_num
>> 16;
719 s
->hob_sector
= sector_num
>> 24;
720 s
->hob_lcyl
= sector_num
>> 32;
721 s
->hob_hcyl
= sector_num
>> 40;
724 cyl
= sector_num
/ (s
->heads
* s
->sectors
);
725 r
= sector_num
% (s
->heads
* s
->sectors
);
728 s
->select
= (s
->select
& 0xf0) | ((r
/ s
->sectors
) & 0x0f);
729 s
->sector
= (r
% s
->sectors
) + 1;
733 static void ide_sector_read(IDEState
*s
)
738 s
->status
= READY_STAT
| SEEK_STAT
;
739 s
->error
= 0; /* not needed by IDE spec, but needed by Windows */
740 sector_num
= ide_get_sector(s
);
743 /* no more sector to read from disk */
744 ide_transfer_stop(s
);
746 #if defined(DEBUG_IDE)
747 printf("read sector=%Ld\n", sector_num
);
749 if (n
> s
->req_nb_sectors
)
750 n
= s
->req_nb_sectors
;
751 ret
= bdrv_read(s
->bs
, sector_num
, s
->io_buffer
, n
);
752 ide_transfer_start(s
, s
->io_buffer
, 512 * n
, ide_sector_read
);
754 ide_set_sector(s
, sector_num
+ n
);
759 /* return 0 if buffer completed */
760 static int dma_buf_rw(BMDMAState
*bm
, int is_write
)
762 IDEState
*s
= bm
->ide_if
;
770 l
= s
->io_buffer_size
- s
->io_buffer_index
;
773 if (bm
->cur_prd_len
== 0) {
774 /* end of table (with a fail safe of one page) */
775 if (bm
->cur_prd_last
||
776 (bm
->cur_addr
- bm
->addr
) >= 4096)
778 cpu_physical_memory_read(bm
->cur_addr
, (uint8_t *)&prd
, 8);
780 prd
.addr
= le32_to_cpu(prd
.addr
);
781 prd
.size
= le32_to_cpu(prd
.size
);
782 len
= prd
.size
& 0xfffe;
785 bm
->cur_prd_len
= len
;
786 bm
->cur_prd_addr
= prd
.addr
;
787 bm
->cur_prd_last
= (prd
.size
& 0x80000000);
789 if (l
> bm
->cur_prd_len
)
793 cpu_physical_memory_write(bm
->cur_prd_addr
,
794 s
->io_buffer
+ s
->io_buffer_index
, l
);
796 cpu_physical_memory_read(bm
->cur_prd_addr
,
797 s
->io_buffer
+ s
->io_buffer_index
, l
);
799 bm
->cur_prd_addr
+= l
;
800 bm
->cur_prd_len
-= l
;
801 s
->io_buffer_index
+= l
;
807 /* XXX: handle errors */
808 static void ide_read_dma_cb(void *opaque
, int ret
)
810 BMDMAState
*bm
= opaque
;
811 IDEState
*s
= bm
->ide_if
;
815 n
= s
->io_buffer_size
>> 9;
816 sector_num
= ide_get_sector(s
);
819 ide_set_sector(s
, sector_num
);
821 if (dma_buf_rw(bm
, 1) == 0)
825 /* end of transfer ? */
826 if (s
->nsector
== 0) {
827 s
->status
= READY_STAT
| SEEK_STAT
;
830 bm
->status
&= ~BM_STATUS_DMAING
;
831 bm
->status
|= BM_STATUS_INT
;
838 /* launch next transfer */
840 if (n
> MAX_MULT_SECTORS
)
841 n
= MAX_MULT_SECTORS
;
842 s
->io_buffer_index
= 0;
843 s
->io_buffer_size
= n
* 512;
845 printf("aio_read: sector_num=%lld n=%d\n", sector_num
, n
);
847 bm
->aiocb
= bdrv_aio_read(s
->bs
, sector_num
, s
->io_buffer
, n
,
848 ide_read_dma_cb
, bm
);
851 static void ide_sector_read_dma(IDEState
*s
)
853 s
->status
= READY_STAT
| SEEK_STAT
| DRQ_STAT
| BUSY_STAT
;
854 s
->io_buffer_index
= 0;
855 s
->io_buffer_size
= 0;
856 ide_dma_start(s
, ide_read_dma_cb
);
859 static void ide_sector_write_timer_cb(void *opaque
)
861 IDEState
*s
= opaque
;
865 static void ide_sector_write(IDEState
*s
)
870 s
->status
= READY_STAT
| SEEK_STAT
;
871 sector_num
= ide_get_sector(s
);
872 #if defined(DEBUG_IDE)
873 printf("write sector=%Ld\n", sector_num
);
876 if (n
> s
->req_nb_sectors
)
877 n
= s
->req_nb_sectors
;
878 ret
= bdrv_write(s
->bs
, sector_num
, s
->io_buffer
, n
);
880 if (s
->nsector
== 0) {
881 /* no more sectors to write */
882 ide_transfer_stop(s
);
885 if (n1
> s
->req_nb_sectors
)
886 n1
= s
->req_nb_sectors
;
887 ide_transfer_start(s
, s
->io_buffer
, 512 * n1
, ide_sector_write
);
889 ide_set_sector(s
, sector_num
+ n
);
892 if (win2k_install_hack
&& ((++s
->irq_count
% 16) == 0)) {
893 /* It seems there is a bug in the Windows 2000 installer HDD
894 IDE driver which fills the disk with empty logs when the
895 IDE write IRQ comes too early. This hack tries to correct
896 that at the expense of slower write performances. Use this
897 option _only_ to install Windows 2000. You must disable it
899 qemu_mod_timer(s
->sector_write_timer
,
900 qemu_get_clock(vm_clock
) + (ticks_per_sec
/ 1000));
908 /* XXX: handle errors */
909 static void ide_write_dma_cb(void *opaque
, int ret
)
911 BMDMAState
*bm
= opaque
;
912 IDEState
*s
= bm
->ide_if
;
916 n
= s
->io_buffer_size
>> 9;
917 sector_num
= ide_get_sector(s
);
920 ide_set_sector(s
, sector_num
);
924 /* end of transfer ? */
925 if (s
->nsector
== 0) {
926 s
->status
= READY_STAT
| SEEK_STAT
;
929 bm
->status
&= ~BM_STATUS_DMAING
;
930 bm
->status
|= BM_STATUS_INT
;
937 /* launch next transfer */
939 if (n
> MAX_MULT_SECTORS
)
940 n
= MAX_MULT_SECTORS
;
941 s
->io_buffer_index
= 0;
942 s
->io_buffer_size
= n
* 512;
944 if (dma_buf_rw(bm
, 0) == 0)
947 printf("aio_write: sector_num=%lld n=%d\n", sector_num
, n
);
949 bm
->aiocb
= bdrv_aio_write(s
->bs
, sector_num
, s
->io_buffer
, n
,
950 ide_write_dma_cb
, bm
);
953 static void ide_sector_write_dma(IDEState
*s
)
955 s
->status
= READY_STAT
| SEEK_STAT
| DRQ_STAT
| BUSY_STAT
;
956 s
->io_buffer_index
= 0;
957 s
->io_buffer_size
= 0;
958 ide_dma_start(s
, ide_write_dma_cb
);
961 static void ide_atapi_cmd_ok(IDEState
*s
)
964 s
->status
= READY_STAT
;
965 s
->nsector
= (s
->nsector
& ~7) | ATAPI_INT_REASON_IO
| ATAPI_INT_REASON_CD
;
969 static void ide_atapi_cmd_error(IDEState
*s
, int sense_key
, int asc
)
971 #ifdef DEBUG_IDE_ATAPI
972 printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key
, asc
);
974 s
->error
= sense_key
<< 4;
975 s
->status
= READY_STAT
| ERR_STAT
;
976 s
->nsector
= (s
->nsector
& ~7) | ATAPI_INT_REASON_IO
| ATAPI_INT_REASON_CD
;
977 s
->sense_key
= sense_key
;
982 static inline void cpu_to_ube16(uint8_t *buf
, int val
)
988 static inline void cpu_to_ube32(uint8_t *buf
, unsigned int val
)
996 static inline int ube16_to_cpu(const uint8_t *buf
)
998 return (buf
[0] << 8) | buf
[1];
1001 static inline int ube32_to_cpu(const uint8_t *buf
)
1003 return (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
1006 static void lba_to_msf(uint8_t *buf
, int lba
)
1009 buf
[0] = (lba
/ 75) / 60;
1010 buf
[1] = (lba
/ 75) % 60;
1014 static void cd_data_to_raw(uint8_t *buf
, int lba
)
1018 memset(buf
+ 1, 0xff, 10);
1022 lba_to_msf(buf
, lba
);
1023 buf
[3] = 0x01; /* mode 1 data */
1027 /* XXX: ECC not computed */
1028 memset(buf
, 0, 288);
1031 static int cd_read_sector(BlockDriverState
*bs
, int lba
, uint8_t *buf
,
1036 switch(sector_size
) {
1038 ret
= bdrv_read(bs
, (int64_t)lba
<< 2, buf
, 4);
1041 ret
= bdrv_read(bs
, (int64_t)lba
<< 2, buf
+ 16, 4);
1044 cd_data_to_raw(buf
, lba
);
1053 static void ide_atapi_io_error(IDEState
*s
, int ret
)
1055 /* XXX: handle more errors */
1056 if (ret
== -ENOMEDIUM
) {
1057 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1058 ASC_MEDIUM_NOT_PRESENT
);
1060 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1061 ASC_LOGICAL_BLOCK_OOR
);
1065 /* The whole ATAPI transfer logic is handled in this function */
1066 static void ide_atapi_cmd_reply_end(IDEState
*s
)
1068 int byte_count_limit
, size
, ret
;
1069 #ifdef DEBUG_IDE_ATAPI
1070 printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
1071 s
->packet_transfer_size
,
1072 s
->elementary_transfer_size
,
1073 s
->io_buffer_index
);
1075 if (s
->packet_transfer_size
<= 0) {
1076 /* end of transfer */
1077 ide_transfer_stop(s
);
1078 s
->status
= READY_STAT
;
1079 s
->nsector
= (s
->nsector
& ~7) | ATAPI_INT_REASON_IO
| ATAPI_INT_REASON_CD
;
1081 #ifdef DEBUG_IDE_ATAPI
1082 printf("status=0x%x\n", s
->status
);
1085 /* see if a new sector must be read */
1086 if (s
->lba
!= -1 && s
->io_buffer_index
>= s
->cd_sector_size
) {
1087 ret
= cd_read_sector(s
->bs
, s
->lba
, s
->io_buffer
, s
->cd_sector_size
);
1089 ide_transfer_stop(s
);
1090 ide_atapi_io_error(s
, ret
);
1094 s
->io_buffer_index
= 0;
1096 if (s
->elementary_transfer_size
> 0) {
1097 /* there are some data left to transmit in this elementary
1099 size
= s
->cd_sector_size
- s
->io_buffer_index
;
1100 if (size
> s
->elementary_transfer_size
)
1101 size
= s
->elementary_transfer_size
;
1102 ide_transfer_start(s
, s
->io_buffer
+ s
->io_buffer_index
,
1103 size
, ide_atapi_cmd_reply_end
);
1104 s
->packet_transfer_size
-= size
;
1105 s
->elementary_transfer_size
-= size
;
1106 s
->io_buffer_index
+= size
;
1108 /* a new transfer is needed */
1109 s
->nsector
= (s
->nsector
& ~7) | ATAPI_INT_REASON_IO
;
1110 byte_count_limit
= s
->lcyl
| (s
->hcyl
<< 8);
1111 #ifdef DEBUG_IDE_ATAPI
1112 printf("byte_count_limit=%d\n", byte_count_limit
);
1114 if (byte_count_limit
== 0xffff)
1116 size
= s
->packet_transfer_size
;
1117 if (size
> byte_count_limit
) {
1118 /* byte count limit must be even if this case */
1119 if (byte_count_limit
& 1)
1121 size
= byte_count_limit
;
1124 s
->hcyl
= size
>> 8;
1125 s
->elementary_transfer_size
= size
;
1126 /* we cannot transmit more than one sector at a time */
1128 if (size
> (s
->cd_sector_size
- s
->io_buffer_index
))
1129 size
= (s
->cd_sector_size
- s
->io_buffer_index
);
1131 ide_transfer_start(s
, s
->io_buffer
+ s
->io_buffer_index
,
1132 size
, ide_atapi_cmd_reply_end
);
1133 s
->packet_transfer_size
-= size
;
1134 s
->elementary_transfer_size
-= size
;
1135 s
->io_buffer_index
+= size
;
1137 #ifdef DEBUG_IDE_ATAPI
1138 printf("status=0x%x\n", s
->status
);
1144 /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
1145 static void ide_atapi_cmd_reply(IDEState
*s
, int size
, int max_size
)
1147 if (size
> max_size
)
1149 s
->lba
= -1; /* no sector read */
1150 s
->packet_transfer_size
= size
;
1151 s
->io_buffer_size
= size
; /* dma: send the reply data as one chunk */
1152 s
->elementary_transfer_size
= 0;
1153 s
->io_buffer_index
= 0;
1156 s
->status
= READY_STAT
| DRQ_STAT
;
1157 ide_dma_start(s
, ide_atapi_cmd_read_dma_cb
);
1159 s
->status
= READY_STAT
;
1160 ide_atapi_cmd_reply_end(s
);
1164 /* start a CD-CDROM read command */
1165 static void ide_atapi_cmd_read_pio(IDEState
*s
, int lba
, int nb_sectors
,
1169 s
->packet_transfer_size
= nb_sectors
* sector_size
;
1170 s
->elementary_transfer_size
= 0;
1171 s
->io_buffer_index
= sector_size
;
1172 s
->cd_sector_size
= sector_size
;
1174 s
->status
= READY_STAT
;
1175 ide_atapi_cmd_reply_end(s
);
1178 /* ATAPI DMA support */
1180 /* XXX: handle read errors */
1181 static void ide_atapi_cmd_read_dma_cb(void *opaque
, int ret
)
1183 BMDMAState
*bm
= opaque
;
1184 IDEState
*s
= bm
->ide_if
;
1188 ide_atapi_io_error(s
, ret
);
1192 if (s
->io_buffer_size
> 0) {
1194 * For a cdrom read sector command (s->lba != -1),
1195 * adjust the lba for the next s->io_buffer_size chunk
1196 * and dma the current chunk.
1197 * For a command != read (s->lba == -1), just transfer
1201 if (s
->cd_sector_size
== 2352) {
1203 cd_data_to_raw(s
->io_buffer
, s
->lba
);
1205 n
= s
->io_buffer_size
>> 11;
1209 s
->packet_transfer_size
-= s
->io_buffer_size
;
1210 if (dma_buf_rw(bm
, 1) == 0)
1214 if (s
->packet_transfer_size
<= 0) {
1215 s
->status
= READY_STAT
;
1216 s
->nsector
= (s
->nsector
& ~7) | ATAPI_INT_REASON_IO
| ATAPI_INT_REASON_CD
;
1219 bm
->status
&= ~BM_STATUS_DMAING
;
1220 bm
->status
|= BM_STATUS_INT
;
1227 s
->io_buffer_index
= 0;
1228 if (s
->cd_sector_size
== 2352) {
1230 s
->io_buffer_size
= s
->cd_sector_size
;
1233 n
= s
->packet_transfer_size
>> 11;
1234 if (n
> (MAX_MULT_SECTORS
/ 4))
1235 n
= (MAX_MULT_SECTORS
/ 4);
1236 s
->io_buffer_size
= n
* 2048;
1240 printf("aio_read_cd: lba=%u n=%d\n", s
->lba
, n
);
1242 bm
->aiocb
= bdrv_aio_read(s
->bs
, (int64_t)s
->lba
<< 2,
1243 s
->io_buffer
+ data_offset
, n
* 4,
1244 ide_atapi_cmd_read_dma_cb
, bm
);
1246 /* Note: media not present is the most likely case */
1247 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1248 ASC_MEDIUM_NOT_PRESENT
);
1253 /* start a CD-CDROM read command with DMA */
1254 /* XXX: test if DMA is available */
1255 static void ide_atapi_cmd_read_dma(IDEState
*s
, int lba
, int nb_sectors
,
1259 s
->packet_transfer_size
= nb_sectors
* sector_size
;
1260 s
->io_buffer_index
= 0;
1261 s
->io_buffer_size
= 0;
1262 s
->cd_sector_size
= sector_size
;
1264 /* XXX: check if BUSY_STAT should be set */
1265 s
->status
= READY_STAT
| DRQ_STAT
| BUSY_STAT
;
1266 ide_dma_start(s
, ide_atapi_cmd_read_dma_cb
);
1269 static void ide_atapi_cmd_read(IDEState
*s
, int lba
, int nb_sectors
,
1272 #ifdef DEBUG_IDE_ATAPI
1273 printf("read %s: LBA=%d nb_sectors=%d\n", s
->atapi_dma
? "dma" : "pio",
1277 ide_atapi_cmd_read_dma(s
, lba
, nb_sectors
, sector_size
);
1279 ide_atapi_cmd_read_pio(s
, lba
, nb_sectors
, sector_size
);
1283 static void ide_atapi_cmd(IDEState
*s
)
1285 const uint8_t *packet
;
1289 packet
= s
->io_buffer
;
1291 #ifdef DEBUG_IDE_ATAPI
1294 printf("ATAPI limit=0x%x packet:", s
->lcyl
| (s
->hcyl
<< 8));
1295 for(i
= 0; i
< ATAPI_PACKET_SIZE
; i
++) {
1296 printf(" %02x", packet
[i
]);
1301 switch(s
->io_buffer
[0]) {
1302 case GPCMD_TEST_UNIT_READY
:
1303 if (bdrv_is_inserted(s
->bs
)) {
1304 ide_atapi_cmd_ok(s
);
1306 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1307 ASC_MEDIUM_NOT_PRESENT
);
1310 case GPCMD_MODE_SENSE_10
:
1313 max_len
= ube16_to_cpu(packet
+ 7);
1314 action
= packet
[2] >> 6;
1315 code
= packet
[2] & 0x3f;
1317 case 0: /* current values */
1319 case 0x01: /* error recovery */
1320 cpu_to_ube16(&buf
[0], 16 + 6);
1336 ide_atapi_cmd_reply(s
, 16, max_len
);
1339 cpu_to_ube16(&buf
[0], 28 + 6);
1354 buf
[14] = (1 << 0) | (1 << 3) | (1 << 5);
1355 if (bdrv_is_locked(s
->bs
))
1358 cpu_to_ube16(&buf
[16], 706);
1361 cpu_to_ube16(&buf
[20], 512);
1362 cpu_to_ube16(&buf
[22], 706);
1367 ide_atapi_cmd_reply(s
, 28, max_len
);
1373 case 1: /* changeable values */
1375 case 2: /* default values */
1378 case 3: /* saved values */
1379 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1380 ASC_SAVING_PARAMETERS_NOT_SUPPORTED
);
1385 case GPCMD_REQUEST_SENSE
:
1386 max_len
= packet
[4];
1388 buf
[0] = 0x70 | (1 << 7);
1389 buf
[2] = s
->sense_key
;
1392 ide_atapi_cmd_reply(s
, 18, max_len
);
1394 case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL
:
1395 if (bdrv_is_inserted(s
->bs
)) {
1396 bdrv_set_locked(s
->bs
, packet
[4] & 1);
1397 ide_atapi_cmd_ok(s
);
1399 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1400 ASC_MEDIUM_NOT_PRESENT
);
1406 int nb_sectors
, lba
;
1408 if (packet
[0] == GPCMD_READ_10
)
1409 nb_sectors
= ube16_to_cpu(packet
+ 7);
1411 nb_sectors
= ube32_to_cpu(packet
+ 6);
1412 lba
= ube32_to_cpu(packet
+ 2);
1413 if (nb_sectors
== 0) {
1414 ide_atapi_cmd_ok(s
);
1417 ide_atapi_cmd_read(s
, lba
, nb_sectors
, 2048);
1422 int nb_sectors
, lba
, transfer_request
;
1424 nb_sectors
= (packet
[6] << 16) | (packet
[7] << 8) | packet
[8];
1425 lba
= ube32_to_cpu(packet
+ 2);
1426 if (nb_sectors
== 0) {
1427 ide_atapi_cmd_ok(s
);
1430 transfer_request
= packet
[9];
1431 switch(transfer_request
& 0xf8) {
1434 ide_atapi_cmd_ok(s
);
1438 ide_atapi_cmd_read(s
, lba
, nb_sectors
, 2048);
1442 ide_atapi_cmd_read(s
, lba
, nb_sectors
, 2352);
1445 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1446 ASC_INV_FIELD_IN_CMD_PACKET
);
1454 int64_t total_sectors
;
1456 bdrv_get_geometry(s
->bs
, &total_sectors
);
1457 total_sectors
>>= 2;
1458 if (total_sectors
<= 0) {
1459 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1460 ASC_MEDIUM_NOT_PRESENT
);
1463 lba
= ube32_to_cpu(packet
+ 2);
1464 if (lba
>= total_sectors
) {
1465 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1466 ASC_LOGICAL_BLOCK_OOR
);
1469 ide_atapi_cmd_ok(s
);
1472 case GPCMD_START_STOP_UNIT
:
1475 start
= packet
[4] & 1;
1476 eject
= (packet
[4] >> 1) & 1;
1478 if (eject
&& !start
) {
1479 /* eject the disk */
1480 bdrv_eject(s
->bs
, 1);
1481 } else if (eject
&& start
) {
1482 /* close the tray */
1483 bdrv_eject(s
->bs
, 0);
1485 ide_atapi_cmd_ok(s
);
1488 case GPCMD_MECHANISM_STATUS
:
1490 max_len
= ube16_to_cpu(packet
+ 8);
1491 cpu_to_ube16(buf
, 0);
1492 /* no current LBA */
1497 cpu_to_ube16(buf
+ 6, 0);
1498 ide_atapi_cmd_reply(s
, 8, max_len
);
1501 case GPCMD_READ_TOC_PMA_ATIP
:
1503 int format
, msf
, start_track
, len
;
1504 int64_t total_sectors
;
1506 bdrv_get_geometry(s
->bs
, &total_sectors
);
1507 total_sectors
>>= 2;
1508 if (total_sectors
<= 0) {
1509 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1510 ASC_MEDIUM_NOT_PRESENT
);
1513 max_len
= ube16_to_cpu(packet
+ 7);
1514 format
= packet
[9] >> 6;
1515 msf
= (packet
[1] >> 1) & 1;
1516 start_track
= packet
[6];
1519 len
= cdrom_read_toc(total_sectors
, buf
, msf
, start_track
);
1522 ide_atapi_cmd_reply(s
, len
, max_len
);
1525 /* multi session : only a single session defined */
1530 ide_atapi_cmd_reply(s
, 12, max_len
);
1533 len
= cdrom_read_toc_raw(total_sectors
, buf
, msf
, start_track
);
1536 ide_atapi_cmd_reply(s
, len
, max_len
);
1540 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1541 ASC_INV_FIELD_IN_CMD_PACKET
);
1546 case GPCMD_READ_CDVD_CAPACITY
:
1548 int64_t total_sectors
;
1550 bdrv_get_geometry(s
->bs
, &total_sectors
);
1551 total_sectors
>>= 2;
1552 if (total_sectors
<= 0) {
1553 ide_atapi_cmd_error(s
, SENSE_NOT_READY
,
1554 ASC_MEDIUM_NOT_PRESENT
);
1557 /* NOTE: it is really the number of sectors minus 1 */
1558 cpu_to_ube32(buf
, total_sectors
- 1);
1559 cpu_to_ube32(buf
+ 4, 2048);
1560 ide_atapi_cmd_reply(s
, 8, 8);
1564 max_len
= packet
[4];
1565 buf
[0] = 0x05; /* CD-ROM */
1566 buf
[1] = 0x80; /* removable */
1567 buf
[2] = 0x00; /* ISO */
1568 buf
[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1569 buf
[4] = 31; /* additionnal length */
1570 buf
[5] = 0; /* reserved */
1571 buf
[6] = 0; /* reserved */
1572 buf
[7] = 0; /* reserved */
1573 padstr8(buf
+ 8, 8, "QEMU");
1574 padstr8(buf
+ 16, 16, "QEMU CD-ROM");
1575 padstr8(buf
+ 32, 4, QEMU_VERSION
);
1576 ide_atapi_cmd_reply(s
, 36, max_len
);
1579 ide_atapi_cmd_error(s
, SENSE_ILLEGAL_REQUEST
,
1580 ASC_ILLEGAL_OPCODE
);
1585 static void ide_cfata_metadata_inquiry(IDEState
*s
)
1590 p
= (uint16_t *) s
->io_buffer
;
1591 memset(p
, 0, 0x200);
1592 spd
= ((s
->mdata_size
- 1) >> 9) + 1;
1594 put_le16(p
+ 0, 0x0001); /* Data format revision */
1595 put_le16(p
+ 1, 0x0000); /* Media property: silicon */
1596 put_le16(p
+ 2, s
->media_changed
); /* Media status */
1597 put_le16(p
+ 3, s
->mdata_size
& 0xffff); /* Capacity in bytes (low) */
1598 put_le16(p
+ 4, s
->mdata_size
>> 16); /* Capacity in bytes (high) */
1599 put_le16(p
+ 5, spd
& 0xffff); /* Sectors per device (low) */
1600 put_le16(p
+ 6, spd
>> 16); /* Sectors per device (high) */
1603 static void ide_cfata_metadata_read(IDEState
*s
)
1607 if (((s
->hcyl
<< 16) | s
->lcyl
) << 9 > s
->mdata_size
+ 2) {
1608 s
->status
= ERR_STAT
;
1609 s
->error
= ABRT_ERR
;
1613 p
= (uint16_t *) s
->io_buffer
;
1614 memset(p
, 0, 0x200);
1616 put_le16(p
+ 0, s
->media_changed
); /* Media status */
1617 memcpy(p
+ 1, s
->mdata_storage
+ (((s
->hcyl
<< 16) | s
->lcyl
) << 9),
1618 MIN(MIN(s
->mdata_size
- (((s
->hcyl
<< 16) | s
->lcyl
) << 9),
1619 s
->nsector
<< 9), 0x200 - 2));
1622 static void ide_cfata_metadata_write(IDEState
*s
)
1624 if (((s
->hcyl
<< 16) | s
->lcyl
) << 9 > s
->mdata_size
+ 2) {
1625 s
->status
= ERR_STAT
;
1626 s
->error
= ABRT_ERR
;
1630 s
->media_changed
= 0;
1632 memcpy(s
->mdata_storage
+ (((s
->hcyl
<< 16) | s
->lcyl
) << 9),
1634 MIN(MIN(s
->mdata_size
- (((s
->hcyl
<< 16) | s
->lcyl
) << 9),
1635 s
->nsector
<< 9), 0x200 - 2));
1638 /* called when the inserted state of the media has changed */
1639 static void cdrom_change_cb(void *opaque
)
1641 IDEState
*s
= opaque
;
1644 /* XXX: send interrupt too */
1645 bdrv_get_geometry(s
->bs
, &nb_sectors
);
1646 s
->nb_sectors
= nb_sectors
;
1649 static void ide_cmd_lba48_transform(IDEState
*s
, int lba48
)
1653 /* handle the 'magic' 0 nsector count conversion here. to avoid
1654 * fiddling with the rest of the read logic, we just store the
1655 * full sector count in ->nsector and ignore ->hob_nsector from now
1661 if (!s
->nsector
&& !s
->hob_nsector
)
1664 int lo
= s
->nsector
;
1665 int hi
= s
->hob_nsector
;
1667 s
->nsector
= (hi
<< 8) | lo
;
1672 static void ide_clear_hob(IDEState
*ide_if
)
1674 /* any write clears HOB high bit of device control register */
1675 ide_if
[0].select
&= ~(1 << 7);
1676 ide_if
[1].select
&= ~(1 << 7);
1679 static void ide_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1681 IDEState
*ide_if
= opaque
;
1687 printf("IDE: write addr=0x%x val=0x%02x\n", addr
, val
);
1695 ide_clear_hob(ide_if
);
1696 /* NOTE: data is written to the two drives */
1697 ide_if
[0].hob_feature
= ide_if
[0].feature
;
1698 ide_if
[1].hob_feature
= ide_if
[1].feature
;
1699 ide_if
[0].feature
= val
;
1700 ide_if
[1].feature
= val
;
1703 ide_clear_hob(ide_if
);
1704 ide_if
[0].hob_nsector
= ide_if
[0].nsector
;
1705 ide_if
[1].hob_nsector
= ide_if
[1].nsector
;
1706 ide_if
[0].nsector
= val
;
1707 ide_if
[1].nsector
= val
;
1710 ide_clear_hob(ide_if
);
1711 ide_if
[0].hob_sector
= ide_if
[0].sector
;
1712 ide_if
[1].hob_sector
= ide_if
[1].sector
;
1713 ide_if
[0].sector
= val
;
1714 ide_if
[1].sector
= val
;
1717 ide_clear_hob(ide_if
);
1718 ide_if
[0].hob_lcyl
= ide_if
[0].lcyl
;
1719 ide_if
[1].hob_lcyl
= ide_if
[1].lcyl
;
1720 ide_if
[0].lcyl
= val
;
1721 ide_if
[1].lcyl
= val
;
1724 ide_clear_hob(ide_if
);
1725 ide_if
[0].hob_hcyl
= ide_if
[0].hcyl
;
1726 ide_if
[1].hob_hcyl
= ide_if
[1].hcyl
;
1727 ide_if
[0].hcyl
= val
;
1728 ide_if
[1].hcyl
= val
;
1731 /* FIXME: HOB readback uses bit 7 */
1732 ide_if
[0].select
= (val
& ~0x10) | 0xa0;
1733 ide_if
[1].select
= (val
| 0x10) | 0xa0;
1735 unit
= (val
>> 4) & 1;
1737 ide_if
->cur_drive
= s
;
1742 #if defined(DEBUG_IDE)
1743 printf("ide: CMD=%02x\n", val
);
1745 s
= ide_if
->cur_drive
;
1746 /* ignore commands to non existant slave */
1747 if (s
!= ide_if
&& !s
->bs
)
1752 if (s
->bs
&& !s
->is_cdrom
) {
1756 ide_cfata_identify(s
);
1757 s
->status
= READY_STAT
| SEEK_STAT
;
1758 ide_transfer_start(s
, s
->io_buffer
, 512, ide_transfer_stop
);
1761 ide_set_signature(s
);
1763 ide_abort_command(s
);
1770 s
->status
= READY_STAT
| SEEK_STAT
;
1774 if (s
->is_cf
&& s
->nsector
== 0) {
1775 /* Disable Read and Write Multiple */
1776 s
->mult_sectors
= 0;
1777 s
->status
= READY_STAT
;
1778 } else if ((s
->nsector
& 0xff) != 0 &&
1779 ((s
->nsector
& 0xff) > MAX_MULT_SECTORS
||
1780 (s
->nsector
& (s
->nsector
- 1)) != 0)) {
1781 ide_abort_command(s
);
1783 s
->mult_sectors
= s
->nsector
& 0xff;
1784 s
->status
= READY_STAT
;
1788 case WIN_VERIFY_EXT
:
1791 case WIN_VERIFY_ONCE
:
1792 /* do sector number check ? */
1793 ide_cmd_lba48_transform(s
, lba48
);
1794 s
->status
= READY_STAT
;
1803 ide_cmd_lba48_transform(s
, lba48
);
1804 s
->req_nb_sectors
= 1;
1810 case WIN_WRITE_ONCE
:
1811 case CFA_WRITE_SECT_WO_ERASE
:
1812 case WIN_WRITE_VERIFY
:
1813 ide_cmd_lba48_transform(s
, lba48
);
1815 s
->status
= SEEK_STAT
| READY_STAT
;
1816 s
->req_nb_sectors
= 1;
1817 ide_transfer_start(s
, s
->io_buffer
, 512, ide_sector_write
);
1818 s
->media_changed
= 1;
1820 case WIN_MULTREAD_EXT
:
1823 if (!s
->mult_sectors
)
1825 ide_cmd_lba48_transform(s
, lba48
);
1826 s
->req_nb_sectors
= s
->mult_sectors
;
1829 case WIN_MULTWRITE_EXT
:
1832 case CFA_WRITE_MULTI_WO_ERASE
:
1833 if (!s
->mult_sectors
)
1835 ide_cmd_lba48_transform(s
, lba48
);
1837 s
->status
= SEEK_STAT
| READY_STAT
;
1838 s
->req_nb_sectors
= s
->mult_sectors
;
1840 if (n
> s
->req_nb_sectors
)
1841 n
= s
->req_nb_sectors
;
1842 ide_transfer_start(s
, s
->io_buffer
, 512 * n
, ide_sector_write
);
1843 s
->media_changed
= 1;
1845 case WIN_READDMA_EXT
:
1848 case WIN_READDMA_ONCE
:
1851 ide_cmd_lba48_transform(s
, lba48
);
1852 ide_sector_read_dma(s
);
1854 case WIN_WRITEDMA_EXT
:
1857 case WIN_WRITEDMA_ONCE
:
1860 ide_cmd_lba48_transform(s
, lba48
);
1861 ide_sector_write_dma(s
);
1862 s
->media_changed
= 1;
1864 case WIN_READ_NATIVE_MAX_EXT
:
1866 case WIN_READ_NATIVE_MAX
:
1867 ide_cmd_lba48_transform(s
, lba48
);
1868 ide_set_sector(s
, s
->nb_sectors
- 1);
1869 s
->status
= READY_STAT
;
1872 case WIN_CHECKPOWERMODE1
:
1873 case WIN_CHECKPOWERMODE2
:
1874 s
->nsector
= 0xff; /* device active or idle */
1875 s
->status
= READY_STAT
;
1878 case WIN_SETFEATURES
:
1881 /* XXX: valid for CDROM ? */
1882 switch(s
->feature
) {
1883 case 0xcc: /* reverting to power-on defaults enable */
1884 case 0x66: /* reverting to power-on defaults disable */
1885 case 0x02: /* write cache enable */
1886 case 0x82: /* write cache disable */
1887 case 0xaa: /* read look-ahead enable */
1888 case 0x55: /* read look-ahead disable */
1889 case 0x05: /* set advanced power management mode */
1890 case 0x85: /* disable advanced power management mode */
1891 case 0x69: /* NOP */
1892 case 0x67: /* NOP */
1893 case 0x96: /* NOP */
1894 case 0x9a: /* NOP */
1895 s
->status
= READY_STAT
| SEEK_STAT
;
1898 case 0x03: { /* set transfer mode */
1899 uint8_t val
= s
->nsector
& 0x07;
1901 switch (s
->nsector
>> 3) {
1902 case 0x00: /* pio default */
1903 case 0x01: /* pio mode */
1904 put_le16(s
->identify_data
+ 63,0x07);
1905 put_le16(s
->identify_data
+ 88,0x3f);
1907 case 0x04: /* mdma mode */
1908 put_le16(s
->identify_data
+ 63,0x07 | (1 << (val
+ 8)));
1909 put_le16(s
->identify_data
+ 88,0x3f);
1911 case 0x08: /* udma mode */
1912 put_le16(s
->identify_data
+ 63,0x07);
1913 put_le16(s
->identify_data
+ 88,0x3f | (1 << (val
+ 8)));
1918 s
->status
= READY_STAT
| SEEK_STAT
;
1926 case WIN_FLUSH_CACHE
:
1927 case WIN_FLUSH_CACHE_EXT
:
1930 s
->status
= READY_STAT
;
1933 case WIN_STANDBYNOW1
:
1934 case WIN_STANDBYNOW2
:
1935 case WIN_IDLEIMMEDIATE
:
1936 case CFA_IDLEIMMEDIATE
:
1939 s
->status
= READY_STAT
;
1942 /* ATAPI commands */
1945 ide_atapi_identify(s
);
1946 s
->status
= READY_STAT
| SEEK_STAT
;
1947 ide_transfer_start(s
, s
->io_buffer
, 512, ide_transfer_stop
);
1949 ide_abort_command(s
);
1954 ide_set_signature(s
);
1955 s
->status
= 0x00; /* NOTE: READY is _not_ set */
1961 ide_set_signature(s
);
1962 s
->status
= 0x00; /* NOTE: READY is _not_ set */
1968 /* overlapping commands not supported */
1969 if (s
->feature
& 0x02)
1971 s
->atapi_dma
= s
->feature
& 1;
1973 ide_transfer_start(s
, s
->io_buffer
, ATAPI_PACKET_SIZE
,
1976 /* CF-ATA commands */
1977 case CFA_REQ_EXT_ERROR_CODE
:
1980 s
->error
= 0x09; /* miscellaneous error */
1981 s
->status
= READY_STAT
;
1984 case CFA_ERASE_SECTORS
:
1985 case CFA_WEAR_LEVEL
:
1988 if (val
== CFA_WEAR_LEVEL
)
1990 if (val
== CFA_ERASE_SECTORS
)
1991 s
->media_changed
= 1;
1993 s
->status
= READY_STAT
;
1996 case CFA_TRANSLATE_SECTOR
:
2000 s
->status
= READY_STAT
;
2001 memset(s
->io_buffer
, 0, 0x200);
2002 s
->io_buffer
[0x00] = s
->hcyl
; /* Cyl MSB */
2003 s
->io_buffer
[0x01] = s
->lcyl
; /* Cyl LSB */
2004 s
->io_buffer
[0x02] = s
->select
; /* Head */
2005 s
->io_buffer
[0x03] = s
->sector
; /* Sector */
2006 s
->io_buffer
[0x04] = ide_get_sector(s
) >> 16; /* LBA MSB */
2007 s
->io_buffer
[0x05] = ide_get_sector(s
) >> 8; /* LBA */
2008 s
->io_buffer
[0x06] = ide_get_sector(s
) >> 0; /* LBA LSB */
2009 s
->io_buffer
[0x13] = 0x00; /* Erase flag */
2010 s
->io_buffer
[0x18] = 0x00; /* Hot count */
2011 s
->io_buffer
[0x19] = 0x00; /* Hot count */
2012 s
->io_buffer
[0x1a] = 0x01; /* Hot count */
2013 ide_transfer_start(s
, s
->io_buffer
, 0x200, ide_transfer_stop
);
2016 case CFA_ACCESS_METADATA_STORAGE
:
2019 switch (s
->feature
) {
2020 case 0x02: /* Inquiry Metadata Storage */
2021 ide_cfata_metadata_inquiry(s
);
2023 case 0x03: /* Read Metadata Storage */
2024 ide_cfata_metadata_read(s
);
2026 case 0x04: /* Write Metadata Storage */
2027 ide_cfata_metadata_write(s
);
2032 ide_transfer_start(s
, s
->io_buffer
, 0x200, ide_transfer_stop
);
2033 s
->status
= 0x00; /* NOTE: READY is _not_ set */
2036 case IBM_SENSE_CONDITION
:
2039 switch (s
->feature
) {
2040 case 0x01: /* sense temperature in device */
2041 s
->nsector
= 0x50; /* +20 C */
2046 s
->status
= READY_STAT
;
2051 ide_abort_command(s
);
2058 static uint32_t ide_ioport_read(void *opaque
, uint32_t addr1
)
2060 IDEState
*ide_if
= opaque
;
2061 IDEState
*s
= ide_if
->cur_drive
;
2066 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2067 //hob = s->select & (1 << 7);
2074 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2079 ret
= s
->hob_feature
;
2082 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2085 ret
= s
->nsector
& 0xff;
2087 ret
= s
->hob_nsector
;
2090 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2095 ret
= s
->hob_sector
;
2098 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2106 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2114 if (!ide_if
[0].bs
&& !ide_if
[1].bs
)
2121 if ((!ide_if
[0].bs
&& !ide_if
[1].bs
) ||
2122 (s
!= ide_if
&& !s
->bs
))
2126 qemu_irq_lower(s
->irq
);
2130 printf("ide: read addr=0x%x val=%02x\n", addr1
, ret
);
2135 static uint32_t ide_status_read(void *opaque
, uint32_t addr
)
2137 IDEState
*ide_if
= opaque
;
2138 IDEState
*s
= ide_if
->cur_drive
;
2141 if ((!ide_if
[0].bs
&& !ide_if
[1].bs
) ||
2142 (s
!= ide_if
&& !s
->bs
))
2147 printf("ide: read status addr=0x%x val=%02x\n", addr
, ret
);
2152 static void ide_cmd_write(void *opaque
, uint32_t addr
, uint32_t val
)
2154 IDEState
*ide_if
= opaque
;
2159 printf("ide: write control addr=0x%x val=%02x\n", addr
, val
);
2161 /* common for both drives */
2162 if (!(ide_if
[0].cmd
& IDE_CMD_RESET
) &&
2163 (val
& IDE_CMD_RESET
)) {
2164 /* reset low to high */
2165 for(i
= 0;i
< 2; i
++) {
2167 s
->status
= BUSY_STAT
| SEEK_STAT
;
2170 } else if ((ide_if
[0].cmd
& IDE_CMD_RESET
) &&
2171 !(val
& IDE_CMD_RESET
)) {
2173 for(i
= 0;i
< 2; i
++) {
2176 s
->status
= 0x00; /* NOTE: READY is _not_ set */
2178 s
->status
= READY_STAT
| SEEK_STAT
;
2179 ide_set_signature(s
);
2183 ide_if
[0].cmd
= val
;
2184 ide_if
[1].cmd
= val
;
2187 static void ide_data_writew(void *opaque
, uint32_t addr
, uint32_t val
)
2189 IDEState
*s
= ((IDEState
*)opaque
)->cur_drive
;
2193 *(uint16_t *)p
= le16_to_cpu(val
);
2196 if (p
>= s
->data_end
)
2197 s
->end_transfer_func(s
);
2200 static uint32_t ide_data_readw(void *opaque
, uint32_t addr
)
2202 IDEState
*s
= ((IDEState
*)opaque
)->cur_drive
;
2206 ret
= cpu_to_le16(*(uint16_t *)p
);
2209 if (p
>= s
->data_end
)
2210 s
->end_transfer_func(s
);
2214 static void ide_data_writel(void *opaque
, uint32_t addr
, uint32_t val
)
2216 IDEState
*s
= ((IDEState
*)opaque
)->cur_drive
;
2220 *(uint32_t *)p
= le32_to_cpu(val
);
2223 if (p
>= s
->data_end
)
2224 s
->end_transfer_func(s
);
2227 static uint32_t ide_data_readl(void *opaque
, uint32_t addr
)
2229 IDEState
*s
= ((IDEState
*)opaque
)->cur_drive
;
2234 ret
= cpu_to_le32(*(uint32_t *)p
);
2237 if (p
>= s
->data_end
)
2238 s
->end_transfer_func(s
);
2242 static void ide_dummy_transfer_stop(IDEState
*s
)
2244 s
->data_ptr
= s
->io_buffer
;
2245 s
->data_end
= s
->io_buffer
;
2246 s
->io_buffer
[0] = 0xff;
2247 s
->io_buffer
[1] = 0xff;
2248 s
->io_buffer
[2] = 0xff;
2249 s
->io_buffer
[3] = 0xff;
2252 static void ide_reset(IDEState
*s
)
2255 s
->mult_sectors
= 0;
2257 s
->mult_sectors
= MAX_MULT_SECTORS
;
2260 s
->status
= READY_STAT
;
2261 ide_set_signature(s
);
2262 /* init the transfer handler so that 0xffff is returned on data
2264 s
->end_transfer_func
= ide_dummy_transfer_stop
;
2265 ide_dummy_transfer_stop(s
);
2266 s
->media_changed
= 0;
2270 uint8_t boot_ind
; /* 0x80 - active */
2271 uint8_t head
; /* starting head */
2272 uint8_t sector
; /* starting sector */
2273 uint8_t cyl
; /* starting cylinder */
2274 uint8_t sys_ind
; /* What partition type */
2275 uint8_t end_head
; /* end head */
2276 uint8_t end_sector
; /* end sector */
2277 uint8_t end_cyl
; /* end cylinder */
2278 uint32_t start_sect
; /* starting sector counting from 0 */
2279 uint32_t nr_sects
; /* nr of sectors in partition */
2280 } __attribute__((packed
));
2282 /* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
2283 static int guess_disk_lchs(IDEState
*s
,
2284 int *pcylinders
, int *pheads
, int *psectors
)
2287 int ret
, i
, heads
, sectors
, cylinders
;
2288 struct partition
*p
;
2291 ret
= bdrv_read(s
->bs
, 0, buf
, 1);
2294 /* test msdos magic */
2295 if (buf
[510] != 0x55 || buf
[511] != 0xaa)
2297 for(i
= 0; i
< 4; i
++) {
2298 p
= ((struct partition
*)(buf
+ 0x1be)) + i
;
2299 nr_sects
= le32_to_cpu(p
->nr_sects
);
2300 if (nr_sects
&& p
->end_head
) {
2301 /* We make the assumption that the partition terminates on
2302 a cylinder boundary */
2303 heads
= p
->end_head
+ 1;
2304 sectors
= p
->end_sector
& 63;
2307 cylinders
= s
->nb_sectors
/ (heads
* sectors
);
2308 if (cylinders
< 1 || cylinders
> 16383)
2311 *psectors
= sectors
;
2312 *pcylinders
= cylinders
;
2314 printf("guessed geometry: LCHS=%d %d %d\n",
2315 cylinders
, heads
, sectors
);
2323 static void ide_init2(IDEState
*ide_state
,
2324 BlockDriverState
*hd0
, BlockDriverState
*hd1
,
2328 static int drive_serial
= 1;
2329 int i
, cylinders
, heads
, secs
, translation
, lba_detected
= 0;
2332 for(i
= 0; i
< 2; i
++) {
2339 bdrv_get_geometry(s
->bs
, &nb_sectors
);
2340 s
->nb_sectors
= nb_sectors
;
2341 /* if a geometry hint is available, use it */
2342 bdrv_get_geometry_hint(s
->bs
, &cylinders
, &heads
, &secs
);
2343 translation
= bdrv_get_translation_hint(s
->bs
);
2344 if (cylinders
!= 0) {
2345 s
->cylinders
= cylinders
;
2349 if (guess_disk_lchs(s
, &cylinders
, &heads
, &secs
) == 0) {
2351 /* if heads > 16, it means that a BIOS LBA
2352 translation was active, so the default
2353 hardware geometry is OK */
2355 goto default_geometry
;
2357 s
->cylinders
= cylinders
;
2360 /* disable any translation to be in sync with
2361 the logical geometry */
2362 if (translation
== BIOS_ATA_TRANSLATION_AUTO
) {
2363 bdrv_set_translation_hint(s
->bs
,
2364 BIOS_ATA_TRANSLATION_NONE
);
2369 /* if no geometry, use a standard physical disk geometry */
2370 cylinders
= nb_sectors
/ (16 * 63);
2371 if (cylinders
> 16383)
2373 else if (cylinders
< 2)
2375 s
->cylinders
= cylinders
;
2378 if ((lba_detected
== 1) && (translation
== BIOS_ATA_TRANSLATION_AUTO
)) {
2379 if ((s
->cylinders
* s
->heads
) <= 131072) {
2380 bdrv_set_translation_hint(s
->bs
,
2381 BIOS_ATA_TRANSLATION_LARGE
);
2383 bdrv_set_translation_hint(s
->bs
,
2384 BIOS_ATA_TRANSLATION_LBA
);
2388 bdrv_set_geometry_hint(s
->bs
, s
->cylinders
, s
->heads
, s
->sectors
);
2390 if (bdrv_get_type_hint(s
->bs
) == BDRV_TYPE_CDROM
) {
2392 bdrv_set_change_cb(s
->bs
, cdrom_change_cb
, s
);
2395 s
->drive_serial
= drive_serial
++;
2397 s
->sector_write_timer
= qemu_new_timer(vm_clock
,
2398 ide_sector_write_timer_cb
, s
);
2403 static void ide_init_ioport(IDEState
*ide_state
, int iobase
, int iobase2
)
2405 register_ioport_write(iobase
, 8, 1, ide_ioport_write
, ide_state
);
2406 register_ioport_read(iobase
, 8, 1, ide_ioport_read
, ide_state
);
2408 register_ioport_read(iobase2
, 1, 1, ide_status_read
, ide_state
);
2409 register_ioport_write(iobase2
, 1, 1, ide_cmd_write
, ide_state
);
2413 register_ioport_write(iobase
, 2, 2, ide_data_writew
, ide_state
);
2414 register_ioport_read(iobase
, 2, 2, ide_data_readw
, ide_state
);
2415 register_ioport_write(iobase
, 4, 4, ide_data_writel
, ide_state
);
2416 register_ioport_read(iobase
, 4, 4, ide_data_readl
, ide_state
);
2419 /***********************************************************/
2420 /* ISA IDE definitions */
2422 void isa_ide_init(int iobase
, int iobase2
, qemu_irq irq
,
2423 BlockDriverState
*hd0
, BlockDriverState
*hd1
)
2425 IDEState
*ide_state
;
2427 ide_state
= qemu_mallocz(sizeof(IDEState
) * 2);
2431 ide_init2(ide_state
, hd0
, hd1
, irq
);
2432 ide_init_ioport(ide_state
, iobase
, iobase2
);
2435 /***********************************************************/
2436 /* PCI IDE definitions */
2438 static void cmd646_update_irq(PCIIDEState
*d
);
2440 static void ide_map(PCIDevice
*pci_dev
, int region_num
,
2441 uint32_t addr
, uint32_t size
, int type
)
2443 PCIIDEState
*d
= (PCIIDEState
*)pci_dev
;
2444 IDEState
*ide_state
;
2446 if (region_num
<= 3) {
2447 ide_state
= &d
->ide_if
[(region_num
>> 1) * 2];
2448 if (region_num
& 1) {
2449 register_ioport_read(addr
+ 2, 1, 1, ide_status_read
, ide_state
);
2450 register_ioport_write(addr
+ 2, 1, 1, ide_cmd_write
, ide_state
);
2452 register_ioport_write(addr
, 8, 1, ide_ioport_write
, ide_state
);
2453 register_ioport_read(addr
, 8, 1, ide_ioport_read
, ide_state
);
2456 register_ioport_write(addr
, 2, 2, ide_data_writew
, ide_state
);
2457 register_ioport_read(addr
, 2, 2, ide_data_readw
, ide_state
);
2458 register_ioport_write(addr
, 4, 4, ide_data_writel
, ide_state
);
2459 register_ioport_read(addr
, 4, 4, ide_data_readl
, ide_state
);
2464 static void ide_dma_start(IDEState
*s
, BlockDriverCompletionFunc
*dma_cb
)
2466 BMDMAState
*bm
= s
->bmdma
;
2470 bm
->dma_cb
= dma_cb
;
2471 bm
->cur_prd_last
= 0;
2472 bm
->cur_prd_addr
= 0;
2473 bm
->cur_prd_len
= 0;
2474 if (bm
->status
& BM_STATUS_DMAING
) {
2479 static void bmdma_cmd_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
2481 BMDMAState
*bm
= opaque
;
2483 printf("%s: 0x%08x\n", __func__
, val
);
2485 if (!(val
& BM_CMD_START
)) {
2486 /* XXX: do it better */
2487 if (bm
->status
& BM_STATUS_DMAING
) {
2488 bm
->status
&= ~BM_STATUS_DMAING
;
2489 /* cancel DMA request */
2494 printf("aio_cancel\n");
2496 bdrv_aio_cancel(bm
->aiocb
);
2500 bm
->cmd
= val
& 0x09;
2502 if (!(bm
->status
& BM_STATUS_DMAING
)) {
2503 bm
->status
|= BM_STATUS_DMAING
;
2504 /* start dma transfer if possible */
2508 bm
->cmd
= val
& 0x09;
2512 static uint32_t bmdma_readb(void *opaque
, uint32_t addr
)
2514 BMDMAState
*bm
= opaque
;
2515 PCIIDEState
*pci_dev
;
2523 pci_dev
= bm
->pci_dev
;
2524 if (pci_dev
->type
== IDE_TYPE_CMD646
) {
2525 val
= pci_dev
->dev
.config
[MRDMODE
];
2534 pci_dev
= bm
->pci_dev
;
2535 if (pci_dev
->type
== IDE_TYPE_CMD646
) {
2536 if (bm
== &pci_dev
->bmdma
[0])
2537 val
= pci_dev
->dev
.config
[UDIDETCR0
];
2539 val
= pci_dev
->dev
.config
[UDIDETCR1
];
2549 printf("bmdma: readb 0x%02x : 0x%02x\n", addr
, val
);
2554 static void bmdma_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
2556 BMDMAState
*bm
= opaque
;
2557 PCIIDEState
*pci_dev
;
2559 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr
, val
);
2563 pci_dev
= bm
->pci_dev
;
2564 if (pci_dev
->type
== IDE_TYPE_CMD646
) {
2565 pci_dev
->dev
.config
[MRDMODE
] =
2566 (pci_dev
->dev
.config
[MRDMODE
] & ~0x30) | (val
& 0x30);
2567 cmd646_update_irq(pci_dev
);
2571 bm
->status
= (val
& 0x60) | (bm
->status
& 1) | (bm
->status
& ~val
& 0x06);
2574 pci_dev
= bm
->pci_dev
;
2575 if (pci_dev
->type
== IDE_TYPE_CMD646
) {
2576 if (bm
== &pci_dev
->bmdma
[0])
2577 pci_dev
->dev
.config
[UDIDETCR0
] = val
;
2579 pci_dev
->dev
.config
[UDIDETCR1
] = val
;
2585 static uint32_t bmdma_addr_readl(void *opaque
, uint32_t addr
)
2587 BMDMAState
*bm
= opaque
;
2591 printf("%s: 0x%08x\n", __func__
, val
);
2596 static void bmdma_addr_writel(void *opaque
, uint32_t addr
, uint32_t val
)
2598 BMDMAState
*bm
= opaque
;
2600 printf("%s: 0x%08x\n", __func__
, val
);
2602 bm
->addr
= val
& ~3;
2603 bm
->cur_addr
= bm
->addr
;
2606 static void bmdma_map(PCIDevice
*pci_dev
, int region_num
,
2607 uint32_t addr
, uint32_t size
, int type
)
2609 PCIIDEState
*d
= (PCIIDEState
*)pci_dev
;
2612 for(i
= 0;i
< 2; i
++) {
2613 BMDMAState
*bm
= &d
->bmdma
[i
];
2614 d
->ide_if
[2 * i
].bmdma
= bm
;
2615 d
->ide_if
[2 * i
+ 1].bmdma
= bm
;
2616 bm
->pci_dev
= (PCIIDEState
*)pci_dev
;
2618 register_ioport_write(addr
, 1, 1, bmdma_cmd_writeb
, bm
);
2620 register_ioport_write(addr
+ 1, 3, 1, bmdma_writeb
, bm
);
2621 register_ioport_read(addr
, 4, 1, bmdma_readb
, bm
);
2623 register_ioport_write(addr
+ 4, 4, 4, bmdma_addr_writel
, bm
);
2624 register_ioport_read(addr
+ 4, 4, 4, bmdma_addr_readl
, bm
);
2629 /* XXX: call it also when the MRDMODE is changed from the PCI config
2631 static void cmd646_update_irq(PCIIDEState
*d
)
2634 pci_level
= ((d
->dev
.config
[MRDMODE
] & MRDMODE_INTR_CH0
) &&
2635 !(d
->dev
.config
[MRDMODE
] & MRDMODE_BLK_CH0
)) ||
2636 ((d
->dev
.config
[MRDMODE
] & MRDMODE_INTR_CH1
) &&
2637 !(d
->dev
.config
[MRDMODE
] & MRDMODE_BLK_CH1
));
2638 qemu_set_irq(d
->dev
.irq
[0], pci_level
);
2641 /* the PCI irq level is the logical OR of the two channels */
2642 static void cmd646_set_irq(void *opaque
, int channel
, int level
)
2644 PCIIDEState
*d
= opaque
;
2647 irq_mask
= MRDMODE_INTR_CH0
<< channel
;
2649 d
->dev
.config
[MRDMODE
] |= irq_mask
;
2651 d
->dev
.config
[MRDMODE
] &= ~irq_mask
;
2652 cmd646_update_irq(d
);
2655 /* CMD646 PCI IDE controller */
2656 void pci_cmd646_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
,
2657 int secondary_ide_enabled
)
2664 d
= (PCIIDEState
*)pci_register_device(bus
, "CMD646 IDE",
2665 sizeof(PCIIDEState
),
2668 d
->type
= IDE_TYPE_CMD646
;
2669 pci_conf
= d
->dev
.config
;
2670 pci_conf
[0x00] = 0x95; // CMD646
2671 pci_conf
[0x01] = 0x10;
2672 pci_conf
[0x02] = 0x46;
2673 pci_conf
[0x03] = 0x06;
2675 pci_conf
[0x08] = 0x07; // IDE controller revision
2676 pci_conf
[0x09] = 0x8f;
2678 pci_conf
[0x0a] = 0x01; // class_sub = PCI_IDE
2679 pci_conf
[0x0b] = 0x01; // class_base = PCI_mass_storage
2680 pci_conf
[0x0e] = 0x00; // header_type
2682 if (secondary_ide_enabled
) {
2683 /* XXX: if not enabled, really disable the seconday IDE controller */
2684 pci_conf
[0x51] = 0x80; /* enable IDE1 */
2687 pci_register_io_region((PCIDevice
*)d
, 0, 0x8,
2688 PCI_ADDRESS_SPACE_IO
, ide_map
);
2689 pci_register_io_region((PCIDevice
*)d
, 1, 0x4,
2690 PCI_ADDRESS_SPACE_IO
, ide_map
);
2691 pci_register_io_region((PCIDevice
*)d
, 2, 0x8,
2692 PCI_ADDRESS_SPACE_IO
, ide_map
);
2693 pci_register_io_region((PCIDevice
*)d
, 3, 0x4,
2694 PCI_ADDRESS_SPACE_IO
, ide_map
);
2695 pci_register_io_region((PCIDevice
*)d
, 4, 0x10,
2696 PCI_ADDRESS_SPACE_IO
, bmdma_map
);
2698 pci_conf
[0x3d] = 0x01; // interrupt on pin 1
2700 for(i
= 0; i
< 4; i
++)
2701 d
->ide_if
[i
].pci_dev
= (PCIDevice
*)d
;
2703 irq
= qemu_allocate_irqs(cmd646_set_irq
, d
, 2);
2704 ide_init2(&d
->ide_if
[0], hd_table
[0], hd_table
[1], irq
[0]);
2705 ide_init2(&d
->ide_if
[2], hd_table
[2], hd_table
[3], irq
[1]);
2708 static void pci_ide_save(QEMUFile
* f
, void *opaque
)
2710 PCIIDEState
*d
= opaque
;
2713 pci_device_save(&d
->dev
, f
);
2715 for(i
= 0; i
< 2; i
++) {
2716 BMDMAState
*bm
= &d
->bmdma
[i
];
2717 qemu_put_8s(f
, &bm
->cmd
);
2718 qemu_put_8s(f
, &bm
->status
);
2719 qemu_put_be32s(f
, &bm
->addr
);
2720 /* XXX: if a transfer is pending, we do not save it yet */
2723 /* per IDE interface data */
2724 for(i
= 0; i
< 2; i
++) {
2725 IDEState
*s
= &d
->ide_if
[i
* 2];
2726 uint8_t drive1_selected
;
2727 qemu_put_8s(f
, &s
->cmd
);
2728 drive1_selected
= (s
->cur_drive
!= s
);
2729 qemu_put_8s(f
, &drive1_selected
);
2732 /* per IDE drive data */
2733 for(i
= 0; i
< 4; i
++) {
2734 IDEState
*s
= &d
->ide_if
[i
];
2735 qemu_put_be32s(f
, &s
->mult_sectors
);
2736 qemu_put_be32s(f
, &s
->identify_set
);
2737 if (s
->identify_set
) {
2738 qemu_put_buffer(f
, (const uint8_t *)s
->identify_data
, 512);
2740 qemu_put_8s(f
, &s
->feature
);
2741 qemu_put_8s(f
, &s
->error
);
2742 qemu_put_be32s(f
, &s
->nsector
);
2743 qemu_put_8s(f
, &s
->sector
);
2744 qemu_put_8s(f
, &s
->lcyl
);
2745 qemu_put_8s(f
, &s
->hcyl
);
2746 qemu_put_8s(f
, &s
->hob_feature
);
2747 qemu_put_8s(f
, &s
->hob_nsector
);
2748 qemu_put_8s(f
, &s
->hob_sector
);
2749 qemu_put_8s(f
, &s
->hob_lcyl
);
2750 qemu_put_8s(f
, &s
->hob_hcyl
);
2751 qemu_put_8s(f
, &s
->select
);
2752 qemu_put_8s(f
, &s
->status
);
2753 qemu_put_8s(f
, &s
->lba48
);
2755 qemu_put_8s(f
, &s
->sense_key
);
2756 qemu_put_8s(f
, &s
->asc
);
2757 /* XXX: if a transfer is pending, we do not save it yet */
2761 static int pci_ide_load(QEMUFile
* f
, void *opaque
, int version_id
)
2763 PCIIDEState
*d
= opaque
;
2766 if (version_id
!= 1)
2768 ret
= pci_device_load(&d
->dev
, f
);
2772 for(i
= 0; i
< 2; i
++) {
2773 BMDMAState
*bm
= &d
->bmdma
[i
];
2774 qemu_get_8s(f
, &bm
->cmd
);
2775 qemu_get_8s(f
, &bm
->status
);
2776 qemu_get_be32s(f
, &bm
->addr
);
2777 /* XXX: if a transfer is pending, we do not save it yet */
2780 /* per IDE interface data */
2781 for(i
= 0; i
< 2; i
++) {
2782 IDEState
*s
= &d
->ide_if
[i
* 2];
2783 uint8_t drive1_selected
;
2784 qemu_get_8s(f
, &s
->cmd
);
2785 qemu_get_8s(f
, &drive1_selected
);
2786 s
->cur_drive
= &d
->ide_if
[i
* 2 + (drive1_selected
!= 0)];
2789 /* per IDE drive data */
2790 for(i
= 0; i
< 4; i
++) {
2791 IDEState
*s
= &d
->ide_if
[i
];
2792 qemu_get_be32s(f
, &s
->mult_sectors
);
2793 qemu_get_be32s(f
, &s
->identify_set
);
2794 if (s
->identify_set
) {
2795 qemu_get_buffer(f
, (uint8_t *)s
->identify_data
, 512);
2797 qemu_get_8s(f
, &s
->feature
);
2798 qemu_get_8s(f
, &s
->error
);
2799 qemu_get_be32s(f
, &s
->nsector
);
2800 qemu_get_8s(f
, &s
->sector
);
2801 qemu_get_8s(f
, &s
->lcyl
);
2802 qemu_get_8s(f
, &s
->hcyl
);
2803 qemu_get_8s(f
, &s
->hob_feature
);
2804 qemu_get_8s(f
, &s
->hob_nsector
);
2805 qemu_get_8s(f
, &s
->hob_sector
);
2806 qemu_get_8s(f
, &s
->hob_lcyl
);
2807 qemu_get_8s(f
, &s
->hob_hcyl
);
2808 qemu_get_8s(f
, &s
->select
);
2809 qemu_get_8s(f
, &s
->status
);
2810 qemu_get_8s(f
, &s
->lba48
);
2812 qemu_get_8s(f
, &s
->sense_key
);
2813 qemu_get_8s(f
, &s
->asc
);
2814 /* XXX: if a transfer is pending, we do not save it yet */
2819 static void piix3_reset(PCIIDEState
*d
)
2821 uint8_t *pci_conf
= d
->dev
.config
;
2823 pci_conf
[0x04] = 0x00;
2824 pci_conf
[0x05] = 0x00;
2825 pci_conf
[0x06] = 0x80; /* FBC */
2826 pci_conf
[0x07] = 0x02; // PCI_status_devsel_medium
2827 pci_conf
[0x20] = 0x01; /* BMIBA: 20-23h */
2830 /* hd_table must contain 4 block drivers */
2831 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2832 void pci_piix3_ide_init(PCIBus
*bus
, BlockDriverState
**hd_table
, int devfn
,
2838 /* register a function 1 of PIIX3 */
2839 d
= (PCIIDEState
*)pci_register_device(bus
, "PIIX3 IDE",
2840 sizeof(PCIIDEState
),
2843 d
->type
= IDE_TYPE_PIIX3
;
2845 pci_conf
= d
->dev
.config
;
2846 pci_conf
[0x00] = 0x86; // Intel
2847 pci_conf
[0x01] = 0x80;
2848 pci_conf
[0x02] = 0x10;
2849 pci_conf
[0x03] = 0x70;
2850 pci_conf
[0x09] = 0x80; // legacy ATA mode
2851 pci_conf
[0x0a] = 0x01; // class_sub = PCI_IDE
2852 pci_conf
[0x0b] = 0x01; // class_base = PCI_mass_storage
2853 pci_conf
[0x0e] = 0x00; // header_type
2857 pci_register_io_region((PCIDevice
*)d
, 4, 0x10,
2858 PCI_ADDRESS_SPACE_IO
, bmdma_map
);
2860 ide_init2(&d
->ide_if
[0], hd_table
[0], hd_table
[1], pic
[14]);
2861 ide_init2(&d
->ide_if
[2], hd_table
[2], hd_table
[3], pic
[15]);
2862 ide_init_ioport(&d
->ide_if
[0], 0x1f0, 0x3f6);
2863 ide_init_ioport(&d
->ide_if
[2], 0x170, 0x376);
2865 register_savevm("ide", 0, 1, pci_ide_save
, pci_ide_load
, d
);
2868 /***********************************************************/
2869 /* MacIO based PowerPC IDE */
2871 /* PowerMac IDE memory IO */
2872 static void pmac_ide_writeb (void *opaque
,
2873 target_phys_addr_t addr
, uint32_t val
)
2875 addr
= (addr
& 0xFFF) >> 4;
2878 ide_ioport_write(opaque
, addr
, val
);
2882 ide_cmd_write(opaque
, 0, val
);
2889 static uint32_t pmac_ide_readb (void *opaque
,target_phys_addr_t addr
)
2893 addr
= (addr
& 0xFFF) >> 4;
2896 retval
= ide_ioport_read(opaque
, addr
);
2900 retval
= ide_status_read(opaque
, 0);
2909 static void pmac_ide_writew (void *opaque
,
2910 target_phys_addr_t addr
, uint32_t val
)
2912 addr
= (addr
& 0xFFF) >> 4;
2913 #ifdef TARGET_WORDS_BIGENDIAN
2917 ide_data_writew(opaque
, 0, val
);
2921 static uint32_t pmac_ide_readw (void *opaque
,target_phys_addr_t addr
)
2925 addr
= (addr
& 0xFFF) >> 4;
2927 retval
= ide_data_readw(opaque
, 0);
2931 #ifdef TARGET_WORDS_BIGENDIAN
2932 retval
= bswap16(retval
);
2937 static void pmac_ide_writel (void *opaque
,
2938 target_phys_addr_t addr
, uint32_t val
)
2940 addr
= (addr
& 0xFFF) >> 4;
2941 #ifdef TARGET_WORDS_BIGENDIAN
2945 ide_data_writel(opaque
, 0, val
);
2949 static uint32_t pmac_ide_readl (void *opaque
,target_phys_addr_t addr
)
2953 addr
= (addr
& 0xFFF) >> 4;
2955 retval
= ide_data_readl(opaque
, 0);
2957 retval
= 0xFFFFFFFF;
2959 #ifdef TARGET_WORDS_BIGENDIAN
2960 retval
= bswap32(retval
);
2965 static CPUWriteMemoryFunc
*pmac_ide_write
[] = {
2971 static CPUReadMemoryFunc
*pmac_ide_read
[] = {
2977 /* hd_table must contain 4 block drivers */
2978 /* PowerMac uses memory mapped registers, not I/O. Return the memory
2979 I/O index to access the ide. */
2980 int pmac_ide_init (BlockDriverState
**hd_table
, qemu_irq irq
)
2983 int pmac_ide_memory
;
2985 ide_if
= qemu_mallocz(sizeof(IDEState
) * 2);
2986 ide_init2(&ide_if
[0], hd_table
[0], hd_table
[1], irq
);
2988 pmac_ide_memory
= cpu_register_io_memory(0, pmac_ide_read
,
2989 pmac_ide_write
, &ide_if
[0]);
2990 return pmac_ide_memory
;
2993 /***********************************************************/
2994 /* CF-ATA Microdrive */
2996 #define METADATA_SIZE 0x20
2998 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
3001 struct pcmcia_card_s card
;
3015 /* Register bitfields */
3018 OPT_MODE_IOMAP16
= 1,
3019 OPT_MODE_IOMAP1
= 2,
3020 OPT_MODE_IOMAP2
= 3,
3031 STAT_CHANGED
= 0x80,
3042 static inline void md_interrupt_update(struct md_s
*s
)
3047 qemu_set_irq(s
->card
.slot
->irq
,
3048 !(s
->stat
& STAT_INT
) && /* Inverted */
3049 !(s
->ctrl
& (CTRL_IEN
| CTRL_SRST
)) &&
3050 !(s
->opt
& OPT_SRESET
));
3053 static void md_set_irq(void *opaque
, int irq
, int level
)
3055 struct md_s
*s
= (struct md_s
*) opaque
;
3057 s
->stat
|= STAT_INT
;
3059 s
->stat
&= ~STAT_INT
;
3061 md_interrupt_update(s
);
3064 static void md_reset(struct md_s
*s
)
3066 s
->opt
= OPT_MODE_MMAP
;
3074 static uint8_t md_attr_read(void *opaque
, uint16_t at
)
3076 struct md_s
*s
= (struct md_s
*) opaque
;
3077 if (at
< s
->attr_base
) {
3078 if (at
< s
->card
.cis_len
)
3079 return s
->card
.cis
[at
];
3087 case 0x00: /* Configuration Option Register */
3089 case 0x02: /* Card Configuration Status Register */
3090 if (s
->ctrl
& CTRL_IEN
)
3091 return s
->stat
& ~STAT_INT
;
3094 case 0x04: /* Pin Replacement Register */
3095 return (s
->pins
& PINS_CRDY
) | 0x0c;
3096 case 0x06: /* Socket and Copy Register */
3100 printf("%s: Bad attribute space register %02x\n", __FUNCTION__
, at
);
3107 static void md_attr_write(void *opaque
, uint16_t at
, uint8_t value
)
3109 struct md_s
*s
= (struct md_s
*) opaque
;
3113 case 0x00: /* Configuration Option Register */
3114 s
->opt
= value
& 0xcf;
3115 if (value
& OPT_SRESET
)
3117 md_interrupt_update(s
);
3119 case 0x02: /* Card Configuration Status Register */
3120 if ((s
->stat
^ value
) & STAT_PWRDWN
)
3121 s
->pins
|= PINS_CRDY
;
3123 s
->stat
|= value
& 0x74;
3124 md_interrupt_update(s
);
3125 /* Word 170 in Identify Device must be equal to STAT_XE */
3127 case 0x04: /* Pin Replacement Register */
3128 s
->pins
&= PINS_CRDY
;
3129 s
->pins
|= value
& PINS_MRDY
;
3131 case 0x06: /* Socket and Copy Register */
3134 printf("%s: Bad attribute space register %02x\n", __FUNCTION__
, at
);
3138 static uint16_t md_common_read(void *opaque
, uint16_t at
)
3140 struct md_s
*s
= (struct md_s
*) opaque
;
3144 switch (s
->opt
& OPT_MODE
) {
3146 if ((at
& ~0x3ff) == 0x400)
3149 case OPT_MODE_IOMAP16
:
3152 case OPT_MODE_IOMAP1
:
3153 if ((at
& ~0xf) == 0x3f0)
3155 else if ((at
& ~0xf) == 0x1f0)
3158 case OPT_MODE_IOMAP2
:
3159 if ((at
& ~0xf) == 0x370)
3161 else if ((at
& ~0xf) == 0x170)
3166 case 0x0: /* Even RD Data */
3168 return ide_data_readw(s
->ide
, 0);
3170 /* TODO: 8-bit accesses */
3174 s
->io
= ide_data_readw(s
->ide
, 0);
3177 s
->cycle
= !s
->cycle
;
3179 case 0x9: /* Odd RD Data */
3181 case 0xd: /* Error */
3182 return ide_ioport_read(s
->ide
, 0x1);
3183 case 0xe: /* Alternate Status */
3184 if (s
->ide
->cur_drive
->bs
)
3185 return s
->ide
->cur_drive
->status
;
3188 case 0xf: /* Device Address */
3189 return 0xc2 | ((~s
->ide
->select
<< 2) & 0x3c);
3191 return ide_ioport_read(s
->ide
, at
);
3197 static void md_common_write(void *opaque
, uint16_t at
, uint16_t value
)
3199 struct md_s
*s
= (struct md_s
*) opaque
;
3202 switch (s
->opt
& OPT_MODE
) {
3204 if ((at
& ~0x3ff) == 0x400)
3207 case OPT_MODE_IOMAP16
:
3210 case OPT_MODE_IOMAP1
:
3211 if ((at
& ~0xf) == 0x3f0)
3213 else if ((at
& ~0xf) == 0x1f0)
3216 case OPT_MODE_IOMAP2
:
3217 if ((at
& ~0xf) == 0x370)
3219 else if ((at
& ~0xf) == 0x170)
3224 case 0x0: /* Even WR Data */
3226 ide_data_writew(s
->ide
, 0, value
);
3229 /* TODO: 8-bit accesses */
3231 ide_data_writew(s
->ide
, 0, s
->io
| (value
<< 8));
3233 s
->io
= value
& 0xff;
3234 s
->cycle
= !s
->cycle
;
3237 s
->io
= value
& 0xff;
3238 s
->cycle
= !s
->cycle
;
3240 case 0xd: /* Features */
3241 ide_ioport_write(s
->ide
, 0x1, value
);
3243 case 0xe: /* Device Control */
3245 if (value
& CTRL_SRST
)
3247 md_interrupt_update(s
);
3250 if (s
->stat
& STAT_PWRDWN
) {
3251 s
->pins
|= PINS_CRDY
;
3252 s
->stat
&= ~STAT_PWRDWN
;
3254 ide_ioport_write(s
->ide
, at
, value
);
3258 static const uint8_t dscm1xxxx_cis
[0x14a] = {
3259 [0x000] = CISTPL_DEVICE
, /* 5V Device Information */
3260 [0x002] = 0x03, /* Tuple length = 4 bytes */
3261 [0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3262 [0x006] = 0x01, /* Size = 2K bytes */
3263 [0x008] = CISTPL_ENDMARK
,
3265 [0x00a] = CISTPL_DEVICE_OC
, /* Additional Device Information */
3266 [0x00c] = 0x04, /* Tuple length = 4 byest */
3267 [0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
3268 [0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3269 [0x012] = 0x01, /* Size = 2K bytes */
3270 [0x014] = CISTPL_ENDMARK
,
3272 [0x016] = CISTPL_JEDEC_C
, /* JEDEC ID */
3273 [0x018] = 0x02, /* Tuple length = 2 bytes */
3274 [0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
3277 [0x01e] = CISTPL_MANFID
, /* Manufacture ID */
3278 [0x020] = 0x04, /* Tuple length = 4 bytes */
3279 [0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
3281 [0x026] = 0x00, /* PLMID_CARD = 0000 */
3284 [0x02a] = CISTPL_VERS_1
, /* Level 1 Version */
3285 [0x02c] = 0x12, /* Tuple length = 23 bytes */
3286 [0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
3287 [0x030] = 0x01, /* Minor Version = 1 */
3303 [0x050] = CISTPL_ENDMARK
,
3305 [0x052] = CISTPL_FUNCID
, /* Function ID */
3306 [0x054] = 0x02, /* Tuple length = 2 bytes */
3307 [0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
3308 [0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
3310 [0x05a] = CISTPL_FUNCE
, /* Function Extension */
3311 [0x05c] = 0x02, /* Tuple length = 2 bytes */
3312 [0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
3313 [0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
3315 [0x062] = CISTPL_FUNCE
, /* Function Extension */
3316 [0x064] = 0x03, /* Tuple length = 3 bytes */
3317 [0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
3318 [0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
3319 [0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
3321 [0x06c] = CISTPL_CONFIG
, /* Configuration */
3322 [0x06e] = 0x05, /* Tuple length = 5 bytes */
3323 [0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
3324 [0x072] = 0x07, /* TPCC_LAST = 7 */
3325 [0x074] = 0x00, /* TPCC_RADR = 0200 */
3327 [0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
3329 [0x07a] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3330 [0x07c] = 0x0b, /* Tuple length = 11 bytes */
3331 [0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
3332 [0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
3333 [0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
3334 [0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3335 [0x086] = 0x55, /* NomV: 5.0 V */
3336 [0x088] = 0x4d, /* MinV: 4.5 V */
3337 [0x08a] = 0x5d, /* MaxV: 5.5 V */
3338 [0x08c] = 0x4e, /* Peakl: 450 mA */
3339 [0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
3340 [0x090] = 0x00, /* Window descriptor: Window length = 0 */
3341 [0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
3343 [0x094] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3344 [0x096] = 0x06, /* Tuple length = 6 bytes */
3345 [0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
3346 [0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3347 [0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3348 [0x09e] = 0xb5, /* NomV: 3.3 V */
3350 [0x0a2] = 0x3e, /* Peakl: 350 mA */
3352 [0x0a4] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3353 [0x0a6] = 0x0d, /* Tuple length = 13 bytes */
3354 [0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
3355 [0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3356 [0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3357 [0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3358 [0x0b0] = 0x55, /* NomV: 5.0 V */
3359 [0x0b2] = 0x4d, /* MinV: 4.5 V */
3360 [0x0b4] = 0x5d, /* MaxV: 5.5 V */
3361 [0x0b6] = 0x4e, /* Peakl: 450 mA */
3362 [0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
3363 [0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
3364 [0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
3365 [0x0be] = 0xff, /* IRQ8..IRQ15 supported */
3366 [0x0c0] = 0x20, /* TPCE_MI = support power down mode */
3368 [0x0c2] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3369 [0x0c4] = 0x06, /* Tuple length = 6 bytes */
3370 [0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
3371 [0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3372 [0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3373 [0x0cc] = 0xb5, /* NomV: 3.3 V */
3375 [0x0d0] = 0x3e, /* Peakl: 350 mA */
3377 [0x0d2] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3378 [0x0d4] = 0x12, /* Tuple length = 18 bytes */
3379 [0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
3380 [0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3381 [0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3382 [0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3383 [0x0de] = 0x55, /* NomV: 5.0 V */
3384 [0x0e0] = 0x4d, /* MinV: 4.5 V */
3385 [0x0e2] = 0x5d, /* MaxV: 5.5 V */
3386 [0x0e4] = 0x4e, /* Peakl: 450 mA */
3387 [0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3388 [0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
3389 [0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
3391 [0x0ee] = 0x07, /* Address block length = 8 */
3392 [0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
3394 [0x0f4] = 0x01, /* Address block length = 2 */
3395 [0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3396 [0x0f8] = 0x20, /* TPCE_MI = support power down mode */
3398 [0x0fa] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3399 [0x0fc] = 0x06, /* Tuple length = 6 bytes */
3400 [0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
3401 [0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3402 [0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3403 [0x104] = 0xb5, /* NomV: 3.3 V */
3405 [0x108] = 0x3e, /* Peakl: 350 mA */
3407 [0x10a] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3408 [0x10c] = 0x12, /* Tuple length = 18 bytes */
3409 [0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
3410 [0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
3411 [0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3412 [0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3413 [0x116] = 0x55, /* NomV: 5.0 V */
3414 [0x118] = 0x4d, /* MinV: 4.5 V */
3415 [0x11a] = 0x5d, /* MaxV: 5.5 V */
3416 [0x11c] = 0x4e, /* Peakl: 450 mA */
3417 [0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
3418 [0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
3419 [0x122] = 0x70, /* Field 1 address = 0x0170 */
3421 [0x126] = 0x07, /* Address block length = 8 */
3422 [0x128] = 0x76, /* Field 2 address = 0x0376 */
3424 [0x12c] = 0x01, /* Address block length = 2 */
3425 [0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
3426 [0x130] = 0x20, /* TPCE_MI = support power down mode */
3428 [0x132] = CISTPL_CFTABLE_ENTRY
, /* 16-bit PC Card Configuration */
3429 [0x134] = 0x06, /* Tuple length = 6 bytes */
3430 [0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
3431 [0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
3432 [0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3433 [0x13c] = 0xb5, /* NomV: 3.3 V */
3435 [0x140] = 0x3e, /* Peakl: 350 mA */
3437 [0x142] = CISTPL_NO_LINK
, /* No Link */
3438 [0x144] = 0x00, /* Tuple length = 0 bytes */
3440 [0x146] = CISTPL_END
, /* Tuple End */
3443 static int dscm1xxxx_attach(void *opaque
)
3445 struct md_s
*md
= (struct md_s
*) opaque
;
3446 md
->card
.attr_read
= md_attr_read
;
3447 md
->card
.attr_write
= md_attr_write
;
3448 md
->card
.common_read
= md_common_read
;
3449 md
->card
.common_write
= md_common_write
;
3450 md
->card
.io_read
= md_common_read
;
3451 md
->card
.io_write
= md_common_write
;
3453 md
->attr_base
= md
->card
.cis
[0x74] | (md
->card
.cis
[0x76] << 8);
3457 md_interrupt_update(md
);
3459 md
->card
.slot
->card_string
= "DSCM-1xxxx Hitachi Microdrive";
3463 static int dscm1xxxx_detach(void *opaque
)
3465 struct md_s
*md
= (struct md_s
*) opaque
;
3470 struct pcmcia_card_s
*dscm1xxxx_init(BlockDriverState
*bdrv
)
3472 struct md_s
*md
= (struct md_s
*) qemu_mallocz(sizeof(struct md_s
));
3473 md
->card
.state
= md
;
3474 md
->card
.attach
= dscm1xxxx_attach
;
3475 md
->card
.detach
= dscm1xxxx_detach
;
3476 md
->card
.cis
= dscm1xxxx_cis
;
3477 md
->card
.cis_len
= sizeof(dscm1xxxx_cis
);
3479 ide_init2(md
->ide
, bdrv
, 0, qemu_allocate_irqs(md_set_irq
, md
, 1)[0]);
3481 md
->ide
->mdata_size
= METADATA_SIZE
;
3482 md
->ide
->mdata_storage
= (uint8_t *) qemu_mallocz(METADATA_SIZE
);