target-sh4/cpu.h

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef _CPU_SH4_H
  21 #define _CPU_SH4_H
  22
  23 #include "config.h"
  24
  25 #define TARGET_LONG_BITS 32
  26 #define TARGET_HAS_ICE 1
  27
  28 #define ELF_MACHINE     EM_SH
  29
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_PAGE_BITS 12     /* 4k XXXXX */
  35
  36 #define SR_MD (1 << 30)
  37 #define SR_RB (1 << 29)
  38 #define SR_BL (1 << 28)
  39 #define SR_FD (1 << 15)
  40 #define SR_M  (1 << 9)
  41 #define SR_Q  (1 << 8)
  42 #define SR_S  (1 << 1)
  43 #define SR_T  (1 << 0)
  44
  45 #define FPSCR_FR (1 << 21)
  46 #define FPSCR_SZ (1 << 20)
  47 #define FPSCR_PR (1 << 19)
  48 #define FPSCR_DN (1 << 18)
  49
  50 #define DELAY_SLOT             (1 << 0) /* Must be the same as SR_T.  */
  51 /* This flag is set if the next insn is a delay slot for a conditional jump.
  52    The dynamic value of the DELAY_SLOT determines whether the jup is taken. */
  53 #define DELAY_SLOT_CONDITIONAL (1 << 1)
  54 /* Those are used in contexts only */
  55 #define BRANCH                 (1 << 2)
  56 #define BRANCH_CONDITIONAL     (1 << 3)
  57 #define MODE_CHANGE            (1 << 4) /* Potential MD|RB change */
  58 #define BRANCH_EXCEPTION       (1 << 5) /* Branch after exception */
  59
  60 /* XXXXX The structure could be made more compact */
  61 typedef struct tlb_t {
  62     uint8_t asid;               /* address space identifier */
  63     uint32_t vpn;               /* virtual page number */
  64     uint8_t v;                  /* validity */
  65     uint32_t ppn;               /* physical page number */
  66     uint8_t sz;                 /* page size */
  67     uint32_t size;              /* cached page size in bytes */
  68     uint8_t sh;                 /* share status */
  69     uint8_t c;                  /* cacheability */
  70     uint8_t pr;                 /* protection key */
  71     uint8_t d;                  /* dirty */
  72     uint8_t wt;                 /* write through */
  73     uint8_t sa;                 /* space attribute (PCMCIA) */
  74     uint8_t tc;                 /* timing control */
  75 } tlb_t;
  76
  77 #define UTLB_SIZE 64
  78 #define ITLB_SIZE 4
  79
  80 typedef struct CPUSH4State {
  81     uint32_t flags;             /* general execution flags */
  82     uint32_t gregs[24];         /* general registers */
  83     float32 fregs[32];          /* floating point registers */
  84     uint32_t sr;                /* status register */
  85     uint32_t ssr;               /* saved status register */
  86     uint32_t spc;               /* saved program counter */
  87     uint32_t gbr;               /* global base register */
  88     uint32_t vbr;               /* vector base register */
  89     uint32_t sgr;               /* saved global register 15 */
  90     uint32_t dbr;               /* debug base register */
  91     uint32_t pc;                /* program counter */
  92     uint32_t delayed_pc;        /* target of delayed jump */
  93     uint32_t mach;              /* multiply and accumulate high */
  94     uint32_t macl;              /* multiply and accumulate low */
  95     uint32_t pr;                /* procedure register */
  96     uint32_t fpscr;             /* floating point status/control register */
  97     uint32_t fpul;              /* floating point communication register */
  98
  99     /* temporary float registers */
 100     float32 ft0, ft1;
 101     float64 dt0, dt1;
 102     float_status fp_status;
 103
 104     /* Those belong to the specific unit (SH7750) but are handled here */
 105     uint32_t mmucr;             /* MMU control register */
 106     uint32_t pteh;              /* page table entry high register */
 107     uint32_t ptel;              /* page table entry low register */
 108     uint32_t ptea;              /* page table entry assistance register */
 109     uint32_t ttb;               /* tranlation table base register */
 110     uint32_t tea;               /* TLB exception address register */
 111     uint32_t tra;               /* TRAPA exception register */
 112     uint32_t expevt;            /* exception event register */
 113     uint32_t intevt;            /* interrupt event register */
 114
 115     jmp_buf jmp_env;
 116     int user_mode_only;
 117     int interrupt_request;
 118     int halted;
 119     int exception_index;
 120      CPU_COMMON tlb_t utlb[UTLB_SIZE];  /* unified translation table */
 121     tlb_t itlb[ITLB_SIZE];      /* instruction translation table */
 122 } CPUSH4State;
 123
 124 CPUSH4State *cpu_sh4_init(void);
 125 int cpu_sh4_exec(CPUSH4State * s);
 126 int cpu_sh4_signal_handler(int host_signum, void *pinfo,
 127                            void *puc);
 128
 129 #include "softfloat.h"
 130
 131 #define CPUState CPUSH4State
 132 #define cpu_init cpu_sh4_init
 133 #define cpu_exec cpu_sh4_exec
 134 #define cpu_gen_code cpu_sh4_gen_code
 135 #define cpu_signal_handler cpu_sh4_signal_handler
 136
 137 #include "cpu-all.h"
 138
 139 /* Memory access type */
 140 enum {
 141     /* Privilege */
 142     ACCESS_PRIV = 0x01,
 143     /* Direction */
 144     ACCESS_WRITE = 0x02,
 145     /* Type of instruction */
 146     ACCESS_CODE = 0x10,
 147     ACCESS_INT = 0x20
 148 };
 149
 150 /* MMU control register */
 151 #define MMUCR    0x1F000010
 152 #define MMUCR_AT (1<<0)
 153 #define MMUCR_SV (1<<8)
 154
 155 #endif                          /* _CPU_SH4_H */