2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define MIPS_DEBUG_DISAS
34 //#define MIPS_DEBUG_SIGN_EXTENSIONS
35 //#define MIPS_SINGLE_STEP
37 #ifdef USE_DIRECT_JUMP
40 #define TBPARAM(x) (long)(x)
44 #define DEF(s, n, copy_size) INDEX_op_ ## s,
50 static uint16_t *gen_opc_ptr
;
51 static uint32_t *gen_opparam_ptr
;
55 /* MIPS major opcodes */
56 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
59 /* indirect opcode tables */
60 OPC_SPECIAL
= (0x00 << 26),
61 OPC_REGIMM
= (0x01 << 26),
62 OPC_CP0
= (0x10 << 26),
63 OPC_CP1
= (0x11 << 26),
64 OPC_CP2
= (0x12 << 26),
65 OPC_CP3
= (0x13 << 26),
66 OPC_SPECIAL2
= (0x1C << 26),
67 OPC_SPECIAL3
= (0x1F << 26),
68 /* arithmetic with immediate */
69 OPC_ADDI
= (0x08 << 26),
70 OPC_ADDIU
= (0x09 << 26),
71 OPC_SLTI
= (0x0A << 26),
72 OPC_SLTIU
= (0x0B << 26),
73 OPC_ANDI
= (0x0C << 26),
74 OPC_ORI
= (0x0D << 26),
75 OPC_XORI
= (0x0E << 26),
76 OPC_LUI
= (0x0F << 26),
77 OPC_DADDI
= (0x18 << 26),
78 OPC_DADDIU
= (0x19 << 26),
79 /* Jump and branches */
81 OPC_JAL
= (0x03 << 26),
82 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
83 OPC_BEQL
= (0x14 << 26),
84 OPC_BNE
= (0x05 << 26),
85 OPC_BNEL
= (0x15 << 26),
86 OPC_BLEZ
= (0x06 << 26),
87 OPC_BLEZL
= (0x16 << 26),
88 OPC_BGTZ
= (0x07 << 26),
89 OPC_BGTZL
= (0x17 << 26),
90 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
92 OPC_LDL
= (0x1A << 26),
93 OPC_LDR
= (0x1B << 26),
94 OPC_LB
= (0x20 << 26),
95 OPC_LH
= (0x21 << 26),
96 OPC_LWL
= (0x22 << 26),
97 OPC_LW
= (0x23 << 26),
98 OPC_LBU
= (0x24 << 26),
99 OPC_LHU
= (0x25 << 26),
100 OPC_LWR
= (0x26 << 26),
101 OPC_LWU
= (0x27 << 26),
102 OPC_SB
= (0x28 << 26),
103 OPC_SH
= (0x29 << 26),
104 OPC_SWL
= (0x2A << 26),
105 OPC_SW
= (0x2B << 26),
106 OPC_SDL
= (0x2C << 26),
107 OPC_SDR
= (0x2D << 26),
108 OPC_SWR
= (0x2E << 26),
109 OPC_LL
= (0x30 << 26),
110 OPC_LLD
= (0x34 << 26),
111 OPC_LD
= (0x37 << 26),
112 OPC_SC
= (0x38 << 26),
113 OPC_SCD
= (0x3C << 26),
114 OPC_SD
= (0x3F << 26),
115 /* Floating point load/store */
116 OPC_LWC1
= (0x31 << 26),
117 OPC_LWC2
= (0x32 << 26),
118 OPC_LDC1
= (0x35 << 26),
119 OPC_LDC2
= (0x36 << 26),
120 OPC_SWC1
= (0x39 << 26),
121 OPC_SWC2
= (0x3A << 26),
122 OPC_SDC1
= (0x3D << 26),
123 OPC_SDC2
= (0x3E << 26),
124 /* MDMX ASE specific */
125 OPC_MDMX
= (0x1E << 26),
126 /* Cache and prefetch */
127 OPC_CACHE
= (0x2F << 26),
128 OPC_PREF
= (0x33 << 26),
129 /* Reserved major opcode */
130 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
133 /* MIPS special opcodes */
134 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
138 OPC_SLL
= 0x00 | OPC_SPECIAL
,
139 /* NOP is SLL r0, r0, 0 */
140 /* SSNOP is SLL r0, r0, 1 */
141 /* EHB is SLL r0, r0, 3 */
142 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
143 OPC_SRA
= 0x03 | OPC_SPECIAL
,
144 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
145 OPC_SRLV
= 0x06 | OPC_SPECIAL
,
146 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
147 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
148 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
149 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
150 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
151 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
152 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
153 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
154 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
155 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
156 /* Multiplication / division */
157 OPC_MULT
= 0x18 | OPC_SPECIAL
,
158 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
159 OPC_DIV
= 0x1A | OPC_SPECIAL
,
160 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
161 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
162 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
163 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
164 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
165 /* 2 registers arithmetic / logic */
166 OPC_ADD
= 0x20 | OPC_SPECIAL
,
167 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
168 OPC_SUB
= 0x22 | OPC_SPECIAL
,
169 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
170 OPC_AND
= 0x24 | OPC_SPECIAL
,
171 OPC_OR
= 0x25 | OPC_SPECIAL
,
172 OPC_XOR
= 0x26 | OPC_SPECIAL
,
173 OPC_NOR
= 0x27 | OPC_SPECIAL
,
174 OPC_SLT
= 0x2A | OPC_SPECIAL
,
175 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
176 OPC_DADD
= 0x2C | OPC_SPECIAL
,
177 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
178 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
179 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
181 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
182 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* inofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* inofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* REGIMM (rt field) opcodes */
218 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
221 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
222 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
223 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
224 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
225 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
226 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
227 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
228 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
229 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
230 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
231 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
232 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
233 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
234 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
235 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
238 /* Special2 opcodes */
239 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
242 /* Multiply & xxx operations */
243 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
244 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
245 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
246 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
247 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
249 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
250 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
251 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
252 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
254 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
257 /* Special3 opcodes */
258 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
261 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
262 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
263 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
264 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
265 OPC_INS
= 0x04 | OPC_SPECIAL3
,
266 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
267 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
268 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
269 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
270 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
271 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
275 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
278 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
279 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
280 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
284 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
287 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
288 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
291 /* Coprocessor 0 (rs field) */
292 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
295 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
296 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
297 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
298 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
299 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
300 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
301 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
302 OPC_C0
= (0x10 << 21) | OPC_CP0
,
303 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
304 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
308 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
311 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
312 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
315 /* Coprocessor 0 (with rs == C0) */
316 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
319 OPC_TLBR
= 0x01 | OPC_C0
,
320 OPC_TLBWI
= 0x02 | OPC_C0
,
321 OPC_TLBWR
= 0x06 | OPC_C0
,
322 OPC_TLBP
= 0x08 | OPC_C0
,
323 OPC_RFE
= 0x10 | OPC_C0
,
324 OPC_ERET
= 0x18 | OPC_C0
,
325 OPC_DERET
= 0x1F | OPC_C0
,
326 OPC_WAIT
= 0x20 | OPC_C0
,
329 /* Coprocessor 1 (rs field) */
330 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
333 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
334 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
335 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
336 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
337 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
338 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
339 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
340 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
341 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
342 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
343 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
344 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
345 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
346 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
347 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
348 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
349 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
350 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
353 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
354 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
357 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
358 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
359 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
360 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
364 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
365 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
369 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
370 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
373 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
376 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
377 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
378 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
379 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
380 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
381 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
382 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
383 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
384 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
387 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
390 OPC_LWXC1
= 0x00 | OPC_CP3
,
391 OPC_LDXC1
= 0x01 | OPC_CP3
,
392 OPC_LUXC1
= 0x05 | OPC_CP3
,
393 OPC_SWXC1
= 0x08 | OPC_CP3
,
394 OPC_SDXC1
= 0x09 | OPC_CP3
,
395 OPC_SUXC1
= 0x0D | OPC_CP3
,
396 OPC_PREFX
= 0x0F | OPC_CP3
,
397 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
398 OPC_MADD_S
= 0x20 | OPC_CP3
,
399 OPC_MADD_D
= 0x21 | OPC_CP3
,
400 OPC_MADD_PS
= 0x26 | OPC_CP3
,
401 OPC_MSUB_S
= 0x28 | OPC_CP3
,
402 OPC_MSUB_D
= 0x29 | OPC_CP3
,
403 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
404 OPC_NMADD_S
= 0x30 | OPC_CP3
,
405 OPC_NMADD_D
= 0x31 | OPC_CP3
,
406 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
407 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
408 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
409 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
413 const unsigned char *regnames
[] =
414 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
415 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
416 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
417 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
419 /* Warning: no function for r0 register (hard wired to zero) */
420 #define GEN32(func, NAME) \
421 static GenOpFunc *NAME ## _table [32] = { \
422 NULL, NAME ## 1, NAME ## 2, NAME ## 3, \
423 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
424 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
425 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
426 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
427 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
428 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
429 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
431 static inline void func(int n) \
433 NAME ## _table[n](); \
436 /* General purpose registers moves */
437 GEN32(gen_op_load_gpr_T0
, gen_op_load_gpr_T0_gpr
);
438 GEN32(gen_op_load_gpr_T1
, gen_op_load_gpr_T1_gpr
);
439 GEN32(gen_op_load_gpr_T2
, gen_op_load_gpr_T2_gpr
);
441 GEN32(gen_op_store_T0_gpr
, gen_op_store_T0_gpr_gpr
);
442 GEN32(gen_op_store_T1_gpr
, gen_op_store_T1_gpr_gpr
);
444 static const char *fregnames
[] =
445 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
446 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
447 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
448 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
450 #define FGEN32(func, NAME) \
451 static GenOpFunc *NAME ## _table [32] = { \
452 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
453 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
454 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
455 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
456 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
457 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
458 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
459 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
461 static inline void func(int n) \
463 NAME ## _table[n](); \
466 FGEN32(gen_op_load_fpr_WT0
, gen_op_load_fpr_WT0_fpr
);
467 FGEN32(gen_op_store_fpr_WT0
, gen_op_store_fpr_WT0_fpr
);
469 FGEN32(gen_op_load_fpr_WT1
, gen_op_load_fpr_WT1_fpr
);
470 FGEN32(gen_op_store_fpr_WT1
, gen_op_store_fpr_WT1_fpr
);
472 FGEN32(gen_op_load_fpr_WT2
, gen_op_load_fpr_WT2_fpr
);
473 FGEN32(gen_op_store_fpr_WT2
, gen_op_store_fpr_WT2_fpr
);
475 FGEN32(gen_op_load_fpr_DT0
, gen_op_load_fpr_DT0_fpr
);
476 FGEN32(gen_op_store_fpr_DT0
, gen_op_store_fpr_DT0_fpr
);
478 FGEN32(gen_op_load_fpr_DT1
, gen_op_load_fpr_DT1_fpr
);
479 FGEN32(gen_op_store_fpr_DT1
, gen_op_store_fpr_DT1_fpr
);
481 FGEN32(gen_op_load_fpr_DT2
, gen_op_load_fpr_DT2_fpr
);
482 FGEN32(gen_op_store_fpr_DT2
, gen_op_store_fpr_DT2_fpr
);
484 FGEN32(gen_op_load_fpr_WTH0
, gen_op_load_fpr_WTH0_fpr
);
485 FGEN32(gen_op_store_fpr_WTH0
, gen_op_store_fpr_WTH0_fpr
);
487 FGEN32(gen_op_load_fpr_WTH1
, gen_op_load_fpr_WTH1_fpr
);
488 FGEN32(gen_op_store_fpr_WTH1
, gen_op_store_fpr_WTH1_fpr
);
490 FGEN32(gen_op_load_fpr_WTH2
, gen_op_load_fpr_WTH2_fpr
);
491 FGEN32(gen_op_store_fpr_WTH2
, gen_op_store_fpr_WTH2_fpr
);
493 #define FOP_CONDS(type, fmt) \
494 static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \
495 gen_op_cmp ## type ## _ ## fmt ## _f, \
496 gen_op_cmp ## type ## _ ## fmt ## _un, \
497 gen_op_cmp ## type ## _ ## fmt ## _eq, \
498 gen_op_cmp ## type ## _ ## fmt ## _ueq, \
499 gen_op_cmp ## type ## _ ## fmt ## _olt, \
500 gen_op_cmp ## type ## _ ## fmt ## _ult, \
501 gen_op_cmp ## type ## _ ## fmt ## _ole, \
502 gen_op_cmp ## type ## _ ## fmt ## _ule, \
503 gen_op_cmp ## type ## _ ## fmt ## _sf, \
504 gen_op_cmp ## type ## _ ## fmt ## _ngle, \
505 gen_op_cmp ## type ## _ ## fmt ## _seq, \
506 gen_op_cmp ## type ## _ ## fmt ## _ngl, \
507 gen_op_cmp ## type ## _ ## fmt ## _lt, \
508 gen_op_cmp ## type ## _ ## fmt ## _nge, \
509 gen_op_cmp ## type ## _ ## fmt ## _le, \
510 gen_op_cmp ## type ## _ ## fmt ## _ngt, \
512 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \
514 gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \
524 typedef struct DisasContext
{
525 struct TranslationBlock
*tb
;
526 target_ulong pc
, saved_pc
;
529 /* Routine used to access memory */
531 uint32_t hflags
, saved_hflags
;
533 target_ulong btarget
;
537 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
538 * exception condition
540 BS_STOP
= 1, /* We want to stop translation for any reason */
541 BS_BRANCH
= 2, /* We reached a branch condition */
542 BS_EXCP
= 3, /* We reached an exception condition */
545 #ifdef MIPS_DEBUG_DISAS
546 #define MIPS_DEBUG(fmt, args...) \
548 if (loglevel & CPU_LOG_TB_IN_ASM) { \
549 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
550 ctx->pc, ctx->opcode , ##args); \
554 #define MIPS_DEBUG(fmt, args...) do { } while(0)
557 #define MIPS_INVAL(op) \
559 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
560 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
563 #define GEN_LOAD_REG_TN(Tn, Rn) \
566 glue(gen_op_reset_, Tn)(); \
568 glue(gen_op_load_gpr_, Tn)(Rn); \
573 #define GEN_LOAD_IMM_TN(Tn, Imm) \
576 glue(gen_op_reset_, Tn)(); \
577 } else if ((int32_t)Imm == Imm) { \
578 glue(gen_op_set_, Tn)(Imm); \
580 glue(gen_op_set64_, Tn)(((uint64_t)Imm) >> 32, (uint32_t)Imm); \
584 #define GEN_LOAD_IMM_TN(Tn, Imm) \
587 glue(gen_op_reset_, Tn)(); \
589 glue(gen_op_set_, Tn)(Imm); \
594 #define GEN_STORE_TN_REG(Rn, Tn) \
597 glue(glue(gen_op_store_, Tn),_gpr)(Rn); \
601 #define GEN_LOAD_FREG_FTN(FTn, Fn) \
603 glue(gen_op_load_fpr_, FTn)(Fn); \
606 #define GEN_STORE_FTN_FREG(Fn, FTn) \
608 glue(gen_op_store_fpr_, FTn)(Fn); \
611 static inline void gen_save_pc(target_ulong pc
)
614 if (pc
== (int32_t)pc
) {
617 gen_op_save_pc64(pc
>> 32, (uint32_t)pc
);
624 static inline void gen_save_btarget(target_ulong btarget
)
627 if (btarget
== (int32_t)btarget
) {
628 gen_op_save_btarget(btarget
);
630 gen_op_save_btarget64(btarget
>> 32, (uint32_t)btarget
);
633 gen_op_save_btarget(btarget
);
637 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
639 #if defined MIPS_DEBUG_DISAS
640 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
641 fprintf(logfile
, "hflags %08x saved %08x\n",
642 ctx
->hflags
, ctx
->saved_hflags
);
645 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
646 gen_save_pc(ctx
->pc
);
647 ctx
->saved_pc
= ctx
->pc
;
649 if (ctx
->hflags
!= ctx
->saved_hflags
) {
650 gen_op_save_state(ctx
->hflags
);
651 ctx
->saved_hflags
= ctx
->hflags
;
652 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
654 gen_op_save_breg_target();
660 /* bcond was already saved by the BL insn */
663 gen_save_btarget(ctx
->btarget
);
669 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
671 ctx
->saved_hflags
= ctx
->hflags
;
672 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
674 gen_op_restore_breg_target();
677 ctx
->btarget
= env
->btarget
;
681 ctx
->btarget
= env
->btarget
;
682 gen_op_restore_bcond();
687 static inline void generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
689 #if defined MIPS_DEBUG_DISAS
690 if (loglevel
& CPU_LOG_TB_IN_ASM
)
691 fprintf(logfile
, "%s: raise exception %d\n", __func__
, excp
);
693 save_cpu_state(ctx
, 1);
695 gen_op_raise_exception(excp
);
697 gen_op_raise_exception_err(excp
, err
);
698 ctx
->bstate
= BS_EXCP
;
701 static inline void generate_exception (DisasContext
*ctx
, int excp
)
703 generate_exception_err (ctx
, excp
, 0);
706 static inline void check_cp1_enabled(DisasContext
*ctx
)
708 if (!(ctx
->hflags
& MIPS_HFLAG_FPU
))
709 generate_exception_err(ctx
, EXCP_CpU
, 1);
712 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
714 if (!(ctx
->hflags
& MIPS_HFLAG_F64
))
715 generate_exception(ctx
, EXCP_RI
);
719 * Verify if floating point register is valid; an operation is not defined
720 * if bit 0 of any register specification is set and the FR bit in the
721 * Status register equals zero, since the register numbers specify an
722 * even-odd pair of adjacent coprocessor general registers. When the FR bit
723 * in the Status register equals one, both even and odd register numbers
724 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
726 * Multiple 64 bit wide registers can be checked by calling
727 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
729 void check_cp1_registers(DisasContext
*ctx
, int regs
)
731 if (!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1))
732 generate_exception(ctx
, EXCP_RI
);
735 /* This code generates a "reserved instruction" exception if the
736 CPU is not a MIPS R2 (or higher) CPU. */
737 static inline void check_mips_r2(CPUState
*env
, DisasContext
*ctx
)
739 if ((env
->CP0_Config0
& (0x7 << CP0C0_AR
)) < (1 << CP0C0_AR
))
740 generate_exception(ctx
, EXCP_RI
);
743 #if defined(CONFIG_USER_ONLY)
744 #define op_ldst(name) gen_op_##name##_raw()
745 #define OP_LD_TABLE(width)
746 #define OP_ST_TABLE(width)
748 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
749 #define OP_LD_TABLE(width) \
750 static GenOpFunc *gen_op_l##width[] = { \
751 &gen_op_l##width##_user, \
752 &gen_op_l##width##_kernel, \
754 #define OP_ST_TABLE(width) \
755 static GenOpFunc *gen_op_s##width[] = { \
756 &gen_op_s##width##_user, \
757 &gen_op_s##width##_kernel, \
794 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
795 int base
, int16_t offset
)
797 const char *opn
= "ldst";
800 GEN_LOAD_IMM_TN(T0
, offset
);
801 } else if (offset
== 0) {
802 gen_op_load_gpr_T0(base
);
804 gen_op_load_gpr_T0(base
);
805 gen_op_set_T1(offset
);
808 /* Don't do NOP if destination is zero: we must perform the actual
815 GEN_STORE_TN_REG(rt
, T0
);
820 GEN_STORE_TN_REG(rt
, T0
);
825 GEN_STORE_TN_REG(rt
, T0
);
829 GEN_LOAD_REG_TN(T1
, rt
);
834 save_cpu_state(ctx
, 1);
835 GEN_LOAD_REG_TN(T1
, rt
);
837 GEN_STORE_TN_REG(rt
, T0
);
841 GEN_LOAD_REG_TN(T1
, rt
);
843 GEN_STORE_TN_REG(rt
, T0
);
847 GEN_LOAD_REG_TN(T1
, rt
);
852 GEN_LOAD_REG_TN(T1
, rt
);
854 GEN_STORE_TN_REG(rt
, T0
);
858 GEN_LOAD_REG_TN(T1
, rt
);
865 GEN_STORE_TN_REG(rt
, T0
);
869 GEN_LOAD_REG_TN(T1
, rt
);
875 GEN_STORE_TN_REG(rt
, T0
);
879 GEN_LOAD_REG_TN(T1
, rt
);
885 GEN_STORE_TN_REG(rt
, T0
);
890 GEN_STORE_TN_REG(rt
, T0
);
894 GEN_LOAD_REG_TN(T1
, rt
);
900 GEN_STORE_TN_REG(rt
, T0
);
904 GEN_LOAD_REG_TN(T1
, rt
);
906 GEN_STORE_TN_REG(rt
, T0
);
910 GEN_LOAD_REG_TN(T1
, rt
);
915 GEN_LOAD_REG_TN(T1
, rt
);
917 GEN_STORE_TN_REG(rt
, T0
);
921 GEN_LOAD_REG_TN(T1
, rt
);
927 GEN_STORE_TN_REG(rt
, T0
);
931 save_cpu_state(ctx
, 1);
932 GEN_LOAD_REG_TN(T1
, rt
);
934 GEN_STORE_TN_REG(rt
, T0
);
939 generate_exception(ctx
, EXCP_RI
);
942 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
946 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
947 int base
, int16_t offset
)
949 const char *opn
= "flt_ldst";
952 GEN_LOAD_IMM_TN(T0
, offset
);
953 } else if (offset
== 0) {
954 gen_op_load_gpr_T0(base
);
956 gen_op_load_gpr_T0(base
);
957 gen_op_set_T1(offset
);
960 /* Don't do NOP if destination is zero: we must perform the actual
966 GEN_STORE_FTN_FREG(ft
, WT0
);
970 GEN_LOAD_FREG_FTN(WT0
, ft
);
976 GEN_STORE_FTN_FREG(ft
, DT0
);
980 GEN_LOAD_FREG_FTN(DT0
, ft
);
986 generate_exception(ctx
, EXCP_RI
);
989 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
992 /* Arithmetic with immediate operand */
993 static void gen_arith_imm (DisasContext
*ctx
, uint32_t opc
, int rt
,
997 const char *opn
= "imm arith";
999 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1000 /* if no destination, treat it as a NOP
1001 * For addi, we must generate the overflow exception when needed.
1006 uimm
= (uint16_t)imm
;
1010 #ifdef TARGET_MIPS64
1016 uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1021 GEN_LOAD_REG_TN(T0
, rs
);
1022 GEN_LOAD_IMM_TN(T1
, uimm
);
1025 GEN_LOAD_IMM_TN(T0
, imm
<< 16);
1030 #ifdef TARGET_MIPS64
1039 GEN_LOAD_REG_TN(T0
, rs
);
1040 GEN_LOAD_IMM_TN(T1
, uimm
);
1045 save_cpu_state(ctx
, 1);
1053 #ifdef TARGET_MIPS64
1055 save_cpu_state(ctx
, 1);
1096 switch ((ctx
->opcode
>> 21) & 0x1f) {
1106 MIPS_INVAL("invalid srl flag");
1107 generate_exception(ctx
, EXCP_RI
);
1111 #ifdef TARGET_MIPS64
1121 switch ((ctx
->opcode
>> 21) & 0x1f) {
1131 MIPS_INVAL("invalid dsrl flag");
1132 generate_exception(ctx
, EXCP_RI
);
1145 switch ((ctx
->opcode
>> 21) & 0x1f) {
1155 MIPS_INVAL("invalid dsrl32 flag");
1156 generate_exception(ctx
, EXCP_RI
);
1163 generate_exception(ctx
, EXCP_RI
);
1166 GEN_STORE_TN_REG(rt
, T0
);
1167 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1171 static void gen_arith (DisasContext
*ctx
, uint32_t opc
,
1172 int rd
, int rs
, int rt
)
1174 const char *opn
= "arith";
1176 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1177 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1178 /* if no destination, treat it as a NOP
1179 * For add & sub, we must generate the overflow exception when needed.
1184 GEN_LOAD_REG_TN(T0
, rs
);
1185 GEN_LOAD_REG_TN(T1
, rt
);
1188 save_cpu_state(ctx
, 1);
1197 save_cpu_state(ctx
, 1);
1205 #ifdef TARGET_MIPS64
1207 save_cpu_state(ctx
, 1);
1216 save_cpu_state(ctx
, 1);
1270 switch ((ctx
->opcode
>> 6) & 0x1f) {
1280 MIPS_INVAL("invalid srlv flag");
1281 generate_exception(ctx
, EXCP_RI
);
1285 #ifdef TARGET_MIPS64
1295 switch ((ctx
->opcode
>> 6) & 0x1f) {
1305 MIPS_INVAL("invalid dsrlv flag");
1306 generate_exception(ctx
, EXCP_RI
);
1313 generate_exception(ctx
, EXCP_RI
);
1316 GEN_STORE_TN_REG(rd
, T0
);
1318 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1321 /* Arithmetic on HI/LO registers */
1322 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1324 const char *opn
= "hilo";
1326 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1327 /* Treat as a NOP */
1334 GEN_STORE_TN_REG(reg
, T0
);
1339 GEN_STORE_TN_REG(reg
, T0
);
1343 GEN_LOAD_REG_TN(T0
, reg
);
1348 GEN_LOAD_REG_TN(T0
, reg
);
1354 generate_exception(ctx
, EXCP_RI
);
1357 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1360 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1363 const char *opn
= "mul/div";
1365 GEN_LOAD_REG_TN(T0
, rs
);
1366 GEN_LOAD_REG_TN(T1
, rt
);
1384 #ifdef TARGET_MIPS64
1420 generate_exception(ctx
, EXCP_RI
);
1423 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
1426 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
1429 const char *opn
= "CLx";
1431 /* Treat as a NOP */
1435 GEN_LOAD_REG_TN(T0
, rs
);
1445 #ifdef TARGET_MIPS64
1457 generate_exception(ctx
, EXCP_RI
);
1460 gen_op_store_T0_gpr(rd
);
1461 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
1465 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
1466 int rs
, int rt
, int16_t imm
)
1471 /* Load needed operands */
1479 /* Compare two registers */
1481 GEN_LOAD_REG_TN(T0
, rs
);
1482 GEN_LOAD_REG_TN(T1
, rt
);
1492 /* Compare register to immediate */
1493 if (rs
!= 0 || imm
!= 0) {
1494 GEN_LOAD_REG_TN(T0
, rs
);
1495 GEN_LOAD_IMM_TN(T1
, (int32_t)imm
);
1502 case OPC_TEQ
: /* rs == rs */
1503 case OPC_TEQI
: /* r0 == 0 */
1504 case OPC_TGE
: /* rs >= rs */
1505 case OPC_TGEI
: /* r0 >= 0 */
1506 case OPC_TGEU
: /* rs >= rs unsigned */
1507 case OPC_TGEIU
: /* r0 >= 0 unsigned */
1511 case OPC_TLT
: /* rs < rs */
1512 case OPC_TLTI
: /* r0 < 0 */
1513 case OPC_TLTU
: /* rs < rs unsigned */
1514 case OPC_TLTIU
: /* r0 < 0 unsigned */
1515 case OPC_TNE
: /* rs != rs */
1516 case OPC_TNEI
: /* r0 != 0 */
1517 /* Never trap: treat as NOP */
1521 generate_exception(ctx
, EXCP_RI
);
1552 generate_exception(ctx
, EXCP_RI
);
1556 save_cpu_state(ctx
, 1);
1558 ctx
->bstate
= BS_STOP
;
1561 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1563 TranslationBlock
*tb
;
1565 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1567 gen_op_goto_tb0(TBPARAM(tb
));
1569 gen_op_goto_tb1(TBPARAM(tb
));
1571 gen_op_set_T0((long)tb
+ n
);
1579 /* Branches (before delay slot) */
1580 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
1581 int rs
, int rt
, int32_t offset
)
1583 target_ulong btarget
= -1;
1587 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1588 #ifdef MIPS_DEBUG_DISAS
1589 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
1591 "Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n",
1595 generate_exception(ctx
, EXCP_RI
);
1599 /* Load needed operands */
1605 /* Compare two registers */
1607 GEN_LOAD_REG_TN(T0
, rs
);
1608 GEN_LOAD_REG_TN(T1
, rt
);
1611 btarget
= ctx
->pc
+ 4 + offset
;
1625 /* Compare to zero */
1627 gen_op_load_gpr_T0(rs
);
1630 btarget
= ctx
->pc
+ 4 + offset
;
1634 /* Jump to immediate */
1635 btarget
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
1639 /* Jump to register */
1640 if (offset
!= 0 && offset
!= 16) {
1641 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
1642 others are reserved. */
1643 MIPS_INVAL("jump hint");
1644 generate_exception(ctx
, EXCP_RI
);
1647 GEN_LOAD_REG_TN(T2
, rs
);
1650 MIPS_INVAL("branch/jump");
1651 generate_exception(ctx
, EXCP_RI
);
1655 /* No condition to be computed */
1657 case OPC_BEQ
: /* rx == rx */
1658 case OPC_BEQL
: /* rx == rx likely */
1659 case OPC_BGEZ
: /* 0 >= 0 */
1660 case OPC_BGEZL
: /* 0 >= 0 likely */
1661 case OPC_BLEZ
: /* 0 <= 0 */
1662 case OPC_BLEZL
: /* 0 <= 0 likely */
1664 ctx
->hflags
|= MIPS_HFLAG_B
;
1665 MIPS_DEBUG("balways");
1667 case OPC_BGEZAL
: /* 0 >= 0 */
1668 case OPC_BGEZALL
: /* 0 >= 0 likely */
1669 /* Always take and link */
1671 ctx
->hflags
|= MIPS_HFLAG_B
;
1672 MIPS_DEBUG("balways and link");
1674 case OPC_BNE
: /* rx != rx */
1675 case OPC_BGTZ
: /* 0 > 0 */
1676 case OPC_BLTZ
: /* 0 < 0 */
1677 /* Treated as NOP */
1678 MIPS_DEBUG("bnever (NOP)");
1680 case OPC_BLTZAL
: /* 0 < 0 */
1681 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1682 gen_op_store_T0_gpr(31);
1683 MIPS_DEBUG("bnever and link");
1685 case OPC_BLTZALL
: /* 0 < 0 likely */
1686 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1687 gen_op_store_T0_gpr(31);
1688 /* Skip the instruction in the delay slot */
1689 MIPS_DEBUG("bnever, link and skip");
1692 case OPC_BNEL
: /* rx != rx likely */
1693 case OPC_BGTZL
: /* 0 > 0 likely */
1694 case OPC_BLTZL
: /* 0 < 0 likely */
1695 /* Skip the instruction in the delay slot */
1696 MIPS_DEBUG("bnever and skip");
1700 ctx
->hflags
|= MIPS_HFLAG_B
;
1701 MIPS_DEBUG("j " TARGET_FMT_lx
, btarget
);
1705 ctx
->hflags
|= MIPS_HFLAG_B
;
1706 MIPS_DEBUG("jal " TARGET_FMT_lx
, btarget
);
1709 ctx
->hflags
|= MIPS_HFLAG_BR
;
1710 MIPS_DEBUG("jr %s", regnames
[rs
]);
1714 ctx
->hflags
|= MIPS_HFLAG_BR
;
1715 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
1718 MIPS_INVAL("branch/jump");
1719 generate_exception(ctx
, EXCP_RI
);
1726 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
1727 regnames
[rs
], regnames
[rt
], btarget
);
1731 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
1732 regnames
[rs
], regnames
[rt
], btarget
);
1736 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
1737 regnames
[rs
], regnames
[rt
], btarget
);
1741 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
1742 regnames
[rs
], regnames
[rt
], btarget
);
1746 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1750 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1754 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1760 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1764 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1768 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1772 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1776 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1780 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1784 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1789 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1791 ctx
->hflags
|= MIPS_HFLAG_BC
;
1797 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btarget
);
1799 ctx
->hflags
|= MIPS_HFLAG_BL
;
1801 gen_op_save_bcond();
1804 MIPS_INVAL("conditional branch/jump");
1805 generate_exception(ctx
, EXCP_RI
);
1809 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
1810 blink
, ctx
->hflags
, btarget
);
1812 ctx
->btarget
= btarget
;
1814 GEN_LOAD_IMM_TN(T0
, ctx
->pc
+ 8);
1815 gen_op_store_T0_gpr(blink
);
1819 /* special3 bitfield operations */
1820 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
1821 int rs
, int lsb
, int msb
)
1823 GEN_LOAD_REG_TN(T1
, rs
);
1828 gen_op_ext(lsb
, msb
+ 1);
1833 gen_op_ext(lsb
, msb
+ 1 + 32);
1838 gen_op_ext(lsb
+ 32, msb
+ 1);
1841 gen_op_ext(lsb
, msb
+ 1);
1846 GEN_LOAD_REG_TN(T0
, rt
);
1847 gen_op_ins(lsb
, msb
- lsb
+ 1);
1852 GEN_LOAD_REG_TN(T0
, rt
);
1853 gen_op_ins(lsb
, msb
- lsb
+ 1 + 32);
1858 GEN_LOAD_REG_TN(T0
, rt
);
1859 gen_op_ins(lsb
+ 32, msb
- lsb
+ 1);
1864 GEN_LOAD_REG_TN(T0
, rt
);
1865 gen_op_ins(lsb
, msb
- lsb
+ 1);
1869 MIPS_INVAL("bitops");
1870 generate_exception(ctx
, EXCP_RI
);
1873 GEN_STORE_TN_REG(rt
, T0
);
1876 /* CP0 (MMU and control) */
1877 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
1879 const char *rn
= "invalid";
1885 gen_op_mfc0_index();
1889 // gen_op_mfc0_mvpcontrol(); /* MT ASE */
1893 // gen_op_mfc0_mvpconf0(); /* MT ASE */
1897 // gen_op_mfc0_mvpconf1(); /* MT ASE */
1907 gen_op_mfc0_random();
1911 // gen_op_mfc0_vpecontrol(); /* MT ASE */
1915 // gen_op_mfc0_vpeconf0(); /* MT ASE */
1919 // gen_op_mfc0_vpeconf1(); /* MT ASE */
1923 // gen_op_mfc0_YQMask(); /* MT ASE */
1927 // gen_op_mfc0_vpeschedule(); /* MT ASE */
1931 // gen_op_mfc0_vpeschefback(); /* MT ASE */
1932 rn
= "VPEScheFBack";
1935 // gen_op_mfc0_vpeopt(); /* MT ASE */
1945 gen_op_mfc0_entrylo0();
1949 // gen_op_mfc0_tcstatus(); /* MT ASE */
1953 // gen_op_mfc0_tcbind(); /* MT ASE */
1957 // gen_op_mfc0_tcrestart(); /* MT ASE */
1961 // gen_op_mfc0_tchalt(); /* MT ASE */
1965 // gen_op_mfc0_tccontext(); /* MT ASE */
1969 // gen_op_mfc0_tcschedule(); /* MT ASE */
1973 // gen_op_mfc0_tcschefback(); /* MT ASE */
1983 gen_op_mfc0_entrylo1();
1993 gen_op_mfc0_context();
1997 // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
1998 rn
= "ContextConfig";
2007 gen_op_mfc0_pagemask();
2011 check_mips_r2(env
, ctx
);
2012 gen_op_mfc0_pagegrain();
2022 gen_op_mfc0_wired();
2026 // gen_op_mfc0_srsconf0(); /* shadow registers */
2030 // gen_op_mfc0_srsconf1(); /* shadow registers */
2034 // gen_op_mfc0_srsconf2(); /* shadow registers */
2038 // gen_op_mfc0_srsconf3(); /* shadow registers */
2042 // gen_op_mfc0_srsconf4(); /* shadow registers */
2052 check_mips_r2(env
, ctx
);
2053 gen_op_mfc0_hwrena();
2063 gen_op_mfc0_badvaddr();
2073 gen_op_mfc0_count();
2076 /* 6,7 are implementation dependent */
2084 gen_op_mfc0_entryhi();
2094 gen_op_mfc0_compare();
2097 /* 6,7 are implementation dependent */
2105 gen_op_mfc0_status();
2109 check_mips_r2(env
, ctx
);
2110 gen_op_mfc0_intctl();
2114 check_mips_r2(env
, ctx
);
2115 gen_op_mfc0_srsctl();
2119 check_mips_r2(env
, ctx
);
2120 gen_op_mfc0_srsmap();
2130 gen_op_mfc0_cause();
2154 check_mips_r2(env
, ctx
);
2155 gen_op_mfc0_ebase();
2165 gen_op_mfc0_config0();
2169 gen_op_mfc0_config1();
2173 gen_op_mfc0_config2();
2177 gen_op_mfc0_config3();
2180 /* 4,5 are reserved */
2181 /* 6,7 are implementation dependent */
2183 gen_op_mfc0_config6();
2187 gen_op_mfc0_config7();
2197 gen_op_mfc0_lladdr();
2207 gen_op_mfc0_watchlo(sel
);
2217 gen_op_mfc0_watchhi(sel
);
2227 #ifdef TARGET_MIPS64
2228 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
2230 gen_op_mfc0_xcontext();
2239 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2242 gen_op_mfc0_framemask();
2251 rn
= "'Diagnostic"; /* implementation dependent */
2256 gen_op_mfc0_debug(); /* EJTAG support */
2260 // gen_op_mfc0_tracecontrol(); /* PDtrace support */
2261 rn
= "TraceControl";
2264 // gen_op_mfc0_tracecontrol2(); /* PDtrace support */
2265 rn
= "TraceControl2";
2268 // gen_op_mfc0_usertracedata(); /* PDtrace support */
2269 rn
= "UserTraceData";
2272 // gen_op_mfc0_debug(); /* PDtrace support */
2282 gen_op_mfc0_depc(); /* EJTAG support */
2292 gen_op_mfc0_performance0();
2293 rn
= "Performance0";
2296 // gen_op_mfc0_performance1();
2297 rn
= "Performance1";
2300 // gen_op_mfc0_performance2();
2301 rn
= "Performance2";
2304 // gen_op_mfc0_performance3();
2305 rn
= "Performance3";
2308 // gen_op_mfc0_performance4();
2309 rn
= "Performance4";
2312 // gen_op_mfc0_performance5();
2313 rn
= "Performance5";
2316 // gen_op_mfc0_performance6();
2317 rn
= "Performance6";
2320 // gen_op_mfc0_performance7();
2321 rn
= "Performance7";
2346 gen_op_mfc0_taglo();
2353 gen_op_mfc0_datalo();
2366 gen_op_mfc0_taghi();
2373 gen_op_mfc0_datahi();
2383 gen_op_mfc0_errorepc();
2393 gen_op_mfc0_desave(); /* EJTAG support */
2403 #if defined MIPS_DEBUG_DISAS
2404 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2405 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2412 #if defined MIPS_DEBUG_DISAS
2413 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2414 fprintf(logfile
, "mfc0 %s (reg %d sel %d)\n",
2418 generate_exception(ctx
, EXCP_RI
);
2421 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2423 const char *rn
= "invalid";
2429 gen_op_mtc0_index();
2433 // gen_op_mtc0_mvpcontrol(); /* MT ASE */
2437 // gen_op_mtc0_mvpconf0(); /* MT ASE */
2441 // gen_op_mtc0_mvpconf1(); /* MT ASE */
2455 // gen_op_mtc0_vpecontrol(); /* MT ASE */
2459 // gen_op_mtc0_vpeconf0(); /* MT ASE */
2463 // gen_op_mtc0_vpeconf1(); /* MT ASE */
2467 // gen_op_mtc0_YQMask(); /* MT ASE */
2471 // gen_op_mtc0_vpeschedule(); /* MT ASE */
2475 // gen_op_mtc0_vpeschefback(); /* MT ASE */
2476 rn
= "VPEScheFBack";
2479 // gen_op_mtc0_vpeopt(); /* MT ASE */
2489 gen_op_mtc0_entrylo0();
2493 // gen_op_mtc0_tcstatus(); /* MT ASE */
2497 // gen_op_mtc0_tcbind(); /* MT ASE */
2501 // gen_op_mtc0_tcrestart(); /* MT ASE */
2505 // gen_op_mtc0_tchalt(); /* MT ASE */
2509 // gen_op_mtc0_tccontext(); /* MT ASE */
2513 // gen_op_mtc0_tcschedule(); /* MT ASE */
2517 // gen_op_mtc0_tcschefback(); /* MT ASE */
2527 gen_op_mtc0_entrylo1();
2537 gen_op_mtc0_context();
2541 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
2542 rn
= "ContextConfig";
2551 gen_op_mtc0_pagemask();
2555 check_mips_r2(env
, ctx
);
2556 gen_op_mtc0_pagegrain();
2566 gen_op_mtc0_wired();
2570 // gen_op_mtc0_srsconf0(); /* shadow registers */
2574 // gen_op_mtc0_srsconf1(); /* shadow registers */
2578 // gen_op_mtc0_srsconf2(); /* shadow registers */
2582 // gen_op_mtc0_srsconf3(); /* shadow registers */
2586 // gen_op_mtc0_srsconf4(); /* shadow registers */
2596 check_mips_r2(env
, ctx
);
2597 gen_op_mtc0_hwrena();
2611 gen_op_mtc0_count();
2614 /* 6,7 are implementation dependent */
2618 /* Stop translation as we may have switched the execution mode */
2619 ctx
->bstate
= BS_STOP
;
2624 gen_op_mtc0_entryhi();
2634 gen_op_mtc0_compare();
2637 /* 6,7 are implementation dependent */
2641 /* Stop translation as we may have switched the execution mode */
2642 ctx
->bstate
= BS_STOP
;
2647 gen_op_mtc0_status();
2648 /* BS_STOP isn't good enough here, hflags may have changed. */
2649 gen_save_pc(ctx
->pc
+ 4);
2650 ctx
->bstate
= BS_EXCP
;
2654 check_mips_r2(env
, ctx
);
2655 gen_op_mtc0_intctl();
2656 /* Stop translation as we may have switched the execution mode */
2657 ctx
->bstate
= BS_STOP
;
2661 check_mips_r2(env
, ctx
);
2662 gen_op_mtc0_srsctl();
2663 /* Stop translation as we may have switched the execution mode */
2664 ctx
->bstate
= BS_STOP
;
2668 check_mips_r2(env
, ctx
);
2669 gen_op_mtc0_srsmap();
2670 /* Stop translation as we may have switched the execution mode */
2671 ctx
->bstate
= BS_STOP
;
2681 gen_op_mtc0_cause();
2687 /* Stop translation as we may have switched the execution mode */
2688 ctx
->bstate
= BS_STOP
;
2707 check_mips_r2(env
, ctx
);
2708 gen_op_mtc0_ebase();
2718 gen_op_mtc0_config0();
2720 /* Stop translation as we may have switched the execution mode */
2721 ctx
->bstate
= BS_STOP
;
2724 /* ignored, read only */
2728 gen_op_mtc0_config2();
2730 /* Stop translation as we may have switched the execution mode */
2731 ctx
->bstate
= BS_STOP
;
2734 /* ignored, read only */
2737 /* 4,5 are reserved */
2738 /* 6,7 are implementation dependent */
2748 rn
= "Invalid config selector";
2765 gen_op_mtc0_watchlo(sel
);
2775 gen_op_mtc0_watchhi(sel
);
2785 #ifdef TARGET_MIPS64
2786 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
2788 gen_op_mtc0_xcontext();
2797 /* Officially reserved, but sel 0 is used for R1x000 framemask */
2800 gen_op_mtc0_framemask();
2809 rn
= "Diagnostic"; /* implementation dependent */
2814 gen_op_mtc0_debug(); /* EJTAG support */
2815 /* BS_STOP isn't good enough here, hflags may have changed. */
2816 gen_save_pc(ctx
->pc
+ 4);
2817 ctx
->bstate
= BS_EXCP
;
2821 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
2822 rn
= "TraceControl";
2823 /* Stop translation as we may have switched the execution mode */
2824 ctx
->bstate
= BS_STOP
;
2827 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
2828 rn
= "TraceControl2";
2829 /* Stop translation as we may have switched the execution mode */
2830 ctx
->bstate
= BS_STOP
;
2833 /* Stop translation as we may have switched the execution mode */
2834 ctx
->bstate
= BS_STOP
;
2835 // gen_op_mtc0_usertracedata(); /* PDtrace support */
2836 rn
= "UserTraceData";
2837 /* Stop translation as we may have switched the execution mode */
2838 ctx
->bstate
= BS_STOP
;
2841 // gen_op_mtc0_debug(); /* PDtrace support */
2842 /* Stop translation as we may have switched the execution mode */
2843 ctx
->bstate
= BS_STOP
;
2853 gen_op_mtc0_depc(); /* EJTAG support */
2863 gen_op_mtc0_performance0();
2864 rn
= "Performance0";
2867 // gen_op_mtc0_performance1();
2868 rn
= "Performance1";
2871 // gen_op_mtc0_performance2();
2872 rn
= "Performance2";
2875 // gen_op_mtc0_performance3();
2876 rn
= "Performance3";
2879 // gen_op_mtc0_performance4();
2880 rn
= "Performance4";
2883 // gen_op_mtc0_performance5();
2884 rn
= "Performance5";
2887 // gen_op_mtc0_performance6();
2888 rn
= "Performance6";
2891 // gen_op_mtc0_performance7();
2892 rn
= "Performance7";
2918 gen_op_mtc0_taglo();
2925 gen_op_mtc0_datalo();
2938 gen_op_mtc0_taghi();
2945 gen_op_mtc0_datahi();
2956 gen_op_mtc0_errorepc();
2966 gen_op_mtc0_desave(); /* EJTAG support */
2972 /* Stop translation as we may have switched the execution mode */
2973 ctx
->bstate
= BS_STOP
;
2978 #if defined MIPS_DEBUG_DISAS
2979 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2980 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
2987 #if defined MIPS_DEBUG_DISAS
2988 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2989 fprintf(logfile
, "mtc0 %s (reg %d sel %d)\n",
2993 generate_exception(ctx
, EXCP_RI
);
2996 #ifdef TARGET_MIPS64
2997 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
2999 const char *rn
= "invalid";
3005 gen_op_mfc0_index();
3009 // gen_op_dmfc0_mvpcontrol(); /* MT ASE */
3013 // gen_op_dmfc0_mvpconf0(); /* MT ASE */
3017 // gen_op_dmfc0_mvpconf1(); /* MT ASE */
3027 gen_op_mfc0_random();
3031 // gen_op_dmfc0_vpecontrol(); /* MT ASE */
3035 // gen_op_dmfc0_vpeconf0(); /* MT ASE */
3039 // gen_op_dmfc0_vpeconf1(); /* MT ASE */
3043 // gen_op_dmfc0_YQMask(); /* MT ASE */
3047 // gen_op_dmfc0_vpeschedule(); /* MT ASE */
3051 // gen_op_dmfc0_vpeschefback(); /* MT ASE */
3052 rn
= "VPEScheFBack";
3055 // gen_op_dmfc0_vpeopt(); /* MT ASE */
3065 gen_op_dmfc0_entrylo0();
3069 // gen_op_dmfc0_tcstatus(); /* MT ASE */
3073 // gen_op_dmfc0_tcbind(); /* MT ASE */
3077 // gen_op_dmfc0_tcrestart(); /* MT ASE */
3081 // gen_op_dmfc0_tchalt(); /* MT ASE */
3085 // gen_op_dmfc0_tccontext(); /* MT ASE */
3089 // gen_op_dmfc0_tcschedule(); /* MT ASE */
3093 // gen_op_dmfc0_tcschefback(); /* MT ASE */
3103 gen_op_dmfc0_entrylo1();
3113 gen_op_dmfc0_context();
3117 // gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
3118 rn
= "ContextConfig";
3127 gen_op_mfc0_pagemask();
3131 check_mips_r2(env
, ctx
);
3132 gen_op_mfc0_pagegrain();
3142 gen_op_mfc0_wired();
3146 // gen_op_dmfc0_srsconf0(); /* shadow registers */
3150 // gen_op_dmfc0_srsconf1(); /* shadow registers */
3154 // gen_op_dmfc0_srsconf2(); /* shadow registers */
3158 // gen_op_dmfc0_srsconf3(); /* shadow registers */
3162 // gen_op_dmfc0_srsconf4(); /* shadow registers */
3172 check_mips_r2(env
, ctx
);
3173 gen_op_mfc0_hwrena();
3183 gen_op_dmfc0_badvaddr();
3193 gen_op_mfc0_count();
3196 /* 6,7 are implementation dependent */
3204 gen_op_dmfc0_entryhi();
3214 gen_op_mfc0_compare();
3217 /* 6,7 are implementation dependent */
3225 gen_op_mfc0_status();
3229 check_mips_r2(env
, ctx
);
3230 gen_op_mfc0_intctl();
3234 check_mips_r2(env
, ctx
);
3235 gen_op_mfc0_srsctl();
3239 check_mips_r2(env
, ctx
);
3240 gen_op_mfc0_srsmap(); /* shadow registers */
3250 gen_op_mfc0_cause();
3274 check_mips_r2(env
, ctx
);
3275 gen_op_mfc0_ebase();
3285 gen_op_mfc0_config0();
3289 gen_op_mfc0_config1();
3293 gen_op_mfc0_config2();
3297 gen_op_mfc0_config3();
3300 /* 6,7 are implementation dependent */
3308 gen_op_dmfc0_lladdr();
3318 gen_op_dmfc0_watchlo(sel
);
3328 gen_op_mfc0_watchhi(sel
);
3338 gen_op_dmfc0_xcontext();
3346 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3349 gen_op_mfc0_framemask();
3358 rn
= "'Diagnostic"; /* implementation dependent */
3363 gen_op_mfc0_debug(); /* EJTAG support */
3367 // gen_op_dmfc0_tracecontrol(); /* PDtrace support */
3368 rn
= "TraceControl";
3371 // gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
3372 rn
= "TraceControl2";
3375 // gen_op_dmfc0_usertracedata(); /* PDtrace support */
3376 rn
= "UserTraceData";
3379 // gen_op_dmfc0_debug(); /* PDtrace support */
3389 gen_op_dmfc0_depc(); /* EJTAG support */
3399 gen_op_mfc0_performance0();
3400 rn
= "Performance0";
3403 // gen_op_dmfc0_performance1();
3404 rn
= "Performance1";
3407 // gen_op_dmfc0_performance2();
3408 rn
= "Performance2";
3411 // gen_op_dmfc0_performance3();
3412 rn
= "Performance3";
3415 // gen_op_dmfc0_performance4();
3416 rn
= "Performance4";
3419 // gen_op_dmfc0_performance5();
3420 rn
= "Performance5";
3423 // gen_op_dmfc0_performance6();
3424 rn
= "Performance6";
3427 // gen_op_dmfc0_performance7();
3428 rn
= "Performance7";
3453 gen_op_mfc0_taglo();
3460 gen_op_mfc0_datalo();
3473 gen_op_mfc0_taghi();
3480 gen_op_mfc0_datahi();
3490 gen_op_dmfc0_errorepc();
3500 gen_op_mfc0_desave(); /* EJTAG support */
3510 #if defined MIPS_DEBUG_DISAS
3511 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3512 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3519 #if defined MIPS_DEBUG_DISAS
3520 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
3521 fprintf(logfile
, "dmfc0 %s (reg %d sel %d)\n",
3525 generate_exception(ctx
, EXCP_RI
);
3528 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, int reg
, int sel
)
3530 const char *rn
= "invalid";
3536 gen_op_mtc0_index();
3540 // gen_op_mtc0_mvpcontrol(); /* MT ASE */
3544 // gen_op_mtc0_mvpconf0(); /* MT ASE */
3548 // gen_op_mtc0_mvpconf1(); /* MT ASE */
3562 // gen_op_mtc0_vpecontrol(); /* MT ASE */
3566 // gen_op_mtc0_vpeconf0(); /* MT ASE */
3570 // gen_op_mtc0_vpeconf1(); /* MT ASE */
3574 // gen_op_mtc0_YQMask(); /* MT ASE */
3578 // gen_op_mtc0_vpeschedule(); /* MT ASE */
3582 // gen_op_mtc0_vpeschefback(); /* MT ASE */
3583 rn
= "VPEScheFBack";
3586 // gen_op_mtc0_vpeopt(); /* MT ASE */
3596 gen_op_mtc0_entrylo0();
3600 // gen_op_mtc0_tcstatus(); /* MT ASE */
3604 // gen_op_mtc0_tcbind(); /* MT ASE */
3608 // gen_op_mtc0_tcrestart(); /* MT ASE */
3612 // gen_op_mtc0_tchalt(); /* MT ASE */
3616 // gen_op_mtc0_tccontext(); /* MT ASE */
3620 // gen_op_mtc0_tcschedule(); /* MT ASE */
3624 // gen_op_mtc0_tcschefback(); /* MT ASE */
3634 gen_op_mtc0_entrylo1();
3644 gen_op_mtc0_context();
3648 // gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
3649 rn
= "ContextConfig";
3658 gen_op_mtc0_pagemask();
3662 check_mips_r2(env
, ctx
);
3663 gen_op_mtc0_pagegrain();
3673 gen_op_mtc0_wired();
3677 // gen_op_mtc0_srsconf0(); /* shadow registers */
3681 // gen_op_mtc0_srsconf1(); /* shadow registers */
3685 // gen_op_mtc0_srsconf2(); /* shadow registers */
3689 // gen_op_mtc0_srsconf3(); /* shadow registers */
3693 // gen_op_mtc0_srsconf4(); /* shadow registers */
3703 check_mips_r2(env
, ctx
);
3704 gen_op_mtc0_hwrena();
3718 gen_op_mtc0_count();
3721 /* 6,7 are implementation dependent */
3725 /* Stop translation as we may have switched the execution mode */
3726 ctx
->bstate
= BS_STOP
;
3731 gen_op_mtc0_entryhi();
3741 gen_op_mtc0_compare();
3744 /* 6,7 are implementation dependent */
3748 /* Stop translation as we may have switched the execution mode */
3749 ctx
->bstate
= BS_STOP
;
3754 gen_op_mtc0_status();
3755 /* BS_STOP isn't good enough here, hflags may have changed. */
3756 gen_save_pc(ctx
->pc
+ 4);
3757 ctx
->bstate
= BS_EXCP
;
3761 check_mips_r2(env
, ctx
);
3762 gen_op_mtc0_intctl();
3763 /* Stop translation as we may have switched the execution mode */
3764 ctx
->bstate
= BS_STOP
;
3768 check_mips_r2(env
, ctx
);
3769 gen_op_mtc0_srsctl();
3770 /* Stop translation as we may have switched the execution mode */
3771 ctx
->bstate
= BS_STOP
;
3775 check_mips_r2(env
, ctx
);
3776 gen_op_mtc0_srsmap();
3777 /* Stop translation as we may have switched the execution mode */
3778 ctx
->bstate
= BS_STOP
;
3788 gen_op_mtc0_cause();
3794 /* Stop translation as we may have switched the execution mode */
3795 ctx
->bstate
= BS_STOP
;
3814 check_mips_r2(env
, ctx
);
3815 gen_op_mtc0_ebase();
3825 gen_op_mtc0_config0();
3827 /* Stop translation as we may have switched the execution mode */
3828 ctx
->bstate
= BS_STOP
;
3835 gen_op_mtc0_config2();
3837 /* Stop translation as we may have switched the execution mode */
3838 ctx
->bstate
= BS_STOP
;
3844 /* 6,7 are implementation dependent */
3846 rn
= "Invalid config selector";
3863 gen_op_mtc0_watchlo(sel
);
3873 gen_op_mtc0_watchhi(sel
);
3883 gen_op_mtc0_xcontext();
3891 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3894 gen_op_mtc0_framemask();
3903 rn
= "Diagnostic"; /* implementation dependent */
3908 gen_op_mtc0_debug(); /* EJTAG support */
3909 /* BS_STOP isn't good enough here, hflags may have changed. */
3910 gen_save_pc(ctx
->pc
+ 4);
3911 ctx
->bstate
= BS_EXCP
;
3915 // gen_op_mtc0_tracecontrol(); /* PDtrace support */
3916 /* Stop translation as we may have switched the execution mode */
3917 ctx
->bstate
= BS_STOP
;
3918 rn
= "TraceControl";
3921 // gen_op_mtc0_tracecontrol2(); /* PDtrace support */
3922 /* Stop translation as we may have switched the execution mode */
3923 ctx
->bstate
= BS_STOP
;
3924 rn
= "TraceControl2";
3927 // gen_op_mtc0_usertracedata(); /* PDtrace support */
3928 /* Stop translation as we may have switched the execution mode */
3929 ctx
->bstate
= BS_STOP
;
3930 rn
= "UserTraceData";
3933 // gen_op_mtc0_debug(); /* PDtrace support */
3934 /* Stop translation as we may have switched the execution mode */
3935 ctx
->bstate
= BS_STOP
;
3945 gen_op_mtc0_depc(); /* EJTAG support */
3955 gen_op_mtc0_performance0();
3956 rn
= "Performance0";
3959 // gen_op_mtc0_performance1();
3960 rn
= "Performance1";
3963 // gen_op_mtc0_performance2();
3964 rn
= "Performance2";
3967 // gen_op_mtc0_performance3();
3968 rn
= "Performance3";
3971 // gen_op_mtc0_performance4();
3972 rn
= "Performance4";
3975 // gen_op_mtc0_performance5();
3976 rn
= "Performance5";
3979 // gen_op_mtc0_performance6();
3980 rn
= "Performance6";
3983 // gen_op_mtc0_performance7();
3984 rn
= "Performance7";
4010 gen_op_mtc0_taglo();
4017 gen_op_mtc0_datalo();
4030 gen_op_mtc0_taghi();
4037 gen_op_mtc0_datahi();
4048 gen_op_mtc0_errorepc();
4058 gen_op_mtc0_desave(); /* EJTAG support */
4064 /* Stop translation as we may have switched the execution mode */
4065 ctx
->bstate
= BS_STOP
;
4070 #if defined MIPS_DEBUG_DISAS
4071 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4072 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4079 #if defined MIPS_DEBUG_DISAS
4080 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4081 fprintf(logfile
, "dmtc0 %s (reg %d sel %d)\n",
4085 generate_exception(ctx
, EXCP_RI
);
4087 #endif /* TARGET_MIPS64 */
4089 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
4091 const char *opn
= "ldst";
4099 gen_mfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4100 gen_op_store_T0_gpr(rt
);
4104 GEN_LOAD_REG_TN(T0
, rt
);
4105 gen_mtc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4108 #ifdef TARGET_MIPS64
4110 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
4111 generate_exception(ctx
, EXCP_RI
);
4116 gen_dmfc0(env
, ctx
, rd
, ctx
->opcode
& 0x7);
4117 gen_op_store_T0_gpr(rt
);
4121 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
4122 generate_exception(ctx
, EXCP_RI
);
4123 GEN_LOAD_REG_TN(T0
, rt
);
4124 gen_dmtc0(env
,ctx
, rd
, ctx
->opcode
& 0x7);
4155 ctx
->bstate
= BS_EXCP
;
4159 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
4161 generate_exception(ctx
, EXCP_RI
);
4164 ctx
->bstate
= BS_EXCP
;
4169 /* If we get an exception, we want to restart at next instruction */
4171 save_cpu_state(ctx
, 1);
4174 ctx
->bstate
= BS_EXCP
;
4179 generate_exception(ctx
, EXCP_RI
);
4182 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
4185 /* CP1 Branches (before delay slot) */
4186 static void gen_compute_branch1 (DisasContext
*ctx
, uint32_t op
,
4187 int32_t cc
, int32_t offset
)
4189 target_ulong btarget
;
4190 const char *opn
= "cp1 cond branch";
4192 btarget
= ctx
->pc
+ 4 + offset
;
4211 ctx
->hflags
|= MIPS_HFLAG_BL
;
4213 gen_op_save_bcond();
4216 gen_op_bc1any2f(cc
);
4220 gen_op_bc1any2t(cc
);
4224 gen_op_bc1any4f(cc
);
4228 gen_op_bc1any4t(cc
);
4231 ctx
->hflags
|= MIPS_HFLAG_BC
;
4236 generate_exception (ctx
, EXCP_RI
);
4239 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
4240 ctx
->hflags
, btarget
);
4241 ctx
->btarget
= btarget
;
4244 /* Coprocessor 1 (FPU) */
4246 #define FOP(func, fmt) (((fmt) << 21) | (func))
4248 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
4250 const char *opn
= "cp1 move";
4254 GEN_LOAD_FREG_FTN(WT0
, fs
);
4256 GEN_STORE_TN_REG(rt
, T0
);
4260 GEN_LOAD_REG_TN(T0
, rt
);
4262 GEN_STORE_FTN_FREG(fs
, WT0
);
4266 GEN_LOAD_IMM_TN(T1
, fs
);
4268 GEN_STORE_TN_REG(rt
, T0
);
4272 GEN_LOAD_IMM_TN(T1
, fs
);
4273 GEN_LOAD_REG_TN(T0
, rt
);
4278 GEN_LOAD_FREG_FTN(DT0
, fs
);
4280 GEN_STORE_TN_REG(rt
, T0
);
4284 GEN_LOAD_REG_TN(T0
, rt
);
4286 GEN_STORE_FTN_FREG(fs
, DT0
);
4290 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4292 GEN_STORE_TN_REG(rt
, T0
);
4296 GEN_LOAD_REG_TN(T0
, rt
);
4298 GEN_STORE_FTN_FREG(fs
, WTH0
);
4303 generate_exception (ctx
, EXCP_RI
);
4306 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
4309 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
4313 GEN_LOAD_REG_TN(T0
, rd
);
4314 GEN_LOAD_REG_TN(T1
, rs
);
4316 ccbit
= 1 << (24 + cc
);
4323 GEN_STORE_TN_REG(rd
, T0
);
4326 #define GEN_MOVCF(fmt) \
4327 static void glue(gen_movcf_, fmt) (DisasContext *ctx, int cc, int tf) \
4332 ccbit = 1 << (24 + cc); \
4336 glue(gen_op_float_movf_, fmt)(ccbit); \
4338 glue(gen_op_float_movt_, fmt)(ccbit); \
4345 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
4346 int ft
, int fs
, int fd
, int cc
)
4348 const char *opn
= "farith";
4349 const char *condnames
[] = {
4367 const char *condnames_abs
[] = {
4385 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
4386 uint32_t func
= ctx
->opcode
& 0x3f;
4388 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
4390 GEN_LOAD_FREG_FTN(WT0
, fs
);
4391 GEN_LOAD_FREG_FTN(WT1
, ft
);
4392 gen_op_float_add_s();
4393 GEN_STORE_FTN_FREG(fd
, WT2
);
4398 GEN_LOAD_FREG_FTN(WT0
, fs
);
4399 GEN_LOAD_FREG_FTN(WT1
, ft
);
4400 gen_op_float_sub_s();
4401 GEN_STORE_FTN_FREG(fd
, WT2
);
4406 GEN_LOAD_FREG_FTN(WT0
, fs
);
4407 GEN_LOAD_FREG_FTN(WT1
, ft
);
4408 gen_op_float_mul_s();
4409 GEN_STORE_FTN_FREG(fd
, WT2
);
4414 GEN_LOAD_FREG_FTN(WT0
, fs
);
4415 GEN_LOAD_FREG_FTN(WT1
, ft
);
4416 gen_op_float_div_s();
4417 GEN_STORE_FTN_FREG(fd
, WT2
);
4422 GEN_LOAD_FREG_FTN(WT0
, fs
);
4423 gen_op_float_sqrt_s();
4424 GEN_STORE_FTN_FREG(fd
, WT2
);
4428 GEN_LOAD_FREG_FTN(WT0
, fs
);
4429 gen_op_float_abs_s();
4430 GEN_STORE_FTN_FREG(fd
, WT2
);
4434 GEN_LOAD_FREG_FTN(WT0
, fs
);
4435 gen_op_float_mov_s();
4436 GEN_STORE_FTN_FREG(fd
, WT2
);
4440 GEN_LOAD_FREG_FTN(WT0
, fs
);
4441 gen_op_float_chs_s();
4442 GEN_STORE_FTN_FREG(fd
, WT2
);
4446 check_cp1_64bitmode(ctx
);
4447 GEN_LOAD_FREG_FTN(WT0
, fs
);
4448 gen_op_float_roundl_s();
4449 GEN_STORE_FTN_FREG(fd
, DT2
);
4453 check_cp1_64bitmode(ctx
);
4454 GEN_LOAD_FREG_FTN(WT0
, fs
);
4455 gen_op_float_truncl_s();
4456 GEN_STORE_FTN_FREG(fd
, DT2
);
4460 check_cp1_64bitmode(ctx
);
4461 GEN_LOAD_FREG_FTN(WT0
, fs
);
4462 gen_op_float_ceill_s();
4463 GEN_STORE_FTN_FREG(fd
, DT2
);
4467 check_cp1_64bitmode(ctx
);
4468 GEN_LOAD_FREG_FTN(WT0
, fs
);
4469 gen_op_float_floorl_s();
4470 GEN_STORE_FTN_FREG(fd
, DT2
);
4474 GEN_LOAD_FREG_FTN(WT0
, fs
);
4475 gen_op_float_roundw_s();
4476 GEN_STORE_FTN_FREG(fd
, WT2
);
4480 GEN_LOAD_FREG_FTN(WT0
, fs
);
4481 gen_op_float_truncw_s();
4482 GEN_STORE_FTN_FREG(fd
, WT2
);
4486 GEN_LOAD_FREG_FTN(WT0
, fs
);
4487 gen_op_float_ceilw_s();
4488 GEN_STORE_FTN_FREG(fd
, WT2
);
4492 GEN_LOAD_FREG_FTN(WT0
, fs
);
4493 gen_op_float_floorw_s();
4494 GEN_STORE_FTN_FREG(fd
, WT2
);
4498 GEN_LOAD_REG_TN(T0
, ft
);
4499 GEN_LOAD_FREG_FTN(WT0
, fs
);
4500 GEN_LOAD_FREG_FTN(WT2
, fd
);
4501 gen_movcf_s(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
4502 GEN_STORE_FTN_FREG(fd
, WT2
);
4506 GEN_LOAD_REG_TN(T0
, ft
);
4507 GEN_LOAD_FREG_FTN(WT0
, fs
);
4508 GEN_LOAD_FREG_FTN(WT2
, fd
);
4509 gen_op_float_movz_s();
4510 GEN_STORE_FTN_FREG(fd
, WT2
);
4514 GEN_LOAD_REG_TN(T0
, ft
);
4515 GEN_LOAD_FREG_FTN(WT0
, fs
);
4516 GEN_LOAD_FREG_FTN(WT2
, fd
);
4517 gen_op_float_movn_s();
4518 GEN_STORE_FTN_FREG(fd
, WT2
);
4522 GEN_LOAD_FREG_FTN(WT0
, fs
);
4523 gen_op_float_recip_s();
4524 GEN_STORE_FTN_FREG(fd
, WT2
);
4528 GEN_LOAD_FREG_FTN(WT0
, fs
);
4529 gen_op_float_rsqrt_s();
4530 GEN_STORE_FTN_FREG(fd
, WT2
);
4534 check_cp1_64bitmode(ctx
);
4535 GEN_LOAD_FREG_FTN(WT0
, fs
);
4536 GEN_LOAD_FREG_FTN(WT2
, fd
);
4537 gen_op_float_recip2_s();
4538 GEN_STORE_FTN_FREG(fd
, WT2
);
4542 check_cp1_64bitmode(ctx
);
4543 GEN_LOAD_FREG_FTN(WT0
, fs
);
4544 gen_op_float_recip1_s();
4545 GEN_STORE_FTN_FREG(fd
, WT2
);
4549 check_cp1_64bitmode(ctx
);
4550 GEN_LOAD_FREG_FTN(WT0
, fs
);
4551 gen_op_float_rsqrt1_s();
4552 GEN_STORE_FTN_FREG(fd
, WT2
);
4556 check_cp1_64bitmode(ctx
);
4557 GEN_LOAD_FREG_FTN(WT0
, fs
);
4558 GEN_LOAD_FREG_FTN(WT2
, ft
);
4559 gen_op_float_rsqrt2_s();
4560 GEN_STORE_FTN_FREG(fd
, WT2
);
4564 check_cp1_registers(ctx
, fd
);
4565 GEN_LOAD_FREG_FTN(WT0
, fs
);
4566 gen_op_float_cvtd_s();
4567 GEN_STORE_FTN_FREG(fd
, DT2
);
4571 GEN_LOAD_FREG_FTN(WT0
, fs
);
4572 gen_op_float_cvtw_s();
4573 GEN_STORE_FTN_FREG(fd
, WT2
);
4577 check_cp1_64bitmode(ctx
);
4578 GEN_LOAD_FREG_FTN(WT0
, fs
);
4579 gen_op_float_cvtl_s();
4580 GEN_STORE_FTN_FREG(fd
, DT2
);
4584 check_cp1_64bitmode(ctx
);
4585 GEN_LOAD_FREG_FTN(WT1
, fs
);
4586 GEN_LOAD_FREG_FTN(WT0
, ft
);
4587 gen_op_float_cvtps_s();
4588 GEN_STORE_FTN_FREG(fd
, DT2
);
4607 GEN_LOAD_FREG_FTN(WT0
, fs
);
4608 GEN_LOAD_FREG_FTN(WT1
, ft
);
4609 if (ctx
->opcode
& (1 << 6)) {
4610 check_cp1_64bitmode(ctx
);
4611 gen_cmpabs_s(func
-48, cc
);
4612 opn
= condnames_abs
[func
-48];
4614 gen_cmp_s(func
-48, cc
);
4615 opn
= condnames
[func
-48];
4619 check_cp1_registers(ctx
, fs
| ft
| fd
);
4620 GEN_LOAD_FREG_FTN(DT0
, fs
);
4621 GEN_LOAD_FREG_FTN(DT1
, ft
);
4622 gen_op_float_add_d();
4623 GEN_STORE_FTN_FREG(fd
, DT2
);
4628 check_cp1_registers(ctx
, fs
| ft
| fd
);
4629 GEN_LOAD_FREG_FTN(DT0
, fs
);
4630 GEN_LOAD_FREG_FTN(DT1
, ft
);
4631 gen_op_float_sub_d();
4632 GEN_STORE_FTN_FREG(fd
, DT2
);
4637 check_cp1_registers(ctx
, fs
| ft
| fd
);
4638 GEN_LOAD_FREG_FTN(DT0
, fs
);
4639 GEN_LOAD_FREG_FTN(DT1
, ft
);
4640 gen_op_float_mul_d();
4641 GEN_STORE_FTN_FREG(fd
, DT2
);
4646 check_cp1_registers(ctx
, fs
| ft
| fd
);
4647 GEN_LOAD_FREG_FTN(DT0
, fs
);
4648 GEN_LOAD_FREG_FTN(DT1
, ft
);
4649 gen_op_float_div_d();
4650 GEN_STORE_FTN_FREG(fd
, DT2
);
4655 check_cp1_registers(ctx
, fs
| fd
);
4656 GEN_LOAD_FREG_FTN(DT0
, fs
);
4657 gen_op_float_sqrt_d();
4658 GEN_STORE_FTN_FREG(fd
, DT2
);
4662 check_cp1_registers(ctx
, fs
| fd
);
4663 GEN_LOAD_FREG_FTN(DT0
, fs
);
4664 gen_op_float_abs_d();
4665 GEN_STORE_FTN_FREG(fd
, DT2
);
4669 check_cp1_registers(ctx
, fs
| fd
);
4670 GEN_LOAD_FREG_FTN(DT0
, fs
);
4671 gen_op_float_mov_d();
4672 GEN_STORE_FTN_FREG(fd
, DT2
);
4676 check_cp1_registers(ctx
, fs
| fd
);
4677 GEN_LOAD_FREG_FTN(DT0
, fs
);
4678 gen_op_float_chs_d();
4679 GEN_STORE_FTN_FREG(fd
, DT2
);
4683 check_cp1_64bitmode(ctx
);
4684 GEN_LOAD_FREG_FTN(DT0
, fs
);
4685 gen_op_float_roundl_d();
4686 GEN_STORE_FTN_FREG(fd
, DT2
);
4690 check_cp1_64bitmode(ctx
);
4691 GEN_LOAD_FREG_FTN(DT0
, fs
);
4692 gen_op_float_truncl_d();
4693 GEN_STORE_FTN_FREG(fd
, DT2
);
4697 check_cp1_64bitmode(ctx
);
4698 GEN_LOAD_FREG_FTN(DT0
, fs
);
4699 gen_op_float_ceill_d();
4700 GEN_STORE_FTN_FREG(fd
, DT2
);
4704 check_cp1_64bitmode(ctx
);
4705 GEN_LOAD_FREG_FTN(DT0
, fs
);
4706 gen_op_float_floorl_d();
4707 GEN_STORE_FTN_FREG(fd
, DT2
);
4711 check_cp1_registers(ctx
, fs
);
4712 GEN_LOAD_FREG_FTN(DT0
, fs
);
4713 gen_op_float_roundw_d();
4714 GEN_STORE_FTN_FREG(fd
, WT2
);
4718 check_cp1_registers(ctx
, fs
);
4719 GEN_LOAD_FREG_FTN(DT0
, fs
);
4720 gen_op_float_truncw_d();
4721 GEN_STORE_FTN_FREG(fd
, WT2
);
4725 check_cp1_registers(ctx
, fs
);
4726 GEN_LOAD_FREG_FTN(DT0
, fs
);
4727 gen_op_float_ceilw_d();
4728 GEN_STORE_FTN_FREG(fd
, WT2
);
4732 check_cp1_registers(ctx
, fs
);
4733 GEN_LOAD_FREG_FTN(DT0
, fs
);
4734 gen_op_float_floorw_d();
4735 GEN_STORE_FTN_FREG(fd
, WT2
);
4739 GEN_LOAD_REG_TN(T0
, ft
);
4740 GEN_LOAD_FREG_FTN(DT0
, fs
);
4741 GEN_LOAD_FREG_FTN(DT2
, fd
);
4742 gen_movcf_d(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
4743 GEN_STORE_FTN_FREG(fd
, DT2
);
4747 GEN_LOAD_REG_TN(T0
, ft
);
4748 GEN_LOAD_FREG_FTN(DT0
, fs
);
4749 GEN_LOAD_FREG_FTN(DT2
, fd
);
4750 gen_op_float_movz_d();
4751 GEN_STORE_FTN_FREG(fd
, DT2
);
4755 GEN_LOAD_REG_TN(T0
, ft
);
4756 GEN_LOAD_FREG_FTN(DT0
, fs
);
4757 GEN_LOAD_FREG_FTN(DT2
, fd
);
4758 gen_op_float_movn_d();
4759 GEN_STORE_FTN_FREG(fd
, DT2
);
4763 check_cp1_registers(ctx
, fs
| fd
);
4764 GEN_LOAD_FREG_FTN(DT0
, fs
);
4765 gen_op_float_recip_d();
4766 GEN_STORE_FTN_FREG(fd
, DT2
);
4770 check_cp1_registers(ctx
, fs
| fd
);
4771 GEN_LOAD_FREG_FTN(DT0
, fs
);
4772 gen_op_float_rsqrt_d();
4773 GEN_STORE_FTN_FREG(fd
, DT2
);
4777 check_cp1_64bitmode(ctx
);
4778 GEN_LOAD_FREG_FTN(DT0
, fs
);
4779 GEN_LOAD_FREG_FTN(DT2
, ft
);
4780 gen_op_float_recip2_d();
4781 GEN_STORE_FTN_FREG(fd
, DT2
);
4785 check_cp1_64bitmode(ctx
);
4786 GEN_LOAD_FREG_FTN(DT0
, fs
);
4787 gen_op_float_recip1_d();
4788 GEN_STORE_FTN_FREG(fd
, DT2
);
4792 check_cp1_64bitmode(ctx
);
4793 GEN_LOAD_FREG_FTN(DT0
, fs
);
4794 gen_op_float_rsqrt1_d();
4795 GEN_STORE_FTN_FREG(fd
, DT2
);
4799 check_cp1_64bitmode(ctx
);
4800 GEN_LOAD_FREG_FTN(DT0
, fs
);
4801 GEN_LOAD_FREG_FTN(DT2
, ft
);
4802 gen_op_float_rsqrt2_d();
4803 GEN_STORE_FTN_FREG(fd
, DT2
);
4822 GEN_LOAD_FREG_FTN(DT0
, fs
);
4823 GEN_LOAD_FREG_FTN(DT1
, ft
);
4824 if (ctx
->opcode
& (1 << 6)) {
4825 check_cp1_64bitmode(ctx
);
4826 gen_cmpabs_d(func
-48, cc
);
4827 opn
= condnames_abs
[func
-48];
4829 check_cp1_registers(ctx
, fs
| ft
);
4830 gen_cmp_d(func
-48, cc
);
4831 opn
= condnames
[func
-48];
4835 check_cp1_registers(ctx
, fs
);
4836 GEN_LOAD_FREG_FTN(DT0
, fs
);
4837 gen_op_float_cvts_d();
4838 GEN_STORE_FTN_FREG(fd
, WT2
);
4842 check_cp1_registers(ctx
, fs
);
4843 GEN_LOAD_FREG_FTN(DT0
, fs
);
4844 gen_op_float_cvtw_d();
4845 GEN_STORE_FTN_FREG(fd
, WT2
);
4849 check_cp1_64bitmode(ctx
);
4850 GEN_LOAD_FREG_FTN(DT0
, fs
);
4851 gen_op_float_cvtl_d();
4852 GEN_STORE_FTN_FREG(fd
, DT2
);
4856 GEN_LOAD_FREG_FTN(WT0
, fs
);
4857 gen_op_float_cvts_w();
4858 GEN_STORE_FTN_FREG(fd
, WT2
);
4862 check_cp1_registers(ctx
, fd
);
4863 GEN_LOAD_FREG_FTN(WT0
, fs
);
4864 gen_op_float_cvtd_w();
4865 GEN_STORE_FTN_FREG(fd
, DT2
);
4869 check_cp1_64bitmode(ctx
);
4870 GEN_LOAD_FREG_FTN(DT0
, fs
);
4871 gen_op_float_cvts_l();
4872 GEN_STORE_FTN_FREG(fd
, WT2
);
4876 check_cp1_64bitmode(ctx
);
4877 GEN_LOAD_FREG_FTN(DT0
, fs
);
4878 gen_op_float_cvtd_l();
4879 GEN_STORE_FTN_FREG(fd
, DT2
);
4884 check_cp1_64bitmode(ctx
);
4885 GEN_LOAD_FREG_FTN(WT0
, fs
);
4886 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4887 gen_op_float_cvtps_pw();
4888 GEN_STORE_FTN_FREG(fd
, WT2
);
4889 GEN_STORE_FTN_FREG(fd
, WTH2
);
4893 check_cp1_64bitmode(ctx
);
4894 GEN_LOAD_FREG_FTN(WT0
, fs
);
4895 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4896 GEN_LOAD_FREG_FTN(WT1
, ft
);
4897 GEN_LOAD_FREG_FTN(WTH1
, ft
);
4898 gen_op_float_add_ps();
4899 GEN_STORE_FTN_FREG(fd
, WT2
);
4900 GEN_STORE_FTN_FREG(fd
, WTH2
);
4904 check_cp1_64bitmode(ctx
);
4905 GEN_LOAD_FREG_FTN(WT0
, fs
);
4906 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4907 GEN_LOAD_FREG_FTN(WT1
, ft
);
4908 GEN_LOAD_FREG_FTN(WTH1
, ft
);
4909 gen_op_float_sub_ps();
4910 GEN_STORE_FTN_FREG(fd
, WT2
);
4911 GEN_STORE_FTN_FREG(fd
, WTH2
);
4915 check_cp1_64bitmode(ctx
);
4916 GEN_LOAD_FREG_FTN(WT0
, fs
);
4917 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4918 GEN_LOAD_FREG_FTN(WT1
, ft
);
4919 GEN_LOAD_FREG_FTN(WTH1
, ft
);
4920 gen_op_float_mul_ps();
4921 GEN_STORE_FTN_FREG(fd
, WT2
);
4922 GEN_STORE_FTN_FREG(fd
, WTH2
);
4926 check_cp1_64bitmode(ctx
);
4927 GEN_LOAD_FREG_FTN(WT0
, fs
);
4928 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4929 gen_op_float_abs_ps();
4930 GEN_STORE_FTN_FREG(fd
, WT2
);
4931 GEN_STORE_FTN_FREG(fd
, WTH2
);
4935 check_cp1_64bitmode(ctx
);
4936 GEN_LOAD_FREG_FTN(WT0
, fs
);
4937 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4938 gen_op_float_mov_ps();
4939 GEN_STORE_FTN_FREG(fd
, WT2
);
4940 GEN_STORE_FTN_FREG(fd
, WTH2
);
4944 check_cp1_64bitmode(ctx
);
4945 GEN_LOAD_FREG_FTN(WT0
, fs
);
4946 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4947 gen_op_float_chs_ps();
4948 GEN_STORE_FTN_FREG(fd
, WT2
);
4949 GEN_STORE_FTN_FREG(fd
, WTH2
);
4953 check_cp1_64bitmode(ctx
);
4954 GEN_LOAD_REG_TN(T0
, ft
);
4955 GEN_LOAD_FREG_FTN(WT0
, fs
);
4956 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4957 GEN_LOAD_FREG_FTN(WT2
, fd
);
4958 GEN_LOAD_FREG_FTN(WTH2
, fd
);
4959 gen_movcf_ps(ctx
, (ft
>> 2) & 0x7, ft
& 0x1);
4960 GEN_STORE_FTN_FREG(fd
, WT2
);
4961 GEN_STORE_FTN_FREG(fd
, WTH2
);
4965 check_cp1_64bitmode(ctx
);
4966 GEN_LOAD_REG_TN(T0
, ft
);
4967 GEN_LOAD_FREG_FTN(WT0
, fs
);
4968 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4969 GEN_LOAD_FREG_FTN(WT2
, fd
);
4970 GEN_LOAD_FREG_FTN(WTH2
, fd
);
4971 gen_op_float_movz_ps();
4972 GEN_STORE_FTN_FREG(fd
, WT2
);
4973 GEN_STORE_FTN_FREG(fd
, WTH2
);
4977 check_cp1_64bitmode(ctx
);
4978 GEN_LOAD_REG_TN(T0
, ft
);
4979 GEN_LOAD_FREG_FTN(WT0
, fs
);
4980 GEN_LOAD_FREG_FTN(WTH0
, fs
);
4981 GEN_LOAD_FREG_FTN(WT2
, fd
);
4982 GEN_LOAD_FREG_FTN(WTH2
, fd
);
4983 gen_op_float_movn_ps();
4984 GEN_STORE_FTN_FREG(fd
, WT2
);
4985 GEN_STORE_FTN_FREG(fd
, WTH2
);
4989 check_cp1_64bitmode(ctx
);
4990 GEN_LOAD_FREG_FTN(WT0
, ft
);
4991 GEN_LOAD_FREG_FTN(WTH0
, ft
);
4992 GEN_LOAD_FREG_FTN(WT1
, fs
);
4993 GEN_LOAD_FREG_FTN(WTH1
, fs
);
4994 gen_op_float_addr_ps();
4995 GEN_STORE_FTN_FREG(fd
, WT2
);
4996 GEN_STORE_FTN_FREG(fd
, WTH2
);
5000 check_cp1_64bitmode(ctx
);
5001 GEN_LOAD_FREG_FTN(WT0
, ft
);
5002 GEN_LOAD_FREG_FTN(WTH0
, ft
);
5003 GEN_LOAD_FREG_FTN(WT1
, fs
);
5004 GEN_LOAD_FREG_FTN(WTH1
, fs
);
5005 gen_op_float_mulr_ps();
5006 GEN_STORE_FTN_FREG(fd
, WT2
);
5007 GEN_STORE_FTN_FREG(fd
, WTH2
);
5011 check_cp1_64bitmode(ctx
);
5012 GEN_LOAD_FREG_FTN(WT0
, fs
);
5013 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5014 GEN_LOAD_FREG_FTN(WT2
, fd
);
5015 GEN_LOAD_FREG_FTN(WTH2
, fd
);
5016 gen_op_float_recip2_ps();
5017 GEN_STORE_FTN_FREG(fd
, WT2
);
5018 GEN_STORE_FTN_FREG(fd
, WTH2
);
5022 check_cp1_64bitmode(ctx
);
5023 GEN_LOAD_FREG_FTN(WT0
, fs
);
5024 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5025 gen_op_float_recip1_ps();
5026 GEN_STORE_FTN_FREG(fd
, WT2
);
5027 GEN_STORE_FTN_FREG(fd
, WTH2
);
5031 check_cp1_64bitmode(ctx
);
5032 GEN_LOAD_FREG_FTN(WT0
, fs
);
5033 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5034 gen_op_float_rsqrt1_ps();
5035 GEN_STORE_FTN_FREG(fd
, WT2
);
5036 GEN_STORE_FTN_FREG(fd
, WTH2
);
5040 check_cp1_64bitmode(ctx
);
5041 GEN_LOAD_FREG_FTN(WT0
, fs
);
5042 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5043 GEN_LOAD_FREG_FTN(WT2
, ft
);
5044 GEN_LOAD_FREG_FTN(WTH2
, ft
);
5045 gen_op_float_rsqrt2_ps();
5046 GEN_STORE_FTN_FREG(fd
, WT2
);
5047 GEN_STORE_FTN_FREG(fd
, WTH2
);
5051 check_cp1_64bitmode(ctx
);
5052 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5053 gen_op_float_cvts_pu();
5054 GEN_STORE_FTN_FREG(fd
, WT2
);
5058 check_cp1_64bitmode(ctx
);
5059 GEN_LOAD_FREG_FTN(WT0
, fs
);
5060 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5061 gen_op_float_cvtpw_ps();
5062 GEN_STORE_FTN_FREG(fd
, WT2
);
5063 GEN_STORE_FTN_FREG(fd
, WTH2
);
5067 check_cp1_64bitmode(ctx
);
5068 GEN_LOAD_FREG_FTN(WT0
, fs
);
5069 gen_op_float_cvts_pl();
5070 GEN_STORE_FTN_FREG(fd
, WT2
);
5074 check_cp1_64bitmode(ctx
);
5075 GEN_LOAD_FREG_FTN(WT0
, fs
);
5076 GEN_LOAD_FREG_FTN(WT1
, ft
);
5077 gen_op_float_pll_ps();
5078 GEN_STORE_FTN_FREG(fd
, DT2
);
5082 check_cp1_64bitmode(ctx
);
5083 GEN_LOAD_FREG_FTN(WT0
, fs
);
5084 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5085 gen_op_float_plu_ps();
5086 GEN_STORE_FTN_FREG(fd
, DT2
);
5090 check_cp1_64bitmode(ctx
);
5091 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5092 GEN_LOAD_FREG_FTN(WT1
, ft
);
5093 gen_op_float_pul_ps();
5094 GEN_STORE_FTN_FREG(fd
, DT2
);
5098 check_cp1_64bitmode(ctx
);
5099 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5100 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5101 gen_op_float_puu_ps();
5102 GEN_STORE_FTN_FREG(fd
, DT2
);
5121 check_cp1_64bitmode(ctx
);
5122 GEN_LOAD_FREG_FTN(WT0
, fs
);
5123 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5124 GEN_LOAD_FREG_FTN(WT1
, ft
);
5125 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5126 if (ctx
->opcode
& (1 << 6)) {
5127 gen_cmpabs_ps(func
-48, cc
);
5128 opn
= condnames_abs
[func
-48];
5130 gen_cmp_ps(func
-48, cc
);
5131 opn
= condnames
[func
-48];
5136 generate_exception (ctx
, EXCP_RI
);
5141 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
5144 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
5147 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
5152 /* Coprocessor 3 (FPU) */
5153 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
5154 int fd
, int fs
, int base
, int index
)
5156 const char *opn
= "extended float load/store";
5159 /* All of those work only on 64bit FPUs. */
5160 check_cp1_64bitmode(ctx
);
5165 GEN_LOAD_REG_TN(T0
, index
);
5166 } else if (index
== 0) {
5167 GEN_LOAD_REG_TN(T0
, base
);
5169 GEN_LOAD_REG_TN(T0
, base
);
5170 GEN_LOAD_REG_TN(T1
, index
);
5173 /* Don't do NOP if destination is zero: we must perform the actual
5179 GEN_STORE_FTN_FREG(fd
, WT0
);
5184 GEN_STORE_FTN_FREG(fd
, DT0
);
5189 GEN_STORE_FTN_FREG(fd
, DT0
);
5193 GEN_LOAD_FREG_FTN(WT0
, fs
);
5199 GEN_LOAD_FREG_FTN(DT0
, fs
);
5205 GEN_LOAD_FREG_FTN(DT0
, fs
);
5212 generate_exception(ctx
, EXCP_RI
);
5215 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
5216 regnames
[index
], regnames
[base
]);
5219 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
5220 int fd
, int fr
, int fs
, int ft
)
5222 const char *opn
= "flt3_arith";
5224 /* All of those work only on 64bit FPUs. */
5225 check_cp1_64bitmode(ctx
);
5228 GEN_LOAD_REG_TN(T0
, fr
);
5229 GEN_LOAD_FREG_FTN(DT0
, fs
);
5230 GEN_LOAD_FREG_FTN(DT1
, ft
);
5231 gen_op_float_alnv_ps();
5232 GEN_STORE_FTN_FREG(fd
, DT2
);
5236 GEN_LOAD_FREG_FTN(WT0
, fs
);
5237 GEN_LOAD_FREG_FTN(WT1
, ft
);
5238 GEN_LOAD_FREG_FTN(WT2
, fr
);
5239 gen_op_float_muladd_s();
5240 GEN_STORE_FTN_FREG(fd
, WT2
);
5244 GEN_LOAD_FREG_FTN(DT0
, fs
);
5245 GEN_LOAD_FREG_FTN(DT1
, ft
);
5246 GEN_LOAD_FREG_FTN(DT2
, fr
);
5247 gen_op_float_muladd_d();
5248 GEN_STORE_FTN_FREG(fd
, DT2
);
5252 GEN_LOAD_FREG_FTN(WT0
, fs
);
5253 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5254 GEN_LOAD_FREG_FTN(WT1
, ft
);
5255 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5256 GEN_LOAD_FREG_FTN(WT2
, fr
);
5257 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5258 gen_op_float_muladd_ps();
5259 GEN_STORE_FTN_FREG(fd
, WT2
);
5260 GEN_STORE_FTN_FREG(fd
, WTH2
);
5264 GEN_LOAD_FREG_FTN(WT0
, fs
);
5265 GEN_LOAD_FREG_FTN(WT1
, ft
);
5266 GEN_LOAD_FREG_FTN(WT2
, fr
);
5267 gen_op_float_mulsub_s();
5268 GEN_STORE_FTN_FREG(fd
, WT2
);
5272 GEN_LOAD_FREG_FTN(DT0
, fs
);
5273 GEN_LOAD_FREG_FTN(DT1
, ft
);
5274 GEN_LOAD_FREG_FTN(DT2
, fr
);
5275 gen_op_float_mulsub_d();
5276 GEN_STORE_FTN_FREG(fd
, DT2
);
5280 GEN_LOAD_FREG_FTN(WT0
, fs
);
5281 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5282 GEN_LOAD_FREG_FTN(WT1
, ft
);
5283 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5284 GEN_LOAD_FREG_FTN(WT2
, fr
);
5285 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5286 gen_op_float_mulsub_ps();
5287 GEN_STORE_FTN_FREG(fd
, WT2
);
5288 GEN_STORE_FTN_FREG(fd
, WTH2
);
5292 GEN_LOAD_FREG_FTN(WT0
, fs
);
5293 GEN_LOAD_FREG_FTN(WT1
, ft
);
5294 GEN_LOAD_FREG_FTN(WT2
, fr
);
5295 gen_op_float_nmuladd_s();
5296 GEN_STORE_FTN_FREG(fd
, WT2
);
5300 GEN_LOAD_FREG_FTN(DT0
, fs
);
5301 GEN_LOAD_FREG_FTN(DT1
, ft
);
5302 GEN_LOAD_FREG_FTN(DT2
, fr
);
5303 gen_op_float_nmuladd_d();
5304 GEN_STORE_FTN_FREG(fd
, DT2
);
5308 GEN_LOAD_FREG_FTN(WT0
, fs
);
5309 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5310 GEN_LOAD_FREG_FTN(WT1
, ft
);
5311 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5312 GEN_LOAD_FREG_FTN(WT2
, fr
);
5313 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5314 gen_op_float_nmuladd_ps();
5315 GEN_STORE_FTN_FREG(fd
, WT2
);
5316 GEN_STORE_FTN_FREG(fd
, WTH2
);
5320 GEN_LOAD_FREG_FTN(WT0
, fs
);
5321 GEN_LOAD_FREG_FTN(WT1
, ft
);
5322 GEN_LOAD_FREG_FTN(WT2
, fr
);
5323 gen_op_float_nmulsub_s();
5324 GEN_STORE_FTN_FREG(fd
, WT2
);
5328 GEN_LOAD_FREG_FTN(DT0
, fs
);
5329 GEN_LOAD_FREG_FTN(DT1
, ft
);
5330 GEN_LOAD_FREG_FTN(DT2
, fr
);
5331 gen_op_float_nmulsub_d();
5332 GEN_STORE_FTN_FREG(fd
, DT2
);
5336 GEN_LOAD_FREG_FTN(WT0
, fs
);
5337 GEN_LOAD_FREG_FTN(WTH0
, fs
);
5338 GEN_LOAD_FREG_FTN(WT1
, ft
);
5339 GEN_LOAD_FREG_FTN(WTH1
, ft
);
5340 GEN_LOAD_FREG_FTN(WT2
, fr
);
5341 GEN_LOAD_FREG_FTN(WTH2
, fr
);
5342 gen_op_float_nmulsub_ps();
5343 GEN_STORE_FTN_FREG(fd
, WT2
);
5344 GEN_STORE_FTN_FREG(fd
, WTH2
);
5349 generate_exception (ctx
, EXCP_RI
);
5352 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
5353 fregnames
[fs
], fregnames
[ft
]);
5356 /* ISA extensions (ASEs) */
5357 /* MIPS16 extension to MIPS32 */
5358 /* SmartMIPS extension to MIPS32 */
5360 #ifdef TARGET_MIPS64
5362 /* MDMX extension to MIPS64 */
5363 /* MIPS-3D extension to MIPS64 */
5367 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
5371 uint32_t op
, op1
, op2
;
5374 /* make sure instructions are on a word boundary */
5375 if (ctx
->pc
& 0x3) {
5376 env
->CP0_BadVAddr
= ctx
->pc
;
5377 generate_exception(ctx
, EXCP_AdEL
);
5381 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
5383 /* Handle blikely not taken case */
5384 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
5385 l1
= gen_new_label();
5387 gen_op_save_state(ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
5388 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
5391 op
= MASK_OP_MAJOR(ctx
->opcode
);
5392 rs
= (ctx
->opcode
>> 21) & 0x1f;
5393 rt
= (ctx
->opcode
>> 16) & 0x1f;
5394 rd
= (ctx
->opcode
>> 11) & 0x1f;
5395 sa
= (ctx
->opcode
>> 6) & 0x1f;
5396 imm
= (int16_t)ctx
->opcode
;
5399 op1
= MASK_SPECIAL(ctx
->opcode
);
5401 case OPC_SLL
: /* Arithmetic with immediate */
5402 case OPC_SRL
... OPC_SRA
:
5403 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
5405 case OPC_SLLV
: /* Arithmetic */
5406 case OPC_SRLV
... OPC_SRAV
:
5407 case OPC_MOVZ
... OPC_MOVN
:
5408 case OPC_ADD
... OPC_NOR
:
5409 case OPC_SLT
... OPC_SLTU
:
5410 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5412 case OPC_MULT
... OPC_DIVU
:
5413 gen_muldiv(ctx
, op1
, rs
, rt
);
5415 case OPC_JR
... OPC_JALR
:
5416 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
5418 case OPC_TGE
... OPC_TEQ
: /* Traps */
5420 gen_trap(ctx
, op1
, rs
, rt
, -1);
5422 case OPC_MFHI
: /* Move from HI/LO */
5424 gen_HILO(ctx
, op1
, rd
);
5427 case OPC_MTLO
: /* Move to HI/LO */
5428 gen_HILO(ctx
, op1
, rs
);
5430 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
5431 #ifdef MIPS_STRICT_STANDARD
5432 MIPS_INVAL("PMON / selsl");
5433 generate_exception(ctx
, EXCP_RI
);
5439 generate_exception(ctx
, EXCP_SYSCALL
);
5442 /* XXX: Hack to work around wrong handling of self-modifying code. */
5444 save_cpu_state(ctx
, 1);
5446 generate_exception(ctx
, EXCP_BREAK
);
5449 #ifdef MIPS_STRICT_STANDARD
5451 generate_exception(ctx
, EXCP_RI
);
5453 /* Implemented as RI exception for now. */
5454 MIPS_INVAL("spim (unofficial)");
5455 generate_exception(ctx
, EXCP_RI
);
5459 /* Treat as a noop. */
5463 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
5464 save_cpu_state(ctx
, 1);
5465 check_cp1_enabled(ctx
);
5466 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
5467 (ctx
->opcode
>> 16) & 1);
5469 generate_exception_err(ctx
, EXCP_CpU
, 1);
5473 #ifdef TARGET_MIPS64
5474 /* MIPS64 specific opcodes */
5476 case OPC_DSRL
... OPC_DSRA
:
5478 case OPC_DSRL32
... OPC_DSRA32
:
5479 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5480 generate_exception(ctx
, EXCP_RI
);
5481 gen_arith_imm(ctx
, op1
, rd
, rt
, sa
);
5484 case OPC_DSRLV
... OPC_DSRAV
:
5485 case OPC_DADD
... OPC_DSUBU
:
5486 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5487 generate_exception(ctx
, EXCP_RI
);
5488 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5490 case OPC_DMULT
... OPC_DDIVU
:
5491 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5492 generate_exception(ctx
, EXCP_RI
);
5493 gen_muldiv(ctx
, op1
, rs
, rt
);
5496 default: /* Invalid */
5497 MIPS_INVAL("special");
5498 generate_exception(ctx
, EXCP_RI
);
5503 op1
= MASK_SPECIAL2(ctx
->opcode
);
5505 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
5506 case OPC_MSUB
... OPC_MSUBU
:
5507 gen_muldiv(ctx
, op1
, rs
, rt
);
5510 gen_arith(ctx
, op1
, rd
, rs
, rt
);
5512 case OPC_CLZ
... OPC_CLO
:
5513 gen_cl(ctx
, op1
, rd
, rs
);
5516 /* XXX: not clear which exception should be raised
5517 * when in debug mode...
5519 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5520 generate_exception(ctx
, EXCP_DBp
);
5522 generate_exception(ctx
, EXCP_DBp
);
5524 /* Treat as a noop */
5526 #ifdef TARGET_MIPS64
5527 case OPC_DCLZ
... OPC_DCLO
:
5528 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5529 generate_exception(ctx
, EXCP_RI
);
5530 gen_cl(ctx
, op1
, rd
, rs
);
5533 default: /* Invalid */
5534 MIPS_INVAL("special2");
5535 generate_exception(ctx
, EXCP_RI
);
5540 check_mips_r2(env
, ctx
);
5541 op1
= MASK_SPECIAL3(ctx
->opcode
);
5545 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
5548 op2
= MASK_BSHFL(ctx
->opcode
);
5551 GEN_LOAD_REG_TN(T1
, rt
);
5555 GEN_LOAD_REG_TN(T1
, rt
);
5559 GEN_LOAD_REG_TN(T1
, rt
);
5562 default: /* Invalid */
5563 MIPS_INVAL("bshfl");
5564 generate_exception(ctx
, EXCP_RI
);
5567 GEN_STORE_TN_REG(rd
, T0
);
5572 save_cpu_state(ctx
, 1);
5573 gen_op_rdhwr_cpunum();
5576 save_cpu_state(ctx
, 1);
5577 gen_op_rdhwr_synci_step();
5580 save_cpu_state(ctx
, 1);
5584 save_cpu_state(ctx
, 1);
5585 gen_op_rdhwr_ccres();
5588 #if defined (CONFIG_USER_ONLY)
5589 gen_op_tls_value ();
5592 default: /* Invalid */
5593 MIPS_INVAL("rdhwr");
5594 generate_exception(ctx
, EXCP_RI
);
5597 GEN_STORE_TN_REG(rt
, T0
);
5599 #ifdef TARGET_MIPS64
5600 case OPC_DEXTM
... OPC_DEXT
:
5601 case OPC_DINSM
... OPC_DINS
:
5602 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5603 generate_exception(ctx
, EXCP_RI
);
5604 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
5607 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5608 generate_exception(ctx
, EXCP_RI
);
5609 op2
= MASK_DBSHFL(ctx
->opcode
);
5612 GEN_LOAD_REG_TN(T1
, rt
);
5616 GEN_LOAD_REG_TN(T1
, rt
);
5619 default: /* Invalid */
5620 MIPS_INVAL("dbshfl");
5621 generate_exception(ctx
, EXCP_RI
);
5624 GEN_STORE_TN_REG(rd
, T0
);
5626 default: /* Invalid */
5627 MIPS_INVAL("special3");
5628 generate_exception(ctx
, EXCP_RI
);
5633 op1
= MASK_REGIMM(ctx
->opcode
);
5635 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
5636 case OPC_BLTZAL
... OPC_BGEZALL
:
5637 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
5639 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
5641 gen_trap(ctx
, op1
, rs
, -1, imm
);
5644 check_mips_r2(env
, ctx
);
5647 default: /* Invalid */
5648 MIPS_INVAL("regimm");
5649 generate_exception(ctx
, EXCP_RI
);
5654 save_cpu_state(ctx
, 1);
5655 gen_op_cp0_enabled();
5656 op1
= MASK_CP0(ctx
->opcode
);
5660 #ifdef TARGET_MIPS64
5664 gen_cp0(env
, ctx
, op1
, rt
, rd
);
5666 case OPC_C0_FIRST
... OPC_C0_LAST
:
5667 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
5670 check_mips_r2(env
, ctx
);
5671 op2
= MASK_MFMC0(ctx
->opcode
);
5675 /* Stop translation as we may have switched the execution mode */
5676 ctx
->bstate
= BS_STOP
;
5680 /* Stop translation as we may have switched the execution mode */
5681 ctx
->bstate
= BS_STOP
;
5683 default: /* Invalid */
5684 MIPS_INVAL("mfmc0");
5685 generate_exception(ctx
, EXCP_RI
);
5688 GEN_STORE_TN_REG(rt
, T0
);
5692 check_mips_r2(env
, ctx
);
5693 /* Shadow registers not implemented. */
5694 GEN_LOAD_REG_TN(T0
, rt
);
5695 GEN_STORE_TN_REG(rd
, T0
);
5699 generate_exception(ctx
, EXCP_RI
);
5703 case OPC_ADDI
... OPC_LUI
: /* Arithmetic with immediate opcode */
5704 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
5706 case OPC_J
... OPC_JAL
: /* Jump */
5707 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
5708 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
5710 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
5711 case OPC_BEQL
... OPC_BGTZL
:
5712 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
5714 case OPC_LB
... OPC_LWR
: /* Load and stores */
5715 case OPC_SB
... OPC_SW
:
5719 gen_ldst(ctx
, op
, rt
, rs
, imm
);
5722 /* Treat as a noop */
5725 /* Treat as a noop */
5728 /* Floating point (COP1). */
5733 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
5734 save_cpu_state(ctx
, 1);
5735 check_cp1_enabled(ctx
);
5736 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
5738 generate_exception_err(ctx
, EXCP_CpU
, 1);
5743 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
5744 save_cpu_state(ctx
, 1);
5745 check_cp1_enabled(ctx
);
5746 op1
= MASK_CP1(ctx
->opcode
);
5750 check_mips_r2(env
, ctx
);
5755 #ifdef TARGET_MIPS64
5759 gen_cp1(ctx
, op1
, rt
, rd
);
5764 gen_compute_branch1(ctx
, MASK_BC1(ctx
->opcode
),
5765 (rt
>> 2) & 0x7, imm
<< 2);
5772 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
5777 generate_exception (ctx
, EXCP_RI
);
5781 generate_exception_err(ctx
, EXCP_CpU
, 1);
5791 /* COP2: Not implemented. */
5792 generate_exception_err(ctx
, EXCP_CpU
, 2);
5796 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
5797 save_cpu_state(ctx
, 1);
5798 check_cp1_enabled(ctx
);
5799 op1
= MASK_CP3(ctx
->opcode
);
5807 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
5825 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
5829 generate_exception (ctx
, EXCP_RI
);
5833 generate_exception_err(ctx
, EXCP_CpU
, 1);
5837 #ifdef TARGET_MIPS64
5838 /* MIPS64 opcodes */
5840 case OPC_LDL
... OPC_LDR
:
5841 case OPC_SDL
... OPC_SDR
:
5846 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5847 generate_exception(ctx
, EXCP_RI
);
5848 gen_ldst(ctx
, op
, rt
, rs
, imm
);
5850 case OPC_DADDI
... OPC_DADDIU
:
5851 if (!(ctx
->hflags
& MIPS_HFLAG_64
))
5852 generate_exception(ctx
, EXCP_RI
);
5853 gen_arith_imm(ctx
, op
, rt
, rs
, imm
);
5856 #ifdef MIPS_HAS_MIPS16
5858 /* MIPS16: Not implemented. */
5860 #ifdef MIPS_HAS_MDMX
5862 /* MDMX: Not implemented. */
5864 default: /* Invalid */
5865 MIPS_INVAL("major opcode");
5866 generate_exception(ctx
, EXCP_RI
);
5869 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
5870 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
5871 /* Branches completion */
5872 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
5873 ctx
->bstate
= BS_BRANCH
;
5874 save_cpu_state(ctx
, 0);
5877 /* unconditional branch */
5878 MIPS_DEBUG("unconditional branch");
5879 gen_goto_tb(ctx
, 0, ctx
->btarget
);
5882 /* blikely taken case */
5883 MIPS_DEBUG("blikely branch taken");
5884 gen_goto_tb(ctx
, 0, ctx
->btarget
);
5887 /* Conditional branch */
5888 MIPS_DEBUG("conditional branch");
5891 l1
= gen_new_label();
5893 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
5895 gen_goto_tb(ctx
, 0, ctx
->btarget
);
5899 /* unconditional branch to register */
5900 MIPS_DEBUG("branch to register");
5906 MIPS_DEBUG("unknown branch");
5913 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
5917 target_ulong pc_start
;
5918 uint16_t *gen_opc_end
;
5921 if (search_pc
&& loglevel
)
5922 fprintf (logfile
, "search pc %d\n", search_pc
);
5925 gen_opc_ptr
= gen_opc_buf
;
5926 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
5927 gen_opparam_ptr
= gen_opparam_buf
;
5932 ctx
.bstate
= BS_NONE
;
5933 /* Restore delay slot state from the tb context. */
5934 ctx
.hflags
= tb
->flags
;
5935 restore_cpu_state(env
, &ctx
);
5936 #if defined(CONFIG_USER_ONLY)
5939 ctx
.mem_idx
= !((ctx
.hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
);
5942 if (loglevel
& CPU_LOG_TB_CPU
) {
5943 fprintf(logfile
, "------------------------------------------------\n");
5944 /* FIXME: This may print out stale hflags from env... */
5945 cpu_dump_state(env
, logfile
, fprintf
, 0);
5948 #ifdef MIPS_DEBUG_DISAS
5949 if (loglevel
& CPU_LOG_TB_IN_ASM
)
5950 fprintf(logfile
, "\ntb %p super %d cond %04x\n",
5951 tb
, ctx
.mem_idx
, ctx
.hflags
);
5953 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
5954 if (env
->nb_breakpoints
> 0) {
5955 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
5956 if (env
->breakpoints
[j
] == ctx
.pc
) {
5957 save_cpu_state(&ctx
, 1);
5958 ctx
.bstate
= BS_BRANCH
;
5960 goto done_generating
;
5966 j
= gen_opc_ptr
- gen_opc_buf
;
5970 gen_opc_instr_start
[lj
++] = 0;
5972 gen_opc_pc
[lj
] = ctx
.pc
;
5973 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
5974 gen_opc_instr_start
[lj
] = 1;
5976 ctx
.opcode
= ldl_code(ctx
.pc
);
5977 decode_opc(env
, &ctx
);
5980 if (env
->singlestep_enabled
)
5983 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
5986 #if defined (MIPS_SINGLE_STEP)
5990 if (env
->singlestep_enabled
) {
5991 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
5994 switch (ctx
.bstate
) {
5996 gen_op_interrupt_restart();
5997 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6000 save_cpu_state(&ctx
, 0);
6001 gen_goto_tb(&ctx
, 0, ctx
.pc
);
6004 gen_op_interrupt_restart();
6014 *gen_opc_ptr
= INDEX_op_end
;
6016 j
= gen_opc_ptr
- gen_opc_buf
;
6019 gen_opc_instr_start
[lj
++] = 0;
6022 tb
->size
= ctx
.pc
- pc_start
;
6025 #if defined MIPS_DEBUG_DISAS
6026 if (loglevel
& CPU_LOG_TB_IN_ASM
)
6027 fprintf(logfile
, "\n");
6029 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
6030 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
6031 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 0);
6032 fprintf(logfile
, "\n");
6034 if (loglevel
& CPU_LOG_TB_OP
) {
6035 fprintf(logfile
, "OP:\n");
6036 dump_ops(gen_opc_buf
, gen_opparam_buf
);
6037 fprintf(logfile
, "\n");
6039 if (loglevel
& CPU_LOG_TB_CPU
) {
6040 fprintf(logfile
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
6047 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
6049 return gen_intermediate_code_internal(env
, tb
, 0);
6052 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
6054 return gen_intermediate_code_internal(env
, tb
, 1);
6057 void fpu_dump_state(CPUState
*env
, FILE *f
,
6058 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6062 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
6064 #define printfpr(fp) \
6067 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
6068 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
6069 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
6072 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
6073 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
6074 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
6075 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
6076 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
6081 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
6082 env
->fcr0
, env
->fcr31
, is_fpu64
, env
->fp_status
, get_float_exception_flags(&env
->fp_status
));
6083 fpu_fprintf(f
, "FT0: "); printfpr(&env
->ft0
);
6084 fpu_fprintf(f
, "FT1: "); printfpr(&env
->ft1
);
6085 fpu_fprintf(f
, "FT2: "); printfpr(&env
->ft2
);
6086 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
6087 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
6088 printfpr(&env
->fpr
[i
]);
6094 void dump_fpu (CPUState
*env
)
6097 fprintf(logfile
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6098 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
6099 fpu_dump_state(env
, logfile
, fprintf
, 0);
6103 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6104 /* Debug help: The architecture requires 32bit code to maintain proper
6105 sign-extened values on 64bit machines. */
6107 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
6109 void cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
6110 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6115 if (!SIGN_EXT_P(env
->PC
))
6116 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->PC
);
6117 if (!SIGN_EXT_P(env
->HI
))
6118 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->HI
);
6119 if (!SIGN_EXT_P(env
->LO
))
6120 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->LO
);
6121 if (!SIGN_EXT_P(env
->btarget
))
6122 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
6124 for (i
= 0; i
< 32; i
++) {
6125 if (!SIGN_EXT_P(env
->gpr
[i
]))
6126 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->gpr
[i
]);
6129 if (!SIGN_EXT_P(env
->CP0_EPC
))
6130 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
6131 if (!SIGN_EXT_P(env
->CP0_LLAddr
))
6132 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->CP0_LLAddr
);
6136 void cpu_dump_state (CPUState
*env
, FILE *f
,
6137 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
6142 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
6143 env
->PC
, env
->HI
, env
->LO
, env
->hflags
, env
->btarget
, env
->bcond
);
6144 for (i
= 0; i
< 32; i
++) {
6146 cpu_fprintf(f
, "GPR%02d:", i
);
6147 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->gpr
[i
]);
6149 cpu_fprintf(f
, "\n");
6152 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
6153 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
6154 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
6155 env
->CP0_Config0
, env
->CP0_Config1
, env
->CP0_LLAddr
);
6156 if (env
->hflags
& MIPS_HFLAG_FPU
)
6157 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
6158 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
6159 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
6163 CPUMIPSState
*cpu_mips_init (void)
6167 env
= qemu_mallocz(sizeof(CPUMIPSState
));
6175 void cpu_reset (CPUMIPSState
*env
)
6177 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
6182 #if !defined(CONFIG_USER_ONLY)
6183 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
6184 /* If the exception was raised from a delay slot,
6185 * come back to the jump. */
6186 env
->CP0_ErrorEPC
= env
->PC
- 4;
6188 env
->CP0_ErrorEPC
= env
->PC
;
6191 env
->PC
= (int32_t)0xBFC00000;
6193 /* SMP not implemented */
6194 env
->CP0_EBase
= 0x80000000;
6195 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
6196 /* vectored interrupts not implemented, timer on int 7,
6197 no performance counters. */
6198 env
->CP0_IntCtl
= 0xe0000000;
6202 for (i
= 0; i
< 7; i
++) {
6203 env
->CP0_WatchLo
[i
] = 0;
6204 env
->CP0_WatchHi
[i
] = 0x80000000;
6206 env
->CP0_WatchLo
[7] = 0;
6207 env
->CP0_WatchHi
[7] = 0;
6209 /* Count register increments in debug mode, EJTAG version 1 */
6210 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
6212 env
->exception_index
= EXCP_NONE
;
6213 #if defined(CONFIG_USER_ONLY)
6214 env
->hflags
|= MIPS_HFLAG_UM
;
6215 env
->user_mode_only
= 1;
6219 #include "translate_init.c"