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Replace tabs by 8 spaces. No code change, by Herve Poussineau.
[qemu/dscho.git] / target-ppc / helper.c
blob84e6c39357021bd5a596cc74d24abe6fd98c518a
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30
31 //#define DEBUG_MMU
32 //#define DEBUG_BATS
33 //#define DEBUG_SOFTWARE_TLB
34 //#define DEBUG_EXCEPTIONS
35 //#define FLUSH_ALL_TLBS
36
37 /*****************************************************************************/
38 /* PowerPC MMU emulation */
39
40 #if defined(CONFIG_USER_ONLY)
41 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42 int is_user, int is_softmmu)
43 {
44 int exception, error_code;
45
46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
59
60 return 1;
61 }
62
63 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64 {
65 return addr;
66 }
67 #else
68 /* Common routines used by software and hardware TLBs emulation */
69 static inline int pte_is_valid (target_ulong pte0)
70 {
71 return pte0 & 0x80000000 ? 1 : 0;
72 }
73
74 static inline void pte_invalidate (target_ulong *pte0)
75 {
76 *pte0 &= ~0x80000000;
77 }
78
79 #define PTE_PTEM_MASK 0x7FFFFFBF
80 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82 static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84 {
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126 #if defined (DEBUG_MMU)
127 if (loglevel != 0)
128 fprintf(logfile, "PTE access granted !\n");
129 #endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133 #if defined (DEBUG_MMU)
134 if (loglevel != 0)
135 fprintf(logfile, "PTE access rejected\n");
136 #endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143 }
144
145 static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147 {
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168 }
169
170 /* Software driven TLB helpers */
171 static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173 {
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185 }
186
187 void ppc6xx_tlb_invalidate_all (CPUState *env)
188 {
189 ppc6xx_tlb_t *tlb;
190 int nr, max;
191
192 #if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196 #endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
202 tlb = &env->tlb[nr].tlb6;
203 #if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205 #endif
206 pte_invalidate(&tlb->pte0);
207 }
208 #if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210 #endif
211 }
212
213 static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216 {
217 #if !defined(FLUSH_ALL_TLBS)
218 ppc6xx_tlb_t *tlb;
219 int way, nr;
220
221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
224 tlb = &env->tlb[nr].tlb6;
225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226 #if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
229 nr, env->nb_tlb, eaddr);
230 }
231 #endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236 #else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239 #endif
240 }
241
242 void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244 {
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246 }
247
248 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250 {
251 ppc6xx_tlb_t *tlb;
252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
255 tlb = &env->tlb[nr].tlb6;
256 #if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
260 }
261 #endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
267 /* Store last way for LRU mechanism */
268 env->last_way = way;
269 }
270
271 static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
272 target_ulong eaddr, int rw, int access_type)
273 {
274 ppc6xx_tlb_t *tlb;
275 int nr, best, way;
276 int ret;
277
278 best = -1;
279 ret = -1; /* No TLB found */
280 for (way = 0; way < env->nb_ways; way++) {
281 nr = ppc6xx_tlb_getnum(env, eaddr, way,
282 access_type == ACCESS_CODE ? 1 : 0);
283 tlb = &env->tlb[nr].tlb6;
284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
286 #if defined (DEBUG_SOFTWARE_TLB)
287 if (loglevel != 0) {
288 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
289 "] <> " ADDRX "\n",
290 nr, env->nb_tlb,
291 pte_is_valid(tlb->pte0) ? "valid" : "inval",
292 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
293 }
294 #endif
295 continue;
296 }
297 #if defined (DEBUG_SOFTWARE_TLB)
298 if (loglevel != 0) {
299 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
300 " %c %c\n",
301 nr, env->nb_tlb,
302 pte_is_valid(tlb->pte0) ? "valid" : "inval",
303 tlb->EPN, eaddr, tlb->pte1,
304 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
305 }
306 #endif
307 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
308 case -3:
309 /* TLB inconsistency */
310 return -1;
311 case -2:
312 /* Access violation */
313 ret = -2;
314 best = nr;
315 break;
316 case -1:
317 default:
318 /* No match */
319 break;
320 case 0:
321 /* access granted */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
325 */
326 ret = 0;
327 best = nr;
328 goto done;
329 }
330 }
331 if (best != -1) {
332 done:
333 #if defined (DEBUG_SOFTWARE_TLB)
334 if (loglevel != 0) {
335 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
337 }
338 #endif
339 /* Update page flags */
340 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
341 }
342
343 return ret;
344 }
345
346 /* Perform BAT hit & translation */
347 static int get_bat (CPUState *env, mmu_ctx_t *ctx,
348 target_ulong virtual, int rw, int type)
349 {
350 target_ulong *BATlt, *BATut, *BATu, *BATl;
351 target_ulong base, BEPIl, BEPIu, bl;
352 int i;
353 int ret = -1;
354
355 #if defined (DEBUG_BATS)
356 if (loglevel != 0) {
357 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
358 type == ACCESS_CODE ? 'I' : 'D', virtual);
359 }
360 #endif
361 switch (type) {
362 case ACCESS_CODE:
363 BATlt = env->IBAT[1];
364 BATut = env->IBAT[0];
365 break;
366 default:
367 BATlt = env->DBAT[1];
368 BATut = env->DBAT[0];
369 break;
370 }
371 #if defined (DEBUG_BATS)
372 if (loglevel != 0) {
373 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
374 type == ACCESS_CODE ? 'I' : 'D', virtual);
375 }
376 #endif
377 base = virtual & 0xFFFC0000;
378 for (i = 0; i < 4; i++) {
379 BATu = &BATut[i];
380 BATl = &BATlt[i];
381 BEPIu = *BATu & 0xF0000000;
382 BEPIl = *BATu & 0x0FFE0000;
383 bl = (*BATu & 0x00001FFC) << 15;
384 #if defined (DEBUG_BATS)
385 if (loglevel != 0) {
386 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
387 " BATl 0x" ADDRX "\n",
388 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
389 *BATu, *BATl);
390 }
391 #endif
392 if ((virtual & 0xF0000000) == BEPIu &&
393 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
394 /* BAT matches */
395 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
396 (msr_pr == 1 && (*BATu & 0x00000001))) {
397 /* Get physical address */
398 ctx->raddr = (*BATl & 0xF0000000) |
399 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
400 (virtual & 0x0001F000);
401 if (*BATl & 0x00000001)
402 ctx->prot = PAGE_READ;
403 if (*BATl & 0x00000002)
404 ctx->prot = PAGE_WRITE | PAGE_READ;
405 #if defined (DEBUG_BATS)
406 if (loglevel != 0) {
407 fprintf(logfile, "BAT %d match: r 0x" PADDRX
408 " prot=%c%c\n",
409 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
410 ctx->prot & PAGE_WRITE ? 'W' : '-');
411 }
412 #endif
413 ret = 0;
414 break;
415 }
416 }
417 }
418 if (ret < 0) {
419 #if defined (DEBUG_BATS)
420 if (loglevel != 0) {
421 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
422 for (i = 0; i < 4; i++) {
423 BATu = &BATut[i];
424 BATl = &BATlt[i];
425 BEPIu = *BATu & 0xF0000000;
426 BEPIl = *BATu & 0x0FFE0000;
427 bl = (*BATu & 0x00001FFC) << 15;
428 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
429 " BATl 0x" ADDRX " \n\t"
430 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
431 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
432 *BATu, *BATl, BEPIu, BEPIl, bl);
433 }
434 }
435 #endif
436 }
437 /* No hit */
438 return ret;
439 }
440
441 /* PTE table lookup */
442 static int find_pte (mmu_ctx_t *ctx, int h, int rw)
443 {
444 target_ulong base, pte0, pte1;
445 int i, good = -1;
446 int ret;
447
448 ret = -1; /* No entry found */
449 base = ctx->pg_addr[h];
450 for (i = 0; i < 8; i++) {
451 pte0 = ldl_phys(base + (i * 8));
452 pte1 = ldl_phys(base + (i * 8) + 4);
453 #if defined (DEBUG_MMU)
454 if (loglevel > 0) {
455 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
456 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
457 base + (i * 8), pte0, pte1,
458 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
459 }
460 #endif
461 switch (pte_check(ctx, pte0, pte1, h, rw)) {
462 case -3:
463 /* PTE inconsistency */
464 return -1;
465 case -2:
466 /* Access violation */
467 ret = -2;
468 good = i;
469 break;
470 case -1:
471 default:
472 /* No PTE match */
473 break;
474 case 0:
475 /* access granted */
476 /* XXX: we should go on looping to check all PTEs consistency
477 * but if we can speed-up the whole thing as the
478 * result would be undefined if PTEs are not consistent.
479 */
480 ret = 0;
481 good = i;
482 goto done;
483 }
484 }
485 if (good != -1) {
486 done:
487 #if defined (DEBUG_MMU)
488 if (loglevel != 0) {
489 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
490 "ret=%d\n",
491 ctx->raddr, ctx->prot, ret);
492 }
493 #endif
494 /* Update page flags */
495 pte1 = ctx->raddr;
496 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
497 stl_phys_notdirty(base + (good * 8) + 4, pte1);
498 }
499
500 return ret;
501 }
502
503 static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
504 target_phys_addr_t hash,
505 target_phys_addr_t mask)
506 {
507 return (sdr1 & 0xFFFF0000) | (hash & mask);
508 }
509
510 /* Perform segment based translation */
511 static int get_segment (CPUState *env, mmu_ctx_t *ctx,
512 target_ulong eaddr, int rw, int type)
513 {
514 target_phys_addr_t sdr, hash, mask;
515 target_ulong sr, vsid, pgidx;
516 int ret = -1, ret2;
517
518 sr = env->sr[eaddr >> 28];
519 #if defined (DEBUG_MMU)
520 if (loglevel > 0) {
521 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
522 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
523 eaddr, eaddr >> 28, sr, env->nip,
524 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
525 }
526 #endif
527 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
528 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
529 if ((sr & 0x80000000) == 0) {
530 #if defined (DEBUG_MMU)
531 if (loglevel > 0)
532 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
533 ctx->key, sr & 0x10000000);
534 #endif
535 /* Check if instruction fetch is allowed, if needed */
536 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
537 /* Page address translation */
538 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
539 vsid = sr & 0x00FFFFFF;
540 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
541 /* Primary table address */
542 sdr = env->sdr1;
543 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
544 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
545 /* Secondary table address */
546 hash = (~hash) & 0x01FFFFC0;
547 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
548 ctx->ptem = (vsid << 7) | (pgidx >> 10);
549 /* Initialize real address with an invalid value */
550 ctx->raddr = (target_ulong)-1;
551 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
552 /* Software TLB search */
553 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
554 } else {
555 #if defined (DEBUG_MMU)
556 if (loglevel != 0) {
557 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
558 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
559 sdr, (uint32_t)vsid, (uint32_t)pgidx,
560 (uint32_t)hash, ctx->pg_addr[0]);
561 }
562 #endif
563 /* Primary table lookup */
564 ret = find_pte(ctx, 0, rw);
565 if (ret < 0) {
566 /* Secondary table lookup */
567 #if defined (DEBUG_MMU)
568 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
569 fprintf(logfile,
570 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
571 "hash=0x%05x pg_addr=0x" PADDRX "\n",
572 sdr, (uint32_t)vsid, (uint32_t)pgidx,
573 (uint32_t)hash, ctx->pg_addr[1]);
574 }
575 #endif
576 ret2 = find_pte(ctx, 1, rw);
577 if (ret2 != -1)
578 ret = ret2;
579 }
580 }
581 } else {
582 #if defined (DEBUG_MMU)
583 if (loglevel != 0)
584 fprintf(logfile, "No access allowed\n");
585 #endif
586 ret = -3;
587 }
588 } else {
589 #if defined (DEBUG_MMU)
590 if (loglevel != 0)
591 fprintf(logfile, "direct store...\n");
592 #endif
593 /* Direct-store segment : absolutely *BUGGY* for now */
594 switch (type) {
595 case ACCESS_INT:
596 /* Integer load/store : only access allowed */
597 break;
598 case ACCESS_CODE:
599 /* No code fetch is allowed in direct-store areas */
600 return -4;
601 case ACCESS_FLOAT:
602 /* Floating point load/store */
603 return -4;
604 case ACCESS_RES:
605 /* lwarx, ldarx or srwcx. */
606 return -4;
607 case ACCESS_CACHE:
608 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
609 /* Should make the instruction do no-op.
610 * As it already do no-op, it's quite easy :-)
611 */
612 ctx->raddr = eaddr;
613 return 0;
614 case ACCESS_EXT:
615 /* eciwx or ecowx */
616 return -4;
617 default:
618 if (logfile) {
619 fprintf(logfile, "ERROR: instruction should not need "
620 "address translation\n");
621 }
622 return -4;
623 }
624 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
625 ctx->raddr = eaddr;
626 ret = 2;
627 } else {
628 ret = -2;
629 }
630 }
631
632 return ret;
633 }
634
635 /* Generic TLB check function for embedded PowerPC implementations */
636 static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
637 target_phys_addr_t *raddrp,
638 target_ulong address, int i)
639 {
640 target_ulong mask;
641
642 /* Check valid flag */
643 if (!(tlb->prot & PAGE_VALID)) {
644 if (loglevel != 0)
645 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
646 return -1;
647 }
648 mask = ~(tlb->size - 1);
649 if (loglevel != 0) {
650 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
651 ADDRX " " ADDRX " %d\n",
652 __func__, i, address, (int)env->spr[SPR_40x_PID],
653 tlb->EPN, mask, (int)tlb->PID);
654 }
655 /* Check PID */
656 if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
657 return -1;
658 /* Check effective address */
659 if ((address & mask) != tlb->EPN)
660 return -1;
661 *raddrp = (tlb->RPN & mask) | (address & ~mask);
662
663 return 0;
664 }
665
666 /* Generic TLB search function for PowerPC embedded implementations */
667 int ppcemb_tlb_search (CPUState *env, target_ulong address)
668 {
669 ppcemb_tlb_t *tlb;
670 target_phys_addr_t raddr;
671 int i, ret;
672
673 /* Default return value is no match */
674 ret = -1;
675 for (i = 0; i < 64; i++) {
676 tlb = &env->tlb[i].tlbe;
677 if (ppcemb_tlb_check(env, tlb, &raddr, address, i) == 0) {
678 ret = i;
679 break;
680 }
681 }
682
683 return ret;
684 }
685
686 /* Helpers specific to PowerPC 40x implementations */
687 void ppc4xx_tlb_invalidate_all (CPUState *env)
688 {
689 ppcemb_tlb_t *tlb;
690 int i;
691
692 for (i = 0; i < env->nb_tlb; i++) {
693 tlb = &env->tlb[i].tlbe;
694 if (tlb->prot & PAGE_VALID) {
695 #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
696 end = tlb->EPN + tlb->size;
697 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
698 tlb_flush_page(env, page);
699 #endif
700 tlb->prot &= ~PAGE_VALID;
701 }
702 }
703 tlb_flush(env, 1);
704 }
705
706 int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
707 target_ulong address, int rw, int access_type)
708 {
709 ppcemb_tlb_t *tlb;
710 target_phys_addr_t raddr;
711 int i, ret, zsel, zpr;
712
713 ret = -1;
714 raddr = -1;
715 for (i = 0; i < env->nb_tlb; i++) {
716 tlb = &env->tlb[i].tlbe;
717 if (ppcemb_tlb_check(env, tlb, &raddr, address, i) < 0)
718 continue;
719 zsel = (tlb->attr >> 4) & 0xF;
720 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
721 if (loglevel != 0) {
722 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
723 __func__, i, zsel, zpr, rw, tlb->attr);
724 }
725 if (access_type == ACCESS_CODE) {
726 /* Check execute enable bit */
727 switch (zpr) {
728 case 0x2:
729 if (msr_pr)
730 goto check_exec_perm;
731 goto exec_granted;
732 case 0x0:
733 if (msr_pr) {
734 ctx->prot = 0;
735 ret = -3;
736 break;
737 }
738 /* No break here */
739 case 0x1:
740 check_exec_perm:
741 /* Check from TLB entry */
742 if (!(tlb->prot & PAGE_EXEC)) {
743 ret = -3;
744 } else {
745 if (tlb->prot & PAGE_WRITE) {
746 ctx->prot = PAGE_READ | PAGE_WRITE;
747 } else {
748 ctx->prot = PAGE_READ;
749 }
750 ret = 0;
751 }
752 break;
753 case 0x3:
754 exec_granted:
755 /* All accesses granted */
756 ctx->prot = PAGE_READ | PAGE_WRITE;
757 ret = 0;
758 break;
759 }
760 } else {
761 switch (zpr) {
762 case 0x2:
763 if (msr_pr)
764 goto check_rw_perm;
765 goto rw_granted;
766 case 0x0:
767 if (msr_pr) {
768 ctx->prot = 0;
769 ret = -2;
770 break;
771 }
772 /* No break here */
773 case 0x1:
774 check_rw_perm:
775 /* Check from TLB entry */
776 /* Check write protection bit */
777 if (tlb->prot & PAGE_WRITE) {
778 ctx->prot = PAGE_READ | PAGE_WRITE;
779 ret = 0;
780 } else {
781 ctx->prot = PAGE_READ;
782 if (rw)
783 ret = -2;
784 else
785 ret = 0;
786 }
787 break;
788 case 0x3:
789 rw_granted:
790 /* All accesses granted */
791 ctx->prot = PAGE_READ | PAGE_WRITE;
792 ret = 0;
793 break;
794 }
795 }
796 if (ret >= 0) {
797 ctx->raddr = raddr;
798 if (loglevel != 0) {
799 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
800 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
801 ret);
802 }
803 return 0;
804 }
805 }
806 if (loglevel != 0) {
807 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
808 " %d %d\n", __func__, address, raddr, ctx->prot,
809 ret);
810 }
811
812 return ret;
813 }
814
815 void store_40x_sler (CPUPPCState *env, uint32_t val)
816 {
817 /* XXX: TO BE FIXED */
818 if (val != 0x00000000) {
819 cpu_abort(env, "Little-endian regions are not supported by now\n");
820 }
821 env->spr[SPR_405_SLER] = val;
822 }
823
824 static int check_physical (CPUState *env, mmu_ctx_t *ctx,
825 target_ulong eaddr, int rw)
826 {
827 int in_plb, ret;
828
829 ctx->raddr = eaddr;
830 ctx->prot = PAGE_READ;
831 ret = 0;
832 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
833 /* 403 family add some particular protections,
834 * using PBL/PBU registers for accesses with no translation.
835 */
836 in_plb =
837 /* Check PLB validity */
838 (env->pb[0] < env->pb[1] &&
839 /* and address in plb area */
840 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
841 (env->pb[2] < env->pb[3] &&
842 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
843 if (in_plb ^ msr_px) {
844 /* Access in protected area */
845 if (rw == 1) {
846 /* Access is not allowed */
847 ret = -2;
848 }
849 } else {
850 /* Read-write access is allowed */
851 ctx->prot |= PAGE_WRITE;
852 }
853 } else {
854 ctx->prot |= PAGE_WRITE;
855 }
856
857 return ret;
858 }
859
860 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
861 int rw, int access_type, int check_BATs)
862 {
863 int ret;
864 #if 0
865 if (loglevel != 0) {
866 fprintf(logfile, "%s\n", __func__);
867 }
868 #endif
869 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
870 (access_type != ACCESS_CODE && msr_dr == 0)) {
871 /* No address translation */
872 ret = check_physical(env, ctx, eaddr, rw);
873 } else {
874 ret = -1;
875 switch (PPC_MMU(env)) {
876 case PPC_FLAGS_MMU_32B:
877 case PPC_FLAGS_MMU_SOFT_6xx:
878 /* Try to find a BAT */
879 if (check_BATs)
880 ret = get_bat(env, ctx, eaddr, rw, access_type);
881 /* No break here */
882 #if defined(TARGET_PPC64)
883 case PPC_FLAGS_MMU_64B:
884 case PPC_FLAGS_MMU_64BRIDGE:
885 #endif
886 if (ret < 0) {
887 /* We didn't match any BAT entry or don't have BATs */
888 ret = get_segment(env, ctx, eaddr, rw, access_type);
889 }
890 break;
891 case PPC_FLAGS_MMU_SOFT_4xx:
892 case PPC_FLAGS_MMU_403:
893 ret = mmu4xx_get_physical_address(env, ctx, eaddr,
894 rw, access_type);
895 break;
896 case PPC_FLAGS_MMU_601:
897 /* XXX: TODO */
898 cpu_abort(env, "601 MMU model not implemented\n");
899 return -1;
900 case PPC_FLAGS_MMU_BOOKE:
901 /* XXX: TODO */
902 cpu_abort(env, "BookeE MMU model not implemented\n");
903 return -1;
904 case PPC_FLAGS_MMU_BOOKE_FSL:
905 /* XXX: TODO */
906 cpu_abort(env, "BookE FSL MMU model not implemented\n");
907 return -1;
908 default:
909 cpu_abort(env, "Unknown or invalid MMU model\n");
910 return -1;
911 }
912 }
913 #if 0
914 if (loglevel != 0) {
915 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
916 __func__, eaddr, ret, ctx->raddr);
917 }
918 #endif
919
920 return ret;
921 }
922
923 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
924 {
925 mmu_ctx_t ctx;
926
927 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
928 return -1;
929
930 return ctx.raddr & TARGET_PAGE_MASK;
931 }
932
933 /* Perform address translation */
934 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
935 int is_user, int is_softmmu)
936 {
937 mmu_ctx_t ctx;
938 int exception = 0, error_code = 0;
939 int access_type;
940 int ret = 0;
941
942 if (rw == 2) {
943 /* code access */
944 rw = 0;
945 access_type = ACCESS_CODE;
946 } else {
947 /* data access */
948 /* XXX: put correct access by using cpu_restore_state()
949 correctly */
950 access_type = ACCESS_INT;
951 // access_type = env->access_type;
952 }
953 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
954 if (ret == 0) {
955 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
956 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
957 is_user, is_softmmu);
958 } else if (ret < 0) {
959 #if defined (DEBUG_MMU)
960 if (loglevel != 0)
961 cpu_dump_state(env, logfile, fprintf, 0);
962 #endif
963 if (access_type == ACCESS_CODE) {
964 exception = EXCP_ISI;
965 switch (ret) {
966 case -1:
967 /* No matches in page tables or TLB */
968 switch (PPC_MMU(env)) {
969 case PPC_FLAGS_MMU_SOFT_6xx:
970 exception = EXCP_I_TLBMISS;
971 env->spr[SPR_IMISS] = address;
972 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
973 error_code = 1 << 18;
974 goto tlb_miss;
975 case PPC_FLAGS_MMU_SOFT_4xx:
976 case PPC_FLAGS_MMU_403:
977 exception = EXCP_40x_ITLBMISS;
978 error_code = 0;
979 env->spr[SPR_40x_DEAR] = address;
980 env->spr[SPR_40x_ESR] = 0x00000000;
981 break;
982 case PPC_FLAGS_MMU_32B:
983 error_code = 0x40000000;
984 break;
985 #if defined(TARGET_PPC64)
986 case PPC_FLAGS_MMU_64B:
987 /* XXX: TODO */
988 cpu_abort(env, "MMU model not implemented\n");
989 return -1;
990 case PPC_FLAGS_MMU_64BRIDGE:
991 /* XXX: TODO */
992 cpu_abort(env, "MMU model not implemented\n");
993 return -1;
994 #endif
995 case PPC_FLAGS_MMU_601:
996 /* XXX: TODO */
997 cpu_abort(env, "MMU model not implemented\n");
998 return -1;
999 case PPC_FLAGS_MMU_BOOKE:
1000 /* XXX: TODO */
1001 cpu_abort(env, "MMU model not implemented\n");
1002 return -1;
1003 case PPC_FLAGS_MMU_BOOKE_FSL:
1004 /* XXX: TODO */
1005 cpu_abort(env, "MMU model not implemented\n");
1006 return -1;
1007 default:
1008 cpu_abort(env, "Unknown or invalid MMU model\n");
1009 return -1;
1010 }
1011 break;
1012 case -2:
1013 /* Access rights violation */
1014 error_code = 0x08000000;
1015 break;
1016 case -3:
1017 /* No execute protection violation */
1018 error_code = 0x10000000;
1019 break;
1020 case -4:
1021 /* Direct store exception */
1022 /* No code fetch is allowed in direct-store areas */
1023 error_code = 0x10000000;
1024 break;
1025 case -5:
1026 /* No match in segment table */
1027 exception = EXCP_ISEG;
1028 error_code = 0;
1029 break;
1030 }
1031 } else {
1032 exception = EXCP_DSI;
1033 switch (ret) {
1034 case -1:
1035 /* No matches in page tables or TLB */
1036 switch (PPC_MMU(env)) {
1037 case PPC_FLAGS_MMU_SOFT_6xx:
1038 if (rw == 1) {
1039 exception = EXCP_DS_TLBMISS;
1040 error_code = 1 << 16;
1041 } else {
1042 exception = EXCP_DL_TLBMISS;
1043 error_code = 0;
1044 }
1045 env->spr[SPR_DMISS] = address;
1046 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1047 tlb_miss:
1048 error_code |= ctx.key << 19;
1049 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1050 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1051 /* Do not alter DAR nor DSISR */
1052 goto out;
1053 case PPC_FLAGS_MMU_SOFT_4xx:
1054 case PPC_FLAGS_MMU_403:
1055 exception = EXCP_40x_DTLBMISS;
1056 error_code = 0;
1057 env->spr[SPR_40x_DEAR] = address;
1058 if (rw)
1059 env->spr[SPR_40x_ESR] = 0x00800000;
1060 else
1061 env->spr[SPR_40x_ESR] = 0x00000000;
1062 break;
1063 case PPC_FLAGS_MMU_32B:
1064 error_code = 0x40000000;
1065 break;
1066 #if defined(TARGET_PPC64)
1067 case PPC_FLAGS_MMU_64B:
1068 /* XXX: TODO */
1069 cpu_abort(env, "MMU model not implemented\n");
1070 return -1;
1071 case PPC_FLAGS_MMU_64BRIDGE:
1072 /* XXX: TODO */
1073 cpu_abort(env, "MMU model not implemented\n");
1074 return -1;
1075 #endif
1076 case PPC_FLAGS_MMU_601:
1077 /* XXX: TODO */
1078 cpu_abort(env, "MMU model not implemented\n");
1079 return -1;
1080 case PPC_FLAGS_MMU_BOOKE:
1081 /* XXX: TODO */
1082 cpu_abort(env, "MMU model not implemented\n");
1083 return -1;
1084 case PPC_FLAGS_MMU_BOOKE_FSL:
1085 /* XXX: TODO */
1086 cpu_abort(env, "MMU model not implemented\n");
1087 return -1;
1088 default:
1089 cpu_abort(env, "Unknown or invalid MMU model\n");
1090 return -1;
1091 }
1092 break;
1093 case -2:
1094 /* Access rights violation */
1095 error_code = 0x08000000;
1096 break;
1097 case -4:
1098 /* Direct store exception */
1099 switch (access_type) {
1100 case ACCESS_FLOAT:
1101 /* Floating point load/store */
1102 exception = EXCP_ALIGN;
1103 error_code = EXCP_ALIGN_FP;
1104 break;
1105 case ACCESS_RES:
1106 /* lwarx, ldarx or srwcx. */
1107 error_code = 0x04000000;
1108 break;
1109 case ACCESS_EXT:
1110 /* eciwx or ecowx */
1111 error_code = 0x04100000;
1112 break;
1113 default:
1114 printf("DSI: invalid exception (%d)\n", ret);
1115 exception = EXCP_PROGRAM;
1116 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
1117 break;
1118 }
1119 break;
1120 case -5:
1121 /* No match in segment table */
1122 exception = EXCP_DSEG;
1123 error_code = 0;
1124 break;
1125 }
1126 if (exception == EXCP_DSI && rw == 1)
1127 error_code |= 0x02000000;
1128 /* Store fault address */
1129 env->spr[SPR_DAR] = address;
1130 env->spr[SPR_DSISR] = error_code;
1131 }
1132 out:
1133 #if 0
1134 printf("%s: set exception to %d %02x\n",
1135 __func__, exception, error_code);
1136 #endif
1137 env->exception_index = exception;
1138 env->error_code = error_code;
1139 ret = 1;
1140 }
1141
1142 return ret;
1143 }
1144
1145 /*****************************************************************************/
1146 /* BATs management */
1147 #if !defined(FLUSH_ALL_TLBS)
1148 static inline void do_invalidate_BAT (CPUPPCState *env,
1149 target_ulong BATu, target_ulong mask)
1150 {
1151 target_ulong base, end, page;
1152
1153 base = BATu & ~0x0001FFFF;
1154 end = base + mask + 0x00020000;
1155 #if defined (DEBUG_BATS)
1156 if (loglevel != 0) {
1157 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1158 base, end, mask);
1159 }
1160 #endif
1161 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1162 tlb_flush_page(env, page);
1163 #if defined (DEBUG_BATS)
1164 if (loglevel != 0)
1165 fprintf(logfile, "Flush done\n");
1166 #endif
1167 }
1168 #endif
1169
1170 static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1171 target_ulong value)
1172 {
1173 #if defined (DEBUG_BATS)
1174 if (loglevel != 0) {
1175 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1176 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1177 }
1178 #endif
1179 }
1180
1181 target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1182 {
1183 return env->IBAT[0][nr];
1184 }
1185
1186 target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1187 {
1188 return env->IBAT[1][nr];
1189 }
1190
1191 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1192 {
1193 target_ulong mask;
1194
1195 dump_store_bat(env, 'I', 0, nr, value);
1196 if (env->IBAT[0][nr] != value) {
1197 mask = (value << 15) & 0x0FFE0000UL;
1198 #if !defined(FLUSH_ALL_TLBS)
1199 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1200 #endif
1201 /* When storing valid upper BAT, mask BEPI and BRPN
1202 * and invalidate all TLBs covered by this BAT
1203 */
1204 mask = (value << 15) & 0x0FFE0000UL;
1205 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1206 (value & ~0x0001FFFFUL & ~mask);
1207 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1208 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1209 #if !defined(FLUSH_ALL_TLBS)
1210 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1211 #else
1212 tlb_flush(env, 1);
1213 #endif
1214 }
1215 }
1216
1217 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1218 {
1219 dump_store_bat(env, 'I', 1, nr, value);
1220 env->IBAT[1][nr] = value;
1221 }
1222
1223 target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1224 {
1225 return env->DBAT[0][nr];
1226 }
1227
1228 target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1229 {
1230 return env->DBAT[1][nr];
1231 }
1232
1233 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1234 {
1235 target_ulong mask;
1236
1237 dump_store_bat(env, 'D', 0, nr, value);
1238 if (env->DBAT[0][nr] != value) {
1239 /* When storing valid upper BAT, mask BEPI and BRPN
1240 * and invalidate all TLBs covered by this BAT
1241 */
1242 mask = (value << 15) & 0x0FFE0000UL;
1243 #if !defined(FLUSH_ALL_TLBS)
1244 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1245 #endif
1246 mask = (value << 15) & 0x0FFE0000UL;
1247 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1248 (value & ~0x0001FFFFUL & ~mask);
1249 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1250 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1251 #if !defined(FLUSH_ALL_TLBS)
1252 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1253 #else
1254 tlb_flush(env, 1);
1255 #endif
1256 }
1257 }
1258
1259 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1260 {
1261 dump_store_bat(env, 'D', 1, nr, value);
1262 env->DBAT[1][nr] = value;
1263 }
1264
1265
1266 /*****************************************************************************/
1267 /* TLB management */
1268 void ppc_tlb_invalidate_all (CPUPPCState *env)
1269 {
1270 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
1271 ppc6xx_tlb_invalidate_all(env);
1272 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
1273 ppc4xx_tlb_invalidate_all(env);
1274 } else {
1275 tlb_flush(env, 1);
1276 }
1277 }
1278
1279 /*****************************************************************************/
1280 /* Special registers manipulation */
1281 #if defined(TARGET_PPC64)
1282 target_ulong ppc_load_asr (CPUPPCState *env)
1283 {
1284 return env->asr;
1285 }
1286
1287 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1288 {
1289 if (env->asr != value) {
1290 env->asr = value;
1291 tlb_flush(env, 1);
1292 }
1293 }
1294 #endif
1295
1296 target_ulong do_load_sdr1 (CPUPPCState *env)
1297 {
1298 return env->sdr1;
1299 }
1300
1301 void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1302 {
1303 #if defined (DEBUG_MMU)
1304 if (loglevel != 0) {
1305 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1306 }
1307 #endif
1308 if (env->sdr1 != value) {
1309 env->sdr1 = value;
1310 tlb_flush(env, 1);
1311 }
1312 }
1313
1314 target_ulong do_load_sr (CPUPPCState *env, int srnum)
1315 {
1316 return env->sr[srnum];
1317 }
1318
1319 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1320 {
1321 #if defined (DEBUG_MMU)
1322 if (loglevel != 0) {
1323 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1324 __func__, srnum, value, env->sr[srnum]);
1325 }
1326 #endif
1327 if (env->sr[srnum] != value) {
1328 env->sr[srnum] = value;
1329 #if !defined(FLUSH_ALL_TLBS) && 0
1330 {
1331 target_ulong page, end;
1332 /* Invalidate 256 MB of virtual memory */
1333 page = (16 << 20) * srnum;
1334 end = page + (16 << 20);
1335 for (; page != end; page += TARGET_PAGE_SIZE)
1336 tlb_flush_page(env, page);
1337 }
1338 #else
1339 tlb_flush(env, 1);
1340 #endif
1341 }
1342 }
1343 #endif /* !defined (CONFIG_USER_ONLY) */
1344
1345 uint32_t ppc_load_xer (CPUPPCState *env)
1346 {
1347 return (xer_so << XER_SO) |
1348 (xer_ov << XER_OV) |
1349 (xer_ca << XER_CA) |
1350 (xer_bc << XER_BC) |
1351 (xer_cmp << XER_CMP);
1352 }
1353
1354 void ppc_store_xer (CPUPPCState *env, uint32_t value)
1355 {
1356 xer_so = (value >> XER_SO) & 0x01;
1357 xer_ov = (value >> XER_OV) & 0x01;
1358 xer_ca = (value >> XER_CA) & 0x01;
1359 xer_cmp = (value >> XER_CMP) & 0xFF;
1360 xer_bc = (value >> XER_BC) & 0x7F;
1361 }
1362
1363 /* Swap temporary saved registers with GPRs */
1364 static inline void swap_gpr_tgpr (CPUPPCState *env)
1365 {
1366 ppc_gpr_t tmp;
1367
1368 tmp = env->gpr[0];
1369 env->gpr[0] = env->tgpr[0];
1370 env->tgpr[0] = tmp;
1371 tmp = env->gpr[1];
1372 env->gpr[1] = env->tgpr[1];
1373 env->tgpr[1] = tmp;
1374 tmp = env->gpr[2];
1375 env->gpr[2] = env->tgpr[2];
1376 env->tgpr[2] = tmp;
1377 tmp = env->gpr[3];
1378 env->gpr[3] = env->tgpr[3];
1379 env->tgpr[3] = tmp;
1380 }
1381
1382 /* GDBstub can read and write MSR... */
1383 target_ulong do_load_msr (CPUPPCState *env)
1384 {
1385 return
1386 #if defined (TARGET_PPC64)
1387 ((target_ulong)msr_sf << MSR_SF) |
1388 ((target_ulong)msr_isf << MSR_ISF) |
1389 ((target_ulong)msr_hv << MSR_HV) |
1390 #endif
1391 ((target_ulong)msr_ucle << MSR_UCLE) |
1392 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1393 ((target_ulong)msr_ap << MSR_AP) |
1394 ((target_ulong)msr_sa << MSR_SA) |
1395 ((target_ulong)msr_key << MSR_KEY) |
1396 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1397 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1398 ((target_ulong)msr_ile << MSR_ILE) |
1399 ((target_ulong)msr_ee << MSR_EE) |
1400 ((target_ulong)msr_pr << MSR_PR) |
1401 ((target_ulong)msr_fp << MSR_FP) |
1402 ((target_ulong)msr_me << MSR_ME) |
1403 ((target_ulong)msr_fe0 << MSR_FE0) |
1404 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1405 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1406 ((target_ulong)msr_fe1 << MSR_FE1) |
1407 ((target_ulong)msr_al << MSR_AL) |
1408 ((target_ulong)msr_ip << MSR_IP) |
1409 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1410 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1411 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1412 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1413 ((target_ulong)msr_ri << MSR_RI) |
1414 ((target_ulong)msr_le << MSR_LE);
1415 }
1416
1417 void do_store_msr (CPUPPCState *env, target_ulong value)
1418 {
1419 int enter_pm;
1420
1421 value &= env->msr_mask;
1422 if (((value >> MSR_IR) & 1) != msr_ir ||
1423 ((value >> MSR_DR) & 1) != msr_dr) {
1424 /* Flush all tlb when changing translation mode */
1425 tlb_flush(env, 1);
1426 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1427 }
1428 #if 0
1429 if (loglevel != 0) {
1430 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1431 }
1432 #endif
1433 switch (PPC_EXCP(env)) {
1434 case PPC_FLAGS_EXCP_602:
1435 case PPC_FLAGS_EXCP_603:
1436 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1437 /* Swap temporary saved registers with GPRs */
1438 swap_gpr_tgpr(env);
1439 }
1440 break;
1441 default:
1442 break;
1443 }
1444 #if defined (TARGET_PPC64)
1445 msr_sf = (value >> MSR_SF) & 1;
1446 msr_isf = (value >> MSR_ISF) & 1;
1447 msr_hv = (value >> MSR_HV) & 1;
1448 #endif
1449 msr_ucle = (value >> MSR_UCLE) & 1;
1450 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1451 msr_ap = (value >> MSR_AP) & 1;
1452 msr_sa = (value >> MSR_SA) & 1;
1453 msr_key = (value >> MSR_KEY) & 1;
1454 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1455 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1456 msr_ile = (value >> MSR_ILE) & 1;
1457 msr_ee = (value >> MSR_EE) & 1;
1458 msr_pr = (value >> MSR_PR) & 1;
1459 msr_fp = (value >> MSR_FP) & 1;
1460 msr_me = (value >> MSR_ME) & 1;
1461 msr_fe0 = (value >> MSR_FE0) & 1;
1462 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1463 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1464 msr_fe1 = (value >> MSR_FE1) & 1;
1465 msr_al = (value >> MSR_AL) & 1;
1466 msr_ip = (value >> MSR_IP) & 1;
1467 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1468 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1469 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1470 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1471 msr_ri = (value >> MSR_RI) & 1;
1472 msr_le = (value >> MSR_LE) & 1;
1473 do_compute_hflags(env);
1474
1475 enter_pm = 0;
1476 switch (PPC_EXCP(env)) {
1477 case PPC_FLAGS_EXCP_603:
1478 /* Don't handle SLEEP mode: we should disable all clocks...
1479 * No dynamic power-management.
1480 */
1481 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1482 enter_pm = 1;
1483 break;
1484 case PPC_FLAGS_EXCP_604:
1485 if (msr_pow == 1)
1486 enter_pm = 1;
1487 break;
1488 case PPC_FLAGS_EXCP_7x0:
1489 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1490 enter_pm = 1;
1491 break;
1492 default:
1493 break;
1494 }
1495 if (enter_pm) {
1496 if (likely(!env->halted)) {
1497 /* power save: exit cpu loop */
1498 env->halted = 1;
1499 env->exception_index = EXCP_HLT;
1500 cpu_loop_exit();
1501 }
1502 }
1503 }
1504
1505 #if defined(TARGET_PPC64)
1506 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
1507 {
1508 do_store_msr(env,
1509 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
1510 }
1511 #endif
1512
1513 void do_compute_hflags (CPUPPCState *env)
1514 {
1515 /* Compute current hflags */
1516 env->hflags = (msr_cm << MSR_CM) | (msr_vr << MSR_VR) |
1517 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1518 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1519 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
1520 #if defined (TARGET_PPC64)
1521 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
1522 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
1523 #endif
1524 }
1525
1526 /*****************************************************************************/
1527 /* Exception processing */
1528 #if defined (CONFIG_USER_ONLY)
1529 void do_interrupt (CPUState *env)
1530 {
1531 env->exception_index = -1;
1532 }
1533
1534 void ppc_hw_interrupt (CPUState *env)
1535 {
1536 env->exception_index = -1;
1537 }
1538 #else /* defined (CONFIG_USER_ONLY) */
1539 static void dump_syscall(CPUState *env)
1540 {
1541 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1542 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
1543 env->gpr[0], env->gpr[3], env->gpr[4],
1544 env->gpr[5], env->gpr[6], env->nip);
1545 }
1546
1547 void do_interrupt (CPUState *env)
1548 {
1549 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1550 int excp, idx;
1551
1552 excp = env->exception_index;
1553 msr = do_load_msr(env);
1554 /* The default is to use SRR0 & SRR1 to save the exception context */
1555 srr_0 = &env->spr[SPR_SRR0];
1556 srr_1 = &env->spr[SPR_SRR1];
1557 asrr_0 = NULL;
1558 asrr_1 = NULL;
1559 #if defined (DEBUG_EXCEPTIONS)
1560 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1561 if (loglevel != 0) {
1562 fprintf(logfile,
1563 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1564 env->nip, excp, env->error_code);
1565 cpu_dump_state(env, logfile, fprintf, 0);
1566 }
1567 }
1568 #endif
1569 if (loglevel & CPU_LOG_INT) {
1570 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1571 env->nip, excp, env->error_code);
1572 }
1573 msr_pow = 0;
1574 idx = -1;
1575 /* Generate informations in save/restore registers */
1576 switch (excp) {
1577 /* Generic PowerPC exceptions */
1578 case EXCP_RESET: /* 0x0100 */
1579 switch (PPC_EXCP(env)) {
1580 case PPC_FLAGS_EXCP_40x:
1581 srr_0 = &env->spr[SPR_40x_SRR2];
1582 srr_1 = &env->spr[SPR_40x_SRR3];
1583 break;
1584 case PPC_FLAGS_EXCP_BOOKE:
1585 idx = 0;
1586 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1587 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1588 break;
1589 default:
1590 if (msr_ip)
1591 excp += 0xFFC00;
1592 excp |= 0xFFC00000;
1593 break;
1594 }
1595 goto store_next;
1596 case EXCP_MACHINE_CHECK: /* 0x0200 */
1597 switch (PPC_EXCP(env)) {
1598 case PPC_FLAGS_EXCP_40x:
1599 srr_0 = &env->spr[SPR_40x_SRR2];
1600 srr_1 = &env->spr[SPR_40x_SRR3];
1601 break;
1602 case PPC_FLAGS_EXCP_BOOKE:
1603 idx = 1;
1604 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1605 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1606 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1607 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1608 msr_ce = 0;
1609 break;
1610 default:
1611 break;
1612 }
1613 msr_me = 0;
1614 break;
1615 case EXCP_DSI: /* 0x0300 */
1616 /* Store exception cause */
1617 /* data location address has been stored
1618 * when the fault has been detected
1619 */
1620 idx = 2;
1621 msr &= ~0xFFFF0000;
1622 #if defined (DEBUG_EXCEPTIONS)
1623 if (loglevel != 0) {
1624 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1625 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1626 }
1627 #endif
1628 goto store_next;
1629 case EXCP_ISI: /* 0x0400 */
1630 /* Store exception cause */
1631 idx = 3;
1632 msr &= ~0xFFFF0000;
1633 msr |= env->error_code;
1634 #if defined (DEBUG_EXCEPTIONS)
1635 if (loglevel != 0) {
1636 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1637 "\n", msr, env->nip);
1638 }
1639 #endif
1640 goto store_next;
1641 case EXCP_EXTERNAL: /* 0x0500 */
1642 idx = 4;
1643 goto store_next;
1644 case EXCP_ALIGN: /* 0x0600 */
1645 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
1646 /* Store exception cause */
1647 idx = 5;
1648 /* Get rS/rD and rA from faulting opcode */
1649 env->spr[SPR_DSISR] |=
1650 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1651 /* data location address has been stored
1652 * when the fault has been detected
1653 */
1654 } else {
1655 /* IO error exception on PowerPC 601 */
1656 /* XXX: TODO */
1657 cpu_abort(env,
1658 "601 IO error exception is not implemented yet !\n");
1659 }
1660 goto store_current;
1661 case EXCP_PROGRAM: /* 0x0700 */
1662 idx = 6;
1663 msr &= ~0xFFFF0000;
1664 switch (env->error_code & ~0xF) {
1665 case EXCP_FP:
1666 if (msr_fe0 == 0 && msr_fe1 == 0) {
1667 #if defined (DEBUG_EXCEPTIONS)
1668 if (loglevel != 0) {
1669 fprintf(logfile, "Ignore floating point exception\n");
1670 }
1671 #endif
1672 return;
1673 }
1674 msr |= 0x00100000;
1675 /* Set FX */
1676 env->fpscr[7] |= 0x8;
1677 /* Finally, update FEX */
1678 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1679 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1680 env->fpscr[7] |= 0x4;
1681 break;
1682 case EXCP_INVAL:
1683 #if defined (DEBUG_EXCEPTIONS)
1684 if (loglevel != 0) {
1685 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1686 env->nip);
1687 }
1688 #endif
1689 msr |= 0x00080000;
1690 break;
1691 case EXCP_PRIV:
1692 msr |= 0x00040000;
1693 break;
1694 case EXCP_TRAP:
1695 idx = 15;
1696 msr |= 0x00020000;
1697 break;
1698 default:
1699 /* Should never occur */
1700 break;
1701 }
1702 msr |= 0x00010000;
1703 goto store_current;
1704 case EXCP_NO_FP: /* 0x0800 */
1705 idx = 7;
1706 msr &= ~0xFFFF0000;
1707 goto store_current;
1708 case EXCP_DECR:
1709 goto store_next;
1710 case EXCP_SYSCALL: /* 0x0C00 */
1711 idx = 8;
1712 /* NOTE: this is a temporary hack to support graphics OSI
1713 calls from the MOL driver */
1714 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1715 env->osi_call) {
1716 if (env->osi_call(env) != 0)
1717 return;
1718 }
1719 if (loglevel & CPU_LOG_INT) {
1720 dump_syscall(env);
1721 }
1722 goto store_next;
1723 case EXCP_TRACE: /* 0x0D00 */
1724 goto store_next;
1725 case EXCP_PERF: /* 0x0F00 */
1726 /* XXX: TODO */
1727 cpu_abort(env,
1728 "Performance counter exception is not implemented yet !\n");
1729 goto store_next;
1730 /* 32 bits PowerPC specific exceptions */
1731 case EXCP_FP_ASSIST: /* 0x0E00 */
1732 /* XXX: TODO */
1733 cpu_abort(env, "Floating point assist exception "
1734 "is not implemented yet !\n");
1735 goto store_next;
1736 /* 64 bits PowerPC exceptions */
1737 case EXCP_DSEG: /* 0x0380 */
1738 /* XXX: TODO */
1739 cpu_abort(env, "Data segment exception is not implemented yet !\n");
1740 goto store_next;
1741 case EXCP_ISEG: /* 0x0480 */
1742 /* XXX: TODO */
1743 cpu_abort(env,
1744 "Instruction segment exception is not implemented yet !\n");
1745 goto store_next;
1746 case EXCP_HDECR: /* 0x0980 */
1747 /* XXX: TODO */
1748 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1749 "yet !\n");
1750 goto store_next;
1751 /* Implementation specific exceptions */
1752 case 0x0A00:
1753 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1754 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
1755 /* Critical interrupt on G2 */
1756 /* XXX: TODO */
1757 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1758 goto store_next;
1759 } else {
1760 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1761 }
1762 return;
1763 case 0x0F20:
1764 idx = 9;
1765 switch (PPC_EXCP(env)) {
1766 case PPC_FLAGS_EXCP_40x:
1767 /* APU unavailable on 405 */
1768 /* XXX: TODO */
1769 cpu_abort(env,
1770 "APU unavailable exception is not implemented yet !\n");
1771 goto store_next;
1772 case PPC_FLAGS_EXCP_74xx:
1773 /* Altivec unavailable */
1774 /* XXX: TODO */
1775 cpu_abort(env, "Altivec unavailable exception "
1776 "is not implemented yet !\n");
1777 goto store_next;
1778 default:
1779 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1780 break;
1781 }
1782 return;
1783 case 0x1000:
1784 idx = 10;
1785 switch (PPC_EXCP(env)) {
1786 case PPC_FLAGS_EXCP_40x:
1787 /* PIT on 4xx */
1788 msr &= ~0xFFFF0000;
1789 #if defined (DEBUG_EXCEPTIONS)
1790 if (loglevel != 0)
1791 fprintf(logfile, "PIT exception\n");
1792 #endif
1793 goto store_next;
1794 case PPC_FLAGS_EXCP_602:
1795 case PPC_FLAGS_EXCP_603:
1796 /* ITLBMISS on 602/603 */
1797 goto store_gprs;
1798 case PPC_FLAGS_EXCP_7x5:
1799 /* ITLBMISS on 745/755 */
1800 goto tlb_miss;
1801 default:
1802 cpu_abort(env, "Invalid exception 0x1000 !\n");
1803 break;
1804 }
1805 return;
1806 case 0x1010:
1807 idx = 11;
1808 switch (PPC_EXCP(env)) {
1809 case PPC_FLAGS_EXCP_40x:
1810 /* FIT on 4xx */
1811 msr &= ~0xFFFF0000;
1812 #if defined (DEBUG_EXCEPTIONS)
1813 if (loglevel != 0)
1814 fprintf(logfile, "FIT exception\n");
1815 #endif
1816 goto store_next;
1817 default:
1818 cpu_abort(env, "Invalid exception 0x1010 !\n");
1819 break;
1820 }
1821 return;
1822 case 0x1020:
1823 idx = 12;
1824 switch (PPC_EXCP(env)) {
1825 case PPC_FLAGS_EXCP_40x:
1826 /* Watchdog on 4xx */
1827 msr &= ~0xFFFF0000;
1828 #if defined (DEBUG_EXCEPTIONS)
1829 if (loglevel != 0)
1830 fprintf(logfile, "WDT exception\n");
1831 #endif
1832 goto store_next;
1833 case PPC_FLAGS_EXCP_BOOKE:
1834 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1835 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1836 break;
1837 default:
1838 cpu_abort(env, "Invalid exception 0x1020 !\n");
1839 break;
1840 }
1841 return;
1842 case 0x1100:
1843 idx = 13;
1844 switch (PPC_EXCP(env)) {
1845 case PPC_FLAGS_EXCP_40x:
1846 /* DTLBMISS on 4xx */
1847 msr &= ~0xFFFF0000;
1848 goto store_next;
1849 case PPC_FLAGS_EXCP_602:
1850 case PPC_FLAGS_EXCP_603:
1851 /* DLTLBMISS on 602/603 */
1852 goto store_gprs;
1853 case PPC_FLAGS_EXCP_7x5:
1854 /* DLTLBMISS on 745/755 */
1855 goto tlb_miss;
1856 default:
1857 cpu_abort(env, "Invalid exception 0x1100 !\n");
1858 break;
1859 }
1860 return;
1861 case 0x1200:
1862 idx = 14;
1863 switch (PPC_EXCP(env)) {
1864 case PPC_FLAGS_EXCP_40x:
1865 /* ITLBMISS on 4xx */
1866 msr &= ~0xFFFF0000;
1867 goto store_next;
1868 case PPC_FLAGS_EXCP_602:
1869 case PPC_FLAGS_EXCP_603:
1870 /* DSTLBMISS on 602/603 */
1871 store_gprs:
1872 /* Swap temporary saved registers with GPRs */
1873 swap_gpr_tgpr(env);
1874 msr_tgpr = 1;
1875 #if defined (DEBUG_SOFTWARE_TLB)
1876 if (loglevel != 0) {
1877 const unsigned char *es;
1878 target_ulong *miss, *cmp;
1879 int en;
1880 if (excp == 0x1000) {
1881 es = "I";
1882 en = 'I';
1883 miss = &env->spr[SPR_IMISS];
1884 cmp = &env->spr[SPR_ICMP];
1885 } else {
1886 if (excp == 0x1100)
1887 es = "DL";
1888 else
1889 es = "DS";
1890 en = 'D';
1891 miss = &env->spr[SPR_DMISS];
1892 cmp = &env->spr[SPR_DCMP];
1893 }
1894 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
1895 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1896 es, en, *miss, en, *cmp,
1897 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
1898 env->error_code);
1899 }
1900 #endif
1901 goto tlb_miss;
1902 case PPC_FLAGS_EXCP_7x5:
1903 /* DSTLBMISS on 745/755 */
1904 tlb_miss:
1905 msr &= ~0xF83F0000;
1906 msr |= env->crf[0] << 28;
1907 msr |= env->error_code; /* key, D/I, S/L bits */
1908 /* Set way using a LRU mechanism */
1909 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
1910 goto store_next;
1911 default:
1912 cpu_abort(env, "Invalid exception 0x1200 !\n");
1913 break;
1914 }
1915 return;
1916 case 0x1300:
1917 switch (PPC_EXCP(env)) {
1918 case PPC_FLAGS_EXCP_601:
1919 case PPC_FLAGS_EXCP_602:
1920 case PPC_FLAGS_EXCP_603:
1921 case PPC_FLAGS_EXCP_604:
1922 case PPC_FLAGS_EXCP_7x0:
1923 case PPC_FLAGS_EXCP_7x5:
1924 /* IABR on 6xx/7xx */
1925 /* XXX: TODO */
1926 cpu_abort(env, "IABR exception is not implemented yet !\n");
1927 goto store_next;
1928 default:
1929 cpu_abort(env, "Invalid exception 0x1300 !\n");
1930 break;
1931 }
1932 return;
1933 case 0x1400:
1934 switch (PPC_EXCP(env)) {
1935 case PPC_FLAGS_EXCP_601:
1936 case PPC_FLAGS_EXCP_602:
1937 case PPC_FLAGS_EXCP_603:
1938 case PPC_FLAGS_EXCP_604:
1939 case PPC_FLAGS_EXCP_7x0:
1940 case PPC_FLAGS_EXCP_7x5:
1941 /* SMI on 6xx/7xx */
1942 /* XXX: TODO */
1943 cpu_abort(env, "SMI exception is not implemented yet !\n");
1944 goto store_next;
1945 default:
1946 cpu_abort(env, "Invalid exception 0x1400 !\n");
1947 break;
1948 }
1949 return;
1950 case 0x1500:
1951 switch (PPC_EXCP(env)) {
1952 case PPC_FLAGS_EXCP_602:
1953 /* Watchdog on 602 */
1954 /* XXX: TODO */
1955 cpu_abort(env,
1956 "602 watchdog exception is not implemented yet !\n");
1957 goto store_next;
1958 case PPC_FLAGS_EXCP_970:
1959 /* Soft patch exception on 970 */
1960 /* XXX: TODO */
1961 cpu_abort(env,
1962 "970 soft-patch exception is not implemented yet !\n");
1963 goto store_next;
1964 case PPC_FLAGS_EXCP_74xx:
1965 /* VPU assist on 74xx */
1966 /* XXX: TODO */
1967 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1968 goto store_next;
1969 default:
1970 cpu_abort(env, "Invalid exception 0x1500 !\n");
1971 break;
1972 }
1973 return;
1974 case 0x1600:
1975 switch (PPC_EXCP(env)) {
1976 case PPC_FLAGS_EXCP_602:
1977 /* Emulation trap on 602 */
1978 /* XXX: TODO */
1979 cpu_abort(env, "602 emulation trap exception "
1980 "is not implemented yet !\n");
1981 goto store_next;
1982 case PPC_FLAGS_EXCP_970:
1983 /* Maintenance exception on 970 */
1984 /* XXX: TODO */
1985 cpu_abort(env,
1986 "970 maintenance exception is not implemented yet !\n");
1987 goto store_next;
1988 default:
1989 cpu_abort(env, "Invalid exception 0x1600 !\n");
1990 break;
1991 }
1992 return;
1993 case 0x1700:
1994 switch (PPC_EXCP(env)) {
1995 case PPC_FLAGS_EXCP_7x0:
1996 case PPC_FLAGS_EXCP_7x5:
1997 /* Thermal management interrupt on G3 */
1998 /* XXX: TODO */
1999 cpu_abort(env, "G3 thermal management exception "
2000 "is not implemented yet !\n");
2001 goto store_next;
2002 case PPC_FLAGS_EXCP_970:
2003 /* VPU assist on 970 */
2004 /* XXX: TODO */
2005 cpu_abort(env,
2006 "970 VPU assist exception is not implemented yet !\n");
2007 goto store_next;
2008 default:
2009 cpu_abort(env, "Invalid exception 0x1700 !\n");
2010 break;
2011 }
2012 return;
2013 case 0x1800:
2014 switch (PPC_EXCP(env)) {
2015 case PPC_FLAGS_EXCP_970:
2016 /* Thermal exception on 970 */
2017 /* XXX: TODO */
2018 cpu_abort(env, "970 thermal management exception "
2019 "is not implemented yet !\n");
2020 goto store_next;
2021 default:
2022 cpu_abort(env, "Invalid exception 0x1800 !\n");
2023 break;
2024 }
2025 return;
2026 case 0x2000:
2027 switch (PPC_EXCP(env)) {
2028 case PPC_FLAGS_EXCP_40x:
2029 /* DEBUG on 4xx */
2030 /* XXX: TODO */
2031 cpu_abort(env, "40x debug exception is not implemented yet !\n");
2032 goto store_next;
2033 case PPC_FLAGS_EXCP_601:
2034 /* Run mode exception on 601 */
2035 /* XXX: TODO */
2036 cpu_abort(env,
2037 "601 run mode exception is not implemented yet !\n");
2038 goto store_next;
2039 case PPC_FLAGS_EXCP_BOOKE:
2040 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2041 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2042 break;
2043 default:
2044 cpu_abort(env, "Invalid exception 0x1800 !\n");
2045 break;
2046 }
2047 return;
2048 /* Other exceptions */
2049 /* Qemu internal exceptions:
2050 * we should never come here with those values: abort execution
2051 */
2052 default:
2053 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
2054 return;
2055 store_current:
2056 /* save current instruction location */
2057 *srr_0 = env->nip - 4;
2058 break;
2059 store_next:
2060 /* save next instruction location */
2061 *srr_0 = env->nip;
2062 break;
2063 }
2064 /* Save msr */
2065 *srr_1 = msr;
2066 if (asrr_0 != NULL)
2067 *asrr_0 = *srr_0;
2068 if (asrr_1 != NULL)
2069 *asrr_1 = *srr_1;
2070 /* If we disactivated any translation, flush TLBs */
2071 if (msr_ir || msr_dr) {
2072 tlb_flush(env, 1);
2073 }
2074 /* reload MSR with correct bits */
2075 msr_ee = 0;
2076 msr_pr = 0;
2077 msr_fp = 0;
2078 msr_fe0 = 0;
2079 msr_se = 0;
2080 msr_be = 0;
2081 msr_fe1 = 0;
2082 msr_ir = 0;
2083 msr_dr = 0;
2084 msr_ri = 0;
2085 msr_le = msr_ile;
2086 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
2087 msr_cm = msr_icm;
2088 if (idx == -1 || (idx >= 16 && idx < 32)) {
2089 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
2090 excp, excp, idx);
2091 }
2092 #if defined(TARGET_PPC64)
2093 if (msr_cm)
2094 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
2095 else
2096 #endif
2097 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
2098 if (idx < 16)
2099 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
2100 else if (idx < 38)
2101 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
2102 } else {
2103 msr_sf = msr_isf;
2104 env->nip = excp;
2105 }
2106 do_compute_hflags(env);
2107 /* Jump to handler */
2108 env->exception_index = EXCP_NONE;
2109 }
2110
2111 void ppc_hw_interrupt (CPUPPCState *env)
2112 {
2113 int raised = 0;
2114
2115 #if 1
2116 if (loglevel & CPU_LOG_INT) {
2117 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2118 __func__, env, env->pending_interrupts,
2119 env->interrupt_request, msr_me, msr_ee);
2120 }
2121 #endif
2122 /* Raise it */
2123 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2124 /* External reset / critical input */
2125 /* XXX: critical input should be handled another way.
2126 * This code is not correct !
2127 */
2128 env->exception_index = EXCP_RESET;
2129 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2130 raised = 1;
2131 }
2132 if (raised == 0 && msr_me != 0) {
2133 /* Machine check exception */
2134 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2135 env->exception_index = EXCP_MACHINE_CHECK;
2136 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2137 raised = 1;
2138 }
2139 }
2140 if (raised == 0 && msr_ee != 0) {
2141 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2142 /* Hypervisor decrementer exception */
2143 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2144 env->exception_index = EXCP_HDECR;
2145 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2146 raised = 1;
2147 } else
2148 #endif
2149 /* Decrementer exception */
2150 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2151 env->exception_index = EXCP_DECR;
2152 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2153 raised = 1;
2154 /* Programmable interval timer on embedded PowerPC */
2155 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2156 env->exception_index = EXCP_40x_PIT;
2157 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2158 raised = 1;
2159 /* Fixed interval timer on embedded PowerPC */
2160 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2161 env->exception_index = EXCP_40x_FIT;
2162 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2163 raised = 1;
2164 /* Watchdog timer on embedded PowerPC */
2165 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2166 env->exception_index = EXCP_40x_WATCHDOG;
2167 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2168 raised = 1;
2169 /* External interrupt */
2170 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2171 env->exception_index = EXCP_EXTERNAL;
2172 /* Taking an external interrupt does not clear the external
2173 * interrupt status
2174 */
2175 #if 0
2176 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2177 #endif
2178 raised = 1;
2179 #if 0 // TODO
2180 /* Thermal interrupt */
2181 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2182 env->exception_index = EXCP_970_THRM;
2183 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2184 raised = 1;
2185 #endif
2186 }
2187 #if 0 // TODO
2188 /* External debug exception */
2189 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2190 env->exception_index = EXCP_xxx;
2191 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2192 raised = 1;
2193 #endif
2194 }
2195 if (raised != 0) {
2196 env->error_code = 0;
2197 do_interrupt(env);
2198 }
2199 }
2200 #endif /* !CONFIG_USER_ONLY */
2201
2202 void cpu_dump_EA (target_ulong EA)
2203 {
2204 FILE *f;
2205
2206 if (logfile) {
2207 f = logfile;
2208 } else {
2209 f = stdout;
2210 return;
2211 }
2212 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2213 }
2214
2215 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2216 {
2217 FILE *f;
2218
2219 if (logfile) {
2220 f = logfile;
2221 } else {
2222 f = stdout;
2223 return;
2224 }
2225 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2226 RA, msr);
2227 }
2228
2229 void cpu_ppc_reset (void *opaque)
2230 {
2231 CPUPPCState *env;
2232
2233 env = opaque;
2234 #if defined (DO_SINGLE_STEP) && 0
2235 /* Single step trace mode */
2236 msr_se = 1;
2237 msr_be = 1;
2238 #endif
2239 msr_fp = 1; /* Allow floating point exceptions */
2240 msr_me = 1; /* Allow machine check exceptions */
2241 #if defined(TARGET_PPC64)
2242 msr_sf = 0; /* Boot in 32 bits mode */
2243 msr_cm = 0;
2244 #endif
2245 #if defined(CONFIG_USER_ONLY)
2246 msr_pr = 1;
2247 tlb_flush(env, 1);
2248 #else
2249 env->nip = 0xFFFFFFFC;
2250 ppc_tlb_invalidate_all(env);
2251 #endif
2252 do_compute_hflags(env);
2253 env->reserve = -1;
2254 }
2255
2256 CPUPPCState *cpu_ppc_init (void)
2257 {
2258 CPUPPCState *env;
2259
2260 env = qemu_mallocz(sizeof(CPUPPCState));
2261 if (!env)
2262 return NULL;
2263 cpu_exec_init(env);
2264 cpu_ppc_reset(env);
2265
2266 return env;
2267 }
2268
2269 void cpu_ppc_close (CPUPPCState *env)
2270 {
2271 /* Should also remove all opcode tables... */
2272 free(env);
2273 }
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