2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 //#define DEBUG_SOFTWARE_TLB
34 //#define DEBUG_EXCEPTIONS
35 //#define FLUSH_ALL_TLBS
37 /*****************************************************************************/
38 /* PowerPC MMU emulation */
40 #if defined(CONFIG_USER_ONLY)
41 int cpu_ppc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
42 int is_user
, int is_softmmu
)
44 int exception
, error_code
;
53 error_code
|= 0x02000000;
54 env
->spr
[SPR_DAR
] = address
;
55 env
->spr
[SPR_DSISR
] = error_code
;
57 env
->exception_index
= exception
;
58 env
->error_code
= error_code
;
63 target_phys_addr_t
cpu_get_phys_page_debug (CPUState
*env
, target_ulong addr
)
68 /* Common routines used by software and hardware TLBs emulation */
69 static inline int pte_is_valid (target_ulong pte0
)
71 return pte0
& 0x80000000 ? 1 : 0;
74 static inline void pte_invalidate (target_ulong
*pte0
)
79 #define PTE_PTEM_MASK 0x7FFFFFBF
80 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
82 static int pte_check (mmu_ctx_t
*ctx
,
83 target_ulong pte0
, target_ulong pte1
, int h
, int rw
)
89 /* Check validity and table match */
90 if (pte_is_valid(pte0
) && (h
== ((pte0
>> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0
& PTE_PTEM_MASK
) == ctx
->ptem
) {
93 if (ctx
->raddr
!= (target_ulong
)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx
->raddr
& PTE_CHECK_MASK
) != (pte1
& PTE_CHECK_MASK
)) {
97 fprintf(logfile
, "Bad RPN/WIMG/PP\n");
101 /* Compute access rights */
104 if ((pte1
& 0x00000003) != 0x3)
105 access
|= PAGE_WRITE
;
107 switch (pte1
& 0x00000003) {
116 access
= PAGE_READ
| PAGE_WRITE
;
120 /* Keep the matching PTE informations */
123 if ((rw
== 0 && (access
& PAGE_READ
)) ||
124 (rw
== 1 && (access
& PAGE_WRITE
))) {
126 #if defined (DEBUG_MMU)
128 fprintf(logfile
, "PTE access granted !\n");
132 /* Access right violation */
133 #if defined (DEBUG_MMU)
135 fprintf(logfile
, "PTE access rejected\n");
145 static int pte_update_flags (mmu_ctx_t
*ctx
, target_ulong
*pte1p
,
150 /* Update page flags */
151 if (!(*pte1p
& 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p
|= 0x00000100;
156 if (!(*pte1p
& 0x00000080)) {
157 if (rw
== 1 && ret
== 0) {
158 /* Update changed flag */
159 *pte1p
|= 0x00000080;
162 /* Force page fault for first write access */
163 ctx
->prot
&= ~PAGE_WRITE
;
170 /* Software driven TLB helpers */
171 static int ppc6xx_tlb_getnum (CPUState
*env
, target_ulong eaddr
,
172 int way
, int is_code
)
176 /* Select TLB num in a way from address */
177 nr
= (eaddr
>> TARGET_PAGE_BITS
) & (env
->tlb_per_way
- 1);
179 nr
+= env
->tlb_per_way
* way
;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code
&& env
->id_tlbs
== 1)
187 void ppc6xx_tlb_invalidate_all (CPUState
*env
)
192 #if defined (DEBUG_SOFTWARE_TLB) && 0
194 fprintf(logfile
, "Invalidate all TLBs\n");
197 /* Invalidate all defined software TLB */
199 if (env
->id_tlbs
== 1)
201 for (nr
= 0; nr
< max
; nr
++) {
202 tlb
= &env
->tlb
[nr
].tlb6
;
203 #if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env
, tlb
->EPN
);
206 pte_invalidate(&tlb
->pte0
);
208 #if defined(FLUSH_ALL_TLBS)
213 static inline void __ppc6xx_tlb_invalidate_virt (CPUState
*env
,
215 int is_code
, int match_epn
)
217 #if !defined(FLUSH_ALL_TLBS)
221 /* Invalidate ITLB + DTLB, all ways */
222 for (way
= 0; way
< env
->nb_ways
; way
++) {
223 nr
= ppc6xx_tlb_getnum(env
, eaddr
, way
, is_code
);
224 tlb
= &env
->tlb
[nr
].tlb6
;
225 if (pte_is_valid(tlb
->pte0
) && (match_epn
== 0 || eaddr
== tlb
->EPN
)) {
226 #if defined (DEBUG_SOFTWARE_TLB)
228 fprintf(logfile
, "TLB invalidate %d/%d " ADDRX
"\n",
229 nr
, env
->nb_tlb
, eaddr
);
232 pte_invalidate(&tlb
->pte0
);
233 tlb_flush_page(env
, tlb
->EPN
);
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env
);
242 void ppc6xx_tlb_invalidate_virt (CPUState
*env
, target_ulong eaddr
,
245 __ppc6xx_tlb_invalidate_virt(env
, eaddr
, is_code
, 0);
248 void ppc6xx_tlb_store (CPUState
*env
, target_ulong EPN
, int way
, int is_code
,
249 target_ulong pte0
, target_ulong pte1
)
254 nr
= ppc6xx_tlb_getnum(env
, EPN
, way
, is_code
);
255 tlb
= &env
->tlb
[nr
].tlb6
;
256 #if defined (DEBUG_SOFTWARE_TLB)
258 fprintf(logfile
, "Set TLB %d/%d EPN " ADDRX
" PTE0 " ADDRX
259 " PTE1 " ADDRX
"\n", nr
, env
->nb_tlb
, EPN
, pte0
, pte1
);
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env
, EPN
, is_code
, 1);
267 /* Store last way for LRU mechanism */
271 static int ppc6xx_tlb_check (CPUState
*env
, mmu_ctx_t
*ctx
,
272 target_ulong eaddr
, int rw
, int access_type
)
279 ret
= -1; /* No TLB found */
280 for (way
= 0; way
< env
->nb_ways
; way
++) {
281 nr
= ppc6xx_tlb_getnum(env
, eaddr
, way
,
282 access_type
== ACCESS_CODE
? 1 : 0);
283 tlb
= &env
->tlb
[nr
].tlb6
;
284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr
& TARGET_PAGE_MASK
) != tlb
->EPN
) {
286 #if defined (DEBUG_SOFTWARE_TLB)
288 fprintf(logfile
, "TLB %d/%d %s [" ADDRX
" " ADDRX
291 pte_is_valid(tlb
->pte0
) ? "valid" : "inval",
292 tlb
->EPN
, tlb
->EPN
+ TARGET_PAGE_SIZE
, eaddr
);
297 #if defined (DEBUG_SOFTWARE_TLB)
299 fprintf(logfile
, "TLB %d/%d %s " ADDRX
" <> " ADDRX
" " ADDRX
302 pte_is_valid(tlb
->pte0
) ? "valid" : "inval",
303 tlb
->EPN
, eaddr
, tlb
->pte1
,
304 rw
? 'S' : 'L', access_type
== ACCESS_CODE
? 'I' : 'D');
307 switch (pte_check(ctx
, tlb
->pte0
, tlb
->pte1
, 0, rw
)) {
309 /* TLB inconsistency */
312 /* Access violation */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
333 #if defined (DEBUG_SOFTWARE_TLB)
335 fprintf(logfile
, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx
->raddr
& TARGET_PAGE_MASK
, ctx
->prot
, ret
);
339 /* Update page flags */
340 pte_update_flags(ctx
, &env
->tlb
[best
].tlb6
.pte1
, ret
, rw
);
346 /* Perform BAT hit & translation */
347 static int get_bat (CPUState
*env
, mmu_ctx_t
*ctx
,
348 target_ulong
virtual, int rw
, int type
)
350 target_ulong
*BATlt
, *BATut
, *BATu
, *BATl
;
351 target_ulong base
, BEPIl
, BEPIu
, bl
;
355 #if defined (DEBUG_BATS)
357 fprintf(logfile
, "%s: %cBAT v 0x" ADDRX
"\n", __func__
,
358 type
== ACCESS_CODE
? 'I' : 'D', virtual);
363 BATlt
= env
->IBAT
[1];
364 BATut
= env
->IBAT
[0];
367 BATlt
= env
->DBAT
[1];
368 BATut
= env
->DBAT
[0];
371 #if defined (DEBUG_BATS)
373 fprintf(logfile
, "%s...: %cBAT v 0x" ADDRX
"\n", __func__
,
374 type
== ACCESS_CODE
? 'I' : 'D', virtual);
377 base
= virtual & 0xFFFC0000;
378 for (i
= 0; i
< 4; i
++) {
381 BEPIu
= *BATu
& 0xF0000000;
382 BEPIl
= *BATu
& 0x0FFE0000;
383 bl
= (*BATu
& 0x00001FFC) << 15;
384 #if defined (DEBUG_BATS)
386 fprintf(logfile
, "%s: %cBAT%d v 0x" ADDRX
" BATu 0x" ADDRX
387 " BATl 0x" ADDRX
"\n",
388 __func__
, type
== ACCESS_CODE
? 'I' : 'D', i
, virtual,
392 if ((virtual & 0xF0000000) == BEPIu
&&
393 ((virtual & 0x0FFE0000) & ~bl
) == BEPIl
) {
395 if ((msr_pr
== 0 && (*BATu
& 0x00000002)) ||
396 (msr_pr
== 1 && (*BATu
& 0x00000001))) {
397 /* Get physical address */
398 ctx
->raddr
= (*BATl
& 0xF0000000) |
399 ((virtual & 0x0FFE0000 & bl
) | (*BATl
& 0x0FFE0000)) |
400 (virtual & 0x0001F000);
401 if (*BATl
& 0x00000001)
402 ctx
->prot
= PAGE_READ
;
403 if (*BATl
& 0x00000002)
404 ctx
->prot
= PAGE_WRITE
| PAGE_READ
;
405 #if defined (DEBUG_BATS)
407 fprintf(logfile
, "BAT %d match: r 0x" PADDRX
409 i
, ctx
->raddr
, ctx
->prot
& PAGE_READ
? 'R' : '-',
410 ctx
->prot
& PAGE_WRITE
? 'W' : '-');
419 #if defined (DEBUG_BATS)
421 fprintf(logfile
, "no BAT match for 0x" ADDRX
":\n", virtual);
422 for (i
= 0; i
< 4; i
++) {
425 BEPIu
= *BATu
& 0xF0000000;
426 BEPIl
= *BATu
& 0x0FFE0000;
427 bl
= (*BATu
& 0x00001FFC) << 15;
428 fprintf(logfile
, "%s: %cBAT%d v 0x" ADDRX
" BATu 0x" ADDRX
429 " BATl 0x" ADDRX
" \n\t"
430 "0x" ADDRX
" 0x" ADDRX
" 0x" ADDRX
"\n",
431 __func__
, type
== ACCESS_CODE
? 'I' : 'D', i
, virtual,
432 *BATu
, *BATl
, BEPIu
, BEPIl
, bl
);
441 /* PTE table lookup */
442 static int find_pte (mmu_ctx_t
*ctx
, int h
, int rw
)
444 target_ulong base
, pte0
, pte1
;
448 ret
= -1; /* No entry found */
449 base
= ctx
->pg_addr
[h
];
450 for (i
= 0; i
< 8; i
++) {
451 pte0
= ldl_phys(base
+ (i
* 8));
452 pte1
= ldl_phys(base
+ (i
* 8) + 4);
453 #if defined (DEBUG_MMU)
455 fprintf(logfile
, "Load pte from 0x" ADDRX
" => 0x" ADDRX
456 " 0x" ADDRX
" %d %d %d 0x" ADDRX
"\n",
457 base
+ (i
* 8), pte0
, pte1
,
458 pte0
>> 31, h
, (pte0
>> 6) & 1, ctx
->ptem
);
461 switch (pte_check(ctx
, pte0
, pte1
, h
, rw
)) {
463 /* PTE inconsistency */
466 /* Access violation */
476 /* XXX: we should go on looping to check all PTEs consistency
477 * but if we can speed-up the whole thing as the
478 * result would be undefined if PTEs are not consistent.
487 #if defined (DEBUG_MMU)
489 fprintf(logfile
, "found PTE at addr 0x" PADDRX
" prot=0x%01x "
491 ctx
->raddr
, ctx
->prot
, ret
);
494 /* Update page flags */
496 if (pte_update_flags(ctx
, &pte1
, ret
, rw
) == 1)
497 stl_phys_notdirty(base
+ (good
* 8) + 4, pte1
);
503 static inline target_phys_addr_t
get_pgaddr (target_phys_addr_t sdr1
,
504 target_phys_addr_t hash
,
505 target_phys_addr_t mask
)
507 return (sdr1
& 0xFFFF0000) | (hash
& mask
);
510 /* Perform segment based translation */
511 static int get_segment (CPUState
*env
, mmu_ctx_t
*ctx
,
512 target_ulong eaddr
, int rw
, int type
)
514 target_phys_addr_t sdr
, hash
, mask
;
515 target_ulong sr
, vsid
, pgidx
;
518 sr
= env
->sr
[eaddr
>> 28];
519 #if defined (DEBUG_MMU)
521 fprintf(logfile
, "Check segment v=0x" ADDRX
" %d 0x" ADDRX
" nip=0x"
522 ADDRX
" lr=0x" ADDRX
" ir=%d dr=%d pr=%d %d t=%d\n",
523 eaddr
, eaddr
>> 28, sr
, env
->nip
,
524 env
->lr
, msr_ir
, msr_dr
, msr_pr
, rw
, type
);
527 ctx
->key
= (((sr
& 0x20000000) && msr_pr
== 1) ||
528 ((sr
& 0x40000000) && msr_pr
== 0)) ? 1 : 0;
529 if ((sr
& 0x80000000) == 0) {
530 #if defined (DEBUG_MMU)
532 fprintf(logfile
, "pte segment: key=%d n=0x" ADDRX
"\n",
533 ctx
->key
, sr
& 0x10000000);
535 /* Check if instruction fetch is allowed, if needed */
536 if (type
!= ACCESS_CODE
|| (sr
& 0x10000000) == 0) {
537 /* Page address translation */
538 pgidx
= (eaddr
>> TARGET_PAGE_BITS
) & 0xFFFF;
539 vsid
= sr
& 0x00FFFFFF;
540 hash
= ((vsid
^ pgidx
) & 0x0007FFFF) << 6;
541 /* Primary table address */
543 mask
= ((sdr
& 0x000001FF) << 16) | 0xFFC0;
544 ctx
->pg_addr
[0] = get_pgaddr(sdr
, hash
, mask
);
545 /* Secondary table address */
546 hash
= (~hash
) & 0x01FFFFC0;
547 ctx
->pg_addr
[1] = get_pgaddr(sdr
, hash
, mask
);
548 ctx
->ptem
= (vsid
<< 7) | (pgidx
>> 10);
549 /* Initialize real address with an invalid value */
550 ctx
->raddr
= (target_ulong
)-1;
551 if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_6xx
)) {
552 /* Software TLB search */
553 ret
= ppc6xx_tlb_check(env
, ctx
, eaddr
, rw
, type
);
555 #if defined (DEBUG_MMU)
557 fprintf(logfile
, "0 sdr1=0x" PADDRX
" vsid=0x%06x "
558 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX
"\n",
559 sdr
, (uint32_t)vsid
, (uint32_t)pgidx
,
560 (uint32_t)hash
, ctx
->pg_addr
[0]);
563 /* Primary table lookup */
564 ret
= find_pte(ctx
, 0, rw
);
566 /* Secondary table lookup */
567 #if defined (DEBUG_MMU)
568 if (eaddr
!= 0xEFFFFFFF && loglevel
!= 0) {
570 "1 sdr1=0x" PADDRX
" vsid=0x%06x api=0x%04x "
571 "hash=0x%05x pg_addr=0x" PADDRX
"\n",
572 sdr
, (uint32_t)vsid
, (uint32_t)pgidx
,
573 (uint32_t)hash
, ctx
->pg_addr
[1]);
576 ret2
= find_pte(ctx
, 1, rw
);
582 #if defined (DEBUG_MMU)
584 fprintf(logfile
, "No access allowed\n");
589 #if defined (DEBUG_MMU)
591 fprintf(logfile
, "direct store...\n");
593 /* Direct-store segment : absolutely *BUGGY* for now */
596 /* Integer load/store : only access allowed */
599 /* No code fetch is allowed in direct-store areas */
602 /* Floating point load/store */
605 /* lwarx, ldarx or srwcx. */
608 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
609 /* Should make the instruction do no-op.
610 * As it already do no-op, it's quite easy :-)
619 fprintf(logfile
, "ERROR: instruction should not need "
620 "address translation\n");
624 if ((rw
== 1 || ctx
->key
!= 1) && (rw
== 0 || ctx
->key
!= 0)) {
635 /* Generic TLB check function for embedded PowerPC implementations */
636 static int ppcemb_tlb_check (CPUState
*env
, ppcemb_tlb_t
*tlb
,
637 target_phys_addr_t
*raddrp
,
638 target_ulong address
, int i
)
642 /* Check valid flag */
643 if (!(tlb
->prot
& PAGE_VALID
)) {
645 fprintf(logfile
, "%s: TLB %d not valid\n", __func__
, i
);
648 mask
= ~(tlb
->size
- 1);
650 fprintf(logfile
, "%s: TLB %d address " ADDRX
" PID %d <=> "
651 ADDRX
" " ADDRX
" %d\n",
652 __func__
, i
, address
, (int)env
->spr
[SPR_40x_PID
],
653 tlb
->EPN
, mask
, (int)tlb
->PID
);
656 if (tlb
->PID
!= 0 && tlb
->PID
!= env
->spr
[SPR_40x_PID
])
658 /* Check effective address */
659 if ((address
& mask
) != tlb
->EPN
)
661 *raddrp
= (tlb
->RPN
& mask
) | (address
& ~mask
);
666 /* Generic TLB search function for PowerPC embedded implementations */
667 int ppcemb_tlb_search (CPUState
*env
, target_ulong address
)
670 target_phys_addr_t raddr
;
673 /* Default return value is no match */
675 for (i
= 0; i
< 64; i
++) {
676 tlb
= &env
->tlb
[i
].tlbe
;
677 if (ppcemb_tlb_check(env
, tlb
, &raddr
, address
, i
) == 0) {
686 /* Helpers specific to PowerPC 40x implementations */
687 void ppc4xx_tlb_invalidate_all (CPUState
*env
)
692 for (i
= 0; i
< env
->nb_tlb
; i
++) {
693 tlb
= &env
->tlb
[i
].tlbe
;
694 if (tlb
->prot
& PAGE_VALID
) {
695 #if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
696 end
= tlb
->EPN
+ tlb
->size
;
697 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
698 tlb_flush_page(env
, page
);
700 tlb
->prot
&= ~PAGE_VALID
;
706 int mmu4xx_get_physical_address (CPUState
*env
, mmu_ctx_t
*ctx
,
707 target_ulong address
, int rw
, int access_type
)
710 target_phys_addr_t raddr
;
711 int i
, ret
, zsel
, zpr
;
715 for (i
= 0; i
< env
->nb_tlb
; i
++) {
716 tlb
= &env
->tlb
[i
].tlbe
;
717 if (ppcemb_tlb_check(env
, tlb
, &raddr
, address
, i
) < 0)
719 zsel
= (tlb
->attr
>> 4) & 0xF;
720 zpr
= (env
->spr
[SPR_40x_ZPR
] >> (28 - (2 * zsel
))) & 0x3;
722 fprintf(logfile
, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
723 __func__
, i
, zsel
, zpr
, rw
, tlb
->attr
);
725 if (access_type
== ACCESS_CODE
) {
726 /* Check execute enable bit */
730 goto check_exec_perm
;
741 /* Check from TLB entry */
742 if (!(tlb
->prot
& PAGE_EXEC
)) {
745 if (tlb
->prot
& PAGE_WRITE
) {
746 ctx
->prot
= PAGE_READ
| PAGE_WRITE
;
748 ctx
->prot
= PAGE_READ
;
755 /* All accesses granted */
756 ctx
->prot
= PAGE_READ
| PAGE_WRITE
;
775 /* Check from TLB entry */
776 /* Check write protection bit */
777 if (tlb
->prot
& PAGE_WRITE
) {
778 ctx
->prot
= PAGE_READ
| PAGE_WRITE
;
781 ctx
->prot
= PAGE_READ
;
790 /* All accesses granted */
791 ctx
->prot
= PAGE_READ
| PAGE_WRITE
;
799 fprintf(logfile
, "%s: access granted " ADDRX
" => " REGX
800 " %d %d\n", __func__
, address
, ctx
->raddr
, ctx
->prot
,
807 fprintf(logfile
, "%s: access refused " ADDRX
" => " REGX
808 " %d %d\n", __func__
, address
, raddr
, ctx
->prot
,
815 void store_40x_sler (CPUPPCState
*env
, uint32_t val
)
817 /* XXX: TO BE FIXED */
818 if (val
!= 0x00000000) {
819 cpu_abort(env
, "Little-endian regions are not supported by now\n");
821 env
->spr
[SPR_405_SLER
] = val
;
824 static int check_physical (CPUState
*env
, mmu_ctx_t
*ctx
,
825 target_ulong eaddr
, int rw
)
830 ctx
->prot
= PAGE_READ
;
832 if (unlikely(msr_pe
!= 0 && PPC_MMU(env
) == PPC_FLAGS_MMU_403
)) {
833 /* 403 family add some particular protections,
834 * using PBL/PBU registers for accesses with no translation.
837 /* Check PLB validity */
838 (env
->pb
[0] < env
->pb
[1] &&
839 /* and address in plb area */
840 eaddr
>= env
->pb
[0] && eaddr
< env
->pb
[1]) ||
841 (env
->pb
[2] < env
->pb
[3] &&
842 eaddr
>= env
->pb
[2] && eaddr
< env
->pb
[3]) ? 1 : 0;
843 if (in_plb
^ msr_px
) {
844 /* Access in protected area */
846 /* Access is not allowed */
850 /* Read-write access is allowed */
851 ctx
->prot
|= PAGE_WRITE
;
854 ctx
->prot
|= PAGE_WRITE
;
860 int get_physical_address (CPUState
*env
, mmu_ctx_t
*ctx
, target_ulong eaddr
,
861 int rw
, int access_type
, int check_BATs
)
866 fprintf(logfile
, "%s\n", __func__
);
869 if ((access_type
== ACCESS_CODE
&& msr_ir
== 0) ||
870 (access_type
!= ACCESS_CODE
&& msr_dr
== 0)) {
871 /* No address translation */
872 ret
= check_physical(env
, ctx
, eaddr
, rw
);
875 switch (PPC_MMU(env
)) {
876 case PPC_FLAGS_MMU_32B
:
877 case PPC_FLAGS_MMU_SOFT_6xx
:
878 /* Try to find a BAT */
880 ret
= get_bat(env
, ctx
, eaddr
, rw
, access_type
);
882 #if defined(TARGET_PPC64)
883 case PPC_FLAGS_MMU_64B
:
884 case PPC_FLAGS_MMU_64BRIDGE
:
887 /* We didn't match any BAT entry or don't have BATs */
888 ret
= get_segment(env
, ctx
, eaddr
, rw
, access_type
);
891 case PPC_FLAGS_MMU_SOFT_4xx
:
892 case PPC_FLAGS_MMU_403
:
893 ret
= mmu4xx_get_physical_address(env
, ctx
, eaddr
,
896 case PPC_FLAGS_MMU_601
:
898 cpu_abort(env
, "601 MMU model not implemented\n");
900 case PPC_FLAGS_MMU_BOOKE
:
902 cpu_abort(env
, "BookeE MMU model not implemented\n");
904 case PPC_FLAGS_MMU_BOOKE_FSL
:
906 cpu_abort(env
, "BookE FSL MMU model not implemented\n");
909 cpu_abort(env
, "Unknown or invalid MMU model\n");
915 fprintf(logfile
, "%s address " ADDRX
" => %d " PADDRX
"\n",
916 __func__
, eaddr
, ret
, ctx
->raddr
);
923 target_phys_addr_t
cpu_get_phys_page_debug (CPUState
*env
, target_ulong addr
)
927 if (unlikely(get_physical_address(env
, &ctx
, addr
, 0, ACCESS_INT
, 1) != 0))
930 return ctx
.raddr
& TARGET_PAGE_MASK
;
933 /* Perform address translation */
934 int cpu_ppc_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
935 int is_user
, int is_softmmu
)
938 int exception
= 0, error_code
= 0;
945 access_type
= ACCESS_CODE
;
948 /* XXX: put correct access by using cpu_restore_state()
950 access_type
= ACCESS_INT
;
951 // access_type = env->access_type;
953 ret
= get_physical_address(env
, &ctx
, address
, rw
, access_type
, 1);
955 ret
= tlb_set_page(env
, address
& TARGET_PAGE_MASK
,
956 ctx
.raddr
& TARGET_PAGE_MASK
, ctx
.prot
,
957 is_user
, is_softmmu
);
958 } else if (ret
< 0) {
959 #if defined (DEBUG_MMU)
961 cpu_dump_state(env
, logfile
, fprintf
, 0);
963 if (access_type
== ACCESS_CODE
) {
964 exception
= EXCP_ISI
;
967 /* No matches in page tables or TLB */
968 switch (PPC_MMU(env
)) {
969 case PPC_FLAGS_MMU_SOFT_6xx
:
970 exception
= EXCP_I_TLBMISS
;
971 env
->spr
[SPR_IMISS
] = address
;
972 env
->spr
[SPR_ICMP
] = 0x80000000 | ctx
.ptem
;
973 error_code
= 1 << 18;
975 case PPC_FLAGS_MMU_SOFT_4xx
:
976 case PPC_FLAGS_MMU_403
:
977 exception
= EXCP_40x_ITLBMISS
;
979 env
->spr
[SPR_40x_DEAR
] = address
;
980 env
->spr
[SPR_40x_ESR
] = 0x00000000;
982 case PPC_FLAGS_MMU_32B
:
983 error_code
= 0x40000000;
985 #if defined(TARGET_PPC64)
986 case PPC_FLAGS_MMU_64B
:
988 cpu_abort(env
, "MMU model not implemented\n");
990 case PPC_FLAGS_MMU_64BRIDGE
:
992 cpu_abort(env
, "MMU model not implemented\n");
995 case PPC_FLAGS_MMU_601
:
997 cpu_abort(env
, "MMU model not implemented\n");
999 case PPC_FLAGS_MMU_BOOKE
:
1001 cpu_abort(env
, "MMU model not implemented\n");
1003 case PPC_FLAGS_MMU_BOOKE_FSL
:
1005 cpu_abort(env
, "MMU model not implemented\n");
1008 cpu_abort(env
, "Unknown or invalid MMU model\n");
1013 /* Access rights violation */
1014 error_code
= 0x08000000;
1017 /* No execute protection violation */
1018 error_code
= 0x10000000;
1021 /* Direct store exception */
1022 /* No code fetch is allowed in direct-store areas */
1023 error_code
= 0x10000000;
1026 /* No match in segment table */
1027 exception
= EXCP_ISEG
;
1032 exception
= EXCP_DSI
;
1035 /* No matches in page tables or TLB */
1036 switch (PPC_MMU(env
)) {
1037 case PPC_FLAGS_MMU_SOFT_6xx
:
1039 exception
= EXCP_DS_TLBMISS
;
1040 error_code
= 1 << 16;
1042 exception
= EXCP_DL_TLBMISS
;
1045 env
->spr
[SPR_DMISS
] = address
;
1046 env
->spr
[SPR_DCMP
] = 0x80000000 | ctx
.ptem
;
1048 error_code
|= ctx
.key
<< 19;
1049 env
->spr
[SPR_HASH1
] = ctx
.pg_addr
[0];
1050 env
->spr
[SPR_HASH2
] = ctx
.pg_addr
[1];
1051 /* Do not alter DAR nor DSISR */
1053 case PPC_FLAGS_MMU_SOFT_4xx
:
1054 case PPC_FLAGS_MMU_403
:
1055 exception
= EXCP_40x_DTLBMISS
;
1057 env
->spr
[SPR_40x_DEAR
] = address
;
1059 env
->spr
[SPR_40x_ESR
] = 0x00800000;
1061 env
->spr
[SPR_40x_ESR
] = 0x00000000;
1063 case PPC_FLAGS_MMU_32B
:
1064 error_code
= 0x40000000;
1066 #if defined(TARGET_PPC64)
1067 case PPC_FLAGS_MMU_64B
:
1069 cpu_abort(env
, "MMU model not implemented\n");
1071 case PPC_FLAGS_MMU_64BRIDGE
:
1073 cpu_abort(env
, "MMU model not implemented\n");
1076 case PPC_FLAGS_MMU_601
:
1078 cpu_abort(env
, "MMU model not implemented\n");
1080 case PPC_FLAGS_MMU_BOOKE
:
1082 cpu_abort(env
, "MMU model not implemented\n");
1084 case PPC_FLAGS_MMU_BOOKE_FSL
:
1086 cpu_abort(env
, "MMU model not implemented\n");
1089 cpu_abort(env
, "Unknown or invalid MMU model\n");
1094 /* Access rights violation */
1095 error_code
= 0x08000000;
1098 /* Direct store exception */
1099 switch (access_type
) {
1101 /* Floating point load/store */
1102 exception
= EXCP_ALIGN
;
1103 error_code
= EXCP_ALIGN_FP
;
1106 /* lwarx, ldarx or srwcx. */
1107 error_code
= 0x04000000;
1110 /* eciwx or ecowx */
1111 error_code
= 0x04100000;
1114 printf("DSI: invalid exception (%d)\n", ret
);
1115 exception
= EXCP_PROGRAM
;
1116 error_code
= EXCP_INVAL
| EXCP_INVAL_INVAL
;
1121 /* No match in segment table */
1122 exception
= EXCP_DSEG
;
1126 if (exception
== EXCP_DSI
&& rw
== 1)
1127 error_code
|= 0x02000000;
1128 /* Store fault address */
1129 env
->spr
[SPR_DAR
] = address
;
1130 env
->spr
[SPR_DSISR
] = error_code
;
1134 printf("%s: set exception to %d %02x\n",
1135 __func__
, exception
, error_code
);
1137 env
->exception_index
= exception
;
1138 env
->error_code
= error_code
;
1145 /*****************************************************************************/
1146 /* BATs management */
1147 #if !defined(FLUSH_ALL_TLBS)
1148 static inline void do_invalidate_BAT (CPUPPCState
*env
,
1149 target_ulong BATu
, target_ulong mask
)
1151 target_ulong base
, end
, page
;
1153 base
= BATu
& ~0x0001FFFF;
1154 end
= base
+ mask
+ 0x00020000;
1155 #if defined (DEBUG_BATS)
1156 if (loglevel
!= 0) {
1157 fprintf(logfile
, "Flush BAT from " ADDRX
" to " ADDRX
" (" ADDRX
")\n",
1161 for (page
= base
; page
!= end
; page
+= TARGET_PAGE_SIZE
)
1162 tlb_flush_page(env
, page
);
1163 #if defined (DEBUG_BATS)
1165 fprintf(logfile
, "Flush done\n");
1170 static inline void dump_store_bat (CPUPPCState
*env
, char ID
, int ul
, int nr
,
1173 #if defined (DEBUG_BATS)
1174 if (loglevel
!= 0) {
1175 fprintf(logfile
, "Set %cBAT%d%c to 0x" ADDRX
" (0x" ADDRX
")\n",
1176 ID
, nr
, ul
== 0 ? 'u' : 'l', value
, env
->nip
);
1181 target_ulong
do_load_ibatu (CPUPPCState
*env
, int nr
)
1183 return env
->IBAT
[0][nr
];
1186 target_ulong
do_load_ibatl (CPUPPCState
*env
, int nr
)
1188 return env
->IBAT
[1][nr
];
1191 void do_store_ibatu (CPUPPCState
*env
, int nr
, target_ulong value
)
1195 dump_store_bat(env
, 'I', 0, nr
, value
);
1196 if (env
->IBAT
[0][nr
] != value
) {
1197 mask
= (value
<< 15) & 0x0FFE0000UL
;
1198 #if !defined(FLUSH_ALL_TLBS)
1199 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1201 /* When storing valid upper BAT, mask BEPI and BRPN
1202 * and invalidate all TLBs covered by this BAT
1204 mask
= (value
<< 15) & 0x0FFE0000UL
;
1205 env
->IBAT
[0][nr
] = (value
& 0x00001FFFUL
) |
1206 (value
& ~0x0001FFFFUL
& ~mask
);
1207 env
->IBAT
[1][nr
] = (env
->IBAT
[1][nr
] & 0x0000007B) |
1208 (env
->IBAT
[1][nr
] & ~0x0001FFFF & ~mask
);
1209 #if !defined(FLUSH_ALL_TLBS)
1210 do_invalidate_BAT(env
, env
->IBAT
[0][nr
], mask
);
1217 void do_store_ibatl (CPUPPCState
*env
, int nr
, target_ulong value
)
1219 dump_store_bat(env
, 'I', 1, nr
, value
);
1220 env
->IBAT
[1][nr
] = value
;
1223 target_ulong
do_load_dbatu (CPUPPCState
*env
, int nr
)
1225 return env
->DBAT
[0][nr
];
1228 target_ulong
do_load_dbatl (CPUPPCState
*env
, int nr
)
1230 return env
->DBAT
[1][nr
];
1233 void do_store_dbatu (CPUPPCState
*env
, int nr
, target_ulong value
)
1237 dump_store_bat(env
, 'D', 0, nr
, value
);
1238 if (env
->DBAT
[0][nr
] != value
) {
1239 /* When storing valid upper BAT, mask BEPI and BRPN
1240 * and invalidate all TLBs covered by this BAT
1242 mask
= (value
<< 15) & 0x0FFE0000UL
;
1243 #if !defined(FLUSH_ALL_TLBS)
1244 do_invalidate_BAT(env
, env
->DBAT
[0][nr
], mask
);
1246 mask
= (value
<< 15) & 0x0FFE0000UL
;
1247 env
->DBAT
[0][nr
] = (value
& 0x00001FFFUL
) |
1248 (value
& ~0x0001FFFFUL
& ~mask
);
1249 env
->DBAT
[1][nr
] = (env
->DBAT
[1][nr
] & 0x0000007B) |
1250 (env
->DBAT
[1][nr
] & ~0x0001FFFF & ~mask
);
1251 #if !defined(FLUSH_ALL_TLBS)
1252 do_invalidate_BAT(env
, env
->DBAT
[0][nr
], mask
);
1259 void do_store_dbatl (CPUPPCState
*env
, int nr
, target_ulong value
)
1261 dump_store_bat(env
, 'D', 1, nr
, value
);
1262 env
->DBAT
[1][nr
] = value
;
1266 /*****************************************************************************/
1267 /* TLB management */
1268 void ppc_tlb_invalidate_all (CPUPPCState
*env
)
1270 if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_6xx
)) {
1271 ppc6xx_tlb_invalidate_all(env
);
1272 } else if (unlikely(PPC_MMU(env
) == PPC_FLAGS_MMU_SOFT_4xx
)) {
1273 ppc4xx_tlb_invalidate_all(env
);
1279 /*****************************************************************************/
1280 /* Special registers manipulation */
1281 #if defined(TARGET_PPC64)
1282 target_ulong
ppc_load_asr (CPUPPCState
*env
)
1287 void ppc_store_asr (CPUPPCState
*env
, target_ulong value
)
1289 if (env
->asr
!= value
) {
1296 target_ulong
do_load_sdr1 (CPUPPCState
*env
)
1301 void do_store_sdr1 (CPUPPCState
*env
, target_ulong value
)
1303 #if defined (DEBUG_MMU)
1304 if (loglevel
!= 0) {
1305 fprintf(logfile
, "%s: 0x" ADDRX
"\n", __func__
, value
);
1308 if (env
->sdr1
!= value
) {
1314 target_ulong
do_load_sr (CPUPPCState
*env
, int srnum
)
1316 return env
->sr
[srnum
];
1319 void do_store_sr (CPUPPCState
*env
, int srnum
, target_ulong value
)
1321 #if defined (DEBUG_MMU)
1322 if (loglevel
!= 0) {
1323 fprintf(logfile
, "%s: reg=%d 0x" ADDRX
" " ADDRX
"\n",
1324 __func__
, srnum
, value
, env
->sr
[srnum
]);
1327 if (env
->sr
[srnum
] != value
) {
1328 env
->sr
[srnum
] = value
;
1329 #if !defined(FLUSH_ALL_TLBS) && 0
1331 target_ulong page
, end
;
1332 /* Invalidate 256 MB of virtual memory */
1333 page
= (16 << 20) * srnum
;
1334 end
= page
+ (16 << 20);
1335 for (; page
!= end
; page
+= TARGET_PAGE_SIZE
)
1336 tlb_flush_page(env
, page
);
1343 #endif /* !defined (CONFIG_USER_ONLY) */
1345 uint32_t ppc_load_xer (CPUPPCState
*env
)
1347 return (xer_so
<< XER_SO
) |
1348 (xer_ov
<< XER_OV
) |
1349 (xer_ca
<< XER_CA
) |
1350 (xer_bc
<< XER_BC
) |
1351 (xer_cmp
<< XER_CMP
);
1354 void ppc_store_xer (CPUPPCState
*env
, uint32_t value
)
1356 xer_so
= (value
>> XER_SO
) & 0x01;
1357 xer_ov
= (value
>> XER_OV
) & 0x01;
1358 xer_ca
= (value
>> XER_CA
) & 0x01;
1359 xer_cmp
= (value
>> XER_CMP
) & 0xFF;
1360 xer_bc
= (value
>> XER_BC
) & 0x7F;
1363 /* Swap temporary saved registers with GPRs */
1364 static inline void swap_gpr_tgpr (CPUPPCState
*env
)
1369 env
->gpr
[0] = env
->tgpr
[0];
1372 env
->gpr
[1] = env
->tgpr
[1];
1375 env
->gpr
[2] = env
->tgpr
[2];
1378 env
->gpr
[3] = env
->tgpr
[3];
1382 /* GDBstub can read and write MSR... */
1383 target_ulong
do_load_msr (CPUPPCState
*env
)
1386 #if defined (TARGET_PPC64)
1387 ((target_ulong
)msr_sf
<< MSR_SF
) |
1388 ((target_ulong
)msr_isf
<< MSR_ISF
) |
1389 ((target_ulong
)msr_hv
<< MSR_HV
) |
1391 ((target_ulong
)msr_ucle
<< MSR_UCLE
) |
1392 ((target_ulong
)msr_vr
<< MSR_VR
) | /* VR / SPE */
1393 ((target_ulong
)msr_ap
<< MSR_AP
) |
1394 ((target_ulong
)msr_sa
<< MSR_SA
) |
1395 ((target_ulong
)msr_key
<< MSR_KEY
) |
1396 ((target_ulong
)msr_pow
<< MSR_POW
) | /* POW / WE */
1397 ((target_ulong
)msr_tlb
<< MSR_TLB
) | /* TLB / TGPE / CE */
1398 ((target_ulong
)msr_ile
<< MSR_ILE
) |
1399 ((target_ulong
)msr_ee
<< MSR_EE
) |
1400 ((target_ulong
)msr_pr
<< MSR_PR
) |
1401 ((target_ulong
)msr_fp
<< MSR_FP
) |
1402 ((target_ulong
)msr_me
<< MSR_ME
) |
1403 ((target_ulong
)msr_fe0
<< MSR_FE0
) |
1404 ((target_ulong
)msr_se
<< MSR_SE
) | /* SE / DWE / UBLE */
1405 ((target_ulong
)msr_be
<< MSR_BE
) | /* BE / DE */
1406 ((target_ulong
)msr_fe1
<< MSR_FE1
) |
1407 ((target_ulong
)msr_al
<< MSR_AL
) |
1408 ((target_ulong
)msr_ip
<< MSR_IP
) |
1409 ((target_ulong
)msr_ir
<< MSR_IR
) | /* IR / IS */
1410 ((target_ulong
)msr_dr
<< MSR_DR
) | /* DR / DS */
1411 ((target_ulong
)msr_pe
<< MSR_PE
) | /* PE / EP */
1412 ((target_ulong
)msr_px
<< MSR_PX
) | /* PX / PMM */
1413 ((target_ulong
)msr_ri
<< MSR_RI
) |
1414 ((target_ulong
)msr_le
<< MSR_LE
);
1417 void do_store_msr (CPUPPCState
*env
, target_ulong value
)
1421 value
&= env
->msr_mask
;
1422 if (((value
>> MSR_IR
) & 1) != msr_ir
||
1423 ((value
>> MSR_DR
) & 1) != msr_dr
) {
1424 /* Flush all tlb when changing translation mode */
1426 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1429 if (loglevel
!= 0) {
1430 fprintf(logfile
, "%s: T0 %08lx\n", __func__
, value
);
1433 switch (PPC_EXCP(env
)) {
1434 case PPC_FLAGS_EXCP_602
:
1435 case PPC_FLAGS_EXCP_603
:
1436 if (((value
>> MSR_TGPR
) & 1) != msr_tgpr
) {
1437 /* Swap temporary saved registers with GPRs */
1444 #if defined (TARGET_PPC64)
1445 msr_sf
= (value
>> MSR_SF
) & 1;
1446 msr_isf
= (value
>> MSR_ISF
) & 1;
1447 msr_hv
= (value
>> MSR_HV
) & 1;
1449 msr_ucle
= (value
>> MSR_UCLE
) & 1;
1450 msr_vr
= (value
>> MSR_VR
) & 1; /* VR / SPE */
1451 msr_ap
= (value
>> MSR_AP
) & 1;
1452 msr_sa
= (value
>> MSR_SA
) & 1;
1453 msr_key
= (value
>> MSR_KEY
) & 1;
1454 msr_pow
= (value
>> MSR_POW
) & 1; /* POW / WE */
1455 msr_tlb
= (value
>> MSR_TLB
) & 1; /* TLB / TGPR / CE */
1456 msr_ile
= (value
>> MSR_ILE
) & 1;
1457 msr_ee
= (value
>> MSR_EE
) & 1;
1458 msr_pr
= (value
>> MSR_PR
) & 1;
1459 msr_fp
= (value
>> MSR_FP
) & 1;
1460 msr_me
= (value
>> MSR_ME
) & 1;
1461 msr_fe0
= (value
>> MSR_FE0
) & 1;
1462 msr_se
= (value
>> MSR_SE
) & 1; /* SE / DWE / UBLE */
1463 msr_be
= (value
>> MSR_BE
) & 1; /* BE / DE */
1464 msr_fe1
= (value
>> MSR_FE1
) & 1;
1465 msr_al
= (value
>> MSR_AL
) & 1;
1466 msr_ip
= (value
>> MSR_IP
) & 1;
1467 msr_ir
= (value
>> MSR_IR
) & 1; /* IR / IS */
1468 msr_dr
= (value
>> MSR_DR
) & 1; /* DR / DS */
1469 msr_pe
= (value
>> MSR_PE
) & 1; /* PE / EP */
1470 msr_px
= (value
>> MSR_PX
) & 1; /* PX / PMM */
1471 msr_ri
= (value
>> MSR_RI
) & 1;
1472 msr_le
= (value
>> MSR_LE
) & 1;
1473 do_compute_hflags(env
);
1476 switch (PPC_EXCP(env
)) {
1477 case PPC_FLAGS_EXCP_603
:
1478 /* Don't handle SLEEP mode: we should disable all clocks...
1479 * No dynamic power-management.
1481 if (msr_pow
== 1 && (env
->spr
[SPR_HID0
] & 0x00C00000) != 0)
1484 case PPC_FLAGS_EXCP_604
:
1488 case PPC_FLAGS_EXCP_7x0
:
1489 if (msr_pow
== 1 && (env
->spr
[SPR_HID0
] & 0x00E00000) != 0)
1496 if (likely(!env
->halted
)) {
1497 /* power save: exit cpu loop */
1499 env
->exception_index
= EXCP_HLT
;
1505 #if defined(TARGET_PPC64)
1506 void ppc_store_msr_32 (CPUPPCState
*env
, uint32_t value
)
1509 (do_load_msr(env
) & ~0xFFFFFFFFULL
) | (value
& 0xFFFFFFFF));
1513 void do_compute_hflags (CPUPPCState
*env
)
1515 /* Compute current hflags */
1516 env
->hflags
= (msr_cm
<< MSR_CM
) | (msr_vr
<< MSR_VR
) |
1517 (msr_ap
<< MSR_AP
) | (msr_sa
<< MSR_SA
) | (msr_pr
<< MSR_PR
) |
1518 (msr_fp
<< MSR_FP
) | (msr_fe0
<< MSR_FE0
) | (msr_se
<< MSR_SE
) |
1519 (msr_be
<< MSR_BE
) | (msr_fe1
<< MSR_FE1
) | (msr_le
<< MSR_LE
);
1520 #if defined (TARGET_PPC64)
1521 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
1522 env
->hflags
|= (msr_sf
<< (MSR_SF
- 32)) | (msr_hv
<< (MSR_HV
- 32));
1526 /*****************************************************************************/
1527 /* Exception processing */
1528 #if defined (CONFIG_USER_ONLY)
1529 void do_interrupt (CPUState
*env
)
1531 env
->exception_index
= -1;
1534 void ppc_hw_interrupt (CPUState
*env
)
1536 env
->exception_index
= -1;
1538 #else /* defined (CONFIG_USER_ONLY) */
1539 static void dump_syscall(CPUState
*env
)
1541 fprintf(logfile
, "syscall r0=0x" REGX
" r3=0x" REGX
" r4=0x" REGX
1542 " r5=0x" REGX
" r6=0x" REGX
" nip=0x" ADDRX
"\n",
1543 env
->gpr
[0], env
->gpr
[3], env
->gpr
[4],
1544 env
->gpr
[5], env
->gpr
[6], env
->nip
);
1547 void do_interrupt (CPUState
*env
)
1549 target_ulong msr
, *srr_0
, *srr_1
, *asrr_0
, *asrr_1
;
1552 excp
= env
->exception_index
;
1553 msr
= do_load_msr(env
);
1554 /* The default is to use SRR0 & SRR1 to save the exception context */
1555 srr_0
= &env
->spr
[SPR_SRR0
];
1556 srr_1
= &env
->spr
[SPR_SRR1
];
1559 #if defined (DEBUG_EXCEPTIONS)
1560 if ((excp
== EXCP_PROGRAM
|| excp
== EXCP_DSI
) && msr_pr
== 1) {
1561 if (loglevel
!= 0) {
1563 "Raise exception at 0x" ADDRX
" => 0x%08x (%02x)\n",
1564 env
->nip
, excp
, env
->error_code
);
1565 cpu_dump_state(env
, logfile
, fprintf
, 0);
1569 if (loglevel
& CPU_LOG_INT
) {
1570 fprintf(logfile
, "Raise exception at 0x" ADDRX
" => 0x%08x (%02x)\n",
1571 env
->nip
, excp
, env
->error_code
);
1575 /* Generate informations in save/restore registers */
1577 /* Generic PowerPC exceptions */
1578 case EXCP_RESET
: /* 0x0100 */
1579 switch (PPC_EXCP(env
)) {
1580 case PPC_FLAGS_EXCP_40x
:
1581 srr_0
= &env
->spr
[SPR_40x_SRR2
];
1582 srr_1
= &env
->spr
[SPR_40x_SRR3
];
1584 case PPC_FLAGS_EXCP_BOOKE
:
1586 srr_0
= &env
->spr
[SPR_BOOKE_CSRR0
];
1587 srr_1
= &env
->spr
[SPR_BOOKE_CSRR1
];
1596 case EXCP_MACHINE_CHECK
: /* 0x0200 */
1597 switch (PPC_EXCP(env
)) {
1598 case PPC_FLAGS_EXCP_40x
:
1599 srr_0
= &env
->spr
[SPR_40x_SRR2
];
1600 srr_1
= &env
->spr
[SPR_40x_SRR3
];
1602 case PPC_FLAGS_EXCP_BOOKE
:
1604 srr_0
= &env
->spr
[SPR_BOOKE_MCSRR0
];
1605 srr_1
= &env
->spr
[SPR_BOOKE_MCSRR1
];
1606 asrr_0
= &env
->spr
[SPR_BOOKE_CSRR0
];
1607 asrr_1
= &env
->spr
[SPR_BOOKE_CSRR1
];
1615 case EXCP_DSI
: /* 0x0300 */
1616 /* Store exception cause */
1617 /* data location address has been stored
1618 * when the fault has been detected
1622 #if defined (DEBUG_EXCEPTIONS)
1623 if (loglevel
!= 0) {
1624 fprintf(logfile
, "DSI exception: DSISR=0x" ADDRX
" DAR=0x" ADDRX
1625 "\n", env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
1629 case EXCP_ISI
: /* 0x0400 */
1630 /* Store exception cause */
1633 msr
|= env
->error_code
;
1634 #if defined (DEBUG_EXCEPTIONS)
1635 if (loglevel
!= 0) {
1636 fprintf(logfile
, "ISI exception: msr=0x" ADDRX
", nip=0x" ADDRX
1637 "\n", msr
, env
->nip
);
1641 case EXCP_EXTERNAL
: /* 0x0500 */
1644 case EXCP_ALIGN
: /* 0x0600 */
1645 if (likely(PPC_EXCP(env
) != PPC_FLAGS_EXCP_601
)) {
1646 /* Store exception cause */
1648 /* Get rS/rD and rA from faulting opcode */
1649 env
->spr
[SPR_DSISR
] |=
1650 (ldl_code((env
->nip
- 4)) & 0x03FF0000) >> 16;
1651 /* data location address has been stored
1652 * when the fault has been detected
1655 /* IO error exception on PowerPC 601 */
1658 "601 IO error exception is not implemented yet !\n");
1661 case EXCP_PROGRAM
: /* 0x0700 */
1664 switch (env
->error_code
& ~0xF) {
1666 if (msr_fe0
== 0 && msr_fe1
== 0) {
1667 #if defined (DEBUG_EXCEPTIONS)
1668 if (loglevel
!= 0) {
1669 fprintf(logfile
, "Ignore floating point exception\n");
1676 env
->fpscr
[7] |= 0x8;
1677 /* Finally, update FEX */
1678 if ((((env
->fpscr
[7] & 0x3) << 3) | (env
->fpscr
[6] >> 1)) &
1679 ((env
->fpscr
[1] << 1) | (env
->fpscr
[0] >> 3)))
1680 env
->fpscr
[7] |= 0x4;
1683 #if defined (DEBUG_EXCEPTIONS)
1684 if (loglevel
!= 0) {
1685 fprintf(logfile
, "Invalid instruction at 0x" ADDRX
"\n",
1699 /* Should never occur */
1704 case EXCP_NO_FP
: /* 0x0800 */
1710 case EXCP_SYSCALL
: /* 0x0C00 */
1712 /* NOTE: this is a temporary hack to support graphics OSI
1713 calls from the MOL driver */
1714 if (env
->gpr
[3] == 0x113724fa && env
->gpr
[4] == 0x77810f9b &&
1716 if (env
->osi_call(env
) != 0)
1719 if (loglevel
& CPU_LOG_INT
) {
1723 case EXCP_TRACE
: /* 0x0D00 */
1725 case EXCP_PERF
: /* 0x0F00 */
1728 "Performance counter exception is not implemented yet !\n");
1730 /* 32 bits PowerPC specific exceptions */
1731 case EXCP_FP_ASSIST
: /* 0x0E00 */
1733 cpu_abort(env
, "Floating point assist exception "
1734 "is not implemented yet !\n");
1736 /* 64 bits PowerPC exceptions */
1737 case EXCP_DSEG
: /* 0x0380 */
1739 cpu_abort(env
, "Data segment exception is not implemented yet !\n");
1741 case EXCP_ISEG
: /* 0x0480 */
1744 "Instruction segment exception is not implemented yet !\n");
1746 case EXCP_HDECR
: /* 0x0980 */
1748 cpu_abort(env
, "Hypervisor decrementer exception is not implemented "
1751 /* Implementation specific exceptions */
1753 if (likely(env
->spr
[SPR_PVR
] == CPU_PPC_G2
||
1754 env
->spr
[SPR_PVR
] == CPU_PPC_G2LE
)) {
1755 /* Critical interrupt on G2 */
1757 cpu_abort(env
, "G2 critical interrupt is not implemented yet !\n");
1760 cpu_abort(env
, "Invalid exception 0x0A00 !\n");
1765 switch (PPC_EXCP(env
)) {
1766 case PPC_FLAGS_EXCP_40x
:
1767 /* APU unavailable on 405 */
1770 "APU unavailable exception is not implemented yet !\n");
1772 case PPC_FLAGS_EXCP_74xx
:
1773 /* Altivec unavailable */
1775 cpu_abort(env
, "Altivec unavailable exception "
1776 "is not implemented yet !\n");
1779 cpu_abort(env
, "Invalid exception 0x0F20 !\n");
1785 switch (PPC_EXCP(env
)) {
1786 case PPC_FLAGS_EXCP_40x
:
1789 #if defined (DEBUG_EXCEPTIONS)
1791 fprintf(logfile
, "PIT exception\n");
1794 case PPC_FLAGS_EXCP_602
:
1795 case PPC_FLAGS_EXCP_603
:
1796 /* ITLBMISS on 602/603 */
1798 case PPC_FLAGS_EXCP_7x5
:
1799 /* ITLBMISS on 745/755 */
1802 cpu_abort(env
, "Invalid exception 0x1000 !\n");
1808 switch (PPC_EXCP(env
)) {
1809 case PPC_FLAGS_EXCP_40x
:
1812 #if defined (DEBUG_EXCEPTIONS)
1814 fprintf(logfile
, "FIT exception\n");
1818 cpu_abort(env
, "Invalid exception 0x1010 !\n");
1824 switch (PPC_EXCP(env
)) {
1825 case PPC_FLAGS_EXCP_40x
:
1826 /* Watchdog on 4xx */
1828 #if defined (DEBUG_EXCEPTIONS)
1830 fprintf(logfile
, "WDT exception\n");
1833 case PPC_FLAGS_EXCP_BOOKE
:
1834 srr_0
= &env
->spr
[SPR_BOOKE_CSRR0
];
1835 srr_1
= &env
->spr
[SPR_BOOKE_CSRR1
];
1838 cpu_abort(env
, "Invalid exception 0x1020 !\n");
1844 switch (PPC_EXCP(env
)) {
1845 case PPC_FLAGS_EXCP_40x
:
1846 /* DTLBMISS on 4xx */
1849 case PPC_FLAGS_EXCP_602
:
1850 case PPC_FLAGS_EXCP_603
:
1851 /* DLTLBMISS on 602/603 */
1853 case PPC_FLAGS_EXCP_7x5
:
1854 /* DLTLBMISS on 745/755 */
1857 cpu_abort(env
, "Invalid exception 0x1100 !\n");
1863 switch (PPC_EXCP(env
)) {
1864 case PPC_FLAGS_EXCP_40x
:
1865 /* ITLBMISS on 4xx */
1868 case PPC_FLAGS_EXCP_602
:
1869 case PPC_FLAGS_EXCP_603
:
1870 /* DSTLBMISS on 602/603 */
1872 /* Swap temporary saved registers with GPRs */
1875 #if defined (DEBUG_SOFTWARE_TLB)
1876 if (loglevel
!= 0) {
1877 const unsigned char *es
;
1878 target_ulong
*miss
, *cmp
;
1880 if (excp
== 0x1000) {
1883 miss
= &env
->spr
[SPR_IMISS
];
1884 cmp
= &env
->spr
[SPR_ICMP
];
1891 miss
= &env
->spr
[SPR_DMISS
];
1892 cmp
= &env
->spr
[SPR_DCMP
];
1894 fprintf(logfile
, "6xx %sTLB miss: %cM " ADDRX
" %cC " ADDRX
1895 " H1 " ADDRX
" H2 " ADDRX
" %08x\n",
1896 es
, en
, *miss
, en
, *cmp
,
1897 env
->spr
[SPR_HASH1
], env
->spr
[SPR_HASH2
],
1902 case PPC_FLAGS_EXCP_7x5
:
1903 /* DSTLBMISS on 745/755 */
1906 msr
|= env
->crf
[0] << 28;
1907 msr
|= env
->error_code
; /* key, D/I, S/L bits */
1908 /* Set way using a LRU mechanism */
1909 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
1912 cpu_abort(env
, "Invalid exception 0x1200 !\n");
1917 switch (PPC_EXCP(env
)) {
1918 case PPC_FLAGS_EXCP_601
:
1919 case PPC_FLAGS_EXCP_602
:
1920 case PPC_FLAGS_EXCP_603
:
1921 case PPC_FLAGS_EXCP_604
:
1922 case PPC_FLAGS_EXCP_7x0
:
1923 case PPC_FLAGS_EXCP_7x5
:
1924 /* IABR on 6xx/7xx */
1926 cpu_abort(env
, "IABR exception is not implemented yet !\n");
1929 cpu_abort(env
, "Invalid exception 0x1300 !\n");
1934 switch (PPC_EXCP(env
)) {
1935 case PPC_FLAGS_EXCP_601
:
1936 case PPC_FLAGS_EXCP_602
:
1937 case PPC_FLAGS_EXCP_603
:
1938 case PPC_FLAGS_EXCP_604
:
1939 case PPC_FLAGS_EXCP_7x0
:
1940 case PPC_FLAGS_EXCP_7x5
:
1941 /* SMI on 6xx/7xx */
1943 cpu_abort(env
, "SMI exception is not implemented yet !\n");
1946 cpu_abort(env
, "Invalid exception 0x1400 !\n");
1951 switch (PPC_EXCP(env
)) {
1952 case PPC_FLAGS_EXCP_602
:
1953 /* Watchdog on 602 */
1956 "602 watchdog exception is not implemented yet !\n");
1958 case PPC_FLAGS_EXCP_970
:
1959 /* Soft patch exception on 970 */
1962 "970 soft-patch exception is not implemented yet !\n");
1964 case PPC_FLAGS_EXCP_74xx
:
1965 /* VPU assist on 74xx */
1967 cpu_abort(env
, "VPU assist exception is not implemented yet !\n");
1970 cpu_abort(env
, "Invalid exception 0x1500 !\n");
1975 switch (PPC_EXCP(env
)) {
1976 case PPC_FLAGS_EXCP_602
:
1977 /* Emulation trap on 602 */
1979 cpu_abort(env
, "602 emulation trap exception "
1980 "is not implemented yet !\n");
1982 case PPC_FLAGS_EXCP_970
:
1983 /* Maintenance exception on 970 */
1986 "970 maintenance exception is not implemented yet !\n");
1989 cpu_abort(env
, "Invalid exception 0x1600 !\n");
1994 switch (PPC_EXCP(env
)) {
1995 case PPC_FLAGS_EXCP_7x0
:
1996 case PPC_FLAGS_EXCP_7x5
:
1997 /* Thermal management interrupt on G3 */
1999 cpu_abort(env
, "G3 thermal management exception "
2000 "is not implemented yet !\n");
2002 case PPC_FLAGS_EXCP_970
:
2003 /* VPU assist on 970 */
2006 "970 VPU assist exception is not implemented yet !\n");
2009 cpu_abort(env
, "Invalid exception 0x1700 !\n");
2014 switch (PPC_EXCP(env
)) {
2015 case PPC_FLAGS_EXCP_970
:
2016 /* Thermal exception on 970 */
2018 cpu_abort(env
, "970 thermal management exception "
2019 "is not implemented yet !\n");
2022 cpu_abort(env
, "Invalid exception 0x1800 !\n");
2027 switch (PPC_EXCP(env
)) {
2028 case PPC_FLAGS_EXCP_40x
:
2031 cpu_abort(env
, "40x debug exception is not implemented yet !\n");
2033 case PPC_FLAGS_EXCP_601
:
2034 /* Run mode exception on 601 */
2037 "601 run mode exception is not implemented yet !\n");
2039 case PPC_FLAGS_EXCP_BOOKE
:
2040 srr_0
= &env
->spr
[SPR_BOOKE_CSRR0
];
2041 srr_1
= &env
->spr
[SPR_BOOKE_CSRR1
];
2044 cpu_abort(env
, "Invalid exception 0x1800 !\n");
2048 /* Other exceptions */
2049 /* Qemu internal exceptions:
2050 * we should never come here with those values: abort execution
2053 cpu_abort(env
, "Invalid exception: code %d (%04x)\n", excp
, excp
);
2056 /* save current instruction location */
2057 *srr_0
= env
->nip
- 4;
2060 /* save next instruction location */
2070 /* If we disactivated any translation, flush TLBs */
2071 if (msr_ir
|| msr_dr
) {
2074 /* reload MSR with correct bits */
2086 if (PPC_EXCP(env
) == PPC_FLAGS_EXCP_BOOKE
) {
2088 if (idx
== -1 || (idx
>= 16 && idx
< 32)) {
2089 cpu_abort(env
, "Invalid exception index for excp %d %08x idx %d\n",
2092 #if defined(TARGET_PPC64)
2094 env
->nip
= (uint64_t)env
->spr
[SPR_BOOKE_IVPR
];
2097 env
->nip
= (uint32_t)env
->spr
[SPR_BOOKE_IVPR
];
2099 env
->nip
|= env
->spr
[SPR_BOOKE_IVOR0
+ idx
];
2101 env
->nip
|= env
->spr
[SPR_BOOKE_IVOR32
+ idx
- 32];
2106 do_compute_hflags(env
);
2107 /* Jump to handler */
2108 env
->exception_index
= EXCP_NONE
;
2111 void ppc_hw_interrupt (CPUPPCState
*env
)
2116 if (loglevel
& CPU_LOG_INT
) {
2117 fprintf(logfile
, "%s: %p pending %08x req %08x me %d ee %d\n",
2118 __func__
, env
, env
->pending_interrupts
,
2119 env
->interrupt_request
, msr_me
, msr_ee
);
2123 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_RESET
)) {
2124 /* External reset / critical input */
2125 /* XXX: critical input should be handled another way.
2126 * This code is not correct !
2128 env
->exception_index
= EXCP_RESET
;
2129 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_RESET
);
2132 if (raised
== 0 && msr_me
!= 0) {
2133 /* Machine check exception */
2134 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_MCK
)) {
2135 env
->exception_index
= EXCP_MACHINE_CHECK
;
2136 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_MCK
);
2140 if (raised
== 0 && msr_ee
!= 0) {
2141 #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2142 /* Hypervisor decrementer exception */
2143 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_HDECR
)) {
2144 env
->exception_index
= EXCP_HDECR
;
2145 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_HDECR
);
2149 /* Decrementer exception */
2150 if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DECR
)) {
2151 env
->exception_index
= EXCP_DECR
;
2152 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DECR
);
2154 /* Programmable interval timer on embedded PowerPC */
2155 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_PIT
)) {
2156 env
->exception_index
= EXCP_40x_PIT
;
2157 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_PIT
);
2159 /* Fixed interval timer on embedded PowerPC */
2160 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_FIT
)) {
2161 env
->exception_index
= EXCP_40x_FIT
;
2162 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_FIT
);
2164 /* Watchdog timer on embedded PowerPC */
2165 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_WDT
)) {
2166 env
->exception_index
= EXCP_40x_WATCHDOG
;
2167 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_WDT
);
2169 /* External interrupt */
2170 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_EXT
)) {
2171 env
->exception_index
= EXCP_EXTERNAL
;
2172 /* Taking an external interrupt does not clear the external
2176 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_EXT
);
2180 /* Thermal interrupt */
2181 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_THERM
)) {
2182 env
->exception_index
= EXCP_970_THRM
;
2183 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_THERM
);
2188 /* External debug exception */
2189 } else if (env
->pending_interrupts
& (1 << PPC_INTERRUPT_DEBUG
)) {
2190 env
->exception_index
= EXCP_xxx
;
2191 env
->pending_interrupts
&= ~(1 << PPC_INTERRUPT_DEBUG
);
2196 env
->error_code
= 0;
2200 #endif /* !CONFIG_USER_ONLY */
2202 void cpu_dump_EA (target_ulong EA
)
2212 fprintf(f
, "Memory access at address " ADDRX
"\n", EA
);
2215 void cpu_dump_rfi (target_ulong RA
, target_ulong msr
)
2225 fprintf(f
, "Return from exception at " ADDRX
" with flags " ADDRX
"\n",
2229 void cpu_ppc_reset (void *opaque
)
2234 #if defined (DO_SINGLE_STEP) && 0
2235 /* Single step trace mode */
2239 msr_fp
= 1; /* Allow floating point exceptions */
2240 msr_me
= 1; /* Allow machine check exceptions */
2241 #if defined(TARGET_PPC64)
2242 msr_sf
= 0; /* Boot in 32 bits mode */
2245 #if defined(CONFIG_USER_ONLY)
2249 env
->nip
= 0xFFFFFFFC;
2250 ppc_tlb_invalidate_all(env
);
2252 do_compute_hflags(env
);
2256 CPUPPCState
*cpu_ppc_init (void)
2260 env
= qemu_mallocz(sizeof(CPUPPCState
));
2269 void cpu_ppc_close (CPUPPCState
*env
)
2271 /* Should also remove all opcode tables... */