target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 #define TARGET_HAS_ICE 1
   5
   6 #define ELF_MACHINE     EM_MIPS
   7
   8 #include "config.h"
   9 #include "mips-defs.h"
  10 #include "cpu-defs.h"
  11 #include "softfloat.h"
  12
  13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
  14 // XXX: move that elsewhere
  15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
  16 typedef unsigned char           uint_fast8_t;
  17 typedef unsigned int            uint_fast16_t;
  18 #endif
  19
  20 typedef union fpr_t fpr_t;
  21 union fpr_t {
  22     float64  fd;   /* ieee double precision */
  23     float32  fs[2];/* ieee single precision */
  24     uint64_t d;    /* binary double fixed-point */
  25     uint32_t w[2]; /* binary single fixed-point */
  26 };
  27 /* define FP_ENDIAN_IDX to access the same location
  28  * in the fpr_t union regardless of the host endianess
  29  */
  30 #if defined(WORDS_BIGENDIAN)
  31 #  define FP_ENDIAN_IDX 1
  32 #else
  33 #  define FP_ENDIAN_IDX 0
  34 #endif
  35
  36 typedef struct r4k_tlb_t r4k_tlb_t;
  37 struct r4k_tlb_t {
  38     target_ulong VPN;
  39     uint32_t PageMask;
  40     uint_fast8_t ASID;
  41     uint_fast16_t G:1;
  42     uint_fast16_t C0:3;
  43     uint_fast16_t C1:3;
  44     uint_fast16_t V0:1;
  45     uint_fast16_t V1:1;
  46     uint_fast16_t D0:1;
  47     uint_fast16_t D1:1;
  48     target_ulong PFN[2];
  49 };
  50
  51 typedef struct mips_def_t mips_def_t;
  52
  53 typedef struct CPUMIPSState CPUMIPSState;
  54 struct CPUMIPSState {
  55     /* General integer registers */
  56     target_ulong gpr[32];
  57     /* Special registers */
  58     target_ulong PC;
  59 #if TARGET_LONG_BITS > HOST_LONG_BITS
  60     target_ulong t0;
  61     target_ulong t1;
  62     target_ulong t2;
  63 #endif
  64     target_ulong HI, LO;
  65     /* Floating point registers */
  66     fpr_t fpr[32];
  67 #ifndef USE_HOST_FLOAT_REGS
  68     fpr_t ft0;
  69     fpr_t ft1;
  70     fpr_t ft2;
  71 #endif
  72     float_status fp_status;
  73     /* fpu implementation/revision register (fir) */
  74     uint32_t fcr0;
  75 #define FCR0_F64 22
  76 #define FCR0_L 21
  77 #define FCR0_W 20
  78 #define FCR0_3D 19
  79 #define FCR0_PS 18
  80 #define FCR0_D 17
  81 #define FCR0_S 16
  82 #define FCR0_PRID 8
  83 #define FCR0_REV 0
  84     /* fcsr */
  85     uint32_t fcr31;
  86 #define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  87 #define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  88 #define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
  89 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  90 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  91 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  92 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  93 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  94 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  95 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  96 #define FP_INEXACT        1
  97 #define FP_UNDERFLOW      2
  98 #define FP_OVERFLOW       4
  99 #define FP_DIV0           8
 100 #define FP_INVALID        16
 101 #define FP_UNIMPLEMENTED  32
 102
 103     uint32_t nb_tlb;
 104     uint32_t tlb_in_use;
 105     uint32_t SEGBITS;
 106     target_ulong SEGMask;
 107     int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
 108     void (*do_tlbwi) (void);
 109     void (*do_tlbwr) (void);
 110     void (*do_tlbp) (void);
 111     void (*do_tlbr) (void);
 112     union {
 113         struct {
 114             r4k_tlb_t tlb[MIPS_TLB_MAX];
 115         } r4k;
 116     } mmu;
 117
 118     int32_t CP0_Index;
 119     int32_t CP0_Random;
 120     target_ulong CP0_EntryLo0;
 121     target_ulong CP0_EntryLo1;
 122     target_ulong CP0_Context;
 123     int32_t CP0_PageMask;
 124     int32_t CP0_PageGrain;
 125     int32_t CP0_Wired;
 126     int32_t CP0_HWREna;
 127     target_ulong CP0_BadVAddr;
 128     int32_t CP0_Count;
 129     target_ulong CP0_EntryHi;
 130     int32_t CP0_Compare;
 131     int32_t CP0_Status;
 132 #define CP0St_CU3   31
 133 #define CP0St_CU2   30
 134 #define CP0St_CU1   29
 135 #define CP0St_CU0   28
 136 #define CP0St_RP    27
 137 #define CP0St_FR    26
 138 #define CP0St_RE    25
 139 #define CP0St_MX    24
 140 #define CP0St_PX    23
 141 #define CP0St_BEV   22
 142 #define CP0St_TS    21
 143 #define CP0St_SR    20
 144 #define CP0St_NMI   19
 145 #define CP0St_IM    8
 146 #define CP0St_KX    7
 147 #define CP0St_SX    6
 148 #define CP0St_UX    5
 149 #define CP0St_UM    4
 150 #define CP0St_R0    3
 151 #define CP0St_ERL   2
 152 #define CP0St_EXL   1
 153 #define CP0St_IE    0
 154     int32_t CP0_IntCtl;
 155     int32_t CP0_SRSCtl;
 156     int32_t CP0_SRSMap;
 157     int32_t CP0_Cause;
 158 #define CP0Ca_BD   31
 159 #define CP0Ca_TI   30
 160 #define CP0Ca_CE   28
 161 #define CP0Ca_DC   27
 162 #define CP0Ca_PCI  26
 163 #define CP0Ca_IV   23
 164 #define CP0Ca_WP   22
 165 #define CP0Ca_IP    8
 166 #define CP0Ca_IP_mask 0x0000FF00
 167 #define CP0Ca_EC    2
 168     target_ulong CP0_EPC;
 169     int32_t CP0_PRid;
 170     int32_t CP0_EBase;
 171     int32_t CP0_Config0;
 172 #define CP0C0_M    31
 173 #define CP0C0_K23  28
 174 #define CP0C0_KU   25
 175 #define CP0C0_MDU  20
 176 #define CP0C0_MM   17
 177 #define CP0C0_BM   16
 178 #define CP0C0_BE   15
 179 #define CP0C0_AT   13
 180 #define CP0C0_AR   10
 181 #define CP0C0_MT   7
 182 #define CP0C0_VI   3
 183 #define CP0C0_K0   0
 184     int32_t CP0_Config1;
 185 #define CP0C1_M    31
 186 #define CP0C1_MMU  25
 187 #define CP0C1_IS   22
 188 #define CP0C1_IL   19
 189 #define CP0C1_IA   16
 190 #define CP0C1_DS   13
 191 #define CP0C1_DL   10
 192 #define CP0C1_DA   7
 193 #define CP0C1_C2   6
 194 #define CP0C1_MD   5
 195 #define CP0C1_PC   4
 196 #define CP0C1_WR   3
 197 #define CP0C1_CA   2
 198 #define CP0C1_EP   1
 199 #define CP0C1_FP   0
 200     int32_t CP0_Config2;
 201 #define CP0C2_M    31
 202 #define CP0C2_TU   28
 203 #define CP0C2_TS   24
 204 #define CP0C2_TL   20
 205 #define CP0C2_TA   16
 206 #define CP0C2_SU   12
 207 #define CP0C2_SS   8
 208 #define CP0C2_SL   4
 209 #define CP0C2_SA   0
 210     int32_t CP0_Config3;
 211 #define CP0C3_M    31
 212 #define CP0C3_DSPP 10
 213 #define CP0C3_LPA  7
 214 #define CP0C3_VEIC 6
 215 #define CP0C3_VInt 5
 216 #define CP0C3_SP   4
 217 #define CP0C3_MT   2
 218 #define CP0C3_SM   1
 219 #define CP0C3_TL   0
 220     int32_t CP0_Config6;
 221     int32_t CP0_Config7;
 222     target_ulong CP0_LLAddr;
 223     target_ulong CP0_WatchLo[8];
 224     int32_t CP0_WatchHi[8];
 225     target_ulong CP0_XContext;
 226     int32_t CP0_Framemask;
 227     int32_t CP0_Debug;
 228 #define CPDB_DBD   31
 229 #define CP0DB_DM   30
 230 #define CP0DB_LSNM 28
 231 #define CP0DB_Doze 27
 232 #define CP0DB_Halt 26
 233 #define CP0DB_CNT  25
 234 #define CP0DB_IBEP 24
 235 #define CP0DB_DBEP 21
 236 #define CP0DB_IEXI 20
 237 #define CP0DB_VER  15
 238 #define CP0DB_DEC  10
 239 #define CP0DB_SSt  8
 240 #define CP0DB_DINT 5
 241 #define CP0DB_DIB  4
 242 #define CP0DB_DDBS 3
 243 #define CP0DB_DDBL 2
 244 #define CP0DB_DBp  1
 245 #define CP0DB_DSS  0
 246     target_ulong CP0_DEPC;
 247     int32_t CP0_Performance0;
 248     int32_t CP0_TagLo;
 249     int32_t CP0_DataLo;
 250     int32_t CP0_TagHi;
 251     int32_t CP0_DataHi;
 252     target_ulong CP0_ErrorEPC;
 253     int32_t CP0_DESAVE;
 254     /* Qemu */
 255     int interrupt_request;
 256     jmp_buf jmp_env;
 257     int exception_index;
 258     int error_code;
 259     int user_mode_only; /* user mode only simulation */
 260     uint32_t hflags;    /* CPU State */
 261     /* TMASK defines different execution modes */
 262 #define MIPS_HFLAG_TMASK  0x007F
 263 #define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
 264 #define MIPS_HFLAG_UM     0x0001 /* user mode                          */
 265 #define MIPS_HFLAG_DM     0x0002 /* Debug mode                         */
 266 #define MIPS_HFLAG_SM     0x0004 /* Supervisor mode                    */
 267 #define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
 268 #define MIPS_HFLAG_FPU    0x0010 /* FPU enabled                        */
 269 #define MIPS_HFLAG_F64    0x0020 /* 64-bit FPU enabled                 */
 270 #define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */
 271     /* If translation is interrupted between the branch instruction and
 272      * the delay slot, record what type of branch it is so that we can
 273      * resume translation properly.  It might be possible to reduce
 274      * this from three bits to two.  */
 275 #define MIPS_HFLAG_BMASK  0x0380
 276 #define MIPS_HFLAG_B      0x0080 /* Unconditional branch               */
 277 #define MIPS_HFLAG_BC     0x0100 /* Conditional branch                 */
 278 #define MIPS_HFLAG_BL     0x0180 /* Likely branch                      */
 279 #define MIPS_HFLAG_BR     0x0200 /* branch to register (can't link TB) */
 280     target_ulong btarget;        /* Jump / branch target               */
 281     int bcond;                   /* Branch condition (if needed)       */
 282
 283     int halted; /* TRUE if the CPU is in suspend state */
 284
 285     int SYNCI_Step; /* Address step size for SYNCI */
 286     int CCRes; /* Cycle count resolution/divisor */
 287     int Status_rw_bitmask; /* Read/write bits in CP0_Status */
 288
 289 #ifdef CONFIG_USER_ONLY
 290     target_ulong tls_value;
 291 #endif
 292
 293     CPU_COMMON
 294
 295     int ram_size;
 296     const char *kernel_filename;
 297     const char *kernel_cmdline;
 298     const char *initrd_filename;
 299
 300     mips_def_t *cpu_model;
 301 #ifndef CONFIG_USER_ONLY
 302     void *irq[8];
 303 #endif
 304
 305     struct QEMUTimer *timer; /* Internal timer */
 306 };
 307
 308 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 309                         target_ulong address, int rw, int access_type);
 310 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 311                            target_ulong address, int rw, int access_type);
 312 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 313                      target_ulong address, int rw, int access_type);
 314 void r4k_do_tlbwi (void);
 315 void r4k_do_tlbwr (void);
 316 void r4k_do_tlbp (void);
 317 void r4k_do_tlbr (void);
 318 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
 319 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 320 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
 321
 322 #define CPUState CPUMIPSState
 323 #define cpu_init cpu_mips_init
 324 #define cpu_exec cpu_mips_exec
 325 #define cpu_gen_code cpu_mips_gen_code
 326 #define cpu_signal_handler cpu_mips_signal_handler
 327
 328 #include "cpu-all.h"
 329
 330 /* Memory access type :
 331  * may be needed for precise access rights control and precise exceptions.
 332  */
 333 enum {
 334     /* 1 bit to define user level / supervisor access */
 335     ACCESS_USER  = 0x00,
 336     ACCESS_SUPER = 0x01,
 337     /* 1 bit to indicate direction */
 338     ACCESS_STORE = 0x02,
 339     /* Type of instruction that generated the access */
 340     ACCESS_CODE  = 0x10, /* Code fetch access                */
 341     ACCESS_INT   = 0x20, /* Integer load/store access        */
 342     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 343 };
 344
 345 /* Exceptions */
 346 enum {
 347     EXCP_NONE          = -1,
 348     EXCP_RESET         = 0,
 349     EXCP_SRESET,
 350     EXCP_DSS,
 351     EXCP_DINT,
 352     EXCP_NMI,
 353     EXCP_MCHECK,
 354     EXCP_EXT_INTERRUPT,
 355     EXCP_DFWATCH,
 356     EXCP_DIB, /* 8 */
 357     EXCP_IWATCH,
 358     EXCP_AdEL,
 359     EXCP_AdES,
 360     EXCP_TLBF,
 361     EXCP_IBE,
 362     EXCP_DBp,
 363     EXCP_SYSCALL,
 364     EXCP_BREAK, /* 16 */
 365     EXCP_CpU,
 366     EXCP_RI,
 367     EXCP_OVERFLOW,
 368     EXCP_TRAP,
 369     EXCP_FPE,
 370     EXCP_DDBS,
 371     EXCP_DWATCH,
 372     EXCP_LAE, /* 24 */
 373     EXCP_SAE,
 374     EXCP_LTLBL,
 375     EXCP_TLBL,
 376     EXCP_TLBS,
 377     EXCP_DBE,
 378     EXCP_DDBL,
 379     EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */
 380                                 /* may change privilege level       */
 381     EXCP_BRANCH        = 0x108, /* branch instruction               */
 382     EXCP_ERET          = 0x10C, /* return from interrupt            */
 383     EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
 384     EXCP_FLUSH         = 0x109,
 385 };
 386
 387 int cpu_mips_exec(CPUMIPSState *s);
 388 CPUMIPSState *cpu_mips_init(void);
 389 uint32_t cpu_mips_get_clock (void);
 390 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 391
 392 #endif /* !defined (__MIPS_CPU_H__) */