Replace tabs by 8 spaces. No code change, by Herve Poussineau.
[qemu/dscho.git] / hw / slavio_timer.c
blob2ade17788e248c2afdceeaa6dbfe372aa0c02bf7
1 /*
2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "vl.h"
26 //#define DEBUG_TIMER
28 #ifdef DEBUG_TIMER
29 #define DPRINTF(fmt, args...) \
30 do { printf("TIMER: " fmt , ##args); } while (0)
31 #else
32 #define DPRINTF(fmt, args...)
33 #endif
36 * Registers of hardware timer in sun4m.
38 * This is the timer/counter part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
43 * are zero. Bit 31 is 1 when count has been reached.
45 * Per-CPU timers interrupt local CPU, system timer uses normal
46 * interrupt routing.
50 typedef struct SLAVIO_TIMERState {
51 qemu_irq irq;
52 ptimer_state *timer;
53 uint32_t count, counthigh, reached;
54 uint64_t limit;
55 int stopped;
56 int mode; // 0 = processor, 1 = user, 2 = system
57 } SLAVIO_TIMERState;
59 #define TIMER_MAXADDR 0x1f
60 #define TIMER_SIZE (TIMER_MAXADDR + 1)
62 // Update count, set irq, update expire_time
63 // Convert from ptimer countdown units
64 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
66 uint64_t count;
68 count = s->limit - (ptimer_get_count(s->timer) << 9);
69 DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
70 s->count);
71 s->count = count & 0xfffffe00;
72 s->counthigh = count >> 32;
75 // timer callback
76 static void slavio_timer_irq(void *opaque)
78 SLAVIO_TIMERState *s = opaque;
80 slavio_timer_get_out(s);
81 DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
82 s->reached = 0x80000000;
83 if (s->mode != 1)
84 qemu_irq_raise(s->irq);
87 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
89 SLAVIO_TIMERState *s = opaque;
90 uint32_t saddr, ret;
92 saddr = (addr & TIMER_MAXADDR) >> 2;
93 switch (saddr) {
94 case 0:
95 // read limit (system counter mode) or read most signifying
96 // part of counter (user mode)
97 if (s->mode != 1) {
98 // clear irq
99 qemu_irq_lower(s->irq);
100 s->reached = 0;
101 ret = s->limit & 0x7fffffff;
103 else {
104 slavio_timer_get_out(s);
105 ret = s->counthigh & 0x7fffffff;
107 break;
108 case 1:
109 // read counter and reached bit (system mode) or read lsbits
110 // of counter (user mode)
111 slavio_timer_get_out(s);
112 if (s->mode != 1)
113 ret = (s->count & 0x7fffffff) | s->reached;
114 else
115 ret = s->count;
116 break;
117 case 3:
118 // read start/stop status
119 ret = s->stopped;
120 break;
121 case 4:
122 // read user/system mode
123 ret = s->mode & 1;
124 break;
125 default:
126 ret = 0;
127 break;
129 DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
131 return ret;
134 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
136 SLAVIO_TIMERState *s = opaque;
137 uint32_t saddr;
138 int reload = 0;
140 DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
141 saddr = (addr & TIMER_MAXADDR) >> 2;
142 switch (saddr) {
143 case 0:
144 // set limit, reset counter
145 reload = 1;
146 qemu_irq_lower(s->irq);
147 // fall through
148 case 2:
149 // set limit without resetting counter
150 s->limit = val & 0x7ffffe00ULL;
151 if (!s->limit)
152 s->limit = 0x7ffffe00ULL;
153 ptimer_set_limit(s->timer, s->limit >> 9, reload);
154 break;
155 case 3:
156 // start/stop user counter
157 if (s->mode == 1) {
158 if (val & 1) {
159 ptimer_stop(s->timer);
160 s->stopped = 1;
162 else {
163 ptimer_run(s->timer, 0);
164 s->stopped = 0;
167 break;
168 case 4:
169 // bit 0: user (1) or system (0) counter mode
170 if (s->mode == 0 || s->mode == 1)
171 s->mode = val & 1;
172 if (s->mode == 1) {
173 qemu_irq_lower(s->irq);
174 s->limit = -1ULL;
176 ptimer_set_limit(s->timer, s->limit >> 9, 1);
177 break;
178 default:
179 break;
183 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
184 slavio_timer_mem_readl,
185 slavio_timer_mem_readl,
186 slavio_timer_mem_readl,
189 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
190 slavio_timer_mem_writel,
191 slavio_timer_mem_writel,
192 slavio_timer_mem_writel,
195 static void slavio_timer_save(QEMUFile *f, void *opaque)
197 SLAVIO_TIMERState *s = opaque;
199 qemu_put_be64s(f, &s->limit);
200 qemu_put_be32s(f, &s->count);
201 qemu_put_be32s(f, &s->counthigh);
202 qemu_put_be32(f, 0); // Was irq
203 qemu_put_be32s(f, &s->reached);
204 qemu_put_be32s(f, &s->stopped);
205 qemu_put_be32s(f, &s->mode);
206 qemu_put_ptimer(f, s->timer);
209 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
211 SLAVIO_TIMERState *s = opaque;
212 uint32_t tmp;
214 if (version_id != 2)
215 return -EINVAL;
217 qemu_get_be64s(f, &s->limit);
218 qemu_get_be32s(f, &s->count);
219 qemu_get_be32s(f, &s->counthigh);
220 qemu_get_be32s(f, &tmp); // Was irq
221 qemu_get_be32s(f, &s->reached);
222 qemu_get_be32s(f, &s->stopped);
223 qemu_get_be32s(f, &s->mode);
224 qemu_get_ptimer(f, s->timer);
226 return 0;
229 static void slavio_timer_reset(void *opaque)
231 SLAVIO_TIMERState *s = opaque;
233 s->limit = 0x7ffffe00ULL;
234 s->count = 0;
235 s->reached = 0;
236 s->mode &= 2;
237 ptimer_set_limit(s->timer, s->limit >> 9, 1);
238 ptimer_run(s->timer, 0);
239 s->stopped = 1;
240 qemu_irq_lower(s->irq);
243 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
245 int slavio_timer_io_memory;
246 SLAVIO_TIMERState *s;
247 QEMUBH *bh;
249 s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
250 if (!s)
251 return;
252 s->irq = irq;
253 s->mode = mode;
254 bh = qemu_bh_new(slavio_timer_irq, s);
255 s->timer = ptimer_init(bh);
256 ptimer_set_period(s->timer, 500ULL);
258 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
259 slavio_timer_mem_write, s);
260 cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
261 register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
262 qemu_register_reset(slavio_timer_reset, s);
263 slavio_timer_reset(s);