hw/serial.c

   1 /*
   2  * QEMU 16450 UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_SERIAL
  27
  28 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  29
  30 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  31 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  32 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  33 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  34
  35 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  36 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  37
  38 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  39 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  40 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  41 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  42
  43 /*
  44  * These are the definitions for the Modem Control Register
  45  */
  46 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  47 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  48 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  49 #define UART_MCR_RTS    0x02    /* RTS complement */
  50 #define UART_MCR_DTR    0x01    /* DTR complement */
  51
  52 /*
  53  * These are the definitions for the Modem Status Register
  54  */
  55 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  56 #define UART_MSR_RI     0x40    /* Ring Indicator */
  57 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  58 #define UART_MSR_CTS    0x10    /* Clear to Send */
  59 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  60 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  61 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  62 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  63 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  64
  65 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  66 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  67 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  68 #define UART_LSR_FE     0x08    /* Frame error indicator */
  69 #define UART_LSR_PE     0x04    /* Parity error indicator */
  70 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  71 #define UART_LSR_DR     0x01    /* Receiver data ready */
  72
  73 struct SerialState {
  74     uint16_t divider;
  75     uint8_t rbr; /* receive register */
  76     uint8_t ier;
  77     uint8_t iir; /* read only */
  78     uint8_t lcr;
  79     uint8_t mcr;
  80     uint8_t lsr; /* read only */
  81     uint8_t msr; /* read only */
  82     uint8_t scr;
  83     /* NOTE: this hidden state is necessary for tx irq generation as
  84        it can be reset while reading iir */
  85     int thr_ipending;
  86     qemu_irq irq;
  87     CharDriverState *chr;
  88     int last_break_enable;
  89     target_phys_addr_t base;
  90     int it_shift;
  91 };
  92
  93 static void serial_update_irq(SerialState *s)
  94 {
  95     if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
  96         s->iir = UART_IIR_RDI;
  97     } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
  98         s->iir = UART_IIR_THRI;
  99     } else {
 100         s->iir = UART_IIR_NO_INT;
 101     }
 102     if (s->iir != UART_IIR_NO_INT) {
 103         qemu_irq_raise(s->irq);
 104     } else {
 105         qemu_irq_lower(s->irq);
 106     }
 107 }
 108
 109 static void serial_update_parameters(SerialState *s)
 110 {
 111     int speed, parity, data_bits, stop_bits;
 112     QEMUSerialSetParams ssp;
 113
 114     if (s->lcr & 0x08) {
 115         if (s->lcr & 0x10)
 116             parity = 'E';
 117         else
 118             parity = 'O';
 119     } else {
 120             parity = 'N';
 121     }
 122     if (s->lcr & 0x04)
 123         stop_bits = 2;
 124     else
 125         stop_bits = 1;
 126     data_bits = (s->lcr & 0x03) + 5;
 127     if (s->divider == 0)
 128         return;
 129     speed = 115200 / s->divider;
 130     ssp.speed = speed;
 131     ssp.parity = parity;
 132     ssp.data_bits = data_bits;
 133     ssp.stop_bits = stop_bits;
 134     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 135 #if 0
 136     printf("speed=%d parity=%c data=%d stop=%d\n",
 137            speed, parity, data_bits, stop_bits);
 138 #endif
 139 }
 140
 141 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 142 {
 143     SerialState *s = opaque;
 144     unsigned char ch;
 145
 146     addr &= 7;
 147 #ifdef DEBUG_SERIAL
 148     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 149 #endif
 150     switch(addr) {
 151     default:
 152     case 0:
 153         if (s->lcr & UART_LCR_DLAB) {
 154             s->divider = (s->divider & 0xff00) | val;
 155             serial_update_parameters(s);
 156         } else {
 157             s->thr_ipending = 0;
 158             s->lsr &= ~UART_LSR_THRE;
 159             serial_update_irq(s);
 160             ch = val;
 161             qemu_chr_write(s->chr, &ch, 1);
 162             s->thr_ipending = 1;
 163             s->lsr |= UART_LSR_THRE;
 164             s->lsr |= UART_LSR_TEMT;
 165             serial_update_irq(s);
 166         }
 167         break;
 168     case 1:
 169         if (s->lcr & UART_LCR_DLAB) {
 170             s->divider = (s->divider & 0x00ff) | (val << 8);
 171             serial_update_parameters(s);
 172         } else {
 173             s->ier = val & 0x0f;
 174             if (s->lsr & UART_LSR_THRE) {
 175                 s->thr_ipending = 1;
 176             }
 177             serial_update_irq(s);
 178         }
 179         break;
 180     case 2:
 181         break;
 182     case 3:
 183         {
 184             int break_enable;
 185             s->lcr = val;
 186             serial_update_parameters(s);
 187             break_enable = (val >> 6) & 1;
 188             if (break_enable != s->last_break_enable) {
 189                 s->last_break_enable = break_enable;
 190                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 191                                &break_enable);
 192             }
 193         }
 194         break;
 195     case 4:
 196         s->mcr = val & 0x1f;
 197         break;
 198     case 5:
 199         break;
 200     case 6:
 201         break;
 202     case 7:
 203         s->scr = val;
 204         break;
 205     }
 206 }
 207
 208 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 209 {
 210     SerialState *s = opaque;
 211     uint32_t ret;
 212
 213     addr &= 7;
 214     switch(addr) {
 215     default:
 216     case 0:
 217         if (s->lcr & UART_LCR_DLAB) {
 218             ret = s->divider & 0xff;
 219         } else {
 220             ret = s->rbr;
 221             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 222             serial_update_irq(s);
 223         }
 224         break;
 225     case 1:
 226         if (s->lcr & UART_LCR_DLAB) {
 227             ret = (s->divider >> 8) & 0xff;
 228         } else {
 229             ret = s->ier;
 230         }
 231         break;
 232     case 2:
 233         ret = s->iir;
 234         /* reset THR pending bit */
 235         if ((ret & 0x7) == UART_IIR_THRI)
 236             s->thr_ipending = 0;
 237         serial_update_irq(s);
 238         break;
 239     case 3:
 240         ret = s->lcr;
 241         break;
 242     case 4:
 243         ret = s->mcr;
 244         break;
 245     case 5:
 246         ret = s->lsr;
 247         break;
 248     case 6:
 249         if (s->mcr & UART_MCR_LOOP) {
 250             /* in loopback, the modem output pins are connected to the
 251                inputs */
 252             ret = (s->mcr & 0x0c) << 4;
 253             ret |= (s->mcr & 0x02) << 3;
 254             ret |= (s->mcr & 0x01) << 5;
 255         } else {
 256             ret = s->msr;
 257         }
 258         break;
 259     case 7:
 260         ret = s->scr;
 261         break;
 262     }
 263 #ifdef DEBUG_SERIAL
 264     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 265 #endif
 266     return ret;
 267 }
 268
 269 static int serial_can_receive(SerialState *s)
 270 {
 271     return !(s->lsr & UART_LSR_DR);
 272 }
 273
 274 static void serial_receive_byte(SerialState *s, int ch)
 275 {
 276     s->rbr = ch;
 277     s->lsr |= UART_LSR_DR;
 278     serial_update_irq(s);
 279 }
 280
 281 static void serial_receive_break(SerialState *s)
 282 {
 283     s->rbr = 0;
 284     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 285     serial_update_irq(s);
 286 }
 287
 288 static int serial_can_receive1(void *opaque)
 289 {
 290     SerialState *s = opaque;
 291     return serial_can_receive(s);
 292 }
 293
 294 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 295 {
 296     SerialState *s = opaque;
 297     serial_receive_byte(s, buf[0]);
 298 }
 299
 300 static void serial_event(void *opaque, int event)
 301 {
 302     SerialState *s = opaque;
 303     if (event == CHR_EVENT_BREAK)
 304         serial_receive_break(s);
 305 }
 306
 307 static void serial_save(QEMUFile *f, void *opaque)
 308 {
 309     SerialState *s = opaque;
 310
 311     qemu_put_be16s(f,&s->divider);
 312     qemu_put_8s(f,&s->rbr);
 313     qemu_put_8s(f,&s->ier);
 314     qemu_put_8s(f,&s->iir);
 315     qemu_put_8s(f,&s->lcr);
 316     qemu_put_8s(f,&s->mcr);
 317     qemu_put_8s(f,&s->lsr);
 318     qemu_put_8s(f,&s->msr);
 319     qemu_put_8s(f,&s->scr);
 320 }
 321
 322 static int serial_load(QEMUFile *f, void *opaque, int version_id)
 323 {
 324     SerialState *s = opaque;
 325
 326     if(version_id > 2)
 327         return -EINVAL;
 328
 329     if (version_id >= 2)
 330         qemu_get_be16s(f, &s->divider);
 331     else
 332         s->divider = qemu_get_byte(f);
 333     qemu_get_8s(f,&s->rbr);
 334     qemu_get_8s(f,&s->ier);
 335     qemu_get_8s(f,&s->iir);
 336     qemu_get_8s(f,&s->lcr);
 337     qemu_get_8s(f,&s->mcr);
 338     qemu_get_8s(f,&s->lsr);
 339     qemu_get_8s(f,&s->msr);
 340     qemu_get_8s(f,&s->scr);
 341
 342     return 0;
 343 }
 344
 345 /* If fd is zero, it means that the serial device uses the console */
 346 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
 347 {
 348     SerialState *s;
 349
 350     s = qemu_mallocz(sizeof(SerialState));
 351     if (!s)
 352         return NULL;
 353     s->irq = irq;
 354     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 355     s->iir = UART_IIR_NO_INT;
 356     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 357
 358     register_savevm("serial", base, 2, serial_save, serial_load, s);
 359
 360     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 361     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 362     s->chr = chr;
 363     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 364                           serial_event, s);
 365     return s;
 366 }
 367
 368 /* Memory mapped interface */
 369 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 370 {
 371     SerialState *s = opaque;
 372
 373     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 374 }
 375
 376 void serial_mm_writeb (void *opaque,
 377                        target_phys_addr_t addr, uint32_t value)
 378 {
 379     SerialState *s = opaque;
 380
 381     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 382 }
 383
 384 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 385 {
 386     SerialState *s = opaque;
 387     uint32_t val;
 388
 389     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 390 #ifdef TARGET_WORDS_BIGENDIAN
 391     val = bswap16(val);
 392 #endif
 393     return val;
 394 }
 395
 396 void serial_mm_writew (void *opaque,
 397                        target_phys_addr_t addr, uint32_t value)
 398 {
 399     SerialState *s = opaque;
 400 #ifdef TARGET_WORDS_BIGENDIAN
 401     value = bswap16(value);
 402 #endif
 403     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 404 }
 405
 406 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 407 {
 408     SerialState *s = opaque;
 409     uint32_t val;
 410
 411     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 412 #ifdef TARGET_WORDS_BIGENDIAN
 413     val = bswap32(val);
 414 #endif
 415     return val;
 416 }
 417
 418 void serial_mm_writel (void *opaque,
 419                        target_phys_addr_t addr, uint32_t value)
 420 {
 421     SerialState *s = opaque;
 422 #ifdef TARGET_WORDS_BIGENDIAN
 423     value = bswap32(value);
 424 #endif
 425     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
 426 }
 427
 428 static CPUReadMemoryFunc *serial_mm_read[] = {
 429     &serial_mm_readb,
 430     &serial_mm_readw,
 431     &serial_mm_readl,
 432 };
 433
 434 static CPUWriteMemoryFunc *serial_mm_write[] = {
 435     &serial_mm_writeb,
 436     &serial_mm_writew,
 437     &serial_mm_writel,
 438 };
 439
 440 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 441                              qemu_irq irq, CharDriverState *chr,
 442                              int ioregister)
 443 {
 444     SerialState *s;
 445     int s_io_memory;
 446
 447     s = qemu_mallocz(sizeof(SerialState));
 448     if (!s)
 449         return NULL;
 450     s->irq = irq;
 451     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 452     s->iir = UART_IIR_NO_INT;
 453     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 454     s->base = base;
 455     s->it_shift = it_shift;
 456
 457     register_savevm("serial", base, 2, serial_save, serial_load, s);
 458
 459     if (ioregister) {
 460         s_io_memory = cpu_register_io_memory(0, serial_mm_read,
 461                                              serial_mm_write, s);
 462         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 463     }
 464     s->chr = chr;
 465     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 466                           serial_event, s);
 467     return s;
 468 }