hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_PCI
  27
  28 struct PCIBus {
  29     int bus_num;
  30     int devfn_min;
  31     pci_set_irq_fn set_irq;
  32     pci_map_irq_fn map_irq;
  33     uint32_t config_reg; /* XXX: suppress */
  34     /* low level pic */
  35     SetIRQFunc *low_set_irq;
  36     qemu_irq *irq_opaque;
  37     PCIDevice *devices[256];
  38     PCIDevice *parent_dev;
  39     PCIBus *next;
  40     /* The bus IRQ state is the logical OR of the connected devices.
  41        Keep a count of the number of devices with raised IRQs.  */
  42     int irq_count[];
  43 };
  44
  45 static void pci_update_mappings(PCIDevice *d);
  46 static void pci_set_irq(void *opaque, int irq_num, int level);
  47
  48 target_phys_addr_t pci_mem_base;
  49 static int pci_irq_index;
  50 static PCIBus *first_bus;
  51
  52 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  53                          qemu_irq *pic, int devfn_min, int nirq)
  54 {
  55     PCIBus *bus;
  56     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  57     bus->set_irq = set_irq;
  58     bus->map_irq = map_irq;
  59     bus->irq_opaque = pic;
  60     bus->devfn_min = devfn_min;
  61     first_bus = bus;
  62     return bus;
  63 }
  64
  65 PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
  66 {
  67     PCIBus *bus;
  68     bus = qemu_mallocz(sizeof(PCIBus));
  69     bus->map_irq = map_irq;
  70     bus->parent_dev = dev;
  71     bus->next = dev->bus->next;
  72     dev->bus->next = bus;
  73     return bus;
  74 }
  75
  76 int pci_bus_num(PCIBus *s)
  77 {
  78     return s->bus_num;
  79 }
  80
  81 void pci_device_save(PCIDevice *s, QEMUFile *f)
  82 {
  83     qemu_put_be32(f, 1); /* PCI device version */
  84     qemu_put_buffer(f, s->config, 256);
  85 }
  86
  87 int pci_device_load(PCIDevice *s, QEMUFile *f)
  88 {
  89     uint32_t version_id;
  90     version_id = qemu_get_be32(f);
  91     if (version_id != 1)
  92         return -EINVAL;
  93     qemu_get_buffer(f, s->config, 256);
  94     pci_update_mappings(s);
  95     return 0;
  96 }
  97
  98 /* -1 for devfn means auto assign */
  99 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 100                                int instance_size, int devfn,
 101                                PCIConfigReadFunc *config_read,
 102                                PCIConfigWriteFunc *config_write)
 103 {
 104     PCIDevice *pci_dev;
 105
 106     if (pci_irq_index >= PCI_DEVICES_MAX)
 107         return NULL;
 108
 109     if (devfn < 0) {
 110         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 111             if (!bus->devices[devfn])
 112                 goto found;
 113         }
 114         return NULL;
 115     found: ;
 116     }
 117     pci_dev = qemu_mallocz(instance_size);
 118     if (!pci_dev)
 119         return NULL;
 120     pci_dev->bus = bus;
 121     pci_dev->devfn = devfn;
 122     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 123     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 124
 125     if (!config_read)
 126         config_read = pci_default_read_config;
 127     if (!config_write)
 128         config_write = pci_default_write_config;
 129     pci_dev->config_read = config_read;
 130     pci_dev->config_write = config_write;
 131     pci_dev->irq_index = pci_irq_index++;
 132     bus->devices[devfn] = pci_dev;
 133     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 134     return pci_dev;
 135 }
 136
 137 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 138                             uint32_t size, int type,
 139                             PCIMapIORegionFunc *map_func)
 140 {
 141     PCIIORegion *r;
 142     uint32_t addr;
 143
 144     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 145         return;
 146     r = &pci_dev->io_regions[region_num];
 147     r->addr = -1;
 148     r->size = size;
 149     r->type = type;
 150     r->map_func = map_func;
 151     if (region_num == PCI_ROM_SLOT) {
 152         addr = 0x30;
 153     } else {
 154         addr = 0x10 + region_num * 4;
 155     }
 156     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 157 }
 158
 159 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 160 {
 161     return addr + pci_mem_base;
 162 }
 163
 164 static void pci_update_mappings(PCIDevice *d)
 165 {
 166     PCIIORegion *r;
 167     int cmd, i;
 168     uint32_t last_addr, new_addr, config_ofs;
 169
 170     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 171     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 172         r = &d->io_regions[i];
 173         if (i == PCI_ROM_SLOT) {
 174             config_ofs = 0x30;
 175         } else {
 176             config_ofs = 0x10 + i * 4;
 177         }
 178         if (r->size != 0) {
 179             if (r->type & PCI_ADDRESS_SPACE_IO) {
 180                 if (cmd & PCI_COMMAND_IO) {
 181                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 182                                                          config_ofs));
 183                     new_addr = new_addr & ~(r->size - 1);
 184                     last_addr = new_addr + r->size - 1;
 185                     /* NOTE: we have only 64K ioports on PC */
 186                     if (last_addr <= new_addr || new_addr == 0 ||
 187                         last_addr >= 0x10000) {
 188                         new_addr = -1;
 189                     }
 190                 } else {
 191                     new_addr = -1;
 192                 }
 193             } else {
 194                 if (cmd & PCI_COMMAND_MEMORY) {
 195                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 196                                                          config_ofs));
 197                     /* the ROM slot has a specific enable bit */
 198                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 199                         goto no_mem_map;
 200                     new_addr = new_addr & ~(r->size - 1);
 201                     last_addr = new_addr + r->size - 1;
 202                     /* NOTE: we do not support wrapping */
 203                     /* XXX: as we cannot support really dynamic
 204                        mappings, we handle specific values as invalid
 205                        mappings. */
 206                     if (last_addr <= new_addr || new_addr == 0 ||
 207                         last_addr == -1) {
 208                         new_addr = -1;
 209                     }
 210                 } else {
 211                 no_mem_map:
 212                     new_addr = -1;
 213                 }
 214             }
 215             /* now do the real mapping */
 216             if (new_addr != r->addr) {
 217                 if (r->addr != -1) {
 218                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 219                         int class;
 220                         /* NOTE: specific hack for IDE in PC case:
 221                            only one byte must be mapped. */
 222                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 223                         if (class == 0x0101 && r->size == 4) {
 224                             isa_unassign_ioport(r->addr + 2, 1);
 225                         } else {
 226                             isa_unassign_ioport(r->addr, r->size);
 227                         }
 228                     } else {
 229                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 230                                                      r->size,
 231                                                      IO_MEM_UNASSIGNED);
 232                     }
 233                 }
 234                 r->addr = new_addr;
 235                 if (r->addr != -1) {
 236                     r->map_func(d, i, r->addr, r->size, r->type);
 237                 }
 238             }
 239         }
 240     }
 241 }
 242
 243 uint32_t pci_default_read_config(PCIDevice *d,
 244                                  uint32_t address, int len)
 245 {
 246     uint32_t val;
 247
 248     switch(len) {
 249     default:
 250     case 4:
 251         if (address <= 0xfc) {
 252             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 253             break;
 254         }
 255         /* fall through */
 256     case 2:
 257         if (address <= 0xfe) {
 258             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 259             break;
 260         }
 261         /* fall through */
 262     case 1:
 263         val = d->config[address];
 264         break;
 265     }
 266     return val;
 267 }
 268
 269 void pci_default_write_config(PCIDevice *d,
 270                               uint32_t address, uint32_t val, int len)
 271 {
 272     int can_write, i;
 273     uint32_t end, addr;
 274
 275     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 276                      (address >= 0x30 && address < 0x34))) {
 277         PCIIORegion *r;
 278         int reg;
 279
 280         if ( address >= 0x30 ) {
 281             reg = PCI_ROM_SLOT;
 282         }else{
 283             reg = (address - 0x10) >> 2;
 284         }
 285         r = &d->io_regions[reg];
 286         if (r->size == 0)
 287             goto default_config;
 288         /* compute the stored value */
 289         if (reg == PCI_ROM_SLOT) {
 290             /* keep ROM enable bit */
 291             val &= (~(r->size - 1)) | 1;
 292         } else {
 293             val &= ~(r->size - 1);
 294             val |= r->type;
 295         }
 296         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 297         pci_update_mappings(d);
 298         return;
 299     }
 300  default_config:
 301     /* not efficient, but simple */
 302     addr = address;
 303     for(i = 0; i < len; i++) {
 304         /* default read/write accesses */
 305         switch(d->config[0x0e]) {
 306         case 0x00:
 307         case 0x80:
 308             switch(addr) {
 309             case 0x00:
 310             case 0x01:
 311             case 0x02:
 312             case 0x03:
 313             case 0x08:
 314             case 0x09:
 315             case 0x0a:
 316             case 0x0b:
 317             case 0x0e:
 318             case 0x10 ... 0x27: /* base */
 319             case 0x30 ... 0x33: /* rom */
 320             case 0x3d:
 321                 can_write = 0;
 322                 break;
 323             default:
 324                 can_write = 1;
 325                 break;
 326             }
 327             break;
 328         default:
 329         case 0x01:
 330             switch(addr) {
 331             case 0x00:
 332             case 0x01:
 333             case 0x02:
 334             case 0x03:
 335             case 0x08:
 336             case 0x09:
 337             case 0x0a:
 338             case 0x0b:
 339             case 0x0e:
 340             case 0x38 ... 0x3b: /* rom */
 341             case 0x3d:
 342                 can_write = 0;
 343                 break;
 344             default:
 345                 can_write = 1;
 346                 break;
 347             }
 348             break;
 349         }
 350         if (can_write) {
 351             d->config[addr] = val;
 352         }
 353         if (++addr > 0xff)
 354                 break;
 355         val >>= 8;
 356     }
 357
 358     end = address + len;
 359     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 360         /* if the command register is modified, we must modify the mappings */
 361         pci_update_mappings(d);
 362     }
 363 }
 364
 365 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 366 {
 367     PCIBus *s = opaque;
 368     PCIDevice *pci_dev;
 369     int config_addr, bus_num;
 370
 371 #if defined(DEBUG_PCI) && 0
 372     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 373            addr, val, len);
 374 #endif
 375     bus_num = (addr >> 16) & 0xff;
 376     while (s && s->bus_num != bus_num)
 377         s = s->next;
 378     if (!s)
 379         return;
 380     pci_dev = s->devices[(addr >> 8) & 0xff];
 381     if (!pci_dev)
 382         return;
 383     config_addr = addr & 0xff;
 384 #if defined(DEBUG_PCI)
 385     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 386            pci_dev->name, config_addr, val, len);
 387 #endif
 388     pci_dev->config_write(pci_dev, config_addr, val, len);
 389 }
 390
 391 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 392 {
 393     PCIBus *s = opaque;
 394     PCIDevice *pci_dev;
 395     int config_addr, bus_num;
 396     uint32_t val;
 397
 398     bus_num = (addr >> 16) & 0xff;
 399     while (s && s->bus_num != bus_num)
 400         s= s->next;
 401     if (!s)
 402         goto fail;
 403     pci_dev = s->devices[(addr >> 8) & 0xff];
 404     if (!pci_dev) {
 405     fail:
 406         switch(len) {
 407         case 1:
 408             val = 0xff;
 409             break;
 410         case 2:
 411             val = 0xffff;
 412             break;
 413         default:
 414         case 4:
 415             val = 0xffffffff;
 416             break;
 417         }
 418         goto the_end;
 419     }
 420     config_addr = addr & 0xff;
 421     val = pci_dev->config_read(pci_dev, config_addr, len);
 422 #if defined(DEBUG_PCI)
 423     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 424            pci_dev->name, config_addr, val, len);
 425 #endif
 426  the_end:
 427 #if defined(DEBUG_PCI) && 0
 428     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 429            addr, val, len);
 430 #endif
 431     return val;
 432 }
 433
 434 /***********************************************************/
 435 /* generic PCI irq support */
 436
 437 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 438 static void pci_set_irq(void *opaque, int irq_num, int level)
 439 {
 440     PCIDevice *pci_dev = (PCIDevice *)opaque;
 441     PCIBus *bus;
 442     int change;
 443
 444     change = level - pci_dev->irq_state[irq_num];
 445     if (!change)
 446         return;
 447
 448     pci_dev->irq_state[irq_num] = level;
 449     for (;;) {
 450         bus = pci_dev->bus;
 451         irq_num = bus->map_irq(pci_dev, irq_num);
 452         if (bus->set_irq)
 453             break;
 454         pci_dev = bus->parent_dev;
 455     }
 456     bus->irq_count[irq_num] += change;
 457     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 458 }
 459
 460 /***********************************************************/
 461 /* monitor info on PCI */
 462
 463 typedef struct {
 464     uint16_t class;
 465     const char *desc;
 466 } pci_class_desc;
 467
 468 static pci_class_desc pci_class_descriptions[] =
 469 {
 470     { 0x0100, "SCSI controller"},
 471     { 0x0101, "IDE controller"},
 472     { 0x0102, "Floppy controller"},
 473     { 0x0103, "IPI controller"},
 474     { 0x0104, "RAID controller"},
 475     { 0x0106, "SATA controller"},
 476     { 0x0107, "SAS controller"},
 477     { 0x0180, "Storage controller"},
 478     { 0x0200, "Ethernet controller"},
 479     { 0x0201, "Token Ring controller"},
 480     { 0x0202, "FDDI controller"},
 481     { 0x0203, "ATM controller"},
 482     { 0x0280, "Network controller"},
 483     { 0x0300, "VGA controller"},
 484     { 0x0301, "XGA controller"},
 485     { 0x0302, "3D controller"},
 486     { 0x0380, "Display controller"},
 487     { 0x0400, "Video controller"},
 488     { 0x0401, "Audio controller"},
 489     { 0x0402, "Phone"},
 490     { 0x0480, "Multimedia controller"},
 491     { 0x0500, "RAM controller"},
 492     { 0x0501, "Flash controller"},
 493     { 0x0580, "Memory controller"},
 494     { 0x0600, "Host bridge"},
 495     { 0x0601, "ISA bridge"},
 496     { 0x0602, "EISA bridge"},
 497     { 0x0603, "MC bridge"},
 498     { 0x0604, "PCI bridge"},
 499     { 0x0605, "PCMCIA bridge"},
 500     { 0x0606, "NUBUS bridge"},
 501     { 0x0607, "CARDBUS bridge"},
 502     { 0x0608, "RACEWAY bridge"},
 503     { 0x0680, "Bridge"},
 504     { 0x0c03, "USB controller"},
 505     { 0, NULL}
 506 };
 507
 508 static void pci_info_device(PCIDevice *d)
 509 {
 510     int i, class;
 511     PCIIORegion *r;
 512     pci_class_desc *desc;
 513
 514     term_printf("  Bus %2d, device %3d, function %d:\n",
 515            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 516     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 517     term_printf("    ");
 518     desc = pci_class_descriptions;
 519     while (desc->desc && class != desc->class)
 520         desc++;
 521     if (desc->desc) {
 522         term_printf("%s", desc->desc);
 523     } else {
 524         term_printf("Class %04x", class);
 525     }
 526     term_printf(": PCI device %04x:%04x\n",
 527            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 528            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 529
 530     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 531         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 532     }
 533     if (class == 0x0604) {
 534         term_printf("      BUS %d.\n", d->config[0x19]);
 535     }
 536     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 537         r = &d->io_regions[i];
 538         if (r->size != 0) {
 539             term_printf("      BAR%d: ", i);
 540             if (r->type & PCI_ADDRESS_SPACE_IO) {
 541                 term_printf("I/O at 0x%04x [0x%04x].\n",
 542                        r->addr, r->addr + r->size - 1);
 543             } else {
 544                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 545                        r->addr, r->addr + r->size - 1);
 546             }
 547         }
 548     }
 549     if (class == 0x0604 && d->config[0x19] != 0) {
 550         pci_for_each_device(d->config[0x19], pci_info_device);
 551     }
 552 }
 553
 554 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 555 {
 556     PCIBus *bus = first_bus;
 557     PCIDevice *d;
 558     int devfn;
 559
 560     while (bus && bus->bus_num != bus_num)
 561         bus = bus->next;
 562     if (bus) {
 563         for(devfn = 0; devfn < 256; devfn++) {
 564             d = bus->devices[devfn];
 565             if (d)
 566                 fn(d);
 567         }
 568     }
 569 }
 570
 571 void pci_info(void)
 572 {
 573     pci_for_each_device(0, pci_info_device);
 574 }
 575
 576 /* Initialize a PCI NIC.  */
 577 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
 578 {
 579     if (strcmp(nd->model, "ne2k_pci") == 0) {
 580         pci_ne2000_init(bus, nd, devfn);
 581     } else if (strcmp(nd->model, "i82551") == 0) {
 582         pci_i82551_init(bus, nd, devfn);
 583     } else if (strcmp(nd->model, "i82557b") == 0) {
 584         pci_i82557b_init(bus, nd, devfn);
 585     } else if (strcmp(nd->model, "i82559er") == 0) {
 586         pci_i82559er_init(bus, nd, devfn);
 587     } else if (strcmp(nd->model, "rtl8139") == 0) {
 588         pci_rtl8139_init(bus, nd, devfn);
 589     } else if (strcmp(nd->model, "pcnet") == 0) {
 590         pci_pcnet_init(bus, nd, devfn);
 591     } else if (strcmp(nd->model, "?") == 0) {
 592         fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
 593                         " ne2k_pci pcnet rtl8139\n");
 594         exit (1);
 595     } else {
 596         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 597         exit (1);
 598     }
 599 }
 600
 601 typedef struct {
 602     PCIDevice dev;
 603     PCIBus *bus;
 604 } PCIBridge;
 605
 606 void pci_bridge_write_config(PCIDevice *d,
 607                              uint32_t address, uint32_t val, int len)
 608 {
 609     PCIBridge *s = (PCIBridge *)d;
 610
 611     if (address == 0x19 || (address == 0x18 && len > 1)) {
 612         if (address == 0x19)
 613             s->bus->bus_num = val & 0xff;
 614         else
 615             s->bus->bus_num = (val >> 8) & 0xff;
 616 #if defined(DEBUG_PCI)
 617         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 618 #endif
 619     }
 620     pci_default_write_config(d, address, val, len);
 621 }
 622
 623 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 624                         pci_map_irq_fn map_irq, const char *name)
 625 {
 626     PCIBridge *s;
 627     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 628                                          devfn, NULL, pci_bridge_write_config);
 629     s->dev.config[0x00] = id >> 16;
 630     s->dev.config[0x01] = id >> 24;
 631     s->dev.config[0x02] = id; // device_id
 632     s->dev.config[0x03] = id >> 8;
 633     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 634     s->dev.config[0x05] = 0x00;
 635     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 636     s->dev.config[0x07] = 0x00; // status = fast devsel
 637     s->dev.config[0x08] = 0x00; // revision
 638     s->dev.config[0x09] = 0x00; // programming i/f
 639     s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
 640     s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
 641     s->dev.config[0x0D] = 0x10; // latency_timer
 642     s->dev.config[0x0E] = 0x81; // header_type
 643     s->dev.config[0x1E] = 0xa0; // secondary status
 644
 645     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 646     return s->bus;
 647 }