hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "vl.h"
  11
  12 #ifdef TARGET_WORDS_BIGENDIAN
  13 #define BIOS_FILENAME "mips_bios.bin"
  14 #else
  15 #define BIOS_FILENAME "mipsel_bios.bin"
  16 #endif
  17
  18 #ifdef TARGET_MIPS64
  19 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
  20 #else
  21 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
  22 #endif
  23
  24 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  25
  26 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  27 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  28 static const int ide_irq[2] = { 14, 15 };
  29
  30 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  31 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  32
  33 extern FILE *logfile;
  34
  35 static PITState *pit; /* PIT i8254 */
  36
  37 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  38
  39 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  40                               uint32_t val)
  41 {
  42     if ((addr & 0xffff) == 0 && val == 42)
  43         qemu_system_reset_request ();
  44     else if ((addr & 0xffff) == 4 && val == 42)
  45         qemu_system_shutdown_request ();
  46 }
  47
  48 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  49 {
  50     return 0;
  51 }
  52
  53 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  54     &mips_qemu_writel,
  55     &mips_qemu_writel,
  56     &mips_qemu_writel,
  57 };
  58
  59 static CPUReadMemoryFunc *mips_qemu_read[] = {
  60     &mips_qemu_readl,
  61     &mips_qemu_readl,
  62     &mips_qemu_readl,
  63 };
  64
  65 static int mips_qemu_iomemtype = 0;
  66
  67 void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
  68                   const char *kernel_cmdline,
  69                   const char *initrd_filename)
  70 {
  71     int64_t entry, kernel_low, kernel_high;
  72     long kernel_size, initrd_size;
  73     ram_addr_t initrd_offset;
  74
  75     kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND,
  76                            &entry, &kernel_low, &kernel_high);
  77     if (kernel_size >= 0) {
  78         if ((entry & ~0x7fffffffULL) == 0x80000000)
  79             entry = (int32_t)entry;
  80         env->PC = entry;
  81     } else {
  82         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  83                 kernel_filename);
  84         exit(1);
  85     }
  86
  87     /* load initrd */
  88     initrd_size = 0;
  89     initrd_offset = 0;
  90     if (initrd_filename) {
  91         initrd_size = get_image_size (initrd_filename);
  92         if (initrd_size > 0) {
  93             initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
  94             if (initrd_offset + initrd_size > ram_size) {
  95                 fprintf(stderr,
  96                         "qemu: memory too small for initial ram disk '%s'\n",
  97                         initrd_filename);
  98                 exit(1);
  99             }
 100             initrd_size = load_image(initrd_filename,
 101                                      phys_ram_base + initrd_offset);
 102         }
 103         if (initrd_size == (target_ulong) -1) {
 104             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 105                     initrd_filename);
 106             exit(1);
 107         }
 108     }
 109
 110     /* Store command line.  */
 111     if (initrd_size > 0) {
 112         int ret;
 113         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 114                       "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
 115                       PHYS_TO_VIRT((uint32_t)initrd_offset),
 116                       initrd_size);
 117         strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
 118     }
 119     else {
 120         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 121     }
 122
 123     *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 124     *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 125 }
 126
 127 static void main_cpu_reset(void *opaque)
 128 {
 129     CPUState *env = opaque;
 130     cpu_reset(env);
 131     cpu_mips_register(env, NULL);
 132
 133     if (env->kernel_filename)
 134         load_kernel (env, env->ram_size, env->kernel_filename,
 135                      env->kernel_cmdline, env->initrd_filename);
 136 }
 137
 138 static
 139 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 140                     DisplayState *ds, const char **fd_filename, int snapshot,
 141                     const char *kernel_filename, const char *kernel_cmdline,
 142                     const char *initrd_filename, const char *cpu_model)
 143 {
 144     char buf[1024];
 145     unsigned long bios_offset;
 146     int bios_size;
 147     CPUState *env;
 148     RTCState *rtc_state;
 149     int i;
 150     mips_def_t *def;
 151     qemu_irq *i8259;
 152
 153     /* init CPUs */
 154     if (cpu_model == NULL) {
 155 #ifdef TARGET_MIPS64
 156         cpu_model = "R4000";
 157 #else
 158         cpu_model = "24Kf";
 159 #endif
 160     }
 161     if (mips_find_by_name(cpu_model, &def) != 0)
 162         def = NULL;
 163     env = cpu_init();
 164     cpu_mips_register(env, def);
 165     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 166     qemu_register_reset(main_cpu_reset, env);
 167
 168     /* allocate RAM */
 169     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 170
 171     if (!mips_qemu_iomemtype) {
 172         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 173                                                      mips_qemu_write, NULL);
 174     }
 175     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 176
 177     /* Try to load a BIOS image. If this fails, we continue regardless,
 178        but initialize the hardware ourselves. When a kernel gets
 179        preloaded we also initialize the hardware, since the BIOS wasn't
 180        run. */
 181     bios_offset = ram_size + vga_ram_size;
 182     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 183     bios_size = load_image(buf, phys_ram_base + bios_offset);
 184     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 185         cpu_register_physical_memory(0x1fc00000,
 186                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 187     } else {
 188         /* not fatal */
 189         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 190                 buf);
 191     }
 192
 193     if (kernel_filename) {
 194         load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
 195                      initrd_filename);
 196         env->ram_size = ram_size;
 197         env->kernel_filename = kernel_filename;
 198         env->kernel_cmdline = kernel_cmdline;
 199         env->initrd_filename = initrd_filename;
 200     }
 201
 202     /* Init CPU internal devices */
 203     cpu_mips_irq_init_cpu(env);
 204     cpu_mips_clock_init(env);
 205     cpu_mips_irqctrl_init();
 206
 207     /* The PIC is attached to the MIPS CPU INT0 pin */
 208     i8259 = i8259_init(env->irq[2]);
 209
 210     rtc_state = rtc_init(0x70, i8259[8]);
 211
 212     /* Register 64 KB of ISA IO space at 0x14000000 */
 213     isa_mmio_init(0x14000000, 0x00010000);
 214     isa_mem_base = 0x10000000;
 215
 216     pit = pit_init(0x40, i8259[0]);
 217
 218     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 219         if (serial_hds[i]) {
 220             serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
 221         }
 222     }
 223
 224     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 225                  vga_ram_size);
 226
 227     if (nd_table[0].vlan) {
 228         if (nd_table[0].model == NULL
 229             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 230             isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
 231         } else if (strcmp(nd_table[0].model, "?") == 0) {
 232             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 233             exit (1);
 234         } else {
 235             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 236             exit (1);
 237         }
 238     }
 239
 240     for(i = 0; i < 2; i++)
 241         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 242                      bs_table[2 * i], bs_table[2 * i + 1]);
 243
 244     i8042_init(i8259[1], i8259[12], 0x60);
 245     ds1225y_init(0x9000, "nvram");
 246 }
 247
 248 QEMUMachine mips_machine = {
 249     "mips",
 250     "mips r4k platform",
 251     mips_r4k_init,
 252 };