2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if !defined (__CPU_ALPHA_H__)
22 #define __CPU_ALPHA_H__
26 #define TARGET_LONG_BITS 64
33 #include "softfloat.h"
35 /* XXX: put this in a common place */
36 #define likely(x) __builtin_expect(!!(x), 1)
37 #define unlikely(x) __builtin_expect(!!(x), 0)
39 #define TARGET_HAS_ICE 1
41 #define ELF_MACHINE EM_ALPHA
43 #define ICACHE_LINE_SIZE 32
44 #define DCACHE_LINE_SIZE 32
46 #define TARGET_PAGE_BITS 12
50 /* Alpha major type */
56 ALPHA_EV5
= 5, /* 21164 */
57 ALPHA_EV45
= 6, /* 21064A */
58 ALPHA_EV56
= 7, /* 21164A */
69 ALPHA_LCA_1
= 1, /* 21066 */
70 ALPHA_LCA_2
= 2, /* 20166 */
71 ALPHA_LCA_3
= 3, /* 21068 */
72 ALPHA_LCA_4
= 4, /* 21068 */
73 ALPHA_LCA_5
= 5, /* 21066A */
74 ALPHA_LCA_6
= 6, /* 21068A */
79 ALPHA_EV5_1
= 1, /* Rev BA, CA */
80 ALPHA_EV5_2
= 2, /* Rev DA, EA */
81 ALPHA_EV5_3
= 3, /* Pass 3 */
82 ALPHA_EV5_4
= 4, /* Pass 3.2 */
83 ALPHA_EV5_5
= 5, /* Pass 4 */
88 ALPHA_EV45_1
= 1, /* Pass 1 */
89 ALPHA_EV45_2
= 2, /* Pass 1.1 */
90 ALPHA_EV45_3
= 3, /* Pass 2 */
95 ALPHA_EV56_1
= 1, /* Pass 1 */
96 ALPHA_EV56_2
= 2, /* Pass 2 */
100 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
101 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
102 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
103 IMPLVER_21364
= 3, /* EV7 & EV79 */
107 AMASK_BWX
= 0x00000001,
108 AMASK_FIX
= 0x00000002,
109 AMASK_CIX
= 0x00000004,
110 AMASK_MVI
= 0x00000100,
111 AMASK_TRAP
= 0x00000200,
112 AMASK_PREFETCH
= 0x00001000,
116 VAX_ROUND_NORMAL
= 0,
121 IEEE_ROUND_NORMAL
= 0,
128 /* IEEE floating-point operations encoding */
140 FP_ROUND_CHOPPED
= 0x0,
141 FP_ROUND_MINUS
= 0x1,
142 FP_ROUND_NORMAL
= 0x2,
143 FP_ROUND_DYNAMIC
= 0x3,
146 /* Internal processor registers */
147 /* XXX: TOFIX: most of those registers are implementation dependant */
168 IPR_HW_INT_CLR
= 0x0E,
174 IPR_IC_FLUSH_ASM
= 0x12,
184 IPR_DTB_ALTMODE
= 0xA6,
231 typedef struct CPUAlphaState CPUAlphaState
;
233 typedef struct pal_handler_t pal_handler_t
;
234 struct pal_handler_t
{
236 void (*reset
)(CPUAlphaState
*env
);
237 /* Uncorrectable hardware error */
238 void (*machine_check
)(CPUAlphaState
*env
);
239 /* Arithmetic exception */
240 void (*arithmetic
)(CPUAlphaState
*env
);
241 /* Interrupt / correctable hardware error */
242 void (*interrupt
)(CPUAlphaState
*env
);
244 void (*dfault
)(CPUAlphaState
*env
);
246 void (*dtb_miss_pal
)(CPUAlphaState
*env
);
247 /* DTB miss native */
248 void (*dtb_miss_native
)(CPUAlphaState
*env
);
249 /* Unaligned access */
250 void (*unalign
)(CPUAlphaState
*env
);
252 void (*itb_miss
)(CPUAlphaState
*env
);
253 /* Instruction stream access violation */
254 void (*itb_acv
)(CPUAlphaState
*env
);
255 /* Reserved or privileged opcode */
256 void (*opcdec
)(CPUAlphaState
*env
);
257 /* Floating point exception */
258 void (*fen
)(CPUAlphaState
*env
);
259 /* Call pal instruction */
260 void (*call_pal
)(CPUAlphaState
*env
, uint32_t palcode
);
263 struct CPUAlphaState
{
266 float_status fp_status
;
271 uint64_t ipr
[IPR_LAST
];
274 int saved_mode
; /* Used for HW_LD / HW_ST */
276 #if TARGET_LONG_BITS > HOST_LONG_BITS
277 /* temporary fixed-point registers
278 * used to emulate 64 bits target on 32 bits hosts
280 target_ulong t0
, t1
, t2
;
283 double ft0
, ft1
, ft2
;
285 /* Those resources are used only in Qemu core */
289 int user_mode_only
; /* user mode only simulation */
295 int interrupt_request
;
300 pal_handler_t
*pal_handler
;
303 #define CPUState CPUAlphaState
304 #define cpu_init cpu_alpha_init
305 #define cpu_exec cpu_alpha_exec
306 #define cpu_gen_code cpu_alpha_gen_code
307 #define cpu_signal_handler cpu_alpha_signal_handler
312 FEATURE_ASN
= 0x00000001,
313 FEATURE_SPS
= 0x00000002,
314 FEATURE_VIRBND
= 0x00000004,
315 FEATURE_TBCHK
= 0x00000008,
322 EXCP_HW_INTERRUPT
= 0x00E0,
323 EXCP_DFAULT
= 0x01E0,
324 EXCP_DTB_MISS_PAL
= 0x09E0,
325 EXCP_ITB_MISS
= 0x03E0,
326 EXCP_ITB_ACV
= 0x07E0,
327 EXCP_DTB_MISS_NATIVE
= 0x08E0,
328 EXCP_UNALIGN
= 0x11E0,
329 EXCP_OPCDEC
= 0x13E0,
331 EXCP_CALL_PAL
= 0x2000,
332 EXCP_CALL_PALP
= 0x3000,
333 EXCP_CALL_PALE
= 0x4000,
334 /* Pseudo exception for console */
335 EXCP_CONSOLE_DISPATCH
= 0x4001,
336 EXCP_CONSOLE_FIXUP
= 0x4002,
339 /* Arithmetic exception */
345 PALCODE_CALL
= 0x00000000,
346 PALCODE_LD
= 0x01000000,
347 PALCODE_ST
= 0x02000000,
348 PALCODE_MFPR
= 0x03000000,
349 PALCODE_MTPR
= 0x04000000,
350 PALCODE_REI
= 0x05000000,
351 PALCODE_INIT
= 0xF0000000,
391 CPUAlphaState
* cpu_alpha_init (void);
392 int cpu_alpha_exec(CPUAlphaState
*s
);
393 /* you can call this signal handler from your SIGBUS and SIGSEGV
394 signal handlers to inform the virtual CPU of exceptions. non zero
395 is returned if the signal was handled by the virtual CPU. */
396 int cpu_alpha_signal_handler(int host_signum
, void *pinfo
,
398 int cpu_alpha_mfpr (CPUState
*env
, int iprn
, uint64_t *valp
);
399 int cpu_alpha_mtpr (CPUState
*env
, int iprn
, uint64_t val
, uint64_t *oldvalp
);
400 void cpu_loop_exit (void);
401 void pal_init (CPUState
*env
);
402 void call_pal (CPUState
*env
, int palcode
);
404 #endif /* !defined (__CPU_ALPHA_H__) */