hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "isa.h"
  29 #include "sysbus.h"
  30
  31 typedef uint32_t pci_addr_t;
  32 #include "pci_host.h"
  33
  34 typedef PCIHostState I440FXState;
  35
  36 typedef struct PIIX3State {
  37     PCIDevice dev;
  38     int pci_irq_levels[4];
  39 } PIIX3State;
  40
  41 typedef struct PIIX3IrqState {
  42     PIIX3State *piix3;
  43     qemu_irq *pic;
  44 } PIIX3IrqState;
  45
  46 struct PCII440FXState {
  47     PCIDevice dev;
  48     target_phys_addr_t isa_page_descs[384 / 4];
  49     uint8_t smm_enabled;
  50     PIIX3IrqState *irq_state;
  51 };
  52
  53 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  54 {
  55     I440FXState *s = opaque;
  56     s->config_reg = val;
  57 }
  58
  59 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  60 {
  61     I440FXState *s = opaque;
  62     return s->config_reg;
  63 }
  64
  65 static void piix3_set_irq(void *opaque, int irq_num, int level);
  66
  67 /* return the global irq number corresponding to a given device irq
  68    pin. We could also use the bus number to have a more precise
  69    mapping. */
  70 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  71 {
  72     int slot_addend;
  73     slot_addend = (pci_dev->devfn >> 3) - 1;
  74     return (irq_num + slot_addend) & 3;
  75 }
  76
  77 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  78 {
  79     uint32_t addr;
  80
  81     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  82     switch(r) {
  83     case 3:
  84         /* RAM */
  85         cpu_register_physical_memory(start, end - start,
  86                                      start);
  87         break;
  88     case 1:
  89         /* ROM (XXX: not quite correct) */
  90         cpu_register_physical_memory(start, end - start,
  91                                      start | IO_MEM_ROM);
  92         break;
  93     case 2:
  94     case 0:
  95         /* XXX: should distinguish read/write cases */
  96         for(addr = start; addr < end; addr += 4096) {
  97             cpu_register_physical_memory(addr, 4096,
  98                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  99         }
 100         break;
 101     }
 102 }
 103
 104 static void i440fx_update_memory_mappings(PCII440FXState *d)
 105 {
 106     int i, r;
 107     uint32_t smram, addr;
 108
 109     update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
 110     for(i = 0; i < 12; i++) {
 111         r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
 112         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 113     }
 114     smram = d->dev.config[0x72];
 115     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 116         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 117     } else {
 118         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 119             cpu_register_physical_memory(addr, 4096,
 120                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 121         }
 122     }
 123 }
 124
 125 void i440fx_set_smm(PCII440FXState *d, int val)
 126 {
 127     val = (val != 0);
 128     if (d->smm_enabled != val) {
 129         d->smm_enabled = val;
 130         i440fx_update_memory_mappings(d);
 131     }
 132 }
 133
 134
 135 /* XXX: suppress when better memory API. We make the assumption that
 136    no device (in particular the VGA) changes the memory mappings in
 137    the 0xa0000-0x100000 range */
 138 void i440fx_init_memory_mappings(PCII440FXState *d)
 139 {
 140     int i;
 141     for(i = 0; i < 96; i++) {
 142         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 143     }
 144 }
 145
 146 static void i440fx_write_config(PCIDevice *dev,
 147                                 uint32_t address, uint32_t val, int len)
 148 {
 149     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 150
 151     /* XXX: implement SMRAM.D_LOCK */
 152     pci_default_write_config(dev, address, val, len);
 153     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 154         i440fx_update_memory_mappings(d);
 155 }
 156
 157 static void i440fx_save(QEMUFile* f, void *opaque)
 158 {
 159     PCII440FXState *d = opaque;
 160
 161     pci_device_save(&d->dev, f);
 162     qemu_put_8s(f, &d->smm_enabled);
 163 }
 164
 165 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
 166 {
 167     PCII440FXState *d = opaque;
 168     int ret, i;
 169
 170     if (version_id > 3)
 171         return -EINVAL;
 172     ret = pci_device_load(&d->dev, f);
 173     if (ret < 0)
 174         return ret;
 175     i440fx_update_memory_mappings(d);
 176     qemu_get_8s(f, &d->smm_enabled);
 177
 178     if (version_id == 2)
 179         for (i = 0; i < 4; i++)
 180             d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 181
 182     return 0;
 183 }
 184
 185 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 186 {
 187     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 188
 189     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 190     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 191
 192     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 193     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 194     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 195     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 196     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 197     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 198     return 0;
 199 }
 200
 201 static int i440fx_initfn(PCIDevice *dev)
 202 {
 203     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 204
 205     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 206     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 207     d->dev.config[0x08] = 0x02; // revision
 208     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 209     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 210
 211     d->dev.config[0x72] = 0x02; /* SMRAM */
 212
 213     register_savevm("I440FX", 0, 3, i440fx_save, i440fx_load, d);
 214     return 0;
 215 }
 216
 217 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 218 {
 219     DeviceState *dev;
 220     PCIBus *b;
 221     PCIDevice *d;
 222     I440FXState *s;
 223     PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
 224
 225     irq_state->pic = pic;
 226     dev = qdev_create(NULL, "i440FX-pcihost");
 227     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 228     b = pci_register_bus(&s->busdev.qdev, "pci.0",
 229                          piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
 230     s->bus = b;
 231     qdev_init(dev);
 232
 233     d = pci_create_simple(b, 0, "i440FX");
 234     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 235     (*pi440fx_state)->irq_state = irq_state;
 236
 237     irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
 238                                  pci_create_simple(b, -1, "PIIX3"));
 239     *piix3_devfn = irq_state->piix3->dev.devfn;
 240
 241     return b;
 242 }
 243
 244 /* PIIX3 PCI to ISA bridge */
 245
 246 static void piix3_set_irq(void *opaque, int irq_num, int level)
 247 {
 248     int i, pic_irq, pic_level;
 249     PIIX3IrqState *irq_state = opaque;
 250
 251     irq_state->piix3->pci_irq_levels[irq_num] = level;
 252
 253     /* now we change the pic irq level according to the piix irq mappings */
 254     /* XXX: optimize */
 255     pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
 256     if (pic_irq < 16) {
 257         /* The pic level is the logical OR of all the PCI irqs mapped
 258            to it */
 259         pic_level = 0;
 260         for (i = 0; i < 4; i++) {
 261             if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
 262                 pic_level |= irq_state->piix3->pci_irq_levels[i];
 263         }
 264         qemu_set_irq(irq_state->pic[pic_irq], pic_level);
 265     }
 266 }
 267
 268 static void piix3_reset(void *opaque)
 269 {
 270     PIIX3State *d = opaque;
 271     uint8_t *pci_conf = d->dev.config;
 272
 273     pci_conf[0x04] = 0x07; // master, memory and I/O
 274     pci_conf[0x05] = 0x00;
 275     pci_conf[0x06] = 0x00;
 276     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 277     pci_conf[0x4c] = 0x4d;
 278     pci_conf[0x4e] = 0x03;
 279     pci_conf[0x4f] = 0x00;
 280     pci_conf[0x60] = 0x80;
 281     pci_conf[0x61] = 0x80;
 282     pci_conf[0x62] = 0x80;
 283     pci_conf[0x63] = 0x80;
 284     pci_conf[0x69] = 0x02;
 285     pci_conf[0x70] = 0x80;
 286     pci_conf[0x76] = 0x0c;
 287     pci_conf[0x77] = 0x0c;
 288     pci_conf[0x78] = 0x02;
 289     pci_conf[0x79] = 0x00;
 290     pci_conf[0x80] = 0x00;
 291     pci_conf[0x82] = 0x00;
 292     pci_conf[0xa0] = 0x08;
 293     pci_conf[0xa2] = 0x00;
 294     pci_conf[0xa3] = 0x00;
 295     pci_conf[0xa4] = 0x00;
 296     pci_conf[0xa5] = 0x00;
 297     pci_conf[0xa6] = 0x00;
 298     pci_conf[0xa7] = 0x00;
 299     pci_conf[0xa8] = 0x0f;
 300     pci_conf[0xaa] = 0x00;
 301     pci_conf[0xab] = 0x00;
 302     pci_conf[0xac] = 0x00;
 303     pci_conf[0xae] = 0x00;
 304
 305     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 306 }
 307
 308 static void piix3_save(QEMUFile* f, void *opaque)
 309 {
 310     PIIX3State *d = opaque;
 311     int i;
 312
 313     pci_device_save(&d->dev, f);
 314
 315     for (i = 0; i < 4; i++)
 316         qemu_put_be32(f, d->pci_irq_levels[i]);
 317 }
 318
 319 static int piix3_load(QEMUFile* f, void *opaque, int version_id)
 320 {
 321     PIIX3State *d = opaque;
 322     int i, ret;
 323
 324     if (version_id > 3 || version_id < 2)
 325         return -EINVAL;
 326     ret = pci_device_load(&d->dev, f);
 327     if (ret < 0)
 328         return ret;
 329     if (version_id >= 3) {
 330         for (i = 0; i < 4; i++)
 331             d->pci_irq_levels[i] = qemu_get_be32(f);
 332     }
 333     return 0;
 334 }
 335
 336 static int piix3_initfn(PCIDevice *dev)
 337 {
 338     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 339     uint8_t *pci_conf;
 340
 341     isa_bus_new(&d->dev.qdev);
 342     register_savevm("PIIX3", 0, 3, piix3_save, piix3_load, d);
 343
 344     pci_conf = d->dev.config;
 345     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 346     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 347     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 348     pci_conf[PCI_HEADER_TYPE] =
 349         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 350
 351     piix3_reset(d);
 352     qemu_register_reset(piix3_reset, d);
 353     return 0;
 354 }
 355
 356 static PCIDeviceInfo i440fx_info[] = {
 357     {
 358         .qdev.name    = "i440FX",
 359         .qdev.desc    = "Host bridge",
 360         .qdev.size    = sizeof(PCII440FXState),
 361         .qdev.no_user = 1,
 362         .init         = i440fx_initfn,
 363         .config_write = i440fx_write_config,
 364     },{
 365         .qdev.name    = "PIIX3",
 366         .qdev.desc    = "ISA bridge",
 367         .qdev.size    = sizeof(PIIX3State),
 368         .qdev.no_user = 1,
 369         .init         = piix3_initfn,
 370     },{
 371         /* end of list */
 372     }
 373 };
 374
 375 static SysBusDeviceInfo i440fx_pcihost_info = {
 376     .init         = i440fx_pcihost_initfn,
 377     .qdev.name    = "i440FX-pcihost",
 378     .qdev.size    = sizeof(I440FXState),
 379     .qdev.no_user = 1,
 380 };
 381
 382 static void i440fx_register(void)
 383 {
 384     sysbus_register_withprop(&i440fx_pcihost_info);
 385     pci_qdev_register_many(i440fx_info);
 386 }
 387 device_init(i440fx_register);