2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
8 * Based on implementation by Paolo Bonzini
9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
12 * Paolo Bonzini <pbonzini@redhat.com>
13 * Dmitry Fleytman <dmitry@daynix.com>
14 * Yan Vugenfirer <yan@daynix.com>
16 * This work is licensed under the terms of the GNU GPL, version 2.
17 * See the COPYING file in the top-level directory.
20 * MSI-X support has been removed for the moment because it leads Windows OS
21 * to crash on startup. The crash happens because Windows driver requires
22 * MSI-X shared memory to be part of the same BAR used for rings state
23 * registers, etc. This is not supported by QEMU infrastructure so separate
24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
28 #include "hw/scsi/scsi.h"
29 #include <block/scsi.h>
30 #include "hw/pci/msi.h"
31 #include "vmw_pvscsi.h"
35 #define PVSCSI_MSI_OFFSET (0x50)
36 #define PVSCSI_USE_64BIT (true)
37 #define PVSCSI_PER_VECTOR_MASK (false)
39 #define PVSCSI_MAX_DEVS (64)
40 #define PVSCSI_MSIX_NUM_VECTORS (1)
42 #define PVSCSI_MAX_CMD_DATA_WORDS \
43 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
45 #define RS_GET_FIELD(rs_pa, field) \
46 (ldl_le_phys(&address_space_memory, \
47 rs_pa + offsetof(struct PVSCSIRingsState, field)))
48 #define RS_SET_FIELD(rs_pa, field, val) \
49 (stl_le_phys(&address_space_memory, \
50 rs_pa + offsetof(struct PVSCSIRingsState, field), val))
52 #define TYPE_PVSCSI "pvscsi"
53 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
55 typedef struct PVSCSIRingInfo
{
57 uint32_t txr_len_mask
;
58 uint32_t rxr_len_mask
;
59 uint32_t msg_len_mask
;
60 uint64_t req_ring_pages_pa
[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
];
61 uint64_t cmp_ring_pages_pa
[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
];
62 uint64_t msg_ring_pages_pa
[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES
];
63 uint64_t consumed_ptr
;
64 uint64_t filled_cmp_ptr
;
65 uint64_t filled_msg_ptr
;
68 typedef struct PVSCSISGState
{
74 typedef QTAILQ_HEAD(, PVSCSIRequest
) PVSCSIRequestList
;
78 MemoryRegion io_space
;
80 QEMUBH
*completion_worker
;
81 PVSCSIRequestList pending_queue
;
82 PVSCSIRequestList completion_queue
;
84 uint64_t reg_interrupt_status
; /* Interrupt status register value */
85 uint64_t reg_interrupt_enabled
; /* Interrupt mask register value */
86 uint64_t reg_command_status
; /* Command status register value */
88 /* Command data adoption mechanism */
89 uint64_t curr_cmd
; /* Last command arrived */
90 uint32_t curr_cmd_data_cntr
; /* Amount of data for last command */
92 /* Collector for current command data */
93 uint32_t curr_cmd_data
[PVSCSI_MAX_CMD_DATA_WORDS
];
95 uint8_t rings_info_valid
; /* Whether data rings initialized */
96 uint8_t msg_ring_info_valid
; /* Whether message ring initialized */
97 uint8_t use_msg
; /* Whether to use message ring */
99 uint8_t msi_used
; /* Whether MSI support was installed successfully */
101 PVSCSIRingInfo rings
; /* Data transfer rings manager */
102 uint32_t resetting
; /* Reset in progress */
105 typedef struct PVSCSIRequest
{
113 struct PVSCSIRingReqDesc req
;
114 struct PVSCSIRingCmpDesc cmp
;
115 QTAILQ_ENTRY(PVSCSIRequest
) next
;
118 /* Integer binary logarithm */
120 pvscsi_log2(uint32_t input
)
124 while (input
>> ++log
) {
130 pvscsi_ring_init_data(PVSCSIRingInfo
*m
, PVSCSICmdDescSetupRings
*ri
)
133 uint32_t txr_len_log2
, rxr_len_log2
;
134 uint32_t req_ring_size
, cmp_ring_size
;
135 m
->rs_pa
= ri
->ringsStatePPN
<< VMW_PAGE_SHIFT
;
137 req_ring_size
= ri
->reqRingNumPages
* PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE
;
138 cmp_ring_size
= ri
->cmpRingNumPages
* PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE
;
139 txr_len_log2
= pvscsi_log2(req_ring_size
- 1);
140 rxr_len_log2
= pvscsi_log2(cmp_ring_size
- 1);
142 m
->txr_len_mask
= MASK(txr_len_log2
);
143 m
->rxr_len_mask
= MASK(rxr_len_log2
);
146 m
->filled_cmp_ptr
= 0;
148 for (i
= 0; i
< ri
->reqRingNumPages
; i
++) {
149 m
->req_ring_pages_pa
[i
] = ri
->reqRingPPNs
[i
] << VMW_PAGE_SHIFT
;
152 for (i
= 0; i
< ri
->cmpRingNumPages
; i
++) {
153 m
->cmp_ring_pages_pa
[i
] = ri
->cmpRingPPNs
[i
] << VMW_PAGE_SHIFT
;
156 RS_SET_FIELD(m
->rs_pa
, reqProdIdx
, 0);
157 RS_SET_FIELD(m
->rs_pa
, reqConsIdx
, 0);
158 RS_SET_FIELD(m
->rs_pa
, reqNumEntriesLog2
, txr_len_log2
);
160 RS_SET_FIELD(m
->rs_pa
, cmpProdIdx
, 0);
161 RS_SET_FIELD(m
->rs_pa
, cmpConsIdx
, 0);
162 RS_SET_FIELD(m
->rs_pa
, cmpNumEntriesLog2
, rxr_len_log2
);
164 trace_pvscsi_ring_init_data(txr_len_log2
, rxr_len_log2
);
166 /* Flush ring state page changes */
171 pvscsi_ring_init_msg(PVSCSIRingInfo
*m
, PVSCSICmdDescSetupMsgRing
*ri
)
177 ring_size
= ri
->numPages
* PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE
;
178 len_log2
= pvscsi_log2(ring_size
- 1);
180 m
->msg_len_mask
= MASK(len_log2
);
182 m
->filled_msg_ptr
= 0;
184 for (i
= 0; i
< ri
->numPages
; i
++) {
185 m
->msg_ring_pages_pa
[i
] = ri
->ringPPNs
[i
] << VMW_PAGE_SHIFT
;
188 RS_SET_FIELD(m
->rs_pa
, msgProdIdx
, 0);
189 RS_SET_FIELD(m
->rs_pa
, msgConsIdx
, 0);
190 RS_SET_FIELD(m
->rs_pa
, msgNumEntriesLog2
, len_log2
);
192 trace_pvscsi_ring_init_msg(len_log2
);
194 /* Flush ring state page changes */
199 pvscsi_ring_cleanup(PVSCSIRingInfo
*mgr
)
202 mgr
->txr_len_mask
= 0;
203 mgr
->rxr_len_mask
= 0;
204 mgr
->msg_len_mask
= 0;
205 mgr
->consumed_ptr
= 0;
206 mgr
->filled_cmp_ptr
= 0;
207 mgr
->filled_msg_ptr
= 0;
208 memset(mgr
->req_ring_pages_pa
, 0, sizeof(mgr
->req_ring_pages_pa
));
209 memset(mgr
->cmp_ring_pages_pa
, 0, sizeof(mgr
->cmp_ring_pages_pa
));
210 memset(mgr
->msg_ring_pages_pa
, 0, sizeof(mgr
->msg_ring_pages_pa
));
214 pvscsi_ring_pop_req_descr(PVSCSIRingInfo
*mgr
)
216 uint32_t ready_ptr
= RS_GET_FIELD(mgr
->rs_pa
, reqProdIdx
);
218 if (ready_ptr
!= mgr
->consumed_ptr
) {
219 uint32_t next_ready_ptr
=
220 mgr
->consumed_ptr
++ & mgr
->txr_len_mask
;
221 uint32_t next_ready_page
=
222 next_ready_ptr
/ PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE
;
223 uint32_t inpage_idx
=
224 next_ready_ptr
% PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE
;
226 return mgr
->req_ring_pages_pa
[next_ready_page
] +
227 inpage_idx
* sizeof(PVSCSIRingReqDesc
);
234 pvscsi_ring_flush_req(PVSCSIRingInfo
*mgr
)
236 RS_SET_FIELD(mgr
->rs_pa
, reqConsIdx
, mgr
->consumed_ptr
);
240 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo
*mgr
)
243 * According to Linux driver code it explicitly verifies that number
244 * of requests being processed by device is less then the size of
245 * completion queue, so device may omit completion queue overflow
246 * conditions check. We assume that this is true for other (Windows)
250 uint32_t free_cmp_ptr
=
251 mgr
->filled_cmp_ptr
++ & mgr
->rxr_len_mask
;
252 uint32_t free_cmp_page
=
253 free_cmp_ptr
/ PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE
;
254 uint32_t inpage_idx
=
255 free_cmp_ptr
% PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE
;
256 return mgr
->cmp_ring_pages_pa
[free_cmp_page
] +
257 inpage_idx
* sizeof(PVSCSIRingCmpDesc
);
261 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo
*mgr
)
263 uint32_t free_msg_ptr
=
264 mgr
->filled_msg_ptr
++ & mgr
->msg_len_mask
;
265 uint32_t free_msg_page
=
266 free_msg_ptr
/ PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE
;
267 uint32_t inpage_idx
=
268 free_msg_ptr
% PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE
;
269 return mgr
->msg_ring_pages_pa
[free_msg_page
] +
270 inpage_idx
* sizeof(PVSCSIRingMsgDesc
);
274 pvscsi_ring_flush_cmp(PVSCSIRingInfo
*mgr
)
276 /* Flush descriptor changes */
279 trace_pvscsi_ring_flush_cmp(mgr
->filled_cmp_ptr
);
281 RS_SET_FIELD(mgr
->rs_pa
, cmpProdIdx
, mgr
->filled_cmp_ptr
);
285 pvscsi_ring_msg_has_room(PVSCSIRingInfo
*mgr
)
287 uint32_t prodIdx
= RS_GET_FIELD(mgr
->rs_pa
, msgProdIdx
);
288 uint32_t consIdx
= RS_GET_FIELD(mgr
->rs_pa
, msgConsIdx
);
290 return (prodIdx
- consIdx
) < (mgr
->msg_len_mask
+ 1);
294 pvscsi_ring_flush_msg(PVSCSIRingInfo
*mgr
)
296 /* Flush descriptor changes */
299 trace_pvscsi_ring_flush_msg(mgr
->filled_msg_ptr
);
301 RS_SET_FIELD(mgr
->rs_pa
, msgProdIdx
, mgr
->filled_msg_ptr
);
305 pvscsi_reset_state(PVSCSIState
*s
)
307 s
->curr_cmd
= PVSCSI_CMD_FIRST
;
308 s
->curr_cmd_data_cntr
= 0;
309 s
->reg_command_status
= PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
310 s
->reg_interrupt_status
= 0;
311 pvscsi_ring_cleanup(&s
->rings
);
312 s
->rings_info_valid
= FALSE
;
313 s
->msg_ring_info_valid
= FALSE
;
314 QTAILQ_INIT(&s
->pending_queue
);
315 QTAILQ_INIT(&s
->completion_queue
);
319 pvscsi_update_irq_status(PVSCSIState
*s
)
321 PCIDevice
*d
= PCI_DEVICE(s
);
322 bool should_raise
= s
->reg_interrupt_enabled
& s
->reg_interrupt_status
;
324 trace_pvscsi_update_irq_level(should_raise
, s
->reg_interrupt_enabled
,
325 s
->reg_interrupt_status
);
327 if (s
->msi_used
&& msi_enabled(d
)) {
329 trace_pvscsi_update_irq_msi();
330 msi_notify(d
, PVSCSI_VECTOR_COMPLETION
);
335 pci_set_irq(d
, !!should_raise
);
339 pvscsi_raise_completion_interrupt(PVSCSIState
*s
)
341 s
->reg_interrupt_status
|= PVSCSI_INTR_CMPL_0
;
343 /* Memory barrier to flush interrupt status register changes*/
346 pvscsi_update_irq_status(s
);
350 pvscsi_raise_message_interrupt(PVSCSIState
*s
)
352 s
->reg_interrupt_status
|= PVSCSI_INTR_MSG_0
;
354 /* Memory barrier to flush interrupt status register changes*/
357 pvscsi_update_irq_status(s
);
361 pvscsi_cmp_ring_put(PVSCSIState
*s
, struct PVSCSIRingCmpDesc
*cmp_desc
)
365 cmp_descr_pa
= pvscsi_ring_pop_cmp_descr(&s
->rings
);
366 trace_pvscsi_cmp_ring_put(cmp_descr_pa
);
367 cpu_physical_memory_write(cmp_descr_pa
, (void *)cmp_desc
,
372 pvscsi_msg_ring_put(PVSCSIState
*s
, struct PVSCSIRingMsgDesc
*msg_desc
)
376 msg_descr_pa
= pvscsi_ring_pop_msg_descr(&s
->rings
);
377 trace_pvscsi_msg_ring_put(msg_descr_pa
);
378 cpu_physical_memory_write(msg_descr_pa
, (void *)msg_desc
,
383 pvscsi_process_completion_queue(void *opaque
)
385 PVSCSIState
*s
= opaque
;
386 PVSCSIRequest
*pvscsi_req
;
387 bool has_completed
= false;
389 while (!QTAILQ_EMPTY(&s
->completion_queue
)) {
390 pvscsi_req
= QTAILQ_FIRST(&s
->completion_queue
);
391 QTAILQ_REMOVE(&s
->completion_queue
, pvscsi_req
, next
);
392 pvscsi_cmp_ring_put(s
, &pvscsi_req
->cmp
);
394 has_completed
= true;
398 pvscsi_ring_flush_cmp(&s
->rings
);
399 pvscsi_raise_completion_interrupt(s
);
404 pvscsi_reset_adapter(PVSCSIState
*s
)
407 qbus_reset_all_fn(&s
->bus
);
409 pvscsi_process_completion_queue(s
);
410 assert(QTAILQ_EMPTY(&s
->pending_queue
));
411 pvscsi_reset_state(s
);
415 pvscsi_schedule_completion_processing(PVSCSIState
*s
)
417 /* Try putting more complete requests on the ring. */
418 if (!QTAILQ_EMPTY(&s
->completion_queue
)) {
419 qemu_bh_schedule(s
->completion_worker
);
424 pvscsi_complete_request(PVSCSIState
*s
, PVSCSIRequest
*r
)
426 assert(!r
->completed
);
428 trace_pvscsi_complete_request(r
->cmp
.context
, r
->cmp
.dataLen
,
430 if (r
->sreq
!= NULL
) {
431 scsi_req_unref(r
->sreq
);
435 QTAILQ_REMOVE(&s
->pending_queue
, r
, next
);
436 QTAILQ_INSERT_TAIL(&s
->completion_queue
, r
, next
);
437 pvscsi_schedule_completion_processing(s
);
440 static QEMUSGList
*pvscsi_get_sg_list(SCSIRequest
*r
)
442 PVSCSIRequest
*req
= r
->hba_private
;
444 trace_pvscsi_get_sg_list(req
->sgl
.nsg
, req
->sgl
.size
);
450 pvscsi_get_next_sg_elem(PVSCSISGState
*sg
)
452 struct PVSCSISGElement elem
;
454 cpu_physical_memory_read(sg
->elemAddr
, (void *)&elem
, sizeof(elem
));
455 if ((elem
.flags
& ~PVSCSI_KNOWN_FLAGS
) != 0) {
457 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
458 * header file but its value is unknown. This flag requires
459 * additional processing, so we put warning here to catch it
460 * some day and make proper implementation
462 trace_pvscsi_get_next_sg_elem(elem
.flags
);
465 sg
->elemAddr
+= sizeof(elem
);
466 sg
->dataAddr
= elem
.addr
;
467 sg
->resid
= elem
.length
;
471 pvscsi_write_sense(PVSCSIRequest
*r
, uint8_t *sense
, int len
)
473 r
->cmp
.senseLen
= MIN(r
->req
.senseLen
, len
);
474 r
->sense_key
= sense
[(sense
[0] & 2) ? 1 : 2];
475 cpu_physical_memory_write(r
->req
.senseAddr
, sense
, r
->cmp
.senseLen
);
479 pvscsi_command_complete(SCSIRequest
*req
, uint32_t status
, size_t resid
)
481 PVSCSIRequest
*pvscsi_req
= req
->hba_private
;
485 trace_pvscsi_command_complete_not_found(req
->tag
);
491 /* Short transfer. */
492 trace_pvscsi_command_complete_data_run();
493 pvscsi_req
->cmp
.hostStatus
= BTSTAT_DATARUN
;
496 pvscsi_req
->cmp
.scsiStatus
= status
;
497 if (pvscsi_req
->cmp
.scsiStatus
== CHECK_CONDITION
) {
498 uint8_t sense
[SCSI_SENSE_BUF_SIZE
];
500 scsi_req_get_sense(pvscsi_req
->sreq
, sense
, sizeof(sense
));
502 trace_pvscsi_command_complete_sense_len(sense_len
);
503 pvscsi_write_sense(pvscsi_req
, sense
, sense_len
);
505 qemu_sglist_destroy(&pvscsi_req
->sgl
);
506 pvscsi_complete_request(s
, pvscsi_req
);
510 pvscsi_send_msg(PVSCSIState
*s
, SCSIDevice
*dev
, uint32_t msg_type
)
512 if (s
->msg_ring_info_valid
&& pvscsi_ring_msg_has_room(&s
->rings
)) {
513 PVSCSIMsgDescDevStatusChanged msg
= {0};
516 msg
.bus
= dev
->channel
;
517 msg
.target
= dev
->id
;
518 msg
.lun
[1] = dev
->lun
;
520 pvscsi_msg_ring_put(s
, (PVSCSIRingMsgDesc
*)&msg
);
521 pvscsi_ring_flush_msg(&s
->rings
);
522 pvscsi_raise_message_interrupt(s
);
527 pvscsi_hotplug(SCSIBus
*bus
, SCSIDevice
*dev
)
529 PVSCSIState
*s
= container_of(bus
, PVSCSIState
, bus
);
530 pvscsi_send_msg(s
, dev
, PVSCSI_MSG_DEV_ADDED
);
534 pvscsi_hot_unplug(SCSIBus
*bus
, SCSIDevice
*dev
)
536 PVSCSIState
*s
= container_of(bus
, PVSCSIState
, bus
);
537 pvscsi_send_msg(s
, dev
, PVSCSI_MSG_DEV_REMOVED
);
541 pvscsi_request_cancelled(SCSIRequest
*req
)
543 PVSCSIRequest
*pvscsi_req
= req
->hba_private
;
544 PVSCSIState
*s
= pvscsi_req
->dev
;
546 if (pvscsi_req
->completed
) {
550 if (pvscsi_req
->dev
->resetting
) {
551 pvscsi_req
->cmp
.hostStatus
= BTSTAT_BUSRESET
;
553 pvscsi_req
->cmp
.hostStatus
= BTSTAT_ABORTQUEUE
;
556 pvscsi_complete_request(s
, pvscsi_req
);
560 pvscsi_device_find(PVSCSIState
*s
, int channel
, int target
,
561 uint8_t *requested_lun
, uint8_t *target_lun
)
563 if (requested_lun
[0] || requested_lun
[2] || requested_lun
[3] ||
564 requested_lun
[4] || requested_lun
[5] || requested_lun
[6] ||
565 requested_lun
[7] || (target
> PVSCSI_MAX_DEVS
)) {
568 *target_lun
= requested_lun
[1];
569 return scsi_device_find(&s
->bus
, channel
, target
, *target_lun
);
573 static PVSCSIRequest
*
574 pvscsi_queue_pending_descriptor(PVSCSIState
*s
, SCSIDevice
**d
,
575 struct PVSCSIRingReqDesc
*descr
)
577 PVSCSIRequest
*pvscsi_req
;
580 pvscsi_req
= g_malloc0(sizeof(*pvscsi_req
));
582 pvscsi_req
->req
= *descr
;
583 pvscsi_req
->cmp
.context
= pvscsi_req
->req
.context
;
584 QTAILQ_INSERT_TAIL(&s
->pending_queue
, pvscsi_req
, next
);
586 *d
= pvscsi_device_find(s
, descr
->bus
, descr
->target
, descr
->lun
, &lun
);
588 pvscsi_req
->lun
= lun
;
595 pvscsi_convert_sglist(PVSCSIRequest
*r
)
598 uint64_t data_length
= r
->req
.dataLen
;
599 PVSCSISGState sg
= r
->sg
;
600 while (data_length
) {
602 pvscsi_get_next_sg_elem(&sg
);
603 trace_pvscsi_convert_sglist(r
->req
.context
, r
->sg
.dataAddr
,
606 assert(data_length
> 0);
607 chunk_size
= MIN((unsigned) data_length
, sg
.resid
);
609 qemu_sglist_add(&r
->sgl
, sg
.dataAddr
, chunk_size
);
612 sg
.dataAddr
+= chunk_size
;
613 data_length
-= chunk_size
;
614 sg
.resid
-= chunk_size
;
619 pvscsi_build_sglist(PVSCSIState
*s
, PVSCSIRequest
*r
)
621 PCIDevice
*d
= PCI_DEVICE(s
);
623 pci_dma_sglist_init(&r
->sgl
, d
, 1);
624 if (r
->req
.flags
& PVSCSI_FLAG_CMD_WITH_SG_LIST
) {
625 pvscsi_convert_sglist(r
);
627 qemu_sglist_add(&r
->sgl
, r
->req
.dataAddr
, r
->req
.dataLen
);
632 pvscsi_process_request_descriptor(PVSCSIState
*s
,
633 struct PVSCSIRingReqDesc
*descr
)
636 PVSCSIRequest
*r
= pvscsi_queue_pending_descriptor(s
, &d
, descr
);
639 trace_pvscsi_process_req_descr(descr
->cdb
[0], descr
->context
);
642 r
->cmp
.hostStatus
= BTSTAT_SELTIMEO
;
643 trace_pvscsi_process_req_descr_unknown_device();
644 pvscsi_complete_request(s
, r
);
648 if (descr
->flags
& PVSCSI_FLAG_CMD_WITH_SG_LIST
) {
649 r
->sg
.elemAddr
= descr
->dataAddr
;
652 r
->sreq
= scsi_req_new(d
, descr
->context
, r
->lun
, descr
->cdb
, r
);
653 if (r
->sreq
->cmd
.mode
== SCSI_XFER_FROM_DEV
&&
654 (descr
->flags
& PVSCSI_FLAG_CMD_DIR_TODEVICE
)) {
655 r
->cmp
.hostStatus
= BTSTAT_BADMSG
;
656 trace_pvscsi_process_req_descr_invalid_dir();
657 scsi_req_cancel(r
->sreq
);
660 if (r
->sreq
->cmd
.mode
== SCSI_XFER_TO_DEV
&&
661 (descr
->flags
& PVSCSI_FLAG_CMD_DIR_TOHOST
)) {
662 r
->cmp
.hostStatus
= BTSTAT_BADMSG
;
663 trace_pvscsi_process_req_descr_invalid_dir();
664 scsi_req_cancel(r
->sreq
);
668 pvscsi_build_sglist(s
, r
);
669 n
= scsi_req_enqueue(r
->sreq
);
672 scsi_req_continue(r
->sreq
);
677 pvscsi_process_io(PVSCSIState
*s
)
679 PVSCSIRingReqDesc descr
;
680 hwaddr next_descr_pa
;
682 assert(s
->rings_info_valid
);
683 while ((next_descr_pa
= pvscsi_ring_pop_req_descr(&s
->rings
)) != 0) {
685 /* Only read after production index verification */
688 trace_pvscsi_process_io(next_descr_pa
);
689 cpu_physical_memory_read(next_descr_pa
, &descr
, sizeof(descr
));
690 pvscsi_process_request_descriptor(s
, &descr
);
693 pvscsi_ring_flush_req(&s
->rings
);
697 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings
*rc
)
700 trace_pvscsi_tx_rings_ppn("Rings State", rc
->ringsStatePPN
);
702 trace_pvscsi_tx_rings_num_pages("Request Ring", rc
->reqRingNumPages
);
703 for (i
= 0; i
< rc
->reqRingNumPages
; i
++) {
704 trace_pvscsi_tx_rings_ppn("Request Ring", rc
->reqRingPPNs
[i
]);
707 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc
->cmpRingNumPages
);
708 for (i
= 0; i
< rc
->cmpRingNumPages
; i
++) {
709 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc
->reqRingPPNs
[i
]);
714 pvscsi_on_cmd_config(PVSCSIState
*s
)
716 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
717 return PVSCSI_COMMAND_PROCESSING_FAILED
;
721 pvscsi_on_cmd_unplug(PVSCSIState
*s
)
723 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
724 return PVSCSI_COMMAND_PROCESSING_FAILED
;
728 pvscsi_on_issue_scsi(PVSCSIState
*s
)
730 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
731 return PVSCSI_COMMAND_PROCESSING_FAILED
;
735 pvscsi_on_cmd_setup_rings(PVSCSIState
*s
)
737 PVSCSICmdDescSetupRings
*rc
=
738 (PVSCSICmdDescSetupRings
*) s
->curr_cmd_data
;
740 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
742 pvscsi_dbg_dump_tx_rings_config(rc
);
743 pvscsi_ring_init_data(&s
->rings
, rc
);
744 s
->rings_info_valid
= TRUE
;
745 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
749 pvscsi_on_cmd_abort(PVSCSIState
*s
)
751 PVSCSICmdDescAbortCmd
*cmd
= (PVSCSICmdDescAbortCmd
*) s
->curr_cmd_data
;
752 PVSCSIRequest
*r
, *next
;
754 trace_pvscsi_on_cmd_abort(cmd
->context
, cmd
->target
);
756 QTAILQ_FOREACH_SAFE(r
, &s
->pending_queue
, next
, next
) {
757 if (r
->req
.context
== cmd
->context
) {
762 assert(!r
->completed
);
763 r
->cmp
.hostStatus
= BTSTAT_ABORTQUEUE
;
764 scsi_req_cancel(r
->sreq
);
767 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
771 pvscsi_on_cmd_unknown(PVSCSIState
*s
)
773 trace_pvscsi_on_cmd_unknown_data(s
->curr_cmd_data
[0]);
774 return PVSCSI_COMMAND_PROCESSING_FAILED
;
778 pvscsi_on_cmd_reset_device(PVSCSIState
*s
)
780 uint8_t target_lun
= 0;
781 struct PVSCSICmdDescResetDevice
*cmd
=
782 (struct PVSCSICmdDescResetDevice
*) s
->curr_cmd_data
;
785 sdev
= pvscsi_device_find(s
, 0, cmd
->target
, cmd
->lun
, &target_lun
);
787 trace_pvscsi_on_cmd_reset_dev(cmd
->target
, (int) target_lun
, sdev
);
791 device_reset(&sdev
->qdev
);
793 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
796 return PVSCSI_COMMAND_PROCESSING_FAILED
;
800 pvscsi_on_cmd_reset_bus(PVSCSIState
*s
)
802 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
805 qbus_reset_all_fn(&s
->bus
);
807 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
811 pvscsi_on_cmd_setup_msg_ring(PVSCSIState
*s
)
813 PVSCSICmdDescSetupMsgRing
*rc
=
814 (PVSCSICmdDescSetupMsgRing
*) s
->curr_cmd_data
;
816 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
819 return PVSCSI_COMMAND_PROCESSING_FAILED
;
822 if (s
->rings_info_valid
) {
823 pvscsi_ring_init_msg(&s
->rings
, rc
);
824 s
->msg_ring_info_valid
= TRUE
;
826 return sizeof(PVSCSICmdDescSetupMsgRing
) / sizeof(uint32_t);
830 pvscsi_on_cmd_adapter_reset(PVSCSIState
*s
)
832 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
834 pvscsi_reset_adapter(s
);
835 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED
;
838 static const struct {
840 uint64_t (*handler_fn
)(PVSCSIState
*s
);
841 } pvscsi_commands
[] = {
842 [PVSCSI_CMD_FIRST
] = {
844 .handler_fn
= pvscsi_on_cmd_unknown
,
847 /* Not implemented, data size defined based on what arrives on windows */
848 [PVSCSI_CMD_CONFIG
] = {
849 .data_size
= 6 * sizeof(uint32_t),
850 .handler_fn
= pvscsi_on_cmd_config
,
853 /* Command not implemented, data size is unknown */
854 [PVSCSI_CMD_ISSUE_SCSI
] = {
856 .handler_fn
= pvscsi_on_issue_scsi
,
859 /* Command not implemented, data size is unknown */
860 [PVSCSI_CMD_DEVICE_UNPLUG
] = {
862 .handler_fn
= pvscsi_on_cmd_unplug
,
865 [PVSCSI_CMD_SETUP_RINGS
] = {
866 .data_size
= sizeof(PVSCSICmdDescSetupRings
),
867 .handler_fn
= pvscsi_on_cmd_setup_rings
,
870 [PVSCSI_CMD_RESET_DEVICE
] = {
871 .data_size
= sizeof(struct PVSCSICmdDescResetDevice
),
872 .handler_fn
= pvscsi_on_cmd_reset_device
,
875 [PVSCSI_CMD_RESET_BUS
] = {
877 .handler_fn
= pvscsi_on_cmd_reset_bus
,
880 [PVSCSI_CMD_SETUP_MSG_RING
] = {
881 .data_size
= sizeof(PVSCSICmdDescSetupMsgRing
),
882 .handler_fn
= pvscsi_on_cmd_setup_msg_ring
,
885 [PVSCSI_CMD_ADAPTER_RESET
] = {
887 .handler_fn
= pvscsi_on_cmd_adapter_reset
,
890 [PVSCSI_CMD_ABORT_CMD
] = {
891 .data_size
= sizeof(struct PVSCSICmdDescAbortCmd
),
892 .handler_fn
= pvscsi_on_cmd_abort
,
897 pvscsi_do_command_processing(PVSCSIState
*s
)
899 size_t bytes_arrived
= s
->curr_cmd_data_cntr
* sizeof(uint32_t);
901 assert(s
->curr_cmd
< PVSCSI_CMD_LAST
);
902 if (bytes_arrived
>= pvscsi_commands
[s
->curr_cmd
].data_size
) {
903 s
->reg_command_status
= pvscsi_commands
[s
->curr_cmd
].handler_fn(s
);
904 s
->curr_cmd
= PVSCSI_CMD_FIRST
;
905 s
->curr_cmd_data_cntr
= 0;
910 pvscsi_on_command_data(PVSCSIState
*s
, uint32_t value
)
912 size_t bytes_arrived
= s
->curr_cmd_data_cntr
* sizeof(uint32_t);
914 assert(bytes_arrived
< sizeof(s
->curr_cmd_data
));
915 s
->curr_cmd_data
[s
->curr_cmd_data_cntr
++] = value
;
917 pvscsi_do_command_processing(s
);
921 pvscsi_on_command(PVSCSIState
*s
, uint64_t cmd_id
)
923 if ((cmd_id
> PVSCSI_CMD_FIRST
) && (cmd_id
< PVSCSI_CMD_LAST
)) {
924 s
->curr_cmd
= cmd_id
;
926 s
->curr_cmd
= PVSCSI_CMD_FIRST
;
927 trace_pvscsi_on_cmd_unknown(cmd_id
);
930 s
->curr_cmd_data_cntr
= 0;
931 s
->reg_command_status
= PVSCSI_COMMAND_NOT_ENOUGH_DATA
;
933 pvscsi_do_command_processing(s
);
937 pvscsi_io_write(void *opaque
, hwaddr addr
,
938 uint64_t val
, unsigned size
)
940 PVSCSIState
*s
= opaque
;
943 case PVSCSI_REG_OFFSET_COMMAND
:
944 pvscsi_on_command(s
, val
);
947 case PVSCSI_REG_OFFSET_COMMAND_DATA
:
948 pvscsi_on_command_data(s
, (uint32_t) val
);
951 case PVSCSI_REG_OFFSET_INTR_STATUS
:
952 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val
);
953 s
->reg_interrupt_status
&= ~val
;
954 pvscsi_update_irq_status(s
);
955 pvscsi_schedule_completion_processing(s
);
958 case PVSCSI_REG_OFFSET_INTR_MASK
:
959 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val
);
960 s
->reg_interrupt_enabled
= val
;
961 pvscsi_update_irq_status(s
);
964 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO
:
965 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val
);
966 pvscsi_process_io(s
);
969 case PVSCSI_REG_OFFSET_KICK_RW_IO
:
970 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val
);
971 pvscsi_process_io(s
);
974 case PVSCSI_REG_OFFSET_DEBUG
:
975 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val
);
979 trace_pvscsi_io_write_unknown(addr
, size
, val
);
986 pvscsi_io_read(void *opaque
, hwaddr addr
, unsigned size
)
988 PVSCSIState
*s
= opaque
;
991 case PVSCSI_REG_OFFSET_INTR_STATUS
:
992 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
993 s
->reg_interrupt_status
);
994 return s
->reg_interrupt_status
;
996 case PVSCSI_REG_OFFSET_INTR_MASK
:
997 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
998 s
->reg_interrupt_status
);
999 return s
->reg_interrupt_enabled
;
1001 case PVSCSI_REG_OFFSET_COMMAND_STATUS
:
1002 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1003 s
->reg_interrupt_status
);
1004 return s
->reg_command_status
;
1007 trace_pvscsi_io_read_unknown(addr
, size
);
1014 pvscsi_init_msi(PVSCSIState
*s
)
1017 PCIDevice
*d
= PCI_DEVICE(s
);
1019 res
= msi_init(d
, PVSCSI_MSI_OFFSET
, PVSCSI_MSIX_NUM_VECTORS
,
1020 PVSCSI_USE_64BIT
, PVSCSI_PER_VECTOR_MASK
);
1022 trace_pvscsi_init_msi_fail(res
);
1023 s
->msi_used
= false;
1032 pvscsi_cleanup_msi(PVSCSIState
*s
)
1034 PCIDevice
*d
= PCI_DEVICE(s
);
1041 static const MemoryRegionOps pvscsi_ops
= {
1042 .read
= pvscsi_io_read
,
1043 .write
= pvscsi_io_write
,
1044 .endianness
= DEVICE_LITTLE_ENDIAN
,
1046 .min_access_size
= 4,
1047 .max_access_size
= 4,
1051 static const struct SCSIBusInfo pvscsi_scsi_info
= {
1053 .max_target
= PVSCSI_MAX_DEVS
,
1057 .get_sg_list
= pvscsi_get_sg_list
,
1058 .complete
= pvscsi_command_complete
,
1059 .cancel
= pvscsi_request_cancelled
,
1060 .hotplug
= pvscsi_hotplug
,
1061 .hot_unplug
= pvscsi_hot_unplug
,
1065 pvscsi_init(PCIDevice
*pci_dev
)
1067 PVSCSIState
*s
= PVSCSI(pci_dev
);
1069 trace_pvscsi_state("init");
1071 /* PCI subsystem ID */
1072 pci_dev
->config
[PCI_SUBSYSTEM_ID
] = 0x00;
1073 pci_dev
->config
[PCI_SUBSYSTEM_ID
+ 1] = 0x10;
1075 /* PCI latency timer = 255 */
1076 pci_dev
->config
[PCI_LATENCY_TIMER
] = 0xff;
1078 /* Interrupt pin A */
1079 pci_config_set_interrupt_pin(pci_dev
->config
, 1);
1081 memory_region_init_io(&s
->io_space
, OBJECT(s
), &pvscsi_ops
, s
,
1082 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE
);
1083 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->io_space
);
1087 s
->completion_worker
= qemu_bh_new(pvscsi_process_completion_queue
, s
);
1088 if (!s
->completion_worker
) {
1089 pvscsi_cleanup_msi(s
);
1090 memory_region_destroy(&s
->io_space
);
1094 scsi_bus_new(&s
->bus
, sizeof(s
->bus
), DEVICE(pci_dev
),
1095 &pvscsi_scsi_info
, NULL
);
1096 pvscsi_reset_state(s
);
1102 pvscsi_uninit(PCIDevice
*pci_dev
)
1104 PVSCSIState
*s
= PVSCSI(pci_dev
);
1106 trace_pvscsi_state("uninit");
1107 qemu_bh_delete(s
->completion_worker
);
1109 pvscsi_cleanup_msi(s
);
1111 memory_region_destroy(&s
->io_space
);
1115 pvscsi_reset(DeviceState
*dev
)
1117 PCIDevice
*d
= PCI_DEVICE(dev
);
1118 PVSCSIState
*s
= PVSCSI(d
);
1120 trace_pvscsi_state("reset");
1121 pvscsi_reset_adapter(s
);
1125 pvscsi_pre_save(void *opaque
)
1127 PVSCSIState
*s
= (PVSCSIState
*) opaque
;
1129 trace_pvscsi_state("presave");
1131 assert(QTAILQ_EMPTY(&s
->pending_queue
));
1132 assert(QTAILQ_EMPTY(&s
->completion_queue
));
1136 pvscsi_post_load(void *opaque
, int version_id
)
1138 trace_pvscsi_state("postload");
1142 static const VMStateDescription vmstate_pvscsi
= {
1145 .minimum_version_id
= 0,
1146 .minimum_version_id_old
= 0,
1147 .pre_save
= pvscsi_pre_save
,
1148 .post_load
= pvscsi_post_load
,
1149 .fields
= (VMStateField
[]) {
1150 VMSTATE_PCI_DEVICE(parent_obj
, PVSCSIState
),
1151 VMSTATE_UINT8(msi_used
, PVSCSIState
),
1152 VMSTATE_UINT32(resetting
, PVSCSIState
),
1153 VMSTATE_UINT64(reg_interrupt_status
, PVSCSIState
),
1154 VMSTATE_UINT64(reg_interrupt_enabled
, PVSCSIState
),
1155 VMSTATE_UINT64(reg_command_status
, PVSCSIState
),
1156 VMSTATE_UINT64(curr_cmd
, PVSCSIState
),
1157 VMSTATE_UINT32(curr_cmd_data_cntr
, PVSCSIState
),
1158 VMSTATE_UINT32_ARRAY(curr_cmd_data
, PVSCSIState
,
1159 ARRAY_SIZE(((PVSCSIState
*)NULL
)->curr_cmd_data
)),
1160 VMSTATE_UINT8(rings_info_valid
, PVSCSIState
),
1161 VMSTATE_UINT8(msg_ring_info_valid
, PVSCSIState
),
1162 VMSTATE_UINT8(use_msg
, PVSCSIState
),
1164 VMSTATE_UINT64(rings
.rs_pa
, PVSCSIState
),
1165 VMSTATE_UINT32(rings
.txr_len_mask
, PVSCSIState
),
1166 VMSTATE_UINT32(rings
.rxr_len_mask
, PVSCSIState
),
1167 VMSTATE_UINT64_ARRAY(rings
.req_ring_pages_pa
, PVSCSIState
,
1168 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
),
1169 VMSTATE_UINT64_ARRAY(rings
.cmp_ring_pages_pa
, PVSCSIState
,
1170 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
),
1171 VMSTATE_UINT64(rings
.consumed_ptr
, PVSCSIState
),
1172 VMSTATE_UINT64(rings
.filled_cmp_ptr
, PVSCSIState
),
1174 VMSTATE_END_OF_LIST()
1179 pvscsi_write_config(PCIDevice
*pci
, uint32_t addr
, uint32_t val
, int len
)
1181 pci_default_write_config(pci
, addr
, val
, len
);
1182 msi_write_config(pci
, addr
, val
, len
);
1185 static Property pvscsi_properties
[] = {
1186 DEFINE_PROP_UINT8("use_msg", PVSCSIState
, use_msg
, 1),
1187 DEFINE_PROP_END_OF_LIST(),
1190 static void pvscsi_class_init(ObjectClass
*klass
, void *data
)
1192 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1193 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1195 k
->init
= pvscsi_init
;
1196 k
->exit
= pvscsi_uninit
;
1197 k
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
1198 k
->device_id
= PCI_DEVICE_ID_VMWARE_PVSCSI
;
1199 k
->class_id
= PCI_CLASS_STORAGE_SCSI
;
1200 k
->subsystem_id
= 0x1000;
1201 dc
->reset
= pvscsi_reset
;
1202 dc
->vmsd
= &vmstate_pvscsi
;
1203 dc
->props
= pvscsi_properties
;
1204 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1205 k
->config_write
= pvscsi_write_config
;
1208 static const TypeInfo pvscsi_info
= {
1209 .name
= TYPE_PVSCSI
,
1210 .parent
= TYPE_PCI_DEVICE
,
1211 .instance_size
= sizeof(PVSCSIState
),
1212 .class_init
= pvscsi_class_init
,
1216 pvscsi_register_types(void)
1218 type_register_static(&pvscsi_info
);
1221 type_init(pvscsi_register_types
);