target-mips/kvm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012-2014 Imagination Technologies Ltd.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10 */
  11
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/error-report.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/kvm.h"
  23 #include "cpu.h"
  24 #include "sysemu/cpus.h"
  25 #include "kvm_mips.h"
  26 #include "exec/memattrs.h"
  27
  28 #define DEBUG_KVM 0
  29
  30 #define DPRINTF(fmt, ...) \
  31     do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
  32
  33 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  34     KVM_CAP_LAST_INFO
  35 };
  36
  37 static void kvm_mips_update_state(void *opaque, int running, RunState state);
  38
  39 unsigned long kvm_arch_vcpu_id(CPUState *cs)
  40 {
  41     return cs->cpu_index;
  42 }
  43
  44 int kvm_arch_init(MachineState *ms, KVMState *s)
  45 {
  46     /* MIPS has 128 signals */
  47     kvm_set_sigmask_len(s, 16);
  48
  49     DPRINTF("%s\n", __func__);
  50     return 0;
  51 }
  52
  53 int kvm_arch_init_vcpu(CPUState *cs)
  54 {
  55     int ret = 0;
  56
  57     qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
  58
  59     DPRINTF("%s\n", __func__);
  60     return ret;
  61 }
  62
  63 void kvm_mips_reset_vcpu(MIPSCPU *cpu)
  64 {
  65     CPUMIPSState *env = &cpu->env;
  66
  67     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
  68         fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
  69         env->CP0_Config1 &= ~(1 << CP0C1_FP);
  70     }
  71
  72     DPRINTF("%s\n", __func__);
  73 }
  74
  75 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  76 {
  77     DPRINTF("%s\n", __func__);
  78     return 0;
  79 }
  80
  81 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
  82 {
  83     DPRINTF("%s\n", __func__);
  84     return 0;
  85 }
  86
  87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
  88 {
  89     CPUMIPSState *env = &cpu->env;
  90
  91     DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
  92     return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
  93 }
  94
  95
  96 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
  97 {
  98     MIPSCPU *cpu = MIPS_CPU(cs);
  99     int r;
 100     struct kvm_mips_interrupt intr;
 101
 102     qemu_mutex_lock_iothread();
 103
 104     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 105             cpu_mips_io_interrupts_pending(cpu)) {
 106         intr.cpu = -1;
 107         intr.irq = 2;
 108         r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 109         if (r < 0) {
 110             error_report("%s: cpu %d: failed to inject IRQ %x",
 111                          __func__, cs->cpu_index, intr.irq);
 112         }
 113     }
 114
 115     qemu_mutex_unlock_iothread();
 116 }
 117
 118 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
 119 {
 120     DPRINTF("%s\n", __func__);
 121     return MEMTXATTRS_UNSPECIFIED;
 122 }
 123
 124 int kvm_arch_process_async_events(CPUState *cs)
 125 {
 126     return cs->halted;
 127 }
 128
 129 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 130 {
 131     int ret;
 132
 133     DPRINTF("%s\n", __func__);
 134     switch (run->exit_reason) {
 135     default:
 136         error_report("%s: unknown exit reason %d",
 137                      __func__, run->exit_reason);
 138         ret = -1;
 139         break;
 140     }
 141
 142     return ret;
 143 }
 144
 145 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
 146 {
 147     DPRINTF("%s\n", __func__);
 148     return true;
 149 }
 150
 151 int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
 152 {
 153     DPRINTF("%s\n", __func__);
 154     return 1;
 155 }
 156
 157 int kvm_arch_on_sigbus(int code, void *addr)
 158 {
 159     DPRINTF("%s\n", __func__);
 160     return 1;
 161 }
 162
 163 void kvm_arch_init_irq_routing(KVMState *s)
 164 {
 165 }
 166
 167 int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
 168 {
 169     CPUState *cs = CPU(cpu);
 170     struct kvm_mips_interrupt intr;
 171
 172     if (!kvm_enabled()) {
 173         return 0;
 174     }
 175
 176     intr.cpu = -1;
 177
 178     if (level) {
 179         intr.irq = irq;
 180     } else {
 181         intr.irq = -irq;
 182     }
 183
 184     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 185
 186     return 0;
 187 }
 188
 189 int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 190 {
 191     CPUState *cs = current_cpu;
 192     CPUState *dest_cs = CPU(cpu);
 193     struct kvm_mips_interrupt intr;
 194
 195     if (!kvm_enabled()) {
 196         return 0;
 197     }
 198
 199     intr.cpu = dest_cs->cpu_index;
 200
 201     if (level) {
 202         intr.irq = irq;
 203     } else {
 204         intr.irq = -irq;
 205     }
 206
 207     DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
 208
 209     kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
 210
 211     return 0;
 212 }
 213
 214 #define MIPS_CP0_32(_R, _S)                                     \
 215     (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
 216
 217 #define MIPS_CP0_64(_R, _S)                                     \
 218     (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
 219
 220 #define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
 221 #define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
 222 #define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
 223 #define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
 224 #define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
 225 #define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
 226 #define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
 227 #define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
 228 #define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
 229 #define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
 230 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 231 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 232 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
 233 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 234
 235 /* CP0_Count control */
 236 #define KVM_REG_MIPS_COUNT_CTL          (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 237                                          0x20000 | 0)
 238 #define KVM_REG_MIPS_COUNT_CTL_DC       0x00000001      /* master disable */
 239 /* CP0_Count resume monotonic nanoseconds */
 240 #define KVM_REG_MIPS_COUNT_RESUME       (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 241                                          0x20000 | 1)
 242 /* CP0_Count rate in Hz */
 243 #define KVM_REG_MIPS_COUNT_HZ           (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
 244                                          0x20000 | 2)
 245
 246 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
 247                                        int32_t *addr)
 248 {
 249     uint64_t val64 = *addr;
 250     struct kvm_one_reg cp0reg = {
 251         .id = reg_id,
 252         .addr = (uintptr_t)&val64
 253     };
 254
 255     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 256 }
 257
 258 static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
 259                                          target_ulong *addr)
 260 {
 261     uint64_t val64 = *addr;
 262     struct kvm_one_reg cp0reg = {
 263         .id = reg_id,
 264         .addr = (uintptr_t)&val64
 265     };
 266
 267     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 268 }
 269
 270 static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
 271                                          uint64_t *addr)
 272 {
 273     struct kvm_one_reg cp0reg = {
 274         .id = reg_id,
 275         .addr = (uintptr_t)addr
 276     };
 277
 278     return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
 279 }
 280
 281 static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
 282                                        int32_t *addr)
 283 {
 284     int ret;
 285     uint64_t val64 = 0;
 286     struct kvm_one_reg cp0reg = {
 287         .id = reg_id,
 288         .addr = (uintptr_t)&val64
 289     };
 290
 291     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 292     if (ret >= 0) {
 293         *addr = val64;
 294     }
 295     return ret;
 296 }
 297
 298 static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,
 299                                          target_ulong *addr)
 300 {
 301     int ret;
 302     uint64_t val64 = 0;
 303     struct kvm_one_reg cp0reg = {
 304         .id = reg_id,
 305         .addr = (uintptr_t)&val64
 306     };
 307
 308     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 309     if (ret >= 0) {
 310         *addr = val64;
 311     }
 312     return ret;
 313 }
 314
 315 static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id,
 316                                          uint64_t *addr)
 317 {
 318     struct kvm_one_reg cp0reg = {
 319         .id = reg_id,
 320         .addr = (uintptr_t)addr
 321     };
 322
 323     return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
 324 }
 325
 326 /*
 327  * We freeze the KVM timer when either the VM clock is stopped or the state is
 328  * saved (the state is dirty).
 329  */
 330
 331 /*
 332  * Save the state of the KVM timer when VM clock is stopped or state is synced
 333  * to QEMU.
 334  */
 335 static int kvm_mips_save_count(CPUState *cs)
 336 {
 337     MIPSCPU *cpu = MIPS_CPU(cs);
 338     CPUMIPSState *env = &cpu->env;
 339     uint64_t count_ctl;
 340     int err, ret = 0;
 341
 342     /* freeze KVM timer */
 343     err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 344     if (err < 0) {
 345         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
 346         ret = err;
 347     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 348         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 349         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 350         if (err < 0) {
 351             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 352             ret = err;
 353         }
 354     }
 355
 356     /* read CP0_Cause */
 357     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 358     if (err < 0) {
 359         DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
 360         ret = err;
 361     }
 362
 363     /* read CP0_Count */
 364     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 365     if (err < 0) {
 366         DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
 367         ret = err;
 368     }
 369
 370     return ret;
 371 }
 372
 373 /*
 374  * Restore the state of the KVM timer when VM clock is restarted or state is
 375  * synced to KVM.
 376  */
 377 static int kvm_mips_restore_count(CPUState *cs)
 378 {
 379     MIPSCPU *cpu = MIPS_CPU(cs);
 380     CPUMIPSState *env = &cpu->env;
 381     uint64_t count_ctl;
 382     int err_dc, err, ret = 0;
 383
 384     /* check the timer is frozen */
 385     err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 386     if (err_dc < 0) {
 387         DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
 388         ret = err_dc;
 389     } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
 390         /* freeze timer (sets COUNT_RESUME for us) */
 391         count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
 392         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 393         if (err < 0) {
 394             DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
 395             ret = err;
 396         }
 397     }
 398
 399     /* load CP0_Cause */
 400     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
 401     if (err < 0) {
 402         DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
 403         ret = err;
 404     }
 405
 406     /* load CP0_Count */
 407     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
 408     if (err < 0) {
 409         DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
 410         ret = err;
 411     }
 412
 413     /* resume KVM timer */
 414     if (err_dc >= 0) {
 415         count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
 416         err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
 417         if (err < 0) {
 418             DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
 419             ret = err;
 420         }
 421     }
 422
 423     return ret;
 424 }
 425
 426 /*
 427  * Handle the VM clock being started or stopped
 428  */
 429 static void kvm_mips_update_state(void *opaque, int running, RunState state)
 430 {
 431     CPUState *cs = opaque;
 432     int ret;
 433     uint64_t count_resume;
 434
 435     /*
 436      * If state is already dirty (synced to QEMU) then the KVM timer state is
 437      * already saved and can be restored when it is synced back to KVM.
 438      */
 439     if (!running) {
 440         if (!cs->kvm_vcpu_dirty) {
 441             ret = kvm_mips_save_count(cs);
 442             if (ret < 0) {
 443                 fprintf(stderr, "Failed saving count\n");
 444             }
 445         }
 446     } else {
 447         /* Set clock restore time to now */
 448         count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
 449         ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
 450                                      &count_resume);
 451         if (ret < 0) {
 452             fprintf(stderr, "Failed setting COUNT_RESUME\n");
 453             return;
 454         }
 455
 456         if (!cs->kvm_vcpu_dirty) {
 457             ret = kvm_mips_restore_count(cs);
 458             if (ret < 0) {
 459                 fprintf(stderr, "Failed restoring count\n");
 460             }
 461         }
 462     }
 463 }
 464
 465 static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
 466 {
 467     MIPSCPU *cpu = MIPS_CPU(cs);
 468     CPUMIPSState *env = &cpu->env;
 469     int err, ret = 0;
 470
 471     (void)level;
 472
 473     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 474     if (err < 0) {
 475         DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
 476         ret = err;
 477     }
 478     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 479                                  &env->CP0_Context);
 480     if (err < 0) {
 481         DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
 482         ret = err;
 483     }
 484     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 485                                  &env->active_tc.CP0_UserLocal);
 486     if (err < 0) {
 487         DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
 488         ret = err;
 489     }
 490     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 491                                &env->CP0_PageMask);
 492     if (err < 0) {
 493         DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
 494         ret = err;
 495     }
 496     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 497     if (err < 0) {
 498         DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
 499         ret = err;
 500     }
 501     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 502     if (err < 0) {
 503         DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
 504         ret = err;
 505     }
 506     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 507                                  &env->CP0_BadVAddr);
 508     if (err < 0) {
 509         DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
 510         ret = err;
 511     }
 512
 513     /* If VM clock stopped then state will be restored when it is restarted */
 514     if (runstate_is_running()) {
 515         err = kvm_mips_restore_count(cs);
 516         if (err < 0) {
 517             ret = err;
 518         }
 519     }
 520
 521     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 522                                  &env->CP0_EntryHi);
 523     if (err < 0) {
 524         DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
 525         ret = err;
 526     }
 527     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 528                                &env->CP0_Compare);
 529     if (err < 0) {
 530         DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
 531         ret = err;
 532     }
 533     err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 534     if (err < 0) {
 535         DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
 536         ret = err;
 537     }
 538     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 539     if (err < 0) {
 540         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
 541         ret = err;
 542     }
 543     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 544                                  &env->CP0_ErrorEPC);
 545     if (err < 0) {
 546         DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
 547         ret = err;
 548     }
 549
 550     return ret;
 551 }
 552
 553 static int kvm_mips_get_cp0_registers(CPUState *cs)
 554 {
 555     MIPSCPU *cpu = MIPS_CPU(cs);
 556     CPUMIPSState *env = &cpu->env;
 557     int err, ret = 0;
 558
 559     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
 560     if (err < 0) {
 561         DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
 562         ret = err;
 563     }
 564     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
 565                                  &env->CP0_Context);
 566     if (err < 0) {
 567         DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
 568         ret = err;
 569     }
 570     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
 571                                  &env->active_tc.CP0_UserLocal);
 572     if (err < 0) {
 573         DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
 574         ret = err;
 575     }
 576     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
 577                                &env->CP0_PageMask);
 578     if (err < 0) {
 579         DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
 580         ret = err;
 581     }
 582     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
 583     if (err < 0) {
 584         DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
 585         ret = err;
 586     }
 587     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
 588     if (err < 0) {
 589         DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
 590         ret = err;
 591     }
 592     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
 593                                  &env->CP0_BadVAddr);
 594     if (err < 0) {
 595         DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
 596         ret = err;
 597     }
 598     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
 599                                  &env->CP0_EntryHi);
 600     if (err < 0) {
 601         DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
 602         ret = err;
 603     }
 604     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
 605                                &env->CP0_Compare);
 606     if (err < 0) {
 607         DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
 608         ret = err;
 609     }
 610     err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
 611     if (err < 0) {
 612         DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
 613         ret = err;
 614     }
 615
 616     /* If VM clock stopped then state was already saved when it was stopped */
 617     if (runstate_is_running()) {
 618         err = kvm_mips_save_count(cs);
 619         if (err < 0) {
 620             ret = err;
 621         }
 622     }
 623
 624     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
 625     if (err < 0) {
 626         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
 627         ret = err;
 628     }
 629     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
 630                                  &env->CP0_ErrorEPC);
 631     if (err < 0) {
 632         DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
 633         ret = err;
 634     }
 635
 636     return ret;
 637 }
 638
 639 int kvm_arch_put_registers(CPUState *cs, int level)
 640 {
 641     MIPSCPU *cpu = MIPS_CPU(cs);
 642     CPUMIPSState *env = &cpu->env;
 643     struct kvm_regs regs;
 644     int ret;
 645     int i;
 646
 647     /* Set the registers based on QEMU's view of things */
 648     for (i = 0; i < 32; i++) {
 649         regs.gpr[i] = env->active_tc.gpr[i];
 650     }
 651
 652     regs.hi = env->active_tc.HI[0];
 653     regs.lo = env->active_tc.LO[0];
 654     regs.pc = env->active_tc.PC;
 655
 656     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
 657
 658     if (ret < 0) {
 659         return ret;
 660     }
 661
 662     ret = kvm_mips_put_cp0_registers(cs, level);
 663     if (ret < 0) {
 664         return ret;
 665     }
 666
 667     return ret;
 668 }
 669
 670 int kvm_arch_get_registers(CPUState *cs)
 671 {
 672     MIPSCPU *cpu = MIPS_CPU(cs);
 673     CPUMIPSState *env = &cpu->env;
 674     int ret = 0;
 675     struct kvm_regs regs;
 676     int i;
 677
 678     /* Get the current register set as KVM seems it */
 679     ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
 680
 681     if (ret < 0) {
 682         return ret;
 683     }
 684
 685     for (i = 0; i < 32; i++) {
 686         env->active_tc.gpr[i] = regs.gpr[i];
 687     }
 688
 689     env->active_tc.HI[0] = regs.hi;
 690     env->active_tc.LO[0] = regs.lo;
 691     env->active_tc.PC = regs.pc;
 692
 693     kvm_mips_get_cp0_registers(cs);
 694
 695     return ret;
 696 }
 697
 698 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 699                              uint64_t address, uint32_t data)
 700 {
 701     return 0;
 702 }
 703
 704 int kvm_arch_msi_data_to_gsi(uint32_t data)
 705 {
 706     abort();
 707 }