4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
19 #include <sys/utsname.h>
21 #include <linux/kvm.h>
22 #include <linux/kvm_para.h>
24 #include "qemu-common.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/kvm_int.h"
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
40 #include "exec/ioport.h"
41 #include "standard-headers/asm-x86/hyperv.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "migration/migration.h"
45 #include "exec/memattrs.h"
50 #define DPRINTF(fmt, ...) \
51 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
53 #define DPRINTF(fmt, ...) \
57 #define MSR_KVM_WALL_CLOCK 0x11
58 #define MSR_KVM_SYSTEM_TIME 0x12
60 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
61 * 255 kvm_msr_entry structs */
62 #define MSR_BUF_SIZE 4096
65 #define BUS_MCEERR_AR 4
68 #define BUS_MCEERR_AO 5
71 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
72 KVM_CAP_INFO(SET_TSS_ADDR
),
73 KVM_CAP_INFO(EXT_CPUID
),
74 KVM_CAP_INFO(MP_STATE
),
78 static bool has_msr_star
;
79 static bool has_msr_hsave_pa
;
80 static bool has_msr_tsc_aux
;
81 static bool has_msr_tsc_adjust
;
82 static bool has_msr_tsc_deadline
;
83 static bool has_msr_feature_control
;
84 static bool has_msr_async_pf_en
;
85 static bool has_msr_pv_eoi_en
;
86 static bool has_msr_misc_enable
;
87 static bool has_msr_smbase
;
88 static bool has_msr_bndcfgs
;
89 static bool has_msr_kvm_steal_time
;
90 static int lm_capable_kernel
;
91 static bool has_msr_hv_hypercall
;
92 static bool has_msr_hv_vapic
;
93 static bool has_msr_hv_tsc
;
94 static bool has_msr_hv_crash
;
95 static bool has_msr_hv_reset
;
96 static bool has_msr_hv_vpindex
;
97 static bool has_msr_hv_runtime
;
98 static bool has_msr_hv_synic
;
99 static bool has_msr_hv_stimer
;
100 static bool has_msr_mtrr
;
101 static bool has_msr_xss
;
103 static bool has_msr_architectural_pmu
;
104 static uint32_t num_architectural_pmu_counters
;
106 static int has_xsave
;
108 static int has_pit_state2
;
110 int kvm_has_pit_state2(void)
112 return has_pit_state2
;
115 bool kvm_has_smm(void)
117 return kvm_check_extension(kvm_state
, KVM_CAP_X86_SMM
);
120 bool kvm_allows_irq0_override(void)
122 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
125 static int kvm_get_tsc(CPUState
*cs
)
127 X86CPU
*cpu
= X86_CPU(cs
);
128 CPUX86State
*env
= &cpu
->env
;
130 struct kvm_msrs info
;
131 struct kvm_msr_entry entries
[1];
135 if (env
->tsc_valid
) {
139 msr_data
.info
.nmsrs
= 1;
140 msr_data
.entries
[0].index
= MSR_IA32_TSC
;
141 env
->tsc_valid
= !runstate_is_running();
143 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
149 env
->tsc
= msr_data
.entries
[0].data
;
153 static inline void do_kvm_synchronize_tsc(void *arg
)
160 void kvm_synchronize_all_tsc(void)
166 run_on_cpu(cpu
, do_kvm_synchronize_tsc
, cpu
);
171 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
173 struct kvm_cpuid2
*cpuid
;
176 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
177 cpuid
= g_malloc0(size
);
179 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
180 if (r
== 0 && cpuid
->nent
>= max
) {
188 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
196 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
199 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
201 struct kvm_cpuid2
*cpuid
;
203 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
209 static const struct kvm_para_features
{
212 } para_features
[] = {
213 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
214 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
215 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
216 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
219 static int get_para_features(KVMState
*s
)
223 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
224 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
225 features
|= (1 << para_features
[i
].feature
);
233 /* Returns the value for a specific register on the cpuid entry
235 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
255 /* Find matching entry for function/index on kvm_cpuid2 struct
257 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
262 for (i
= 0; i
< cpuid
->nent
; ++i
) {
263 if (cpuid
->entries
[i
].function
== function
&&
264 cpuid
->entries
[i
].index
== index
) {
265 return &cpuid
->entries
[i
];
272 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
273 uint32_t index
, int reg
)
275 struct kvm_cpuid2
*cpuid
;
277 uint32_t cpuid_1_edx
;
280 cpuid
= get_supported_cpuid(s
);
282 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
285 ret
= cpuid_entry_get_reg(entry
, reg
);
288 /* Fixups for the data returned by KVM, below */
290 if (function
== 1 && reg
== R_EDX
) {
291 /* KVM before 2.6.30 misreports the following features */
292 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
293 } else if (function
== 1 && reg
== R_ECX
) {
294 /* We can set the hypervisor flag, even if KVM does not return it on
295 * GET_SUPPORTED_CPUID
297 ret
|= CPUID_EXT_HYPERVISOR
;
298 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
299 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
300 * and the irqchip is in the kernel.
302 if (kvm_irqchip_in_kernel() &&
303 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
304 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
307 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
308 * without the in-kernel irqchip
310 if (!kvm_irqchip_in_kernel()) {
311 ret
&= ~CPUID_EXT_X2APIC
;
313 } else if (function
== 6 && reg
== R_EAX
) {
314 ret
|= CPUID_6_EAX_ARAT
; /* safe to allow because of emulated APIC */
315 } else if (function
== 0x80000001 && reg
== R_EDX
) {
316 /* On Intel, kvm returns cpuid according to the Intel spec,
317 * so add missing bits according to the AMD spec:
319 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
320 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
325 /* fallback for older kernels */
326 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
327 ret
= get_para_features(s
);
333 typedef struct HWPoisonPage
{
335 QLIST_ENTRY(HWPoisonPage
) list
;
338 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
339 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
341 static void kvm_unpoison_all(void *param
)
343 HWPoisonPage
*page
, *next_page
;
345 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
346 QLIST_REMOVE(page
, list
);
347 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
352 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
356 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
357 if (page
->ram_addr
== ram_addr
) {
361 page
= g_new(HWPoisonPage
, 1);
362 page
->ram_addr
= ram_addr
;
363 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
366 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
371 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
374 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
379 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
381 CPUX86State
*env
= &cpu
->env
;
382 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
383 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
384 uint64_t mcg_status
= MCG_STATUS_MCIP
;
386 if (code
== BUS_MCEERR_AR
) {
387 status
|= MCI_STATUS_AR
| 0x134;
388 mcg_status
|= MCG_STATUS_EIPV
;
391 mcg_status
|= MCG_STATUS_RIPV
;
393 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
394 (MCM_ADDR_PHYS
<< 6) | 0xc,
395 cpu_x86_support_mca_broadcast(env
) ?
396 MCE_INJECT_BROADCAST
: 0);
399 static void hardware_memory_error(void)
401 fprintf(stderr
, "Hardware memory error!\n");
405 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
407 X86CPU
*cpu
= X86_CPU(c
);
408 CPUX86State
*env
= &cpu
->env
;
412 if ((env
->mcg_cap
& MCG_SER_P
) && addr
413 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
414 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
415 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
416 fprintf(stderr
, "Hardware memory error for memory used by "
417 "QEMU itself instead of guest system!\n");
418 /* Hope we are lucky for AO MCE */
419 if (code
== BUS_MCEERR_AO
) {
422 hardware_memory_error();
425 kvm_hwpoison_page_add(ram_addr
);
426 kvm_mce_inject(cpu
, paddr
, code
);
428 if (code
== BUS_MCEERR_AO
) {
430 } else if (code
== BUS_MCEERR_AR
) {
431 hardware_memory_error();
439 int kvm_arch_on_sigbus(int code
, void *addr
)
441 X86CPU
*cpu
= X86_CPU(first_cpu
);
443 if ((cpu
->env
.mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
447 /* Hope we are lucky for AO MCE */
448 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
449 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
,
451 fprintf(stderr
, "Hardware memory error for memory used by "
452 "QEMU itself instead of guest system!: %p\n", addr
);
455 kvm_hwpoison_page_add(ram_addr
);
456 kvm_mce_inject(X86_CPU(first_cpu
), paddr
, code
);
458 if (code
== BUS_MCEERR_AO
) {
460 } else if (code
== BUS_MCEERR_AR
) {
461 hardware_memory_error();
469 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
471 CPUX86State
*env
= &cpu
->env
;
473 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
474 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
475 struct kvm_x86_mce mce
;
477 env
->exception_injected
= -1;
480 * There must be at least one bank in use if an MCE is pending.
481 * Find it and use its values for the event injection.
483 for (bank
= 0; bank
< bank_num
; bank
++) {
484 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
488 assert(bank
< bank_num
);
491 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
492 mce
.mcg_status
= env
->mcg_status
;
493 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
494 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
496 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
501 static void cpu_update_state(void *opaque
, int running
, RunState state
)
503 CPUX86State
*env
= opaque
;
506 env
->tsc_valid
= false;
510 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
512 X86CPU
*cpu
= X86_CPU(cs
);
516 #ifndef KVM_CPUID_SIGNATURE_NEXT
517 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
520 static bool hyperv_hypercall_available(X86CPU
*cpu
)
522 return cpu
->hyperv_vapic
||
523 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
526 static bool hyperv_enabled(X86CPU
*cpu
)
528 CPUState
*cs
= CPU(cpu
);
529 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
530 (hyperv_hypercall_available(cpu
) ||
532 cpu
->hyperv_relaxed_timing
||
535 cpu
->hyperv_vpindex
||
536 cpu
->hyperv_runtime
||
541 static int kvm_arch_set_tsc_khz(CPUState
*cs
)
543 X86CPU
*cpu
= X86_CPU(cs
);
544 CPUX86State
*env
= &cpu
->env
;
551 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
) ?
552 kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
) :
555 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
556 * TSC frequency doesn't match the one we want.
558 int cur_freq
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
559 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
561 if (cur_freq
<= 0 || cur_freq
!= env
->tsc_khz
) {
562 error_report("warning: TSC frequency mismatch between "
563 "VM and host, and TSC scaling unavailable");
571 static Error
*invtsc_mig_blocker
;
573 #define KVM_MAX_CPUID_ENTRIES 100
575 int kvm_arch_init_vcpu(CPUState
*cs
)
578 struct kvm_cpuid2 cpuid
;
579 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
580 } QEMU_PACKED cpuid_data
;
581 X86CPU
*cpu
= X86_CPU(cs
);
582 CPUX86State
*env
= &cpu
->env
;
583 uint32_t limit
, i
, j
, cpuid_i
;
585 struct kvm_cpuid_entry2
*c
;
586 uint32_t signature
[3];
587 int kvm_base
= KVM_CPUID_SIGNATURE
;
590 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
594 /* Paravirtualization CPUIDs */
595 if (hyperv_enabled(cpu
)) {
596 c
= &cpuid_data
.entries
[cpuid_i
++];
597 c
->function
= HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
598 if (!cpu
->hyperv_vendor_id
) {
599 memcpy(signature
, "Microsoft Hv", 12);
601 size_t len
= strlen(cpu
->hyperv_vendor_id
);
604 error_report("hv-vendor-id truncated to 12 characters");
607 memset(signature
, 0, 12);
608 memcpy(signature
, cpu
->hyperv_vendor_id
, len
);
610 c
->eax
= HYPERV_CPUID_MIN
;
611 c
->ebx
= signature
[0];
612 c
->ecx
= signature
[1];
613 c
->edx
= signature
[2];
615 c
= &cpuid_data
.entries
[cpuid_i
++];
616 c
->function
= HYPERV_CPUID_INTERFACE
;
617 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
618 c
->eax
= signature
[0];
623 c
= &cpuid_data
.entries
[cpuid_i
++];
624 c
->function
= HYPERV_CPUID_VERSION
;
628 c
= &cpuid_data
.entries
[cpuid_i
++];
629 c
->function
= HYPERV_CPUID_FEATURES
;
630 if (cpu
->hyperv_relaxed_timing
) {
631 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
633 if (cpu
->hyperv_vapic
) {
634 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
635 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
636 has_msr_hv_vapic
= true;
638 if (cpu
->hyperv_time
&&
639 kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
640 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
641 c
->eax
|= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE
;
643 has_msr_hv_tsc
= true;
645 if (cpu
->hyperv_crash
&& has_msr_hv_crash
) {
646 c
->edx
|= HV_X64_GUEST_CRASH_MSR_AVAILABLE
;
648 c
->edx
|= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE
;
649 if (cpu
->hyperv_reset
&& has_msr_hv_reset
) {
650 c
->eax
|= HV_X64_MSR_RESET_AVAILABLE
;
652 if (cpu
->hyperv_vpindex
&& has_msr_hv_vpindex
) {
653 c
->eax
|= HV_X64_MSR_VP_INDEX_AVAILABLE
;
655 if (cpu
->hyperv_runtime
&& has_msr_hv_runtime
) {
656 c
->eax
|= HV_X64_MSR_VP_RUNTIME_AVAILABLE
;
658 if (cpu
->hyperv_synic
) {
661 if (!has_msr_hv_synic
||
662 kvm_vcpu_enable_cap(cs
, KVM_CAP_HYPERV_SYNIC
, 0)) {
663 fprintf(stderr
, "Hyper-V SynIC is not supported by kernel\n");
667 c
->eax
|= HV_X64_MSR_SYNIC_AVAILABLE
;
668 env
->msr_hv_synic_version
= HV_SYNIC_VERSION_1
;
669 for (sint
= 0; sint
< ARRAY_SIZE(env
->msr_hv_synic_sint
); sint
++) {
670 env
->msr_hv_synic_sint
[sint
] = HV_SYNIC_SINT_MASKED
;
673 if (cpu
->hyperv_stimer
) {
674 if (!has_msr_hv_stimer
) {
675 fprintf(stderr
, "Hyper-V timers aren't supported by kernel\n");
678 c
->eax
|= HV_X64_MSR_SYNTIMER_AVAILABLE
;
680 c
= &cpuid_data
.entries
[cpuid_i
++];
681 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
682 if (cpu
->hyperv_relaxed_timing
) {
683 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
685 if (has_msr_hv_vapic
) {
686 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
688 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
690 c
= &cpuid_data
.entries
[cpuid_i
++];
691 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
695 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
696 has_msr_hv_hypercall
= true;
699 if (cpu
->expose_kvm
) {
700 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
701 c
= &cpuid_data
.entries
[cpuid_i
++];
702 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
703 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
704 c
->ebx
= signature
[0];
705 c
->ecx
= signature
[1];
706 c
->edx
= signature
[2];
708 c
= &cpuid_data
.entries
[cpuid_i
++];
709 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
710 c
->eax
= env
->features
[FEAT_KVM
];
712 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
714 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
716 has_msr_kvm_steal_time
= c
->eax
& (1 << KVM_FEATURE_STEAL_TIME
);
719 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
721 for (i
= 0; i
<= limit
; i
++) {
722 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
723 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
726 c
= &cpuid_data
.entries
[cpuid_i
++];
730 /* Keep reading function 2 till all the input is received */
734 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
735 KVM_CPUID_FLAG_STATE_READ_NEXT
;
736 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
737 times
= c
->eax
& 0xff;
739 for (j
= 1; j
< times
; ++j
) {
740 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
741 fprintf(stderr
, "cpuid_data is full, no space for "
742 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
745 c
= &cpuid_data
.entries
[cpuid_i
++];
747 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
748 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
756 if (i
== 0xd && j
== 64) {
760 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
762 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
764 if (i
== 4 && c
->eax
== 0) {
767 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
770 if (i
== 0xd && c
->eax
== 0) {
773 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
774 fprintf(stderr
, "cpuid_data is full, no space for "
775 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
778 c
= &cpuid_data
.entries
[cpuid_i
++];
784 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
792 cpu_x86_cpuid(env
, 0x0a, 0, &ver
, &unused
, &unused
, &unused
);
793 if ((ver
& 0xff) > 0) {
794 has_msr_architectural_pmu
= true;
795 num_architectural_pmu_counters
= (ver
& 0xff00) >> 8;
797 /* Shouldn't be more than 32, since that's the number of bits
798 * available in EBX to tell us _which_ counters are available.
801 if (num_architectural_pmu_counters
> MAX_GP_COUNTERS
) {
802 num_architectural_pmu_counters
= MAX_GP_COUNTERS
;
807 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
809 for (i
= 0x80000000; i
<= limit
; i
++) {
810 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
811 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
814 c
= &cpuid_data
.entries
[cpuid_i
++];
818 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
821 /* Call Centaur's CPUID instructions they are supported. */
822 if (env
->cpuid_xlevel2
> 0) {
823 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
825 for (i
= 0xC0000000; i
<= limit
; i
++) {
826 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
827 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
830 c
= &cpuid_data
.entries
[cpuid_i
++];
834 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
838 cpuid_data
.cpuid
.nent
= cpuid_i
;
840 if (((env
->cpuid_version
>> 8)&0xF) >= 6
841 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
842 (CPUID_MCE
| CPUID_MCA
)
843 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
844 uint64_t mcg_cap
, unsupported_caps
;
848 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
850 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
854 if (banks
< (env
->mcg_cap
& MCG_CAP_BANKS_MASK
)) {
855 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
856 (int)(env
->mcg_cap
& MCG_CAP_BANKS_MASK
), banks
);
860 unsupported_caps
= env
->mcg_cap
& ~(mcg_cap
| MCG_CAP_BANKS_MASK
);
861 if (unsupported_caps
) {
862 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64
,
866 env
->mcg_cap
&= mcg_cap
| MCG_CAP_BANKS_MASK
;
867 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &env
->mcg_cap
);
869 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
874 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
876 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
878 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
879 !!(c
->ecx
& CPUID_EXT_SMX
);
882 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 0x80000007, 0);
883 if (c
&& (c
->edx
& 1<<8) && invtsc_mig_blocker
== NULL
) {
885 error_setg(&invtsc_mig_blocker
,
886 "State blocked by non-migratable CPU device"
888 migrate_add_blocker(invtsc_mig_blocker
);
890 vmstate_x86_cpu
.unmigratable
= 1;
893 cpuid_data
.cpuid
.padding
= 0;
894 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
899 r
= kvm_arch_set_tsc_khz(cs
);
904 /* vcpu's TSC frequency is either specified by user, or following
905 * the value used by KVM if the former is not present. In the
906 * latter case, we query it from KVM and record in env->tsc_khz,
907 * so that vcpu's TSC frequency can be migrated later via this field.
910 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GET_TSC_KHZ
) ?
911 kvm_vcpu_ioctl(cs
, KVM_GET_TSC_KHZ
) :
919 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
921 cpu
->kvm_msr_buf
= g_malloc0(MSR_BUF_SIZE
);
923 if (env
->features
[FEAT_1_EDX
] & CPUID_MTRR
) {
926 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_RDTSCP
)) {
927 has_msr_tsc_aux
= false;
933 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
935 CPUX86State
*env
= &cpu
->env
;
937 env
->exception_injected
= -1;
938 env
->interrupt_injected
= -1;
940 if (kvm_irqchip_in_kernel()) {
941 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
942 KVM_MP_STATE_UNINITIALIZED
;
944 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
948 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
950 CPUX86State
*env
= &cpu
->env
;
952 /* APs get directly into wait-for-SIPI state. */
953 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
954 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
958 static int kvm_get_supported_msrs(KVMState
*s
)
960 static int kvm_supported_msrs
;
964 if (kvm_supported_msrs
== 0) {
965 struct kvm_msr_list msr_list
, *kvm_msr_list
;
967 kvm_supported_msrs
= -1;
969 /* Obtain MSR list from KVM. These are the MSRs that we must
972 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
973 if (ret
< 0 && ret
!= -E2BIG
) {
976 /* Old kernel modules had a bug and could write beyond the provided
977 memory. Allocate at least a safe amount of 1K. */
978 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
980 sizeof(msr_list
.indices
[0])));
982 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
983 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
987 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
988 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
992 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
993 has_msr_hsave_pa
= true;
996 if (kvm_msr_list
->indices
[i
] == MSR_TSC_AUX
) {
997 has_msr_tsc_aux
= true;
1000 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
1001 has_msr_tsc_adjust
= true;
1004 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
1005 has_msr_tsc_deadline
= true;
1008 if (kvm_msr_list
->indices
[i
] == MSR_IA32_SMBASE
) {
1009 has_msr_smbase
= true;
1012 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
1013 has_msr_misc_enable
= true;
1016 if (kvm_msr_list
->indices
[i
] == MSR_IA32_BNDCFGS
) {
1017 has_msr_bndcfgs
= true;
1020 if (kvm_msr_list
->indices
[i
] == MSR_IA32_XSS
) {
1024 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_CRASH_CTL
) {
1025 has_msr_hv_crash
= true;
1028 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_RESET
) {
1029 has_msr_hv_reset
= true;
1032 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_INDEX
) {
1033 has_msr_hv_vpindex
= true;
1036 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_VP_RUNTIME
) {
1037 has_msr_hv_runtime
= true;
1040 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_SCONTROL
) {
1041 has_msr_hv_synic
= true;
1044 if (kvm_msr_list
->indices
[i
] == HV_X64_MSR_STIMER0_CONFIG
) {
1045 has_msr_hv_stimer
= true;
1051 g_free(kvm_msr_list
);
1057 static Notifier smram_machine_done
;
1058 static KVMMemoryListener smram_listener
;
1059 static AddressSpace smram_address_space
;
1060 static MemoryRegion smram_as_root
;
1061 static MemoryRegion smram_as_mem
;
1063 static void register_smram_listener(Notifier
*n
, void *unused
)
1065 MemoryRegion
*smram
=
1066 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
1068 /* Outer container... */
1069 memory_region_init(&smram_as_root
, OBJECT(kvm_state
), "mem-container-smram", ~0ull);
1070 memory_region_set_enabled(&smram_as_root
, true);
1072 /* ... with two regions inside: normal system memory with low
1075 memory_region_init_alias(&smram_as_mem
, OBJECT(kvm_state
), "mem-smram",
1076 get_system_memory(), 0, ~0ull);
1077 memory_region_add_subregion_overlap(&smram_as_root
, 0, &smram_as_mem
, 0);
1078 memory_region_set_enabled(&smram_as_mem
, true);
1081 /* ... SMRAM with higher priority */
1082 memory_region_add_subregion_overlap(&smram_as_root
, 0, smram
, 10);
1083 memory_region_set_enabled(smram
, true);
1086 address_space_init(&smram_address_space
, &smram_as_root
, "KVM-SMRAM");
1087 kvm_memory_listener_register(kvm_state
, &smram_listener
,
1088 &smram_address_space
, 1);
1091 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
1093 uint64_t identity_base
= 0xfffbc000;
1094 uint64_t shadow_mem
;
1096 struct utsname utsname
;
1098 #ifdef KVM_CAP_XSAVE
1099 has_xsave
= kvm_check_extension(s
, KVM_CAP_XSAVE
);
1103 has_xcrs
= kvm_check_extension(s
, KVM_CAP_XCRS
);
1106 #ifdef KVM_CAP_PIT_STATE2
1107 has_pit_state2
= kvm_check_extension(s
, KVM_CAP_PIT_STATE2
);
1110 ret
= kvm_get_supported_msrs(s
);
1116 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
1119 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1120 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1121 * Since these must be part of guest physical memory, we need to allocate
1122 * them, both by setting their start addresses in the kernel and by
1123 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1125 * Older KVM versions may not support setting the identity map base. In
1126 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1129 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
1130 /* Allows up to 16M BIOSes. */
1131 identity_base
= 0xfeffc000;
1133 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
1139 /* Set TSS base one page after EPT identity map. */
1140 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
1145 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1146 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
1148 fprintf(stderr
, "e820_add_entry() table is full\n");
1151 qemu_register_reset(kvm_unpoison_all
, NULL
);
1153 shadow_mem
= machine_kvm_shadow_mem(ms
);
1154 if (shadow_mem
!= -1) {
1156 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
1162 if (kvm_check_extension(s
, KVM_CAP_X86_SMM
)) {
1163 smram_machine_done
.notify
= register_smram_listener
;
1164 qemu_add_machine_init_done_notifier(&smram_machine_done
);
1169 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1171 lhs
->selector
= rhs
->selector
;
1172 lhs
->base
= rhs
->base
;
1173 lhs
->limit
= rhs
->limit
;
1185 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
1187 unsigned flags
= rhs
->flags
;
1188 lhs
->selector
= rhs
->selector
;
1189 lhs
->base
= rhs
->base
;
1190 lhs
->limit
= rhs
->limit
;
1191 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
1192 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
1193 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
1194 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
1195 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
1196 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
1197 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
1198 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
1199 lhs
->unusable
= !lhs
->present
;
1203 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
1205 lhs
->selector
= rhs
->selector
;
1206 lhs
->base
= rhs
->base
;
1207 lhs
->limit
= rhs
->limit
;
1208 if (rhs
->unusable
) {
1211 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
1212 (rhs
->present
* DESC_P_MASK
) |
1213 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
1214 (rhs
->db
<< DESC_B_SHIFT
) |
1215 (rhs
->s
* DESC_S_MASK
) |
1216 (rhs
->l
<< DESC_L_SHIFT
) |
1217 (rhs
->g
* DESC_G_MASK
) |
1218 (rhs
->avl
* DESC_AVL_MASK
);
1222 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
1225 *kvm_reg
= *qemu_reg
;
1227 *qemu_reg
= *kvm_reg
;
1231 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
1233 CPUX86State
*env
= &cpu
->env
;
1234 struct kvm_regs regs
;
1238 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
1244 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
1245 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
1246 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
1247 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
1248 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
1249 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
1250 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
1251 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
1252 #ifdef TARGET_X86_64
1253 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
1254 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
1255 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
1256 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
1257 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
1258 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
1259 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
1260 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
1263 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
1264 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
1267 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
1273 static int kvm_put_fpu(X86CPU
*cpu
)
1275 CPUX86State
*env
= &cpu
->env
;
1279 memset(&fpu
, 0, sizeof fpu
);
1280 fpu
.fsw
= env
->fpus
& ~(7 << 11);
1281 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
1282 fpu
.fcw
= env
->fpuc
;
1283 fpu
.last_opcode
= env
->fpop
;
1284 fpu
.last_ip
= env
->fpip
;
1285 fpu
.last_dp
= env
->fpdp
;
1286 for (i
= 0; i
< 8; ++i
) {
1287 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
1289 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
1290 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1291 stq_p(&fpu
.xmm
[i
][0], env
->xmm_regs
[i
].ZMM_Q(0));
1292 stq_p(&fpu
.xmm
[i
][8], env
->xmm_regs
[i
].ZMM_Q(1));
1294 fpu
.mxcsr
= env
->mxcsr
;
1296 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
1299 #define XSAVE_FCW_FSW 0
1300 #define XSAVE_FTW_FOP 1
1301 #define XSAVE_CWD_RIP 2
1302 #define XSAVE_CWD_RDP 4
1303 #define XSAVE_MXCSR 6
1304 #define XSAVE_ST_SPACE 8
1305 #define XSAVE_XMM_SPACE 40
1306 #define XSAVE_XSTATE_BV 128
1307 #define XSAVE_YMMH_SPACE 144
1308 #define XSAVE_BNDREGS 240
1309 #define XSAVE_BNDCSR 256
1310 #define XSAVE_OPMASK 272
1311 #define XSAVE_ZMM_Hi256 288
1312 #define XSAVE_Hi16_ZMM 416
1313 #define XSAVE_PKRU 672
1315 #define XSAVE_BYTE_OFFSET(word_offset) \
1316 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1318 #define ASSERT_OFFSET(word_offset, field) \
1319 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1320 offsetof(X86XSaveArea, field))
1322 ASSERT_OFFSET(XSAVE_FCW_FSW
, legacy
.fcw
);
1323 ASSERT_OFFSET(XSAVE_FTW_FOP
, legacy
.ftw
);
1324 ASSERT_OFFSET(XSAVE_CWD_RIP
, legacy
.fpip
);
1325 ASSERT_OFFSET(XSAVE_CWD_RDP
, legacy
.fpdp
);
1326 ASSERT_OFFSET(XSAVE_MXCSR
, legacy
.mxcsr
);
1327 ASSERT_OFFSET(XSAVE_ST_SPACE
, legacy
.fpregs
);
1328 ASSERT_OFFSET(XSAVE_XMM_SPACE
, legacy
.xmm_regs
);
1329 ASSERT_OFFSET(XSAVE_XSTATE_BV
, header
.xstate_bv
);
1330 ASSERT_OFFSET(XSAVE_YMMH_SPACE
, avx_state
);
1331 ASSERT_OFFSET(XSAVE_BNDREGS
, bndreg_state
);
1332 ASSERT_OFFSET(XSAVE_BNDCSR
, bndcsr_state
);
1333 ASSERT_OFFSET(XSAVE_OPMASK
, opmask_state
);
1334 ASSERT_OFFSET(XSAVE_ZMM_Hi256
, zmm_hi256_state
);
1335 ASSERT_OFFSET(XSAVE_Hi16_ZMM
, hi16_zmm_state
);
1336 ASSERT_OFFSET(XSAVE_PKRU
, pkru_state
);
1338 static int kvm_put_xsave(X86CPU
*cpu
)
1340 CPUX86State
*env
= &cpu
->env
;
1341 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1342 uint16_t cwd
, swd
, twd
;
1346 return kvm_put_fpu(cpu
);
1349 memset(xsave
, 0, sizeof(struct kvm_xsave
));
1351 swd
= env
->fpus
& ~(7 << 11);
1352 swd
|= (env
->fpstt
& 7) << 11;
1354 for (i
= 0; i
< 8; ++i
) {
1355 twd
|= (!env
->fptags
[i
]) << i
;
1357 xsave
->legacy
.fcw
= cwd
;
1358 xsave
->legacy
.fsw
= swd
;
1359 xsave
->legacy
.ftw
= twd
;
1360 xsave
->legacy
.fpop
= env
->fpop
;
1361 xsave
->legacy
.fpip
= env
->fpip
;
1362 xsave
->legacy
.fpdp
= env
->fpdp
;
1363 memcpy(&xsave
->legacy
.fpregs
, env
->fpregs
,
1364 sizeof env
->fpregs
);
1365 xsave
->legacy
.mxcsr
= env
->mxcsr
;
1366 xsave
->header
.xstate_bv
= env
->xstate_bv
;
1367 memcpy(&xsave
->bndreg_state
.bnd_regs
, env
->bnd_regs
,
1368 sizeof env
->bnd_regs
);
1369 xsave
->bndcsr_state
.bndcsr
= env
->bndcs_regs
;
1370 memcpy(&xsave
->opmask_state
.opmask_regs
, env
->opmask_regs
,
1371 sizeof env
->opmask_regs
);
1373 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1374 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1375 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1376 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1377 stq_p(xmm
, env
->xmm_regs
[i
].ZMM_Q(0));
1378 stq_p(xmm
+8, env
->xmm_regs
[i
].ZMM_Q(1));
1379 stq_p(ymmh
, env
->xmm_regs
[i
].ZMM_Q(2));
1380 stq_p(ymmh
+8, env
->xmm_regs
[i
].ZMM_Q(3));
1381 stq_p(zmmh
, env
->xmm_regs
[i
].ZMM_Q(4));
1382 stq_p(zmmh
+8, env
->xmm_regs
[i
].ZMM_Q(5));
1383 stq_p(zmmh
+16, env
->xmm_regs
[i
].ZMM_Q(6));
1384 stq_p(zmmh
+24, env
->xmm_regs
[i
].ZMM_Q(7));
1387 #ifdef TARGET_X86_64
1388 memcpy(&xsave
->hi16_zmm_state
.hi16_zmm
, &env
->xmm_regs
[16],
1389 16 * sizeof env
->xmm_regs
[16]);
1390 memcpy(&xsave
->pkru_state
, &env
->pkru
, sizeof env
->pkru
);
1392 r
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1396 static int kvm_put_xcrs(X86CPU
*cpu
)
1398 CPUX86State
*env
= &cpu
->env
;
1399 struct kvm_xcrs xcrs
= {};
1407 xcrs
.xcrs
[0].xcr
= 0;
1408 xcrs
.xcrs
[0].value
= env
->xcr0
;
1409 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1412 static int kvm_put_sregs(X86CPU
*cpu
)
1414 CPUX86State
*env
= &cpu
->env
;
1415 struct kvm_sregs sregs
;
1417 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1418 if (env
->interrupt_injected
>= 0) {
1419 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1420 (uint64_t)1 << (env
->interrupt_injected
% 64);
1423 if ((env
->eflags
& VM_MASK
)) {
1424 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1425 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1426 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1427 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1428 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1429 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1431 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1432 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1433 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1434 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1435 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1436 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1439 set_seg(&sregs
.tr
, &env
->tr
);
1440 set_seg(&sregs
.ldt
, &env
->ldt
);
1442 sregs
.idt
.limit
= env
->idt
.limit
;
1443 sregs
.idt
.base
= env
->idt
.base
;
1444 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1445 sregs
.gdt
.limit
= env
->gdt
.limit
;
1446 sregs
.gdt
.base
= env
->gdt
.base
;
1447 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1449 sregs
.cr0
= env
->cr
[0];
1450 sregs
.cr2
= env
->cr
[2];
1451 sregs
.cr3
= env
->cr
[3];
1452 sregs
.cr4
= env
->cr
[4];
1454 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
1455 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
1457 sregs
.efer
= env
->efer
;
1459 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1462 static void kvm_msr_buf_reset(X86CPU
*cpu
)
1464 memset(cpu
->kvm_msr_buf
, 0, MSR_BUF_SIZE
);
1467 static void kvm_msr_entry_add(X86CPU
*cpu
, uint32_t index
, uint64_t value
)
1469 struct kvm_msrs
*msrs
= cpu
->kvm_msr_buf
;
1470 void *limit
= ((void *)msrs
) + MSR_BUF_SIZE
;
1471 struct kvm_msr_entry
*entry
= &msrs
->entries
[msrs
->nmsrs
];
1473 assert((void *)(entry
+ 1) <= limit
);
1475 entry
->index
= index
;
1476 entry
->reserved
= 0;
1477 entry
->data
= value
;
1481 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1483 CPUX86State
*env
= &cpu
->env
;
1486 if (!has_msr_tsc_deadline
) {
1490 kvm_msr_buf_reset(cpu
);
1491 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1493 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1503 * Provide a separate write service for the feature control MSR in order to
1504 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1505 * before writing any other state because forcibly leaving nested mode
1506 * invalidates the VCPU state.
1508 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1512 if (!has_msr_feature_control
) {
1516 kvm_msr_buf_reset(cpu
);
1517 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
,
1518 cpu
->env
.msr_ia32_feature_control
);
1520 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1529 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1531 CPUX86State
*env
= &cpu
->env
;
1535 kvm_msr_buf_reset(cpu
);
1537 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1538 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1539 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1540 kvm_msr_entry_add(cpu
, MSR_PAT
, env
->pat
);
1542 kvm_msr_entry_add(cpu
, MSR_STAR
, env
->star
);
1544 if (has_msr_hsave_pa
) {
1545 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1547 if (has_msr_tsc_aux
) {
1548 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, env
->tsc_aux
);
1550 if (has_msr_tsc_adjust
) {
1551 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, env
->tsc_adjust
);
1553 if (has_msr_misc_enable
) {
1554 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
,
1555 env
->msr_ia32_misc_enable
);
1557 if (has_msr_smbase
) {
1558 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, env
->smbase
);
1560 if (has_msr_bndcfgs
) {
1561 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1564 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, env
->xss
);
1566 #ifdef TARGET_X86_64
1567 if (lm_capable_kernel
) {
1568 kvm_msr_entry_add(cpu
, MSR_CSTAR
, env
->cstar
);
1569 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, env
->kernelgsbase
);
1570 kvm_msr_entry_add(cpu
, MSR_FMASK
, env
->fmask
);
1571 kvm_msr_entry_add(cpu
, MSR_LSTAR
, env
->lstar
);
1575 * The following MSRs have side effects on the guest or are too heavy
1576 * for normal writeback. Limit them to reset or full state updates.
1578 if (level
>= KVM_PUT_RESET_STATE
) {
1579 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, env
->tsc
);
1580 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, env
->system_time_msr
);
1581 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1582 if (has_msr_async_pf_en
) {
1583 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
1585 if (has_msr_pv_eoi_en
) {
1586 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, env
->pv_eoi_en_msr
);
1588 if (has_msr_kvm_steal_time
) {
1589 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, env
->steal_time_msr
);
1591 if (has_msr_architectural_pmu
) {
1592 /* Stop the counter. */
1593 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1594 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1596 /* Set the counter values. */
1597 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1598 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
,
1599 env
->msr_fixed_counters
[i
]);
1601 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1602 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
,
1603 env
->msr_gp_counters
[i
]);
1604 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
,
1605 env
->msr_gp_evtsel
[i
]);
1607 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
,
1608 env
->msr_global_status
);
1609 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1610 env
->msr_global_ovf_ctrl
);
1612 /* Now start the PMU. */
1613 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
,
1614 env
->msr_fixed_ctr_ctrl
);
1615 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
,
1616 env
->msr_global_ctrl
);
1618 if (has_msr_hv_hypercall
) {
1619 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
,
1620 env
->msr_hv_guest_os_id
);
1621 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
,
1622 env
->msr_hv_hypercall
);
1624 if (has_msr_hv_vapic
) {
1625 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
,
1628 if (has_msr_hv_tsc
) {
1629 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, env
->msr_hv_tsc
);
1631 if (has_msr_hv_crash
) {
1634 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++)
1635 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
,
1636 env
->msr_hv_crash_params
[j
]);
1638 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_CTL
,
1639 HV_X64_MSR_CRASH_CTL_NOTIFY
);
1641 if (has_msr_hv_runtime
) {
1642 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, env
->msr_hv_runtime
);
1644 if (cpu
->hyperv_synic
) {
1647 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
,
1648 env
->msr_hv_synic_control
);
1649 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
,
1650 env
->msr_hv_synic_version
);
1651 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
,
1652 env
->msr_hv_synic_evt_page
);
1653 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
,
1654 env
->msr_hv_synic_msg_page
);
1656 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_synic_sint
); j
++) {
1657 kvm_msr_entry_add(cpu
, HV_X64_MSR_SINT0
+ j
,
1658 env
->msr_hv_synic_sint
[j
]);
1661 if (has_msr_hv_stimer
) {
1664 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_config
); j
++) {
1665 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_CONFIG
+ j
* 2,
1666 env
->msr_hv_stimer_config
[j
]);
1669 for (j
= 0; j
< ARRAY_SIZE(env
->msr_hv_stimer_count
); j
++) {
1670 kvm_msr_entry_add(cpu
, HV_X64_MSR_STIMER0_COUNT
+ j
* 2,
1671 env
->msr_hv_stimer_count
[j
]);
1675 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, env
->mtrr_deftype
);
1676 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, env
->mtrr_fixed
[0]);
1677 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, env
->mtrr_fixed
[1]);
1678 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, env
->mtrr_fixed
[2]);
1679 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, env
->mtrr_fixed
[3]);
1680 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, env
->mtrr_fixed
[4]);
1681 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, env
->mtrr_fixed
[5]);
1682 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, env
->mtrr_fixed
[6]);
1683 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, env
->mtrr_fixed
[7]);
1684 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, env
->mtrr_fixed
[8]);
1685 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, env
->mtrr_fixed
[9]);
1686 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, env
->mtrr_fixed
[10]);
1687 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
1688 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
),
1689 env
->mtrr_var
[i
].base
);
1690 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
),
1691 env
->mtrr_var
[i
].mask
);
1695 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1696 * kvm_put_msr_feature_control. */
1701 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, env
->mcg_status
);
1702 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, env
->mcg_ctl
);
1703 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1704 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1708 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, cpu
->kvm_msr_buf
);
1713 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
1718 static int kvm_get_fpu(X86CPU
*cpu
)
1720 CPUX86State
*env
= &cpu
->env
;
1724 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1729 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1730 env
->fpus
= fpu
.fsw
;
1731 env
->fpuc
= fpu
.fcw
;
1732 env
->fpop
= fpu
.last_opcode
;
1733 env
->fpip
= fpu
.last_ip
;
1734 env
->fpdp
= fpu
.last_dp
;
1735 for (i
= 0; i
< 8; ++i
) {
1736 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1738 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1739 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1740 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(&fpu
.xmm
[i
][0]);
1741 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(&fpu
.xmm
[i
][8]);
1743 env
->mxcsr
= fpu
.mxcsr
;
1748 static int kvm_get_xsave(X86CPU
*cpu
)
1750 CPUX86State
*env
= &cpu
->env
;
1751 X86XSaveArea
*xsave
= env
->kvm_xsave_buf
;
1753 uint16_t cwd
, swd
, twd
;
1756 return kvm_get_fpu(cpu
);
1759 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1764 cwd
= xsave
->legacy
.fcw
;
1765 swd
= xsave
->legacy
.fsw
;
1766 twd
= xsave
->legacy
.ftw
;
1767 env
->fpop
= xsave
->legacy
.fpop
;
1768 env
->fpstt
= (swd
>> 11) & 7;
1771 for (i
= 0; i
< 8; ++i
) {
1772 env
->fptags
[i
] = !((twd
>> i
) & 1);
1774 env
->fpip
= xsave
->legacy
.fpip
;
1775 env
->fpdp
= xsave
->legacy
.fpdp
;
1776 env
->mxcsr
= xsave
->legacy
.mxcsr
;
1777 memcpy(env
->fpregs
, &xsave
->legacy
.fpregs
,
1778 sizeof env
->fpregs
);
1779 env
->xstate_bv
= xsave
->header
.xstate_bv
;
1780 memcpy(env
->bnd_regs
, &xsave
->bndreg_state
.bnd_regs
,
1781 sizeof env
->bnd_regs
);
1782 env
->bndcs_regs
= xsave
->bndcsr_state
.bndcsr
;
1783 memcpy(env
->opmask_regs
, &xsave
->opmask_state
.opmask_regs
,
1784 sizeof env
->opmask_regs
);
1786 for (i
= 0; i
< CPU_NB_REGS
; i
++) {
1787 uint8_t *xmm
= xsave
->legacy
.xmm_regs
[i
];
1788 uint8_t *ymmh
= xsave
->avx_state
.ymmh
[i
];
1789 uint8_t *zmmh
= xsave
->zmm_hi256_state
.zmm_hi256
[i
];
1790 env
->xmm_regs
[i
].ZMM_Q(0) = ldq_p(xmm
);
1791 env
->xmm_regs
[i
].ZMM_Q(1) = ldq_p(xmm
+8);
1792 env
->xmm_regs
[i
].ZMM_Q(2) = ldq_p(ymmh
);
1793 env
->xmm_regs
[i
].ZMM_Q(3) = ldq_p(ymmh
+8);
1794 env
->xmm_regs
[i
].ZMM_Q(4) = ldq_p(zmmh
);
1795 env
->xmm_regs
[i
].ZMM_Q(5) = ldq_p(zmmh
+8);
1796 env
->xmm_regs
[i
].ZMM_Q(6) = ldq_p(zmmh
+16);
1797 env
->xmm_regs
[i
].ZMM_Q(7) = ldq_p(zmmh
+24);
1800 #ifdef TARGET_X86_64
1801 memcpy(&env
->xmm_regs
[16], &xsave
->hi16_zmm_state
.hi16_zmm
,
1802 16 * sizeof env
->xmm_regs
[16]);
1803 memcpy(&env
->pkru
, &xsave
->pkru_state
, sizeof env
->pkru
);
1808 static int kvm_get_xcrs(X86CPU
*cpu
)
1810 CPUX86State
*env
= &cpu
->env
;
1812 struct kvm_xcrs xcrs
;
1818 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1823 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1824 /* Only support xcr0 now */
1825 if (xcrs
.xcrs
[i
].xcr
== 0) {
1826 env
->xcr0
= xcrs
.xcrs
[i
].value
;
1833 static int kvm_get_sregs(X86CPU
*cpu
)
1835 CPUX86State
*env
= &cpu
->env
;
1836 struct kvm_sregs sregs
;
1840 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1845 /* There can only be one pending IRQ set in the bitmap at a time, so try
1846 to find it and save its number instead (-1 for none). */
1847 env
->interrupt_injected
= -1;
1848 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1849 if (sregs
.interrupt_bitmap
[i
]) {
1850 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1851 env
->interrupt_injected
= i
* 64 + bit
;
1856 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1857 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1858 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1859 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1860 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1861 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1863 get_seg(&env
->tr
, &sregs
.tr
);
1864 get_seg(&env
->ldt
, &sregs
.ldt
);
1866 env
->idt
.limit
= sregs
.idt
.limit
;
1867 env
->idt
.base
= sregs
.idt
.base
;
1868 env
->gdt
.limit
= sregs
.gdt
.limit
;
1869 env
->gdt
.base
= sregs
.gdt
.base
;
1871 env
->cr
[0] = sregs
.cr0
;
1872 env
->cr
[2] = sregs
.cr2
;
1873 env
->cr
[3] = sregs
.cr3
;
1874 env
->cr
[4] = sregs
.cr4
;
1876 env
->efer
= sregs
.efer
;
1878 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1880 #define HFLAG_COPY_MASK \
1881 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1882 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1883 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1884 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1886 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
1887 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1888 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1889 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1890 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1891 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1893 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
1894 hflags
|= HF_OSFXSR_MASK
;
1897 if (env
->efer
& MSR_EFER_LMA
) {
1898 hflags
|= HF_LMA_MASK
;
1901 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1902 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1904 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1905 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1906 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1907 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1908 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1909 !(hflags
& HF_CS32_MASK
)) {
1910 hflags
|= HF_ADDSEG_MASK
;
1912 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1913 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1916 env
->hflags
= hflags
;
1921 static int kvm_get_msrs(X86CPU
*cpu
)
1923 CPUX86State
*env
= &cpu
->env
;
1924 struct kvm_msr_entry
*msrs
= cpu
->kvm_msr_buf
->entries
;
1927 kvm_msr_buf_reset(cpu
);
1929 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_CS
, 0);
1930 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_ESP
, 0);
1931 kvm_msr_entry_add(cpu
, MSR_IA32_SYSENTER_EIP
, 0);
1932 kvm_msr_entry_add(cpu
, MSR_PAT
, 0);
1934 kvm_msr_entry_add(cpu
, MSR_STAR
, 0);
1936 if (has_msr_hsave_pa
) {
1937 kvm_msr_entry_add(cpu
, MSR_VM_HSAVE_PA
, 0);
1939 if (has_msr_tsc_aux
) {
1940 kvm_msr_entry_add(cpu
, MSR_TSC_AUX
, 0);
1942 if (has_msr_tsc_adjust
) {
1943 kvm_msr_entry_add(cpu
, MSR_TSC_ADJUST
, 0);
1945 if (has_msr_tsc_deadline
) {
1946 kvm_msr_entry_add(cpu
, MSR_IA32_TSCDEADLINE
, 0);
1948 if (has_msr_misc_enable
) {
1949 kvm_msr_entry_add(cpu
, MSR_IA32_MISC_ENABLE
, 0);
1951 if (has_msr_smbase
) {
1952 kvm_msr_entry_add(cpu
, MSR_IA32_SMBASE
, 0);
1954 if (has_msr_feature_control
) {
1955 kvm_msr_entry_add(cpu
, MSR_IA32_FEATURE_CONTROL
, 0);
1957 if (has_msr_bndcfgs
) {
1958 kvm_msr_entry_add(cpu
, MSR_IA32_BNDCFGS
, 0);
1961 kvm_msr_entry_add(cpu
, MSR_IA32_XSS
, 0);
1965 if (!env
->tsc_valid
) {
1966 kvm_msr_entry_add(cpu
, MSR_IA32_TSC
, 0);
1967 env
->tsc_valid
= !runstate_is_running();
1970 #ifdef TARGET_X86_64
1971 if (lm_capable_kernel
) {
1972 kvm_msr_entry_add(cpu
, MSR_CSTAR
, 0);
1973 kvm_msr_entry_add(cpu
, MSR_KERNELGSBASE
, 0);
1974 kvm_msr_entry_add(cpu
, MSR_FMASK
, 0);
1975 kvm_msr_entry_add(cpu
, MSR_LSTAR
, 0);
1978 kvm_msr_entry_add(cpu
, MSR_KVM_SYSTEM_TIME
, 0);
1979 kvm_msr_entry_add(cpu
, MSR_KVM_WALL_CLOCK
, 0);
1980 if (has_msr_async_pf_en
) {
1981 kvm_msr_entry_add(cpu
, MSR_KVM_ASYNC_PF_EN
, 0);
1983 if (has_msr_pv_eoi_en
) {
1984 kvm_msr_entry_add(cpu
, MSR_KVM_PV_EOI_EN
, 0);
1986 if (has_msr_kvm_steal_time
) {
1987 kvm_msr_entry_add(cpu
, MSR_KVM_STEAL_TIME
, 0);
1989 if (has_msr_architectural_pmu
) {
1990 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1991 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1992 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_STATUS
, 0);
1993 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_GLOBAL_OVF_CTRL
, 0);
1994 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1995 kvm_msr_entry_add(cpu
, MSR_CORE_PERF_FIXED_CTR0
+ i
, 0);
1997 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1998 kvm_msr_entry_add(cpu
, MSR_P6_PERFCTR0
+ i
, 0);
1999 kvm_msr_entry_add(cpu
, MSR_P6_EVNTSEL0
+ i
, 0);
2004 kvm_msr_entry_add(cpu
, MSR_MCG_STATUS
, 0);
2005 kvm_msr_entry_add(cpu
, MSR_MCG_CTL
, 0);
2006 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
2007 kvm_msr_entry_add(cpu
, MSR_MC0_CTL
+ i
, 0);
2011 if (has_msr_hv_hypercall
) {
2012 kvm_msr_entry_add(cpu
, HV_X64_MSR_HYPERCALL
, 0);
2013 kvm_msr_entry_add(cpu
, HV_X64_MSR_GUEST_OS_ID
, 0);
2015 if (has_msr_hv_vapic
) {
2016 kvm_msr_entry_add(cpu
, HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
2018 if (has_msr_hv_tsc
) {
2019 kvm_msr_entry_add(cpu
, HV_X64_MSR_REFERENCE_TSC
, 0);
2021 if (has_msr_hv_crash
) {
2024 for (j
= 0; j
< HV_X64_MSR_CRASH_PARAMS
; j
++) {
2025 kvm_msr_entry_add(cpu
, HV_X64_MSR_CRASH_P0
+ j
, 0);
2028 if (has_msr_hv_runtime
) {
2029 kvm_msr_entry_add(cpu
, HV_X64_MSR_VP_RUNTIME
, 0);
2031 if (cpu
->hyperv_synic
) {
2034 kvm_msr_entry_add(cpu
, HV_X64_MSR_SCONTROL
, 0);
2035 kvm_msr_entry_add(cpu
, HV_X64_MSR_SVERSION
, 0);
2036 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIEFP
, 0);
2037 kvm_msr_entry_add(cpu
, HV_X64_MSR_SIMP
, 0);
2038 for (msr
= HV_X64_MSR_SINT0
; msr
<= HV_X64_MSR_SINT15
; msr
++) {
2039 kvm_msr_entry_add(cpu
, msr
, 0);
2042 if (has_msr_hv_stimer
) {
2045 for (msr
= HV_X64_MSR_STIMER0_CONFIG
; msr
<= HV_X64_MSR_STIMER3_COUNT
;
2047 kvm_msr_entry_add(cpu
, msr
, 0);
2051 kvm_msr_entry_add(cpu
, MSR_MTRRdefType
, 0);
2052 kvm_msr_entry_add(cpu
, MSR_MTRRfix64K_00000
, 0);
2053 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_80000
, 0);
2054 kvm_msr_entry_add(cpu
, MSR_MTRRfix16K_A0000
, 0);
2055 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C0000
, 0);
2056 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_C8000
, 0);
2057 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D0000
, 0);
2058 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_D8000
, 0);
2059 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E0000
, 0);
2060 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_E8000
, 0);
2061 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F0000
, 0);
2062 kvm_msr_entry_add(cpu
, MSR_MTRRfix4K_F8000
, 0);
2063 for (i
= 0; i
< MSR_MTRRcap_VCNT
; i
++) {
2064 kvm_msr_entry_add(cpu
, MSR_MTRRphysBase(i
), 0);
2065 kvm_msr_entry_add(cpu
, MSR_MTRRphysMask(i
), 0);
2069 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, cpu
->kvm_msr_buf
);
2074 assert(ret
== cpu
->kvm_msr_buf
->nmsrs
);
2075 for (i
= 0; i
< ret
; i
++) {
2076 uint32_t index
= msrs
[i
].index
;
2078 case MSR_IA32_SYSENTER_CS
:
2079 env
->sysenter_cs
= msrs
[i
].data
;
2081 case MSR_IA32_SYSENTER_ESP
:
2082 env
->sysenter_esp
= msrs
[i
].data
;
2084 case MSR_IA32_SYSENTER_EIP
:
2085 env
->sysenter_eip
= msrs
[i
].data
;
2088 env
->pat
= msrs
[i
].data
;
2091 env
->star
= msrs
[i
].data
;
2093 #ifdef TARGET_X86_64
2095 env
->cstar
= msrs
[i
].data
;
2097 case MSR_KERNELGSBASE
:
2098 env
->kernelgsbase
= msrs
[i
].data
;
2101 env
->fmask
= msrs
[i
].data
;
2104 env
->lstar
= msrs
[i
].data
;
2108 env
->tsc
= msrs
[i
].data
;
2111 env
->tsc_aux
= msrs
[i
].data
;
2113 case MSR_TSC_ADJUST
:
2114 env
->tsc_adjust
= msrs
[i
].data
;
2116 case MSR_IA32_TSCDEADLINE
:
2117 env
->tsc_deadline
= msrs
[i
].data
;
2119 case MSR_VM_HSAVE_PA
:
2120 env
->vm_hsave
= msrs
[i
].data
;
2122 case MSR_KVM_SYSTEM_TIME
:
2123 env
->system_time_msr
= msrs
[i
].data
;
2125 case MSR_KVM_WALL_CLOCK
:
2126 env
->wall_clock_msr
= msrs
[i
].data
;
2128 case MSR_MCG_STATUS
:
2129 env
->mcg_status
= msrs
[i
].data
;
2132 env
->mcg_ctl
= msrs
[i
].data
;
2134 case MSR_IA32_MISC_ENABLE
:
2135 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
2137 case MSR_IA32_SMBASE
:
2138 env
->smbase
= msrs
[i
].data
;
2140 case MSR_IA32_FEATURE_CONTROL
:
2141 env
->msr_ia32_feature_control
= msrs
[i
].data
;
2143 case MSR_IA32_BNDCFGS
:
2144 env
->msr_bndcfgs
= msrs
[i
].data
;
2147 env
->xss
= msrs
[i
].data
;
2150 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
2151 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
2152 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
2155 case MSR_KVM_ASYNC_PF_EN
:
2156 env
->async_pf_en_msr
= msrs
[i
].data
;
2158 case MSR_KVM_PV_EOI_EN
:
2159 env
->pv_eoi_en_msr
= msrs
[i
].data
;
2161 case MSR_KVM_STEAL_TIME
:
2162 env
->steal_time_msr
= msrs
[i
].data
;
2164 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
2165 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
2167 case MSR_CORE_PERF_GLOBAL_CTRL
:
2168 env
->msr_global_ctrl
= msrs
[i
].data
;
2170 case MSR_CORE_PERF_GLOBAL_STATUS
:
2171 env
->msr_global_status
= msrs
[i
].data
;
2173 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
2174 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
2176 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
2177 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
2179 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
2180 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
2182 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
2183 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
2185 case HV_X64_MSR_HYPERCALL
:
2186 env
->msr_hv_hypercall
= msrs
[i
].data
;
2188 case HV_X64_MSR_GUEST_OS_ID
:
2189 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
2191 case HV_X64_MSR_APIC_ASSIST_PAGE
:
2192 env
->msr_hv_vapic
= msrs
[i
].data
;
2194 case HV_X64_MSR_REFERENCE_TSC
:
2195 env
->msr_hv_tsc
= msrs
[i
].data
;
2197 case HV_X64_MSR_CRASH_P0
... HV_X64_MSR_CRASH_P4
:
2198 env
->msr_hv_crash_params
[index
- HV_X64_MSR_CRASH_P0
] = msrs
[i
].data
;
2200 case HV_X64_MSR_VP_RUNTIME
:
2201 env
->msr_hv_runtime
= msrs
[i
].data
;
2203 case HV_X64_MSR_SCONTROL
:
2204 env
->msr_hv_synic_control
= msrs
[i
].data
;
2206 case HV_X64_MSR_SVERSION
:
2207 env
->msr_hv_synic_version
= msrs
[i
].data
;
2209 case HV_X64_MSR_SIEFP
:
2210 env
->msr_hv_synic_evt_page
= msrs
[i
].data
;
2212 case HV_X64_MSR_SIMP
:
2213 env
->msr_hv_synic_msg_page
= msrs
[i
].data
;
2215 case HV_X64_MSR_SINT0
... HV_X64_MSR_SINT15
:
2216 env
->msr_hv_synic_sint
[index
- HV_X64_MSR_SINT0
] = msrs
[i
].data
;
2218 case HV_X64_MSR_STIMER0_CONFIG
:
2219 case HV_X64_MSR_STIMER1_CONFIG
:
2220 case HV_X64_MSR_STIMER2_CONFIG
:
2221 case HV_X64_MSR_STIMER3_CONFIG
:
2222 env
->msr_hv_stimer_config
[(index
- HV_X64_MSR_STIMER0_CONFIG
)/2] =
2225 case HV_X64_MSR_STIMER0_COUNT
:
2226 case HV_X64_MSR_STIMER1_COUNT
:
2227 case HV_X64_MSR_STIMER2_COUNT
:
2228 case HV_X64_MSR_STIMER3_COUNT
:
2229 env
->msr_hv_stimer_count
[(index
- HV_X64_MSR_STIMER0_COUNT
)/2] =
2232 case MSR_MTRRdefType
:
2233 env
->mtrr_deftype
= msrs
[i
].data
;
2235 case MSR_MTRRfix64K_00000
:
2236 env
->mtrr_fixed
[0] = msrs
[i
].data
;
2238 case MSR_MTRRfix16K_80000
:
2239 env
->mtrr_fixed
[1] = msrs
[i
].data
;
2241 case MSR_MTRRfix16K_A0000
:
2242 env
->mtrr_fixed
[2] = msrs
[i
].data
;
2244 case MSR_MTRRfix4K_C0000
:
2245 env
->mtrr_fixed
[3] = msrs
[i
].data
;
2247 case MSR_MTRRfix4K_C8000
:
2248 env
->mtrr_fixed
[4] = msrs
[i
].data
;
2250 case MSR_MTRRfix4K_D0000
:
2251 env
->mtrr_fixed
[5] = msrs
[i
].data
;
2253 case MSR_MTRRfix4K_D8000
:
2254 env
->mtrr_fixed
[6] = msrs
[i
].data
;
2256 case MSR_MTRRfix4K_E0000
:
2257 env
->mtrr_fixed
[7] = msrs
[i
].data
;
2259 case MSR_MTRRfix4K_E8000
:
2260 env
->mtrr_fixed
[8] = msrs
[i
].data
;
2262 case MSR_MTRRfix4K_F0000
:
2263 env
->mtrr_fixed
[9] = msrs
[i
].data
;
2265 case MSR_MTRRfix4K_F8000
:
2266 env
->mtrr_fixed
[10] = msrs
[i
].data
;
2268 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT
- 1):
2270 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].mask
= msrs
[i
].data
;
2272 env
->mtrr_var
[MSR_MTRRphysIndex(index
)].base
= msrs
[i
].data
;
2281 static int kvm_put_mp_state(X86CPU
*cpu
)
2283 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
2285 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
2288 static int kvm_get_mp_state(X86CPU
*cpu
)
2290 CPUState
*cs
= CPU(cpu
);
2291 CPUX86State
*env
= &cpu
->env
;
2292 struct kvm_mp_state mp_state
;
2295 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
2299 env
->mp_state
= mp_state
.mp_state
;
2300 if (kvm_irqchip_in_kernel()) {
2301 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
2306 static int kvm_get_apic(X86CPU
*cpu
)
2308 DeviceState
*apic
= cpu
->apic_state
;
2309 struct kvm_lapic_state kapic
;
2312 if (apic
&& kvm_irqchip_in_kernel()) {
2313 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
2318 kvm_get_apic_state(apic
, &kapic
);
2323 static int kvm_put_apic(X86CPU
*cpu
)
2325 DeviceState
*apic
= cpu
->apic_state
;
2326 struct kvm_lapic_state kapic
;
2328 if (apic
&& kvm_irqchip_in_kernel()) {
2329 kvm_put_apic_state(apic
, &kapic
);
2331 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_LAPIC
, &kapic
);
2336 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
2338 CPUState
*cs
= CPU(cpu
);
2339 CPUX86State
*env
= &cpu
->env
;
2340 struct kvm_vcpu_events events
= {};
2342 if (!kvm_has_vcpu_events()) {
2346 events
.exception
.injected
= (env
->exception_injected
>= 0);
2347 events
.exception
.nr
= env
->exception_injected
;
2348 events
.exception
.has_error_code
= env
->has_error_code
;
2349 events
.exception
.error_code
= env
->error_code
;
2350 events
.exception
.pad
= 0;
2352 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
2353 events
.interrupt
.nr
= env
->interrupt_injected
;
2354 events
.interrupt
.soft
= env
->soft_interrupt
;
2356 events
.nmi
.injected
= env
->nmi_injected
;
2357 events
.nmi
.pending
= env
->nmi_pending
;
2358 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
2361 events
.sipi_vector
= env
->sipi_vector
;
2363 if (has_msr_smbase
) {
2364 events
.smi
.smm
= !!(env
->hflags
& HF_SMM_MASK
);
2365 events
.smi
.smm_inside_nmi
= !!(env
->hflags2
& HF2_SMM_INSIDE_NMI_MASK
);
2366 if (kvm_irqchip_in_kernel()) {
2367 /* As soon as these are moved to the kernel, remove them
2368 * from cs->interrupt_request.
2370 events
.smi
.pending
= cs
->interrupt_request
& CPU_INTERRUPT_SMI
;
2371 events
.smi
.latched_init
= cs
->interrupt_request
& CPU_INTERRUPT_INIT
;
2372 cs
->interrupt_request
&= ~(CPU_INTERRUPT_INIT
| CPU_INTERRUPT_SMI
);
2374 /* Keep these in cs->interrupt_request. */
2375 events
.smi
.pending
= 0;
2376 events
.smi
.latched_init
= 0;
2378 events
.flags
|= KVM_VCPUEVENT_VALID_SMM
;
2382 if (level
>= KVM_PUT_RESET_STATE
) {
2384 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
2387 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
2390 static int kvm_get_vcpu_events(X86CPU
*cpu
)
2392 CPUX86State
*env
= &cpu
->env
;
2393 struct kvm_vcpu_events events
;
2396 if (!kvm_has_vcpu_events()) {
2400 memset(&events
, 0, sizeof(events
));
2401 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
2405 env
->exception_injected
=
2406 events
.exception
.injected
? events
.exception
.nr
: -1;
2407 env
->has_error_code
= events
.exception
.has_error_code
;
2408 env
->error_code
= events
.exception
.error_code
;
2410 env
->interrupt_injected
=
2411 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
2412 env
->soft_interrupt
= events
.interrupt
.soft
;
2414 env
->nmi_injected
= events
.nmi
.injected
;
2415 env
->nmi_pending
= events
.nmi
.pending
;
2416 if (events
.nmi
.masked
) {
2417 env
->hflags2
|= HF2_NMI_MASK
;
2419 env
->hflags2
&= ~HF2_NMI_MASK
;
2422 if (events
.flags
& KVM_VCPUEVENT_VALID_SMM
) {
2423 if (events
.smi
.smm
) {
2424 env
->hflags
|= HF_SMM_MASK
;
2426 env
->hflags
&= ~HF_SMM_MASK
;
2428 if (events
.smi
.pending
) {
2429 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2431 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
2433 if (events
.smi
.smm_inside_nmi
) {
2434 env
->hflags2
|= HF2_SMM_INSIDE_NMI_MASK
;
2436 env
->hflags2
&= ~HF2_SMM_INSIDE_NMI_MASK
;
2438 if (events
.smi
.latched_init
) {
2439 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2441 cpu_reset_interrupt(CPU(cpu
), CPU_INTERRUPT_INIT
);
2445 env
->sipi_vector
= events
.sipi_vector
;
2450 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
2452 CPUState
*cs
= CPU(cpu
);
2453 CPUX86State
*env
= &cpu
->env
;
2455 unsigned long reinject_trap
= 0;
2457 if (!kvm_has_vcpu_events()) {
2458 if (env
->exception_injected
== 1) {
2459 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
2460 } else if (env
->exception_injected
== 3) {
2461 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
2463 env
->exception_injected
= -1;
2467 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2468 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2469 * by updating the debug state once again if single-stepping is on.
2470 * Another reason to call kvm_update_guest_debug here is a pending debug
2471 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2472 * reinject them via SET_GUEST_DEBUG.
2474 if (reinject_trap
||
2475 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
2476 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
2481 static int kvm_put_debugregs(X86CPU
*cpu
)
2483 CPUX86State
*env
= &cpu
->env
;
2484 struct kvm_debugregs dbgregs
;
2487 if (!kvm_has_debugregs()) {
2491 for (i
= 0; i
< 4; i
++) {
2492 dbgregs
.db
[i
] = env
->dr
[i
];
2494 dbgregs
.dr6
= env
->dr
[6];
2495 dbgregs
.dr7
= env
->dr
[7];
2498 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
2501 static int kvm_get_debugregs(X86CPU
*cpu
)
2503 CPUX86State
*env
= &cpu
->env
;
2504 struct kvm_debugregs dbgregs
;
2507 if (!kvm_has_debugregs()) {
2511 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
2515 for (i
= 0; i
< 4; i
++) {
2516 env
->dr
[i
] = dbgregs
.db
[i
];
2518 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
2519 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
2524 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
2526 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2529 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
2531 if (level
>= KVM_PUT_RESET_STATE
) {
2532 ret
= kvm_put_msr_feature_control(x86_cpu
);
2538 if (level
== KVM_PUT_FULL_STATE
) {
2539 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2540 * because TSC frequency mismatch shouldn't abort migration,
2541 * unless the user explicitly asked for a more strict TSC
2542 * setting (e.g. using an explicit "tsc-freq" option).
2544 kvm_arch_set_tsc_khz(cpu
);
2547 ret
= kvm_getput_regs(x86_cpu
, 1);
2551 ret
= kvm_put_xsave(x86_cpu
);
2555 ret
= kvm_put_xcrs(x86_cpu
);
2559 ret
= kvm_put_sregs(x86_cpu
);
2563 /* must be before kvm_put_msrs */
2564 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
2568 ret
= kvm_put_msrs(x86_cpu
, level
);
2572 if (level
>= KVM_PUT_RESET_STATE
) {
2573 ret
= kvm_put_mp_state(x86_cpu
);
2577 ret
= kvm_put_apic(x86_cpu
);
2583 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
2588 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
2592 ret
= kvm_put_debugregs(x86_cpu
);
2597 ret
= kvm_guest_debug_workarounds(x86_cpu
);
2604 int kvm_arch_get_registers(CPUState
*cs
)
2606 X86CPU
*cpu
= X86_CPU(cs
);
2609 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
2611 ret
= kvm_getput_regs(cpu
, 0);
2615 ret
= kvm_get_xsave(cpu
);
2619 ret
= kvm_get_xcrs(cpu
);
2623 ret
= kvm_get_sregs(cpu
);
2627 ret
= kvm_get_msrs(cpu
);
2631 ret
= kvm_get_mp_state(cpu
);
2635 ret
= kvm_get_apic(cpu
);
2639 ret
= kvm_get_vcpu_events(cpu
);
2643 ret
= kvm_get_debugregs(cpu
);
2649 cpu_sync_bndcs_hflags(&cpu
->env
);
2653 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
2655 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2656 CPUX86State
*env
= &x86_cpu
->env
;
2660 if (cpu
->interrupt_request
& (CPU_INTERRUPT_NMI
| CPU_INTERRUPT_SMI
)) {
2661 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
2662 qemu_mutex_lock_iothread();
2663 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
2664 qemu_mutex_unlock_iothread();
2665 DPRINTF("injected NMI\n");
2666 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
2668 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
2672 if (cpu
->interrupt_request
& CPU_INTERRUPT_SMI
) {
2673 qemu_mutex_lock_iothread();
2674 cpu
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
2675 qemu_mutex_unlock_iothread();
2676 DPRINTF("injected SMI\n");
2677 ret
= kvm_vcpu_ioctl(cpu
, KVM_SMI
);
2679 fprintf(stderr
, "KVM: injection failed, SMI lost (%s)\n",
2685 if (!kvm_pic_in_kernel()) {
2686 qemu_mutex_lock_iothread();
2689 /* Force the VCPU out of its inner loop to process any INIT requests
2690 * or (for userspace APIC, but it is cheap to combine the checks here)
2691 * pending TPR access reports.
2693 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
2694 if ((cpu
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2695 !(env
->hflags
& HF_SMM_MASK
)) {
2696 cpu
->exit_request
= 1;
2698 if (cpu
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2699 cpu
->exit_request
= 1;
2703 if (!kvm_pic_in_kernel()) {
2704 /* Try to inject an interrupt if the guest can accept it */
2705 if (run
->ready_for_interrupt_injection
&&
2706 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2707 (env
->eflags
& IF_MASK
)) {
2710 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
2711 irq
= cpu_get_pic_interrupt(env
);
2713 struct kvm_interrupt intr
;
2716 DPRINTF("injected interrupt %d\n", irq
);
2717 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
2720 "KVM: injection failed, interrupt lost (%s)\n",
2726 /* If we have an interrupt but the guest is not ready to receive an
2727 * interrupt, request an interrupt window exit. This will
2728 * cause a return to userspace as soon as the guest is ready to
2729 * receive interrupts. */
2730 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
2731 run
->request_interrupt_window
= 1;
2733 run
->request_interrupt_window
= 0;
2736 DPRINTF("setting tpr\n");
2737 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
2739 qemu_mutex_unlock_iothread();
2743 MemTxAttrs
kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
2745 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2746 CPUX86State
*env
= &x86_cpu
->env
;
2748 if (run
->flags
& KVM_RUN_X86_SMM
) {
2749 env
->hflags
|= HF_SMM_MASK
;
2751 env
->hflags
&= HF_SMM_MASK
;
2754 env
->eflags
|= IF_MASK
;
2756 env
->eflags
&= ~IF_MASK
;
2759 /* We need to protect the apic state against concurrent accesses from
2760 * different threads in case the userspace irqchip is used. */
2761 if (!kvm_irqchip_in_kernel()) {
2762 qemu_mutex_lock_iothread();
2764 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
2765 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
2766 if (!kvm_irqchip_in_kernel()) {
2767 qemu_mutex_unlock_iothread();
2769 return cpu_get_mem_attrs(env
);
2772 int kvm_arch_process_async_events(CPUState
*cs
)
2774 X86CPU
*cpu
= X86_CPU(cs
);
2775 CPUX86State
*env
= &cpu
->env
;
2777 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
2778 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2779 assert(env
->mcg_cap
);
2781 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
2783 kvm_cpu_synchronize_state(cs
);
2785 if (env
->exception_injected
== EXCP08_DBLE
) {
2786 /* this means triple fault */
2787 qemu_system_reset_request();
2788 cs
->exit_request
= 1;
2791 env
->exception_injected
= EXCP12_MCHK
;
2792 env
->has_error_code
= 0;
2795 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
2796 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
2800 if ((cs
->interrupt_request
& CPU_INTERRUPT_INIT
) &&
2801 !(env
->hflags
& HF_SMM_MASK
)) {
2802 kvm_cpu_synchronize_state(cs
);
2806 if (kvm_irqchip_in_kernel()) {
2810 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2811 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
2812 apic_poll_irq(cpu
->apic_state
);
2814 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2815 (env
->eflags
& IF_MASK
)) ||
2816 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2819 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
2820 kvm_cpu_synchronize_state(cs
);
2823 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2824 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
2825 kvm_cpu_synchronize_state(cs
);
2826 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
2827 env
->tpr_access_type
);
2833 static int kvm_handle_halt(X86CPU
*cpu
)
2835 CPUState
*cs
= CPU(cpu
);
2836 CPUX86State
*env
= &cpu
->env
;
2838 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2839 (env
->eflags
& IF_MASK
)) &&
2840 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2848 static int kvm_handle_tpr_access(X86CPU
*cpu
)
2850 CPUState
*cs
= CPU(cpu
);
2851 struct kvm_run
*run
= cs
->kvm_run
;
2853 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
2854 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
2859 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2861 static const uint8_t int3
= 0xcc;
2863 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
2864 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
2870 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2874 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
2875 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
2887 static int nb_hw_breakpoint
;
2889 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
2893 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2894 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
2895 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
2902 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
2903 target_ulong len
, int type
)
2906 case GDB_BREAKPOINT_HW
:
2909 case GDB_WATCHPOINT_WRITE
:
2910 case GDB_WATCHPOINT_ACCESS
:
2917 if (addr
& (len
- 1)) {
2929 if (nb_hw_breakpoint
== 4) {
2932 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
2935 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
2936 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
2937 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
2943 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
2944 target_ulong len
, int type
)
2948 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
2953 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
2958 void kvm_arch_remove_all_hw_breakpoints(void)
2960 nb_hw_breakpoint
= 0;
2963 static CPUWatchpoint hw_watchpoint
;
2965 static int kvm_handle_debug(X86CPU
*cpu
,
2966 struct kvm_debug_exit_arch
*arch_info
)
2968 CPUState
*cs
= CPU(cpu
);
2969 CPUX86State
*env
= &cpu
->env
;
2973 if (arch_info
->exception
== 1) {
2974 if (arch_info
->dr6
& (1 << 14)) {
2975 if (cs
->singlestep_enabled
) {
2979 for (n
= 0; n
< 4; n
++) {
2980 if (arch_info
->dr6
& (1 << n
)) {
2981 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
2987 cs
->watchpoint_hit
= &hw_watchpoint
;
2988 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2989 hw_watchpoint
.flags
= BP_MEM_WRITE
;
2993 cs
->watchpoint_hit
= &hw_watchpoint
;
2994 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2995 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
3001 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
3005 cpu_synchronize_state(cs
);
3006 assert(env
->exception_injected
== -1);
3009 env
->exception_injected
= arch_info
->exception
;
3010 env
->has_error_code
= 0;
3016 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
3018 const uint8_t type_code
[] = {
3019 [GDB_BREAKPOINT_HW
] = 0x0,
3020 [GDB_WATCHPOINT_WRITE
] = 0x1,
3021 [GDB_WATCHPOINT_ACCESS
] = 0x3
3023 const uint8_t len_code
[] = {
3024 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3028 if (kvm_sw_breakpoints_active(cpu
)) {
3029 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
3031 if (nb_hw_breakpoint
> 0) {
3032 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
3033 dbg
->arch
.debugreg
[7] = 0x0600;
3034 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
3035 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
3036 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
3037 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
3038 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
3043 static bool host_supports_vmx(void)
3045 uint32_t ecx
, unused
;
3047 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
3048 return ecx
& CPUID_EXT_VMX
;
3051 #define VMX_INVALID_GUEST_STATE 0x80000021
3053 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
3055 X86CPU
*cpu
= X86_CPU(cs
);
3059 switch (run
->exit_reason
) {
3061 DPRINTF("handle_hlt\n");
3062 qemu_mutex_lock_iothread();
3063 ret
= kvm_handle_halt(cpu
);
3064 qemu_mutex_unlock_iothread();
3066 case KVM_EXIT_SET_TPR
:
3069 case KVM_EXIT_TPR_ACCESS
:
3070 qemu_mutex_lock_iothread();
3071 ret
= kvm_handle_tpr_access(cpu
);
3072 qemu_mutex_unlock_iothread();
3074 case KVM_EXIT_FAIL_ENTRY
:
3075 code
= run
->fail_entry
.hardware_entry_failure_reason
;
3076 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
3078 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
3080 "\nIf you're running a guest on an Intel machine without "
3081 "unrestricted mode\n"
3082 "support, the failure can be most likely due to the guest "
3083 "entering an invalid\n"
3084 "state for Intel VT. For example, the guest maybe running "
3085 "in big real mode\n"
3086 "which is not supported on less recent Intel processors."
3091 case KVM_EXIT_EXCEPTION
:
3092 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
3093 run
->ex
.exception
, run
->ex
.error_code
);
3096 case KVM_EXIT_DEBUG
:
3097 DPRINTF("kvm_exit_debug\n");
3098 qemu_mutex_lock_iothread();
3099 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
3100 qemu_mutex_unlock_iothread();
3102 case KVM_EXIT_HYPERV
:
3103 ret
= kvm_hv_handle_exit(cpu
, &run
->hyperv
);
3105 case KVM_EXIT_IOAPIC_EOI
:
3106 ioapic_eoi_broadcast(run
->eoi
.vector
);
3110 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
3118 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
3120 X86CPU
*cpu
= X86_CPU(cs
);
3121 CPUX86State
*env
= &cpu
->env
;
3123 kvm_cpu_synchronize_state(cs
);
3124 return !(env
->cr
[0] & CR0_PE_MASK
) ||
3125 ((env
->segs
[R_CS
].selector
& 3) != 3);
3128 void kvm_arch_init_irq_routing(KVMState
*s
)
3130 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
3131 /* If kernel can't do irq routing, interrupt source
3132 * override 0->2 cannot be set up as required by HPET.
3133 * So we have to disable it.
3137 /* We know at this point that we're using the in-kernel
3138 * irqchip, so we can use irqfds, and on x86 we know
3139 * we can use msi via irqfd and GSI routing.
3141 kvm_msi_via_irqfd_allowed
= true;
3142 kvm_gsi_routing_allowed
= true;
3144 if (kvm_irqchip_is_split()) {
3147 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3148 MSI routes for signaling interrupts to the local apics. */
3149 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
3150 struct MSIMessage msg
= { 0x0, 0x0 };
3151 if (kvm_irqchip_add_msi_route(s
, msg
, NULL
) < 0) {
3152 error_report("Could not enable split IRQ mode.");
3159 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
3162 if (machine_kernel_irqchip_split(ms
)) {
3163 ret
= kvm_vm_enable_cap(s
, KVM_CAP_SPLIT_IRQCHIP
, 0, 24);
3165 error_report("Could not enable split irqchip mode: %s\n",
3169 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3170 kvm_split_irqchip
= true;
3178 /* Classic KVM device assignment interface. Will remain x86 only. */
3179 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
3180 uint32_t flags
, uint32_t *dev_id
)
3182 struct kvm_assigned_pci_dev dev_data
= {
3183 .segnr
= dev_addr
->domain
,
3184 .busnr
= dev_addr
->bus
,
3185 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
3190 dev_data
.assigned_dev_id
=
3191 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
3193 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
3198 *dev_id
= dev_data
.assigned_dev_id
;
3203 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
3205 struct kvm_assigned_pci_dev dev_data
= {
3206 .assigned_dev_id
= dev_id
,
3209 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
3212 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3213 uint32_t irq_type
, uint32_t guest_irq
)
3215 struct kvm_assigned_irq assigned_irq
= {
3216 .assigned_dev_id
= dev_id
,
3217 .guest_irq
= guest_irq
,
3221 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
3222 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
3224 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
3228 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
3231 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
3232 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
3234 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
3237 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
3239 struct kvm_assigned_pci_dev dev_data
= {
3240 .assigned_dev_id
= dev_id
,
3241 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
3244 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
3247 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
3250 struct kvm_assigned_irq assigned_irq
= {
3251 .assigned_dev_id
= dev_id
,
3255 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
3258 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
3260 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
3261 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
3264 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
3266 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
3267 KVM_DEV_IRQ_GUEST_MSI
, virq
);
3270 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
3272 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
3273 KVM_DEV_IRQ_HOST_MSI
);
3276 bool kvm_device_msix_supported(KVMState
*s
)
3278 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3279 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3280 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
3283 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
3284 uint32_t nr_vectors
)
3286 struct kvm_assigned_msix_nr msix_nr
= {
3287 .assigned_dev_id
= dev_id
,
3288 .entry_nr
= nr_vectors
,
3291 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
3294 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
3297 struct kvm_assigned_msix_entry msix_entry
= {
3298 .assigned_dev_id
= dev_id
,
3303 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
3306 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
3308 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
3309 KVM_DEV_IRQ_GUEST_MSIX
, 0);
3312 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
3314 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
3315 KVM_DEV_IRQ_HOST_MSIX
);
3318 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
3319 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
3324 int kvm_arch_msi_data_to_gsi(uint32_t data
)