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sdl2: move sdl_update to new sdl2-2d.c
[qemu/cris-port.git] / hw / sparc / sun4m.c
blob8273199f11a440ae6388e15a595beb5dae92a859
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/error-report.h"
26 #include "qemu/timer.h"
27 #include "hw/sparc/sun4m.h"
28 #include "hw/timer/m48t59.h"
29 #include "hw/sparc/sparc32_dma.h"
30 #include "hw/block/fdc.h"
31 #include "sysemu/sysemu.h"
32 #include "net/net.h"
33 #include "hw/boards.h"
34 #include "hw/nvram/openbios_firmware_abi.h"
35 #include "hw/scsi/esp.h"
36 #include "hw/i386/pc.h"
37 #include "hw/isa/isa.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/char/escc.h"
40 #include "hw/empty_slot.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "sysemu/block-backend.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * See for example: http://www.sunhelp.org/faq/sunref1.html
60 */
61
62 #define KERNEL_LOAD_ADDR 0x00004000
63 #define CMDLINE_ADDR 0x007ff000
64 #define INITRD_LOAD_ADDR 0x00800000
65 #define PROM_SIZE_MAX (1024 * 1024)
66 #define PROM_VADDR 0xffd00000
67 #define PROM_FILENAME "openbios-sparc32"
68 #define CFG_ADDR 0xd00000510ULL
69 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
70 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
71 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
72
73 #define MAX_CPUS 16
74 #define MAX_PILS 16
75 #define MAX_VSIMMS 4
76
77 #define ESCC_CLOCK 4915200
78
79 struct sun4m_hwdef {
80 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
81 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
82 hwaddr serial_base, fd_base;
83 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
84 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
85 hwaddr bpp_base, dbri_base, sx_base;
86 struct {
87 hwaddr reg_base, vram_base;
88 } vsimm[MAX_VSIMMS];
89 hwaddr ecc_base;
90 uint64_t max_mem;
91 const char * const default_cpu_model;
92 uint32_t ecc_version;
93 uint32_t iommu_version;
94 uint16_t machine_id;
95 uint8_t nvram_machine_id;
96 };
97
98 int DMA_get_channel_mode (int nchan)
99 {
100 return 0;
101 }
102 int DMA_read_memory (int nchan, void *buf, int pos, int size)
103 {
104 return 0;
105 }
106 int DMA_write_memory (int nchan, void *buf, int pos, int size)
107 {
108 return 0;
109 }
110 void DMA_hold_DREQ (int nchan) {}
111 void DMA_release_DREQ (int nchan) {}
112 void DMA_schedule(int nchan) {}
113
114 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
115 {
116 }
117
118 void DMA_register_channel (int nchan,
119 DMA_transfer_handler transfer_handler,
120 void *opaque)
121 {
122 }
123
124 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
125 {
126 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
127 return 0;
128 }
129
130 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
131 const char *cmdline, const char *boot_devices,
132 ram_addr_t RAM_size, uint32_t kernel_size,
133 int width, int height, int depth,
134 int nvram_machine_id, const char *arch)
135 {
136 unsigned int i;
137 uint32_t start, end;
138 uint8_t image[0x1ff0];
139 struct OpenBIOS_nvpart_v1 *part_header;
140
141 memset(image, '\0', sizeof(image));
142
143 start = 0;
144
145 // OpenBIOS nvram variables
146 // Variable partition
147 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
148 part_header->signature = OPENBIOS_PART_SYSTEM;
149 pstrcpy(part_header->name, sizeof(part_header->name), "system");
150
151 end = start + sizeof(struct OpenBIOS_nvpart_v1);
152 for (i = 0; i < nb_prom_envs; i++)
153 end = OpenBIOS_set_var(image, end, prom_envs[i]);
154
155 // End marker
156 image[end++] = '\0';
157
158 end = start + ((end - start + 15) & ~15);
159 OpenBIOS_finish_partition(part_header, end - start);
160
161 // free partition
162 start = end;
163 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
164 part_header->signature = OPENBIOS_PART_FREE;
165 pstrcpy(part_header->name, sizeof(part_header->name), "free");
166
167 end = 0x1fd0;
168 OpenBIOS_finish_partition(part_header, end - start);
169
170 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
171 nvram_machine_id);
172
173 for (i = 0; i < sizeof(image); i++)
174 m48t59_write(nvram, i, image[i]);
175 }
176
177 static DeviceState *slavio_intctl;
178
179 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
180 {
181 if (slavio_intctl)
182 slavio_pic_info(mon, slavio_intctl);
183 }
184
185 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
186 {
187 if (slavio_intctl)
188 slavio_irq_info(mon, slavio_intctl);
189 }
190
191 void cpu_check_irqs(CPUSPARCState *env)
192 {
193 CPUState *cs;
194
195 if (env->pil_in && (env->interrupt_index == 0 ||
196 (env->interrupt_index & ~15) == TT_EXTINT)) {
197 unsigned int i;
198
199 for (i = 15; i > 0; i--) {
200 if (env->pil_in & (1 << i)) {
201 int old_interrupt = env->interrupt_index;
202
203 env->interrupt_index = TT_EXTINT | i;
204 if (old_interrupt != env->interrupt_index) {
205 cs = CPU(sparc_env_get_cpu(env));
206 trace_sun4m_cpu_interrupt(i);
207 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
208 }
209 break;
210 }
211 }
212 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
213 cs = CPU(sparc_env_get_cpu(env));
214 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
215 env->interrupt_index = 0;
216 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
217 }
218 }
219
220 static void cpu_kick_irq(SPARCCPU *cpu)
221 {
222 CPUSPARCState *env = &cpu->env;
223 CPUState *cs = CPU(cpu);
224
225 cs->halted = 0;
226 cpu_check_irqs(env);
227 qemu_cpu_kick(cs);
228 }
229
230 static void cpu_set_irq(void *opaque, int irq, int level)
231 {
232 SPARCCPU *cpu = opaque;
233 CPUSPARCState *env = &cpu->env;
234
235 if (level) {
236 trace_sun4m_cpu_set_irq_raise(irq);
237 env->pil_in |= 1 << irq;
238 cpu_kick_irq(cpu);
239 } else {
240 trace_sun4m_cpu_set_irq_lower(irq);
241 env->pil_in &= ~(1 << irq);
242 cpu_check_irqs(env);
243 }
244 }
245
246 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
247 {
248 }
249
250 static void main_cpu_reset(void *opaque)
251 {
252 SPARCCPU *cpu = opaque;
253 CPUState *cs = CPU(cpu);
254
255 cpu_reset(cs);
256 cs->halted = 0;
257 }
258
259 static void secondary_cpu_reset(void *opaque)
260 {
261 SPARCCPU *cpu = opaque;
262 CPUState *cs = CPU(cpu);
263
264 cpu_reset(cs);
265 cs->halted = 1;
266 }
267
268 static void cpu_halt_signal(void *opaque, int irq, int level)
269 {
270 if (level && current_cpu) {
271 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
272 }
273 }
274
275 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
276 {
277 return addr - 0xf0000000ULL;
278 }
279
280 static unsigned long sun4m_load_kernel(const char *kernel_filename,
281 const char *initrd_filename,
282 ram_addr_t RAM_size)
283 {
284 int linux_boot;
285 unsigned int i;
286 long initrd_size, kernel_size;
287 uint8_t *ptr;
288
289 linux_boot = (kernel_filename != NULL);
290
291 kernel_size = 0;
292 if (linux_boot) {
293 int bswap_needed;
294
295 #ifdef BSWAP_NEEDED
296 bswap_needed = 1;
297 #else
298 bswap_needed = 0;
299 #endif
300 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
301 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
302 if (kernel_size < 0)
303 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
304 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
305 TARGET_PAGE_SIZE);
306 if (kernel_size < 0)
307 kernel_size = load_image_targphys(kernel_filename,
308 KERNEL_LOAD_ADDR,
309 RAM_size - KERNEL_LOAD_ADDR);
310 if (kernel_size < 0) {
311 fprintf(stderr, "qemu: could not load kernel '%s'\n",
312 kernel_filename);
313 exit(1);
314 }
315
316 /* load initrd */
317 initrd_size = 0;
318 if (initrd_filename) {
319 initrd_size = load_image_targphys(initrd_filename,
320 INITRD_LOAD_ADDR,
321 RAM_size - INITRD_LOAD_ADDR);
322 if (initrd_size < 0) {
323 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
324 initrd_filename);
325 exit(1);
326 }
327 }
328 if (initrd_size > 0) {
329 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
330 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
331 if (ldl_p(ptr) == 0x48647253) { // HdrS
332 stl_p(ptr + 16, INITRD_LOAD_ADDR);
333 stl_p(ptr + 20, initrd_size);
334 break;
335 }
336 }
337 }
338 }
339 return kernel_size;
340 }
341
342 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
343 {
344 DeviceState *dev;
345 SysBusDevice *s;
346
347 dev = qdev_create(NULL, "iommu");
348 qdev_prop_set_uint32(dev, "version", version);
349 qdev_init_nofail(dev);
350 s = SYS_BUS_DEVICE(dev);
351 sysbus_connect_irq(s, 0, irq);
352 sysbus_mmio_map(s, 0, addr);
353
354 return s;
355 }
356
357 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
358 void *iommu, qemu_irq *dev_irq, int is_ledma)
359 {
360 DeviceState *dev;
361 SysBusDevice *s;
362
363 dev = qdev_create(NULL, "sparc32_dma");
364 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
365 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
366 qdev_init_nofail(dev);
367 s = SYS_BUS_DEVICE(dev);
368 sysbus_connect_irq(s, 0, parent_irq);
369 *dev_irq = qdev_get_gpio_in(dev, 0);
370 sysbus_mmio_map(s, 0, daddr);
371
372 return s;
373 }
374
375 static void lance_init(NICInfo *nd, hwaddr leaddr,
376 void *dma_opaque, qemu_irq irq)
377 {
378 DeviceState *dev;
379 SysBusDevice *s;
380 qemu_irq reset;
381
382 qemu_check_nic_model(&nd_table[0], "lance");
383
384 dev = qdev_create(NULL, "lance");
385 qdev_set_nic_properties(dev, nd);
386 qdev_prop_set_ptr(dev, "dma", dma_opaque);
387 qdev_init_nofail(dev);
388 s = SYS_BUS_DEVICE(dev);
389 sysbus_mmio_map(s, 0, leaddr);
390 sysbus_connect_irq(s, 0, irq);
391 reset = qdev_get_gpio_in(dev, 0);
392 qdev_connect_gpio_out(dma_opaque, 0, reset);
393 }
394
395 static DeviceState *slavio_intctl_init(hwaddr addr,
396 hwaddr addrg,
397 qemu_irq **parent_irq)
398 {
399 DeviceState *dev;
400 SysBusDevice *s;
401 unsigned int i, j;
402
403 dev = qdev_create(NULL, "slavio_intctl");
404 qdev_init_nofail(dev);
405
406 s = SYS_BUS_DEVICE(dev);
407
408 for (i = 0; i < MAX_CPUS; i++) {
409 for (j = 0; j < MAX_PILS; j++) {
410 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
411 }
412 }
413 sysbus_mmio_map(s, 0, addrg);
414 for (i = 0; i < MAX_CPUS; i++) {
415 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
416 }
417
418 return dev;
419 }
420
421 #define SYS_TIMER_OFFSET 0x10000ULL
422 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
423
424 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
425 qemu_irq *cpu_irqs, unsigned int num_cpus)
426 {
427 DeviceState *dev;
428 SysBusDevice *s;
429 unsigned int i;
430
431 dev = qdev_create(NULL, "slavio_timer");
432 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
433 qdev_init_nofail(dev);
434 s = SYS_BUS_DEVICE(dev);
435 sysbus_connect_irq(s, 0, master_irq);
436 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
437
438 for (i = 0; i < MAX_CPUS; i++) {
439 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
440 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
441 }
442 }
443
444 static qemu_irq slavio_system_powerdown;
445
446 static void slavio_powerdown_req(Notifier *n, void *opaque)
447 {
448 qemu_irq_raise(slavio_system_powerdown);
449 }
450
451 static Notifier slavio_system_powerdown_notifier = {
452 .notify = slavio_powerdown_req
453 };
454
455 #define MISC_LEDS 0x01600000
456 #define MISC_CFG 0x01800000
457 #define MISC_DIAG 0x01a00000
458 #define MISC_MDM 0x01b00000
459 #define MISC_SYS 0x01f00000
460
461 static void slavio_misc_init(hwaddr base,
462 hwaddr aux1_base,
463 hwaddr aux2_base, qemu_irq irq,
464 qemu_irq fdc_tc)
465 {
466 DeviceState *dev;
467 SysBusDevice *s;
468
469 dev = qdev_create(NULL, "slavio_misc");
470 qdev_init_nofail(dev);
471 s = SYS_BUS_DEVICE(dev);
472 if (base) {
473 /* 8 bit registers */
474 /* Slavio control */
475 sysbus_mmio_map(s, 0, base + MISC_CFG);
476 /* Diagnostics */
477 sysbus_mmio_map(s, 1, base + MISC_DIAG);
478 /* Modem control */
479 sysbus_mmio_map(s, 2, base + MISC_MDM);
480 /* 16 bit registers */
481 /* ss600mp diag LEDs */
482 sysbus_mmio_map(s, 3, base + MISC_LEDS);
483 /* 32 bit registers */
484 /* System control */
485 sysbus_mmio_map(s, 4, base + MISC_SYS);
486 }
487 if (aux1_base) {
488 /* AUX 1 (Misc System Functions) */
489 sysbus_mmio_map(s, 5, aux1_base);
490 }
491 if (aux2_base) {
492 /* AUX 2 (Software Powerdown Control) */
493 sysbus_mmio_map(s, 6, aux2_base);
494 }
495 sysbus_connect_irq(s, 0, irq);
496 sysbus_connect_irq(s, 1, fdc_tc);
497 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
498 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
499 }
500
501 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
502 {
503 DeviceState *dev;
504 SysBusDevice *s;
505
506 dev = qdev_create(NULL, "eccmemctl");
507 qdev_prop_set_uint32(dev, "version", version);
508 qdev_init_nofail(dev);
509 s = SYS_BUS_DEVICE(dev);
510 sysbus_connect_irq(s, 0, irq);
511 sysbus_mmio_map(s, 0, base);
512 if (version == 0) { // SS-600MP only
513 sysbus_mmio_map(s, 1, base + 0x1000);
514 }
515 }
516
517 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
518 {
519 DeviceState *dev;
520 SysBusDevice *s;
521
522 dev = qdev_create(NULL, "apc");
523 qdev_init_nofail(dev);
524 s = SYS_BUS_DEVICE(dev);
525 /* Power management (APC) XXX: not a Slavio device */
526 sysbus_mmio_map(s, 0, power_base);
527 sysbus_connect_irq(s, 0, cpu_halt);
528 }
529
530 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
531 int height, int depth)
532 {
533 DeviceState *dev;
534 SysBusDevice *s;
535
536 dev = qdev_create(NULL, "SUNW,tcx");
537 qdev_prop_set_uint32(dev, "vram_size", vram_size);
538 qdev_prop_set_uint16(dev, "width", width);
539 qdev_prop_set_uint16(dev, "height", height);
540 qdev_prop_set_uint16(dev, "depth", depth);
541 qdev_prop_set_uint64(dev, "prom_addr", addr);
542 qdev_init_nofail(dev);
543 s = SYS_BUS_DEVICE(dev);
544
545 /* 10/ROM : FCode ROM */
546 sysbus_mmio_map(s, 0, addr);
547 /* 2/STIP : Stipple */
548 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
549 /* 3/BLIT : Blitter */
550 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
551 /* 5/RSTIP : Raw Stipple */
552 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
553 /* 6/RBLIT : Raw Blitter */
554 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
555 /* 7/TEC : Transform Engine */
556 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
557 /* 8/CMAP : DAC */
558 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
559 /* 9/THC : */
560 if (depth == 8) {
561 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
562 } else {
563 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
564 }
565 /* 11/DHC : */
566 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
567 /* 12/ALT : */
568 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
569 /* 0/DFB8 : 8-bit plane */
570 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
571 /* 1/DFB24 : 24bit plane */
572 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
573 /* 4/RDFB32: Raw framebuffer. Control plane */
574 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
575 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
576 if (depth == 8) {
577 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
578 }
579
580 sysbus_connect_irq(s, 0, irq);
581 }
582
583 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
584 int height, int depth)
585 {
586 DeviceState *dev;
587 SysBusDevice *s;
588
589 dev = qdev_create(NULL, "cgthree");
590 qdev_prop_set_uint32(dev, "vram-size", vram_size);
591 qdev_prop_set_uint16(dev, "width", width);
592 qdev_prop_set_uint16(dev, "height", height);
593 qdev_prop_set_uint16(dev, "depth", depth);
594 qdev_prop_set_uint64(dev, "prom-addr", addr);
595 qdev_init_nofail(dev);
596 s = SYS_BUS_DEVICE(dev);
597
598 /* FCode ROM */
599 sysbus_mmio_map(s, 0, addr);
600 /* DAC */
601 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
602 /* 8-bit plane */
603 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
604
605 sysbus_connect_irq(s, 0, irq);
606 }
607
608 /* NCR89C100/MACIO Internal ID register */
609
610 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
611
612 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
613
614 static void idreg_init(hwaddr addr)
615 {
616 DeviceState *dev;
617 SysBusDevice *s;
618
619 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
620 qdev_init_nofail(dev);
621 s = SYS_BUS_DEVICE(dev);
622
623 sysbus_mmio_map(s, 0, addr);
624 cpu_physical_memory_write_rom(&address_space_memory,
625 addr, idreg_data, sizeof(idreg_data));
626 }
627
628 #define MACIO_ID_REGISTER(obj) \
629 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
630
631 typedef struct IDRegState {
632 SysBusDevice parent_obj;
633
634 MemoryRegion mem;
635 } IDRegState;
636
637 static int idreg_init1(SysBusDevice *dev)
638 {
639 IDRegState *s = MACIO_ID_REGISTER(dev);
640
641 memory_region_init_ram(&s->mem, OBJECT(s),
642 "sun4m.idreg", sizeof(idreg_data), &error_abort);
643 vmstate_register_ram_global(&s->mem);
644 memory_region_set_readonly(&s->mem, true);
645 sysbus_init_mmio(dev, &s->mem);
646 return 0;
647 }
648
649 static void idreg_class_init(ObjectClass *klass, void *data)
650 {
651 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
652
653 k->init = idreg_init1;
654 }
655
656 static const TypeInfo idreg_info = {
657 .name = TYPE_MACIO_ID_REGISTER,
658 .parent = TYPE_SYS_BUS_DEVICE,
659 .instance_size = sizeof(IDRegState),
660 .class_init = idreg_class_init,
661 };
662
663 #define TYPE_TCX_AFX "tcx_afx"
664 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
665
666 typedef struct AFXState {
667 SysBusDevice parent_obj;
668
669 MemoryRegion mem;
670 } AFXState;
671
672 /* SS-5 TCX AFX register */
673 static void afx_init(hwaddr addr)
674 {
675 DeviceState *dev;
676 SysBusDevice *s;
677
678 dev = qdev_create(NULL, TYPE_TCX_AFX);
679 qdev_init_nofail(dev);
680 s = SYS_BUS_DEVICE(dev);
681
682 sysbus_mmio_map(s, 0, addr);
683 }
684
685 static int afx_init1(SysBusDevice *dev)
686 {
687 AFXState *s = TCX_AFX(dev);
688
689 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_abort);
690 vmstate_register_ram_global(&s->mem);
691 sysbus_init_mmio(dev, &s->mem);
692 return 0;
693 }
694
695 static void afx_class_init(ObjectClass *klass, void *data)
696 {
697 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
698
699 k->init = afx_init1;
700 }
701
702 static const TypeInfo afx_info = {
703 .name = TYPE_TCX_AFX,
704 .parent = TYPE_SYS_BUS_DEVICE,
705 .instance_size = sizeof(AFXState),
706 .class_init = afx_class_init,
707 };
708
709 #define TYPE_OPENPROM "openprom"
710 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
711
712 typedef struct PROMState {
713 SysBusDevice parent_obj;
714
715 MemoryRegion prom;
716 } PROMState;
717
718 /* Boot PROM (OpenBIOS) */
719 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
720 {
721 hwaddr *base_addr = (hwaddr *)opaque;
722 return addr + *base_addr - PROM_VADDR;
723 }
724
725 static void prom_init(hwaddr addr, const char *bios_name)
726 {
727 DeviceState *dev;
728 SysBusDevice *s;
729 char *filename;
730 int ret;
731
732 dev = qdev_create(NULL, TYPE_OPENPROM);
733 qdev_init_nofail(dev);
734 s = SYS_BUS_DEVICE(dev);
735
736 sysbus_mmio_map(s, 0, addr);
737
738 /* load boot prom */
739 if (bios_name == NULL) {
740 bios_name = PROM_FILENAME;
741 }
742 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
743 if (filename) {
744 ret = load_elf(filename, translate_prom_address, &addr, NULL,
745 NULL, NULL, 1, ELF_MACHINE, 0);
746 if (ret < 0 || ret > PROM_SIZE_MAX) {
747 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
748 }
749 g_free(filename);
750 } else {
751 ret = -1;
752 }
753 if (ret < 0 || ret > PROM_SIZE_MAX) {
754 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
755 exit(1);
756 }
757 }
758
759 static int prom_init1(SysBusDevice *dev)
760 {
761 PROMState *s = OPENPROM(dev);
762
763 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
764 &error_abort);
765 vmstate_register_ram_global(&s->prom);
766 memory_region_set_readonly(&s->prom, true);
767 sysbus_init_mmio(dev, &s->prom);
768 return 0;
769 }
770
771 static Property prom_properties[] = {
772 {/* end of property list */},
773 };
774
775 static void prom_class_init(ObjectClass *klass, void *data)
776 {
777 DeviceClass *dc = DEVICE_CLASS(klass);
778 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
779
780 k->init = prom_init1;
781 dc->props = prom_properties;
782 }
783
784 static const TypeInfo prom_info = {
785 .name = TYPE_OPENPROM,
786 .parent = TYPE_SYS_BUS_DEVICE,
787 .instance_size = sizeof(PROMState),
788 .class_init = prom_class_init,
789 };
790
791 #define TYPE_SUN4M_MEMORY "memory"
792 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
793
794 typedef struct RamDevice {
795 SysBusDevice parent_obj;
796
797 MemoryRegion ram;
798 uint64_t size;
799 } RamDevice;
800
801 /* System RAM */
802 static int ram_init1(SysBusDevice *dev)
803 {
804 RamDevice *d = SUN4M_RAM(dev);
805
806 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size,
807 &error_abort);
808 vmstate_register_ram_global(&d->ram);
809 sysbus_init_mmio(dev, &d->ram);
810 return 0;
811 }
812
813 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
814 uint64_t max_mem)
815 {
816 DeviceState *dev;
817 SysBusDevice *s;
818 RamDevice *d;
819
820 /* allocate RAM */
821 if ((uint64_t)RAM_size > max_mem) {
822 fprintf(stderr,
823 "qemu: Too much memory for this machine: %d, maximum %d\n",
824 (unsigned int)(RAM_size / (1024 * 1024)),
825 (unsigned int)(max_mem / (1024 * 1024)));
826 exit(1);
827 }
828 dev = qdev_create(NULL, "memory");
829 s = SYS_BUS_DEVICE(dev);
830
831 d = SUN4M_RAM(dev);
832 d->size = RAM_size;
833 qdev_init_nofail(dev);
834
835 sysbus_mmio_map(s, 0, addr);
836 }
837
838 static Property ram_properties[] = {
839 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
840 DEFINE_PROP_END_OF_LIST(),
841 };
842
843 static void ram_class_init(ObjectClass *klass, void *data)
844 {
845 DeviceClass *dc = DEVICE_CLASS(klass);
846 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
847
848 k->init = ram_init1;
849 dc->props = ram_properties;
850 }
851
852 static const TypeInfo ram_info = {
853 .name = TYPE_SUN4M_MEMORY,
854 .parent = TYPE_SYS_BUS_DEVICE,
855 .instance_size = sizeof(RamDevice),
856 .class_init = ram_class_init,
857 };
858
859 static void cpu_devinit(const char *cpu_model, unsigned int id,
860 uint64_t prom_addr, qemu_irq **cpu_irqs)
861 {
862 CPUState *cs;
863 SPARCCPU *cpu;
864 CPUSPARCState *env;
865
866 cpu = cpu_sparc_init(cpu_model);
867 if (cpu == NULL) {
868 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
869 exit(1);
870 }
871 env = &cpu->env;
872
873 cpu_sparc_set_id(env, id);
874 if (id == 0) {
875 qemu_register_reset(main_cpu_reset, cpu);
876 } else {
877 qemu_register_reset(secondary_cpu_reset, cpu);
878 cs = CPU(cpu);
879 cs->halted = 1;
880 }
881 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
882 env->prom_addr = prom_addr;
883 }
884
885 static void dummy_fdc_tc(void *opaque, int irq, int level)
886 {
887 }
888
889 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
890 MachineState *machine)
891 {
892 const char *cpu_model = machine->cpu_model;
893 unsigned int i;
894 void *iommu, *espdma, *ledma, *nvram;
895 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
896 espdma_irq, ledma_irq;
897 qemu_irq esp_reset, dma_enable;
898 qemu_irq fdc_tc;
899 qemu_irq *cpu_halt;
900 unsigned long kernel_size;
901 DriveInfo *fd[MAX_FD];
902 FWCfgState *fw_cfg;
903 unsigned int num_vsimms;
904
905 /* init CPUs */
906 if (!cpu_model)
907 cpu_model = hwdef->default_cpu_model;
908
909 for(i = 0; i < smp_cpus; i++) {
910 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
911 }
912
913 for (i = smp_cpus; i < MAX_CPUS; i++)
914 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
915
916
917 /* set up devices */
918 ram_init(0, machine->ram_size, hwdef->max_mem);
919 /* models without ECC don't trap when missing ram is accessed */
920 if (!hwdef->ecc_base) {
921 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
922 }
923
924 prom_init(hwdef->slavio_base, bios_name);
925
926 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
927 hwdef->intctl_base + 0x10000ULL,
928 cpu_irqs);
929
930 for (i = 0; i < 32; i++) {
931 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
932 }
933 for (i = 0; i < MAX_CPUS; i++) {
934 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
935 }
936
937 if (hwdef->idreg_base) {
938 idreg_init(hwdef->idreg_base);
939 }
940
941 if (hwdef->afx_base) {
942 afx_init(hwdef->afx_base);
943 }
944
945 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
946 slavio_irq[30]);
947
948 if (hwdef->iommu_pad_base) {
949 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
950 Software shouldn't use aliased addresses, neither should it crash
951 when does. Using empty_slot instead of aliasing can help with
952 debugging such accesses */
953 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
954 }
955
956 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
957 iommu, &espdma_irq, 0);
958
959 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
960 slavio_irq[16], iommu, &ledma_irq, 1);
961
962 if (graphic_depth != 8 && graphic_depth != 24) {
963 error_report("Unsupported depth: %d", graphic_depth);
964 exit (1);
965 }
966 num_vsimms = 0;
967 if (num_vsimms == 0) {
968 if (vga_interface_type == VGA_CG3) {
969 if (graphic_depth != 8) {
970 error_report("Unsupported depth: %d", graphic_depth);
971 exit(1);
972 }
973
974 if (!(graphic_width == 1024 && graphic_height == 768) &&
975 !(graphic_width == 1152 && graphic_height == 900)) {
976 error_report("Unsupported resolution: %d x %d", graphic_width,
977 graphic_height);
978 exit(1);
979 }
980
981 /* sbus irq 5 */
982 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
983 graphic_width, graphic_height, graphic_depth);
984 } else {
985 /* If no display specified, default to TCX */
986 if (graphic_depth != 8 && graphic_depth != 24) {
987 error_report("Unsupported depth: %d", graphic_depth);
988 exit(1);
989 }
990
991 if (!(graphic_width == 1024 && graphic_height == 768)) {
992 error_report("Unsupported resolution: %d x %d",
993 graphic_width, graphic_height);
994 exit(1);
995 }
996
997 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
998 graphic_width, graphic_height, graphic_depth);
999 }
1000 }
1001
1002 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
1003 /* vsimm registers probed by OBP */
1004 if (hwdef->vsimm[i].reg_base) {
1005 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
1006 }
1007 }
1008
1009 if (hwdef->sx_base) {
1010 empty_slot_init(hwdef->sx_base, 0x2000);
1011 }
1012
1013 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1014
1015 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1016
1017 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1018
1019 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1020 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1021 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1022 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1023 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1024 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1025
1026 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1027 if (hwdef->apc_base) {
1028 apc_init(hwdef->apc_base, cpu_halt[0]);
1029 }
1030
1031 if (hwdef->fd_base) {
1032 /* there is zero or one floppy drive */
1033 memset(fd, 0, sizeof(fd));
1034 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1035 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1036 &fdc_tc);
1037 } else {
1038 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1039 }
1040
1041 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1042 slavio_irq[30], fdc_tc);
1043
1044 if (drive_get_max_bus(IF_SCSI) > 0) {
1045 fprintf(stderr, "qemu: too many SCSI bus\n");
1046 exit(1);
1047 }
1048
1049 esp_init(hwdef->esp_base, 2,
1050 espdma_memory_read, espdma_memory_write,
1051 espdma, espdma_irq, &esp_reset, &dma_enable);
1052
1053 qdev_connect_gpio_out(espdma, 0, esp_reset);
1054 qdev_connect_gpio_out(espdma, 1, dma_enable);
1055
1056 if (hwdef->cs_base) {
1057 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1058 slavio_irq[5]);
1059 }
1060
1061 if (hwdef->dbri_base) {
1062 /* ISDN chip with attached CS4215 audio codec */
1063 /* prom space */
1064 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1065 /* reg space */
1066 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1067 }
1068
1069 if (hwdef->bpp_base) {
1070 /* parallel port */
1071 empty_slot_init(hwdef->bpp_base, 0x20);
1072 }
1073
1074 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1075 machine->initrd_filename,
1076 machine->ram_size);
1077
1078 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1079 machine->boot_order, machine->ram_size, kernel_size,
1080 graphic_width, graphic_height, graphic_depth,
1081 hwdef->nvram_machine_id, "Sun4m");
1082
1083 if (hwdef->ecc_base)
1084 ecc_init(hwdef->ecc_base, slavio_irq[28],
1085 hwdef->ecc_version);
1086
1087 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1088 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1089 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1090 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1091 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1093 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1094 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1095 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1096 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1097 if (machine->kernel_cmdline) {
1098 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1099 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1100 machine->kernel_cmdline);
1101 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1102 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1103 strlen(machine->kernel_cmdline) + 1);
1104 } else {
1105 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1106 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1107 }
1108 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1109 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1110 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1111 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1112 }
1113
1114 enum {
1115 ss5_id = 32,
1116 vger_id,
1117 lx_id,
1118 ss4_id,
1119 scls_id,
1120 sbook_id,
1121 ss10_id = 64,
1122 ss20_id,
1123 ss600mp_id,
1124 };
1125
1126 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1127 /* SS-5 */
1128 {
1129 .iommu_base = 0x10000000,
1130 .iommu_pad_base = 0x10004000,
1131 .iommu_pad_len = 0x0fffb000,
1132 .tcx_base = 0x50000000,
1133 .cs_base = 0x6c000000,
1134 .slavio_base = 0x70000000,
1135 .ms_kb_base = 0x71000000,
1136 .serial_base = 0x71100000,
1137 .nvram_base = 0x71200000,
1138 .fd_base = 0x71400000,
1139 .counter_base = 0x71d00000,
1140 .intctl_base = 0x71e00000,
1141 .idreg_base = 0x78000000,
1142 .dma_base = 0x78400000,
1143 .esp_base = 0x78800000,
1144 .le_base = 0x78c00000,
1145 .apc_base = 0x6a000000,
1146 .afx_base = 0x6e000000,
1147 .aux1_base = 0x71900000,
1148 .aux2_base = 0x71910000,
1149 .nvram_machine_id = 0x80,
1150 .machine_id = ss5_id,
1151 .iommu_version = 0x05000000,
1152 .max_mem = 0x10000000,
1153 .default_cpu_model = "Fujitsu MB86904",
1154 },
1155 /* SS-10 */
1156 {
1157 .iommu_base = 0xfe0000000ULL,
1158 .tcx_base = 0xe20000000ULL,
1159 .slavio_base = 0xff0000000ULL,
1160 .ms_kb_base = 0xff1000000ULL,
1161 .serial_base = 0xff1100000ULL,
1162 .nvram_base = 0xff1200000ULL,
1163 .fd_base = 0xff1700000ULL,
1164 .counter_base = 0xff1300000ULL,
1165 .intctl_base = 0xff1400000ULL,
1166 .idreg_base = 0xef0000000ULL,
1167 .dma_base = 0xef0400000ULL,
1168 .esp_base = 0xef0800000ULL,
1169 .le_base = 0xef0c00000ULL,
1170 .apc_base = 0xefa000000ULL, // XXX should not exist
1171 .aux1_base = 0xff1800000ULL,
1172 .aux2_base = 0xff1a01000ULL,
1173 .ecc_base = 0xf00000000ULL,
1174 .ecc_version = 0x10000000, // version 0, implementation 1
1175 .nvram_machine_id = 0x72,
1176 .machine_id = ss10_id,
1177 .iommu_version = 0x03000000,
1178 .max_mem = 0xf00000000ULL,
1179 .default_cpu_model = "TI SuperSparc II",
1180 },
1181 /* SS-600MP */
1182 {
1183 .iommu_base = 0xfe0000000ULL,
1184 .tcx_base = 0xe20000000ULL,
1185 .slavio_base = 0xff0000000ULL,
1186 .ms_kb_base = 0xff1000000ULL,
1187 .serial_base = 0xff1100000ULL,
1188 .nvram_base = 0xff1200000ULL,
1189 .counter_base = 0xff1300000ULL,
1190 .intctl_base = 0xff1400000ULL,
1191 .dma_base = 0xef0081000ULL,
1192 .esp_base = 0xef0080000ULL,
1193 .le_base = 0xef0060000ULL,
1194 .apc_base = 0xefa000000ULL, // XXX should not exist
1195 .aux1_base = 0xff1800000ULL,
1196 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1197 .ecc_base = 0xf00000000ULL,
1198 .ecc_version = 0x00000000, // version 0, implementation 0
1199 .nvram_machine_id = 0x71,
1200 .machine_id = ss600mp_id,
1201 .iommu_version = 0x01000000,
1202 .max_mem = 0xf00000000ULL,
1203 .default_cpu_model = "TI SuperSparc II",
1204 },
1205 /* SS-20 */
1206 {
1207 .iommu_base = 0xfe0000000ULL,
1208 .tcx_base = 0xe20000000ULL,
1209 .slavio_base = 0xff0000000ULL,
1210 .ms_kb_base = 0xff1000000ULL,
1211 .serial_base = 0xff1100000ULL,
1212 .nvram_base = 0xff1200000ULL,
1213 .fd_base = 0xff1700000ULL,
1214 .counter_base = 0xff1300000ULL,
1215 .intctl_base = 0xff1400000ULL,
1216 .idreg_base = 0xef0000000ULL,
1217 .dma_base = 0xef0400000ULL,
1218 .esp_base = 0xef0800000ULL,
1219 .le_base = 0xef0c00000ULL,
1220 .bpp_base = 0xef4800000ULL,
1221 .apc_base = 0xefa000000ULL, // XXX should not exist
1222 .aux1_base = 0xff1800000ULL,
1223 .aux2_base = 0xff1a01000ULL,
1224 .dbri_base = 0xee0000000ULL,
1225 .sx_base = 0xf80000000ULL,
1226 .vsimm = {
1227 {
1228 .reg_base = 0x9c000000ULL,
1229 .vram_base = 0xfc000000ULL
1230 }, {
1231 .reg_base = 0x90000000ULL,
1232 .vram_base = 0xf0000000ULL
1233 }, {
1234 .reg_base = 0x94000000ULL
1235 }, {
1236 .reg_base = 0x98000000ULL
1237 }
1238 },
1239 .ecc_base = 0xf00000000ULL,
1240 .ecc_version = 0x20000000, // version 0, implementation 2
1241 .nvram_machine_id = 0x72,
1242 .machine_id = ss20_id,
1243 .iommu_version = 0x13000000,
1244 .max_mem = 0xf00000000ULL,
1245 .default_cpu_model = "TI SuperSparc II",
1246 },
1247 /* Voyager */
1248 {
1249 .iommu_base = 0x10000000,
1250 .tcx_base = 0x50000000,
1251 .slavio_base = 0x70000000,
1252 .ms_kb_base = 0x71000000,
1253 .serial_base = 0x71100000,
1254 .nvram_base = 0x71200000,
1255 .fd_base = 0x71400000,
1256 .counter_base = 0x71d00000,
1257 .intctl_base = 0x71e00000,
1258 .idreg_base = 0x78000000,
1259 .dma_base = 0x78400000,
1260 .esp_base = 0x78800000,
1261 .le_base = 0x78c00000,
1262 .apc_base = 0x71300000, // pmc
1263 .aux1_base = 0x71900000,
1264 .aux2_base = 0x71910000,
1265 .nvram_machine_id = 0x80,
1266 .machine_id = vger_id,
1267 .iommu_version = 0x05000000,
1268 .max_mem = 0x10000000,
1269 .default_cpu_model = "Fujitsu MB86904",
1270 },
1271 /* LX */
1272 {
1273 .iommu_base = 0x10000000,
1274 .iommu_pad_base = 0x10004000,
1275 .iommu_pad_len = 0x0fffb000,
1276 .tcx_base = 0x50000000,
1277 .slavio_base = 0x70000000,
1278 .ms_kb_base = 0x71000000,
1279 .serial_base = 0x71100000,
1280 .nvram_base = 0x71200000,
1281 .fd_base = 0x71400000,
1282 .counter_base = 0x71d00000,
1283 .intctl_base = 0x71e00000,
1284 .idreg_base = 0x78000000,
1285 .dma_base = 0x78400000,
1286 .esp_base = 0x78800000,
1287 .le_base = 0x78c00000,
1288 .aux1_base = 0x71900000,
1289 .aux2_base = 0x71910000,
1290 .nvram_machine_id = 0x80,
1291 .machine_id = lx_id,
1292 .iommu_version = 0x04000000,
1293 .max_mem = 0x10000000,
1294 .default_cpu_model = "TI MicroSparc I",
1295 },
1296 /* SS-4 */
1297 {
1298 .iommu_base = 0x10000000,
1299 .tcx_base = 0x50000000,
1300 .cs_base = 0x6c000000,
1301 .slavio_base = 0x70000000,
1302 .ms_kb_base = 0x71000000,
1303 .serial_base = 0x71100000,
1304 .nvram_base = 0x71200000,
1305 .fd_base = 0x71400000,
1306 .counter_base = 0x71d00000,
1307 .intctl_base = 0x71e00000,
1308 .idreg_base = 0x78000000,
1309 .dma_base = 0x78400000,
1310 .esp_base = 0x78800000,
1311 .le_base = 0x78c00000,
1312 .apc_base = 0x6a000000,
1313 .aux1_base = 0x71900000,
1314 .aux2_base = 0x71910000,
1315 .nvram_machine_id = 0x80,
1316 .machine_id = ss4_id,
1317 .iommu_version = 0x05000000,
1318 .max_mem = 0x10000000,
1319 .default_cpu_model = "Fujitsu MB86904",
1320 },
1321 /* SPARCClassic */
1322 {
1323 .iommu_base = 0x10000000,
1324 .tcx_base = 0x50000000,
1325 .slavio_base = 0x70000000,
1326 .ms_kb_base = 0x71000000,
1327 .serial_base = 0x71100000,
1328 .nvram_base = 0x71200000,
1329 .fd_base = 0x71400000,
1330 .counter_base = 0x71d00000,
1331 .intctl_base = 0x71e00000,
1332 .idreg_base = 0x78000000,
1333 .dma_base = 0x78400000,
1334 .esp_base = 0x78800000,
1335 .le_base = 0x78c00000,
1336 .apc_base = 0x6a000000,
1337 .aux1_base = 0x71900000,
1338 .aux2_base = 0x71910000,
1339 .nvram_machine_id = 0x80,
1340 .machine_id = scls_id,
1341 .iommu_version = 0x05000000,
1342 .max_mem = 0x10000000,
1343 .default_cpu_model = "TI MicroSparc I",
1344 },
1345 /* SPARCbook */
1346 {
1347 .iommu_base = 0x10000000,
1348 .tcx_base = 0x50000000, // XXX
1349 .slavio_base = 0x70000000,
1350 .ms_kb_base = 0x71000000,
1351 .serial_base = 0x71100000,
1352 .nvram_base = 0x71200000,
1353 .fd_base = 0x71400000,
1354 .counter_base = 0x71d00000,
1355 .intctl_base = 0x71e00000,
1356 .idreg_base = 0x78000000,
1357 .dma_base = 0x78400000,
1358 .esp_base = 0x78800000,
1359 .le_base = 0x78c00000,
1360 .apc_base = 0x6a000000,
1361 .aux1_base = 0x71900000,
1362 .aux2_base = 0x71910000,
1363 .nvram_machine_id = 0x80,
1364 .machine_id = sbook_id,
1365 .iommu_version = 0x05000000,
1366 .max_mem = 0x10000000,
1367 .default_cpu_model = "TI MicroSparc I",
1368 },
1369 };
1370
1371 /* SPARCstation 5 hardware initialisation */
1372 static void ss5_init(MachineState *machine)
1373 {
1374 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1375 }
1376
1377 /* SPARCstation 10 hardware initialisation */
1378 static void ss10_init(MachineState *machine)
1379 {
1380 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1381 }
1382
1383 /* SPARCserver 600MP hardware initialisation */
1384 static void ss600mp_init(MachineState *machine)
1385 {
1386 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1387 }
1388
1389 /* SPARCstation 20 hardware initialisation */
1390 static void ss20_init(MachineState *machine)
1391 {
1392 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1393 }
1394
1395 /* SPARCstation Voyager hardware initialisation */
1396 static void vger_init(MachineState *machine)
1397 {
1398 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1399 }
1400
1401 /* SPARCstation LX hardware initialisation */
1402 static void ss_lx_init(MachineState *machine)
1403 {
1404 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1405 }
1406
1407 /* SPARCstation 4 hardware initialisation */
1408 static void ss4_init(MachineState *machine)
1409 {
1410 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1411 }
1412
1413 /* SPARCClassic hardware initialisation */
1414 static void scls_init(MachineState *machine)
1415 {
1416 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1417 }
1418
1419 /* SPARCbook hardware initialisation */
1420 static void sbook_init(MachineState *machine)
1421 {
1422 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1423 }
1424
1425 static QEMUMachine ss5_machine = {
1426 .name = "SS-5",
1427 .desc = "Sun4m platform, SPARCstation 5",
1428 .init = ss5_init,
1429 .block_default_type = IF_SCSI,
1430 .is_default = 1,
1431 .default_boot_order = "c",
1432 };
1433
1434 static QEMUMachine ss10_machine = {
1435 .name = "SS-10",
1436 .desc = "Sun4m platform, SPARCstation 10",
1437 .init = ss10_init,
1438 .block_default_type = IF_SCSI,
1439 .max_cpus = 4,
1440 .default_boot_order = "c",
1441 };
1442
1443 static QEMUMachine ss600mp_machine = {
1444 .name = "SS-600MP",
1445 .desc = "Sun4m platform, SPARCserver 600MP",
1446 .init = ss600mp_init,
1447 .block_default_type = IF_SCSI,
1448 .max_cpus = 4,
1449 .default_boot_order = "c",
1450 };
1451
1452 static QEMUMachine ss20_machine = {
1453 .name = "SS-20",
1454 .desc = "Sun4m platform, SPARCstation 20",
1455 .init = ss20_init,
1456 .block_default_type = IF_SCSI,
1457 .max_cpus = 4,
1458 .default_boot_order = "c",
1459 };
1460
1461 static QEMUMachine voyager_machine = {
1462 .name = "Voyager",
1463 .desc = "Sun4m platform, SPARCstation Voyager",
1464 .init = vger_init,
1465 .block_default_type = IF_SCSI,
1466 .default_boot_order = "c",
1467 };
1468
1469 static QEMUMachine ss_lx_machine = {
1470 .name = "LX",
1471 .desc = "Sun4m platform, SPARCstation LX",
1472 .init = ss_lx_init,
1473 .block_default_type = IF_SCSI,
1474 .default_boot_order = "c",
1475 };
1476
1477 static QEMUMachine ss4_machine = {
1478 .name = "SS-4",
1479 .desc = "Sun4m platform, SPARCstation 4",
1480 .init = ss4_init,
1481 .block_default_type = IF_SCSI,
1482 .default_boot_order = "c",
1483 };
1484
1485 static QEMUMachine scls_machine = {
1486 .name = "SPARCClassic",
1487 .desc = "Sun4m platform, SPARCClassic",
1488 .init = scls_init,
1489 .block_default_type = IF_SCSI,
1490 .default_boot_order = "c",
1491 };
1492
1493 static QEMUMachine sbook_machine = {
1494 .name = "SPARCbook",
1495 .desc = "Sun4m platform, SPARCbook",
1496 .init = sbook_init,
1497 .block_default_type = IF_SCSI,
1498 .default_boot_order = "c",
1499 };
1500
1501 static void sun4m_register_types(void)
1502 {
1503 type_register_static(&idreg_info);
1504 type_register_static(&afx_info);
1505 type_register_static(&prom_info);
1506 type_register_static(&ram_info);
1507 }
1508
1509 static void sun4m_machine_init(void)
1510 {
1511 qemu_register_machine(&ss5_machine);
1512 qemu_register_machine(&ss10_machine);
1513 qemu_register_machine(&ss600mp_machine);
1514 qemu_register_machine(&ss20_machine);
1515 qemu_register_machine(&voyager_machine);
1516 qemu_register_machine(&ss_lx_machine);
1517 qemu_register_machine(&ss4_machine);
1518 qemu_register_machine(&scls_machine);
1519 qemu_register_machine(&sbook_machine);
1520 }
1521
1522 type_init(sun4m_register_types)
1523 machine_init(sun4m_machine_init);
CRIS target port of Qemu