2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/block-backend.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
61 #include "hw/mem/pc-dimm.h"
63 #include "qapi/visitor.h"
64 #include "qapi-visit.h"
66 /* debug PC/ISA interrupts */
70 #define DPRINTF(fmt, ...) \
71 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #define DPRINTF(fmt, ...)
76 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables
77 * (128K) and other BIOS datastructures (less than 4K reported to be used at
78 * the moment, 32K should be enough for a while). */
79 static unsigned acpi_data_size
= 0x20000 + 0x8000;
80 void pc_set_legacy_acpi_data_size(void)
82 acpi_data_size
= 0x10000;
85 #define BIOS_CFG_IOPORT 0x510
86 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
87 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
88 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
89 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
90 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
92 #define E820_NR_ENTRIES 16
98 } QEMU_PACKED
__attribute((__aligned__(4)));
102 struct e820_entry entry
[E820_NR_ENTRIES
];
103 } QEMU_PACKED
__attribute((__aligned__(4)));
105 static struct e820_table e820_reserve
;
106 static struct e820_entry
*e820_table
;
107 static unsigned e820_entries
;
108 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
110 void gsi_handler(void *opaque
, int n
, int level
)
112 GSIState
*s
= opaque
;
114 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
115 if (n
< ISA_NUM_IRQS
) {
116 qemu_set_irq(s
->i8259_irq
[n
], level
);
118 qemu_set_irq(s
->ioapic_irq
[n
], level
);
121 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
126 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
128 return 0xffffffffffffffffULL
;
131 /* MSDOS compatibility mode FPU exception support */
132 static qemu_irq ferr_irq
;
134 void pc_register_ferr_irq(qemu_irq irq
)
139 /* XXX: add IGNNE support */
140 void cpu_set_ferr(CPUX86State
*s
)
142 qemu_irq_raise(ferr_irq
);
145 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
148 qemu_irq_lower(ferr_irq
);
151 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
153 return 0xffffffffffffffffULL
;
157 uint64_t cpu_get_tsc(CPUX86State
*env
)
159 return cpu_get_ticks();
164 static cpu_set_smm_t smm_set
;
165 static void *smm_arg
;
167 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
169 assert(smm_set
== NULL
);
170 assert(smm_arg
== NULL
);
175 void cpu_smm_update(CPUX86State
*env
)
177 if (smm_set
&& smm_arg
&& CPU(x86_env_get_cpu(env
)) == first_cpu
) {
178 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
184 int cpu_get_pic_interrupt(CPUX86State
*env
)
186 X86CPU
*cpu
= x86_env_get_cpu(env
);
189 intno
= apic_get_interrupt(cpu
->apic_state
);
193 /* read the irq from the PIC */
194 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
198 intno
= pic_read_irq(isa_pic
);
202 static void pic_irq_request(void *opaque
, int irq
, int level
)
204 CPUState
*cs
= first_cpu
;
205 X86CPU
*cpu
= X86_CPU(cs
);
207 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
208 if (cpu
->apic_state
) {
211 if (apic_accept_pic_intr(cpu
->apic_state
)) {
212 apic_deliver_pic_intr(cpu
->apic_state
, level
);
217 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
219 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
224 /* PC cmos mappings */
226 #define REG_EQUIPMENT_BYTE 0x14
228 static int cmos_get_fd_drive_type(FDriveType fd0
)
234 /* 1.44 Mb 3"5 drive */
238 /* 2.88 Mb 3"5 drive */
242 /* 1.2 Mb 5"5 drive */
245 case FDRIVE_DRV_NONE
:
253 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
254 int16_t cylinders
, int8_t heads
, int8_t sectors
)
256 rtc_set_memory(s
, type_ofs
, 47);
257 rtc_set_memory(s
, info_ofs
, cylinders
);
258 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
259 rtc_set_memory(s
, info_ofs
+ 2, heads
);
260 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
261 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
262 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
263 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
264 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
265 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
268 /* convert boot_device letter to something recognizable by the bios */
269 static int boot_device2nibble(char boot_device
)
271 switch(boot_device
) {
274 return 0x01; /* floppy boot */
276 return 0x02; /* hard drive boot */
278 return 0x03; /* CD-ROM boot */
280 return 0x04; /* Network boot */
285 static int set_boot_dev(ISADevice
*s
, const char *boot_device
)
287 #define PC_MAX_BOOT_DEVICES 3
288 int nbds
, bds
[3] = { 0, };
291 nbds
= strlen(boot_device
);
292 if (nbds
> PC_MAX_BOOT_DEVICES
) {
293 error_report("Too many boot devices for PC");
296 for (i
= 0; i
< nbds
; i
++) {
297 bds
[i
] = boot_device2nibble(boot_device
[i
]);
299 error_report("Invalid boot device for PC: '%c'",
304 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
305 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
309 static int pc_boot_set(void *opaque
, const char *boot_device
)
311 return set_boot_dev(opaque
, boot_device
);
314 typedef struct pc_cmos_init_late_arg
{
315 ISADevice
*rtc_state
;
317 } pc_cmos_init_late_arg
;
319 static void pc_cmos_init_late(void *opaque
)
321 pc_cmos_init_late_arg
*arg
= opaque
;
322 ISADevice
*s
= arg
->rtc_state
;
324 int8_t heads
, sectors
;
329 if (ide_get_geometry(arg
->idebus
[0], 0,
330 &cylinders
, &heads
, §ors
) >= 0) {
331 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
334 if (ide_get_geometry(arg
->idebus
[0], 1,
335 &cylinders
, &heads
, §ors
) >= 0) {
336 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
339 rtc_set_memory(s
, 0x12, val
);
342 for (i
= 0; i
< 4; i
++) {
343 /* NOTE: ide_get_geometry() returns the physical
344 geometry. It is always such that: 1 <= sects <= 63, 1
345 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
346 geometry can be different if a translation is done. */
347 if (ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
348 &cylinders
, &heads
, §ors
) >= 0) {
349 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
350 assert((trans
& ~3) == 0);
351 val
|= trans
<< (i
* 2);
354 rtc_set_memory(s
, 0x39, val
);
356 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
359 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
360 const char *boot_device
, MachineState
*machine
,
361 ISADevice
*floppy
, BusState
*idebus0
, BusState
*idebus1
,
365 FDriveType fd_type
[2] = { FDRIVE_DRV_NONE
, FDRIVE_DRV_NONE
};
366 static pc_cmos_init_late_arg arg
;
367 PCMachineState
*pc_machine
= PC_MACHINE(machine
);
369 /* various important CMOS locations needed by PC/Bochs bios */
372 /* base memory (first MiB) */
373 val
= MIN(ram_size
/ 1024, 640);
374 rtc_set_memory(s
, 0x15, val
);
375 rtc_set_memory(s
, 0x16, val
>> 8);
376 /* extended memory (next 64MiB) */
377 if (ram_size
> 1024 * 1024) {
378 val
= (ram_size
- 1024 * 1024) / 1024;
384 rtc_set_memory(s
, 0x17, val
);
385 rtc_set_memory(s
, 0x18, val
>> 8);
386 rtc_set_memory(s
, 0x30, val
);
387 rtc_set_memory(s
, 0x31, val
>> 8);
388 /* memory between 16MiB and 4GiB */
389 if (ram_size
> 16 * 1024 * 1024) {
390 val
= (ram_size
- 16 * 1024 * 1024) / 65536;
396 rtc_set_memory(s
, 0x34, val
);
397 rtc_set_memory(s
, 0x35, val
>> 8);
398 /* memory above 4GiB */
399 val
= above_4g_mem_size
/ 65536;
400 rtc_set_memory(s
, 0x5b, val
);
401 rtc_set_memory(s
, 0x5c, val
>> 8);
402 rtc_set_memory(s
, 0x5d, val
>> 16);
404 /* set the number of CPU */
405 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
407 object_property_add_link(OBJECT(machine
), "rtc_state",
409 (Object
**)&pc_machine
->rtc
,
410 object_property_allow_set_link
,
411 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
412 object_property_set_link(OBJECT(machine
), OBJECT(s
),
413 "rtc_state", &error_abort
);
415 if (set_boot_dev(s
, boot_device
)) {
421 for (i
= 0; i
< 2; i
++) {
422 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
425 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
426 cmos_get_fd_drive_type(fd_type
[1]);
427 rtc_set_memory(s
, 0x10, val
);
431 if (fd_type
[0] < FDRIVE_DRV_NONE
) {
434 if (fd_type
[1] < FDRIVE_DRV_NONE
) {
441 val
|= 0x01; /* 1 drive, ready for boot */
444 val
|= 0x41; /* 2 drives, ready for boot */
447 val
|= 0x02; /* FPU is there */
448 val
|= 0x04; /* PS/2 mouse installed */
449 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
453 arg
.idebus
[0] = idebus0
;
454 arg
.idebus
[1] = idebus1
;
455 qemu_register_reset(pc_cmos_init_late
, &arg
);
458 #define TYPE_PORT92 "port92"
459 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
461 /* port 92 stuff: could be split off */
462 typedef struct Port92State
{
463 ISADevice parent_obj
;
470 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
473 Port92State
*s
= opaque
;
474 int oldval
= s
->outport
;
476 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
478 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
479 if ((val
& 1) && !(oldval
& 1)) {
480 qemu_system_reset_request();
484 static uint64_t port92_read(void *opaque
, hwaddr addr
,
487 Port92State
*s
= opaque
;
491 DPRINTF("port92: read 0x%02x\n", ret
);
495 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
497 Port92State
*s
= PORT92(dev
);
499 s
->a20_out
= a20_out
;
502 static const VMStateDescription vmstate_port92_isa
= {
505 .minimum_version_id
= 1,
506 .fields
= (VMStateField
[]) {
507 VMSTATE_UINT8(outport
, Port92State
),
508 VMSTATE_END_OF_LIST()
512 static void port92_reset(DeviceState
*d
)
514 Port92State
*s
= PORT92(d
);
519 static const MemoryRegionOps port92_ops
= {
521 .write
= port92_write
,
523 .min_access_size
= 1,
524 .max_access_size
= 1,
526 .endianness
= DEVICE_LITTLE_ENDIAN
,
529 static void port92_initfn(Object
*obj
)
531 Port92State
*s
= PORT92(obj
);
533 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
538 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
540 ISADevice
*isadev
= ISA_DEVICE(dev
);
541 Port92State
*s
= PORT92(dev
);
543 isa_register_ioport(isadev
, &s
->io
, 0x92);
546 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
548 DeviceClass
*dc
= DEVICE_CLASS(klass
);
550 dc
->realize
= port92_realizefn
;
551 dc
->reset
= port92_reset
;
552 dc
->vmsd
= &vmstate_port92_isa
;
554 * Reason: unlike ordinary ISA devices, this one needs additional
555 * wiring: its A20 output line needs to be wired up by
558 dc
->cannot_instantiate_with_device_add_yet
= true;
561 static const TypeInfo port92_info
= {
563 .parent
= TYPE_ISA_DEVICE
,
564 .instance_size
= sizeof(Port92State
),
565 .instance_init
= port92_initfn
,
566 .class_init
= port92_class_initfn
,
569 static void port92_register_types(void)
571 type_register_static(&port92_info
);
574 type_init(port92_register_types
)
576 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
578 X86CPU
*cpu
= opaque
;
580 /* XXX: send to all CPUs ? */
581 /* XXX: add logic to handle multiple A20 line sources */
582 x86_cpu_set_a20(cpu
, level
);
585 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
587 int index
= le32_to_cpu(e820_reserve
.count
);
588 struct e820_entry
*entry
;
590 if (type
!= E820_RAM
) {
591 /* old FW_CFG_E820_TABLE entry -- reservations only */
592 if (index
>= E820_NR_ENTRIES
) {
595 entry
= &e820_reserve
.entry
[index
++];
597 entry
->address
= cpu_to_le64(address
);
598 entry
->length
= cpu_to_le64(length
);
599 entry
->type
= cpu_to_le32(type
);
601 e820_reserve
.count
= cpu_to_le32(index
);
604 /* new "etc/e820" file -- include ram too */
605 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
606 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
607 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
608 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
614 int e820_get_num_entries(void)
619 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
621 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
622 *address
= le64_to_cpu(e820_table
[idx
].address
);
623 *length
= le64_to_cpu(e820_table
[idx
].length
);
629 /* Calculates the limit to CPU APIC ID values
631 * This function returns the limit for the APIC ID value, so that all
632 * CPU APIC IDs are < pc_apic_id_limit().
634 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
636 static unsigned int pc_apic_id_limit(unsigned int max_cpus
)
638 return x86_cpu_apic_id_from_index(max_cpus
- 1) + 1;
641 static FWCfgState
*bochs_bios_init(void)
644 uint8_t *smbios_tables
, *smbios_anchor
;
645 size_t smbios_tables_len
, smbios_anchor_len
;
646 uint64_t *numa_fw_cfg
;
648 unsigned int apic_id_limit
= pc_apic_id_limit(max_cpus
);
650 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
651 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
653 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
654 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
655 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
656 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
659 * So, this means we must not use max_cpus, here, but the maximum possible
660 * APIC ID value, plus one.
662 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
663 * the APIC ID, not the "CPU index"
665 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)apic_id_limit
);
666 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
667 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
668 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
669 acpi_tables
, acpi_tables_len
);
670 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
672 smbios_tables
= smbios_get_table_legacy(&smbios_tables_len
);
674 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
675 smbios_tables
, smbios_tables_len
);
678 smbios_get_tables(&smbios_tables
, &smbios_tables_len
,
679 &smbios_anchor
, &smbios_anchor_len
);
681 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
682 smbios_tables
, smbios_tables_len
);
683 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
684 smbios_anchor
, smbios_anchor_len
);
687 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
688 &e820_reserve
, sizeof(e820_reserve
));
689 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
690 sizeof(struct e820_entry
) * e820_entries
);
692 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
693 /* allocate memory for the NUMA channel: one (64bit) word for the number
694 * of nodes, one word for each VCPU->node and one word for each node to
695 * hold the amount of memory.
697 numa_fw_cfg
= g_new0(uint64_t, 1 + apic_id_limit
+ nb_numa_nodes
);
698 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
699 for (i
= 0; i
< max_cpus
; i
++) {
700 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
701 assert(apic_id
< apic_id_limit
);
702 for (j
= 0; j
< nb_numa_nodes
; j
++) {
703 if (test_bit(i
, numa_info
[j
].node_cpu
)) {
704 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(j
);
709 for (i
= 0; i
< nb_numa_nodes
; i
++) {
710 numa_fw_cfg
[apic_id_limit
+ 1 + i
] = cpu_to_le64(numa_info
[i
].node_mem
);
712 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
713 (1 + apic_id_limit
+ nb_numa_nodes
) *
714 sizeof(*numa_fw_cfg
));
719 static long get_file_size(FILE *f
)
723 /* XXX: on Unix systems, using fstat() probably makes more sense */
726 fseek(f
, 0, SEEK_END
);
728 fseek(f
, where
, SEEK_SET
);
733 static void load_linux(FWCfgState
*fw_cfg
,
734 const char *kernel_filename
,
735 const char *initrd_filename
,
736 const char *kernel_cmdline
,
740 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
742 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
743 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
747 /* Align to 16 bytes as a paranoia measure */
748 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
750 /* load the kernel header */
751 f
= fopen(kernel_filename
, "rb");
752 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
753 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
754 MIN(ARRAY_SIZE(header
), kernel_size
)) {
755 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
756 kernel_filename
, strerror(errno
));
760 /* kernel protocol version */
762 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
764 if (ldl_p(header
+0x202) == 0x53726448) {
765 protocol
= lduw_p(header
+0x206);
767 /* This looks like a multiboot kernel. If it is, let's stop
768 treating it like a Linux kernel. */
769 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
770 kernel_cmdline
, kernel_size
, header
)) {
776 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
779 cmdline_addr
= 0x9a000 - cmdline_size
;
781 } else if (protocol
< 0x202) {
782 /* High but ancient kernel */
784 cmdline_addr
= 0x9a000 - cmdline_size
;
785 prot_addr
= 0x100000;
787 /* High and recent kernel */
789 cmdline_addr
= 0x20000;
790 prot_addr
= 0x100000;
795 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
796 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
797 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
803 /* highest address for loading the initrd */
804 if (protocol
>= 0x203) {
805 initrd_max
= ldl_p(header
+0x22c);
807 initrd_max
= 0x37ffffff;
810 if (initrd_max
>= max_ram_size
- acpi_data_size
) {
811 initrd_max
= max_ram_size
- acpi_data_size
- 1;
814 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
815 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
816 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
818 if (protocol
>= 0x202) {
819 stl_p(header
+0x228, cmdline_addr
);
821 stw_p(header
+0x20, 0xA33F);
822 stw_p(header
+0x22, cmdline_addr
-real_addr
);
825 /* handle vga= parameter */
826 vmode
= strstr(kernel_cmdline
, "vga=");
828 unsigned int video_mode
;
831 if (!strncmp(vmode
, "normal", 6)) {
833 } else if (!strncmp(vmode
, "ext", 3)) {
835 } else if (!strncmp(vmode
, "ask", 3)) {
838 video_mode
= strtol(vmode
, NULL
, 0);
840 stw_p(header
+0x1fa, video_mode
);
844 /* High nybble = B reserved for QEMU; low nybble is revision number.
845 If this code is substantially changed, you may want to consider
846 incrementing the revision. */
847 if (protocol
>= 0x200) {
848 header
[0x210] = 0xB0;
851 if (protocol
>= 0x201) {
852 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
853 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
857 if (initrd_filename
) {
858 if (protocol
< 0x200) {
859 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
863 initrd_size
= get_image_size(initrd_filename
);
864 if (initrd_size
< 0) {
865 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
866 initrd_filename
, strerror(errno
));
870 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
872 initrd_data
= g_malloc(initrd_size
);
873 load_image(initrd_filename
, initrd_data
);
875 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
876 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
877 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
879 stl_p(header
+0x218, initrd_addr
);
880 stl_p(header
+0x21c, initrd_size
);
883 /* load kernel and setup */
884 setup_size
= header
[0x1f1];
885 if (setup_size
== 0) {
888 setup_size
= (setup_size
+1)*512;
889 kernel_size
-= setup_size
;
891 setup
= g_malloc(setup_size
);
892 kernel
= g_malloc(kernel_size
);
893 fseek(f
, 0, SEEK_SET
);
894 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
895 fprintf(stderr
, "fread() failed\n");
898 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
899 fprintf(stderr
, "fread() failed\n");
903 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
905 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
906 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
907 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
909 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
910 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
911 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
913 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
914 option_rom
[nb_option_roms
].bootindex
= 0;
918 #define NE2000_NB_MAX 6
920 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
922 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
924 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
926 static int nb_ne2k
= 0;
928 if (nb_ne2k
== NE2000_NB_MAX
)
930 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
931 ne2000_irq
[nb_ne2k
], nd
);
935 DeviceState
*cpu_get_current_apic(void)
938 X86CPU
*cpu
= X86_CPU(current_cpu
);
939 return cpu
->apic_state
;
945 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
947 X86CPU
*cpu
= opaque
;
950 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
954 static X86CPU
*pc_new_cpu(const char *cpu_model
, int64_t apic_id
,
955 DeviceState
*icc_bridge
, Error
**errp
)
958 Error
*local_err
= NULL
;
960 cpu
= cpu_x86_create(cpu_model
, icc_bridge
, &local_err
);
961 if (local_err
!= NULL
) {
962 error_propagate(errp
, local_err
);
966 object_property_set_int(OBJECT(cpu
), apic_id
, "apic-id", &local_err
);
967 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
970 error_propagate(errp
, local_err
);
971 object_unref(OBJECT(cpu
));
977 static const char *current_cpu_model
;
979 void pc_hot_add_cpu(const int64_t id
, Error
**errp
)
981 DeviceState
*icc_bridge
;
982 int64_t apic_id
= x86_cpu_apic_id_from_index(id
);
985 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
989 if (cpu_exists(apic_id
)) {
990 error_setg(errp
, "Unable to add CPU: %" PRIi64
991 ", it already exists", id
);
995 if (id
>= max_cpus
) {
996 error_setg(errp
, "Unable to add CPU: %" PRIi64
997 ", max allowed: %d", id
, max_cpus
- 1);
1001 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1002 error_setg(errp
, "Unable to add CPU: %" PRIi64
1003 ", resulting APIC ID (%" PRIi64
") is too large",
1008 icc_bridge
= DEVICE(object_resolve_path_type("icc-bridge",
1009 TYPE_ICC_BRIDGE
, NULL
));
1010 pc_new_cpu(current_cpu_model
, apic_id
, icc_bridge
, errp
);
1013 void pc_cpus_init(const char *cpu_model
, DeviceState
*icc_bridge
)
1017 Error
*error
= NULL
;
1018 unsigned long apic_id_limit
;
1021 if (cpu_model
== NULL
) {
1022 #ifdef TARGET_X86_64
1023 cpu_model
= "qemu64";
1025 cpu_model
= "qemu32";
1028 current_cpu_model
= cpu_model
;
1030 apic_id_limit
= pc_apic_id_limit(max_cpus
);
1031 if (apic_id_limit
> ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1032 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1037 for (i
= 0; i
< smp_cpus
; i
++) {
1038 cpu
= pc_new_cpu(cpu_model
, x86_cpu_apic_id_from_index(i
),
1039 icc_bridge
, &error
);
1041 error_report("%s", error_get_pretty(error
));
1047 /* map APIC MMIO area if CPU has APIC */
1048 if (cpu
&& cpu
->apic_state
) {
1049 /* XXX: what if the base changes? */
1050 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge
), 0,
1051 APIC_DEFAULT_ADDRESS
, 0x1000);
1054 /* tell smbios about cpuid version and features */
1055 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
1058 /* pci-info ROM file. Little endian format */
1059 typedef struct PcRomPciInfo
{
1066 typedef struct PcGuestInfoState
{
1068 Notifier machine_done
;
1072 void pc_guest_info_machine_done(Notifier
*notifier
, void *data
)
1074 PcGuestInfoState
*guest_info_state
= container_of(notifier
,
1077 acpi_setup(&guest_info_state
->info
);
1080 PcGuestInfo
*pc_guest_info_init(ram_addr_t below_4g_mem_size
,
1081 ram_addr_t above_4g_mem_size
)
1083 PcGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1084 PcGuestInfo
*guest_info
= &guest_info_state
->info
;
1087 guest_info
->ram_size_below_4g
= below_4g_mem_size
;
1088 guest_info
->ram_size
= below_4g_mem_size
+ above_4g_mem_size
;
1089 guest_info
->apic_id_limit
= pc_apic_id_limit(max_cpus
);
1090 guest_info
->apic_xrupt_override
= kvm_allows_irq0_override();
1091 guest_info
->numa_nodes
= nb_numa_nodes
;
1092 guest_info
->node_mem
= g_malloc0(guest_info
->numa_nodes
*
1093 sizeof *guest_info
->node_mem
);
1094 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1095 guest_info
->node_mem
[i
] = numa_info
[i
].node_mem
;
1098 guest_info
->node_cpu
= g_malloc0(guest_info
->apic_id_limit
*
1099 sizeof *guest_info
->node_cpu
);
1101 for (i
= 0; i
< max_cpus
; i
++) {
1102 unsigned int apic_id
= x86_cpu_apic_id_from_index(i
);
1103 assert(apic_id
< guest_info
->apic_id_limit
);
1104 for (j
= 0; j
< nb_numa_nodes
; j
++) {
1105 if (test_bit(i
, numa_info
[j
].node_cpu
)) {
1106 guest_info
->node_cpu
[apic_id
] = j
;
1112 guest_info_state
->machine_done
.notify
= pc_guest_info_machine_done
;
1113 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1117 /* setup pci memory address space mapping into system address space */
1118 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1119 MemoryRegion
*pci_address_space
)
1121 /* Set to lower priority than RAM */
1122 memory_region_add_subregion_overlap(system_memory
, 0x0,
1123 pci_address_space
, -1);
1126 void pc_acpi_init(const char *default_dsdt
)
1130 if (acpi_tables
!= NULL
) {
1131 /* manually set via -acpitable, leave it alone */
1135 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, default_dsdt
);
1136 if (filename
== NULL
) {
1137 fprintf(stderr
, "WARNING: failed to find %s\n", default_dsdt
);
1143 arg
= g_strdup_printf("file=%s", filename
);
1145 /* creates a deep copy of "arg" */
1146 opts
= qemu_opts_parse(qemu_find_opts("acpi"), arg
, 0);
1147 g_assert(opts
!= NULL
);
1149 acpi_table_add_builtin(opts
, &err
);
1151 error_report("WARNING: failed to load %s: %s", filename
,
1152 error_get_pretty(err
));
1160 FWCfgState
*xen_load_linux(const char *kernel_filename
,
1161 const char *kernel_cmdline
,
1162 const char *initrd_filename
,
1163 ram_addr_t below_4g_mem_size
,
1164 PcGuestInfo
*guest_info
)
1169 assert(kernel_filename
!= NULL
);
1171 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
1174 load_linux(fw_cfg
, kernel_filename
, initrd_filename
,
1175 kernel_cmdline
, below_4g_mem_size
);
1176 for (i
= 0; i
< nb_option_roms
; i
++) {
1177 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1178 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1179 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1181 guest_info
->fw_cfg
= fw_cfg
;
1185 FWCfgState
*pc_memory_init(MachineState
*machine
,
1186 MemoryRegion
*system_memory
,
1187 ram_addr_t below_4g_mem_size
,
1188 ram_addr_t above_4g_mem_size
,
1189 MemoryRegion
*rom_memory
,
1190 MemoryRegion
**ram_memory
,
1191 PcGuestInfo
*guest_info
)
1194 MemoryRegion
*ram
, *option_rom_mr
;
1195 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1197 PCMachineState
*pcms
= PC_MACHINE(machine
);
1199 assert(machine
->ram_size
== below_4g_mem_size
+ above_4g_mem_size
);
1201 linux_boot
= (machine
->kernel_filename
!= NULL
);
1203 /* Allocate RAM. We allocate it as a single memory region and use
1204 * aliases to address portions of it, mostly for backwards compatibility
1205 * with older qemus that used qemu_ram_alloc().
1207 ram
= g_malloc(sizeof(*ram
));
1208 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1211 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1212 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1213 0, below_4g_mem_size
);
1214 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1215 e820_add_entry(0, below_4g_mem_size
, E820_RAM
);
1216 if (above_4g_mem_size
> 0) {
1217 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1218 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1219 below_4g_mem_size
, above_4g_mem_size
);
1220 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1222 e820_add_entry(0x100000000ULL
, above_4g_mem_size
, E820_RAM
);
1225 if (!guest_info
->has_reserved_memory
&&
1226 (machine
->ram_slots
||
1227 (machine
->maxram_size
> machine
->ram_size
))) {
1228 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1230 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1235 /* initialize hotplug memory address space */
1236 if (guest_info
->has_reserved_memory
&&
1237 (machine
->ram_size
< machine
->maxram_size
)) {
1238 ram_addr_t hotplug_mem_size
=
1239 machine
->maxram_size
- machine
->ram_size
;
1241 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1242 error_report("unsupported amount of memory slots: %"PRIu64
,
1243 machine
->ram_slots
);
1247 pcms
->hotplug_memory_base
=
1248 ROUND_UP(0x100000000ULL
+ above_4g_mem_size
, 1ULL << 30);
1250 if (pcms
->enforce_aligned_dimm
) {
1251 /* size hotplug region assuming 1G page max alignment per slot */
1252 hotplug_mem_size
+= (1ULL << 30) * machine
->ram_slots
;
1255 if ((pcms
->hotplug_memory_base
+ hotplug_mem_size
) <
1257 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1258 machine
->maxram_size
);
1262 memory_region_init(&pcms
->hotplug_memory
, OBJECT(pcms
),
1263 "hotplug-memory", hotplug_mem_size
);
1264 memory_region_add_subregion(system_memory
, pcms
->hotplug_memory_base
,
1265 &pcms
->hotplug_memory
);
1268 /* Initialize PC system firmware */
1269 pc_system_firmware_init(rom_memory
, guest_info
->isapc_ram_fw
);
1271 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1272 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1274 vmstate_register_ram_global(option_rom_mr
);
1275 memory_region_add_subregion_overlap(rom_memory
,
1280 fw_cfg
= bochs_bios_init();
1283 if (guest_info
->has_reserved_memory
&& pcms
->hotplug_memory_base
) {
1284 uint64_t *val
= g_malloc(sizeof(*val
));
1285 *val
= cpu_to_le64(ROUND_UP(pcms
->hotplug_memory_base
, 0x1ULL
<< 30));
1286 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1290 load_linux(fw_cfg
, machine
->kernel_filename
, machine
->initrd_filename
,
1291 machine
->kernel_cmdline
, below_4g_mem_size
);
1294 for (i
= 0; i
< nb_option_roms
; i
++) {
1295 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1297 guest_info
->fw_cfg
= fw_cfg
;
1301 qemu_irq
*pc_allocate_cpu_irq(void)
1303 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1306 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1308 DeviceState
*dev
= NULL
;
1311 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1312 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1313 } else if (isa_bus
) {
1314 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1315 dev
= isadev
? DEVICE(isadev
) : NULL
;
1320 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1322 CPUState
*cpu
= current_cpu
;
1329 static const MemoryRegionOps ioport80_io_ops
= {
1330 .write
= ioport80_write
,
1331 .read
= ioport80_read
,
1332 .endianness
= DEVICE_NATIVE_ENDIAN
,
1334 .min_access_size
= 1,
1335 .max_access_size
= 1,
1339 static const MemoryRegionOps ioportF0_io_ops
= {
1340 .write
= ioportF0_write
,
1341 .read
= ioportF0_read
,
1342 .endianness
= DEVICE_NATIVE_ENDIAN
,
1344 .min_access_size
= 1,
1345 .max_access_size
= 1,
1349 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
1350 ISADevice
**rtc_state
,
1356 DriveInfo
*fd
[MAX_FD
];
1357 DeviceState
*hpet
= NULL
;
1358 int pit_isa_irq
= 0;
1359 qemu_irq pit_alt_irq
= NULL
;
1360 qemu_irq rtc_irq
= NULL
;
1362 ISADevice
*i8042
, *port92
, *vmmouse
, *pit
= NULL
;
1363 qemu_irq
*cpu_exit_irq
;
1364 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
1365 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
1367 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
1368 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
1370 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
1371 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
1374 * Check if an HPET shall be created.
1376 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1377 * when the HPET wants to take over. Thus we have to disable the latter.
1379 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1380 /* In order to set property, here not using sysbus_try_create_simple */
1381 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
1383 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1384 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1387 uint8_t compat
= object_property_get_int(OBJECT(hpet
),
1390 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
1392 qdev_init_nofail(hpet
);
1393 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
1395 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
1396 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
1399 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
1400 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
1403 *rtc_state
= rtc_init(isa_bus
, 2000, rtc_irq
);
1405 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1407 if (!xen_enabled()) {
1408 if (kvm_irqchip_in_kernel()) {
1409 pit
= kvm_pit_init(isa_bus
, 0x40);
1411 pit
= pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
1414 /* connect PIT to output control line of the HPET */
1415 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
1417 pcspk_init(isa_bus
, pit
);
1420 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1421 if (serial_hds
[i
]) {
1422 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
1426 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1427 if (parallel_hds
[i
]) {
1428 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
1432 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1433 i8042
= isa_create_simple(isa_bus
, "i8042");
1434 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1436 vmport_init(isa_bus
);
1437 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
1442 DeviceState
*dev
= DEVICE(vmmouse
);
1443 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
1444 qdev_init_nofail(dev
);
1446 port92
= isa_create_simple(isa_bus
, "port92");
1447 port92_init(port92
, &a20_line
[1]);
1449 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1450 DMA_init(0, cpu_exit_irq
);
1452 for(i
= 0; i
< MAX_FD
; i
++) {
1453 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1455 *floppy
= fdctrl_init_isa(isa_bus
, fd
);
1458 void pc_nic_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1462 for (i
= 0; i
< nb_nics
; i
++) {
1463 NICInfo
*nd
= &nd_table
[i
];
1465 if (!pci_bus
|| (nd
->model
&& strcmp(nd
->model
, "ne2k_isa") == 0)) {
1466 pc_init_ne2k_isa(isa_bus
, nd
);
1468 pci_nic_init_nofail(nd
, pci_bus
, "e1000", NULL
);
1473 void pc_pci_device_init(PCIBus
*pci_bus
)
1478 max_bus
= drive_get_max_bus(IF_SCSI
);
1479 for (bus
= 0; bus
<= max_bus
; bus
++) {
1480 pci_create_simple(pci_bus
, -1, "lsi53c895a");
1484 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
1490 if (kvm_irqchip_in_kernel()) {
1491 dev
= qdev_create(NULL
, "kvm-ioapic");
1493 dev
= qdev_create(NULL
, "ioapic");
1496 object_property_add_child(object_resolve_path(parent_name
, NULL
),
1497 "ioapic", OBJECT(dev
), NULL
);
1499 qdev_init_nofail(dev
);
1500 d
= SYS_BUS_DEVICE(dev
);
1501 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
1503 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
1504 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1508 static void pc_generic_machine_class_init(ObjectClass
*oc
, void *data
)
1510 MachineClass
*mc
= MACHINE_CLASS(oc
);
1511 QEMUMachine
*qm
= data
;
1513 mc
->family
= qm
->family
;
1514 mc
->name
= qm
->name
;
1515 mc
->alias
= qm
->alias
;
1516 mc
->desc
= qm
->desc
;
1517 mc
->init
= qm
->init
;
1518 mc
->reset
= qm
->reset
;
1519 mc
->hot_add_cpu
= qm
->hot_add_cpu
;
1520 mc
->kvm_type
= qm
->kvm_type
;
1521 mc
->block_default_type
= qm
->block_default_type
;
1522 mc
->units_per_default_bus
= qm
->units_per_default_bus
;
1523 mc
->max_cpus
= qm
->max_cpus
;
1524 mc
->no_serial
= qm
->no_serial
;
1525 mc
->no_parallel
= qm
->no_parallel
;
1526 mc
->use_virtcon
= qm
->use_virtcon
;
1527 mc
->use_sclp
= qm
->use_sclp
;
1528 mc
->no_floppy
= qm
->no_floppy
;
1529 mc
->no_cdrom
= qm
->no_cdrom
;
1530 mc
->no_sdcard
= qm
->no_sdcard
;
1531 mc
->is_default
= qm
->is_default
;
1532 mc
->default_machine_opts
= qm
->default_machine_opts
;
1533 mc
->default_boot_order
= qm
->default_boot_order
;
1534 mc
->default_display
= qm
->default_display
;
1535 mc
->compat_props
= qm
->compat_props
;
1536 mc
->hw_version
= qm
->hw_version
;
1539 void qemu_register_pc_machine(QEMUMachine
*m
)
1541 char *name
= g_strconcat(m
->name
, TYPE_MACHINE_SUFFIX
, NULL
);
1544 .parent
= TYPE_PC_MACHINE
,
1545 .class_init
= pc_generic_machine_class_init
,
1546 .class_data
= (void *)m
,
1553 static int pc_dimm_count(Object
*obj
, void *opaque
)
1555 int *count
= opaque
;
1557 if (object_dynamic_cast(obj
, TYPE_PC_DIMM
)) {
1561 object_child_foreach(obj
, pc_dimm_count
, opaque
);
1565 static int pc_existing_dimms_capacity(Object
*obj
, void *opaque
)
1567 Error
*local_err
= NULL
;
1568 uint64_t *size
= opaque
;
1570 if (object_dynamic_cast(obj
, TYPE_PC_DIMM
)) {
1571 (*size
) += object_property_get_int(obj
, PC_DIMM_SIZE_PROP
, &local_err
);
1574 qerror_report_err(local_err
);
1575 error_free(local_err
);
1580 object_child_foreach(obj
, pc_dimm_count
, opaque
);
1584 static void pc_dimm_plug(HotplugHandler
*hotplug_dev
,
1585 DeviceState
*dev
, Error
**errp
)
1588 HotplugHandlerClass
*hhc
;
1589 Error
*local_err
= NULL
;
1590 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1591 MachineState
*machine
= MACHINE(hotplug_dev
);
1592 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
1593 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
1594 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
1595 uint64_t existing_dimms_capacity
= 0;
1596 uint64_t align
= TARGET_PAGE_SIZE
;
1599 addr
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
, &local_err
);
1604 if (memory_region_get_alignment(mr
) && pcms
->enforce_aligned_dimm
) {
1605 align
= memory_region_get_alignment(mr
);
1608 addr
= pc_dimm_get_free_addr(pcms
->hotplug_memory_base
,
1609 memory_region_size(&pcms
->hotplug_memory
),
1610 !addr
? NULL
: &addr
, align
,
1611 memory_region_size(mr
), &local_err
);
1616 if (pc_existing_dimms_capacity(OBJECT(machine
), &existing_dimms_capacity
)) {
1617 error_setg(&local_err
, "failed to get total size of existing DIMMs");
1621 if (existing_dimms_capacity
+ memory_region_size(mr
) >
1622 machine
->maxram_size
- machine
->ram_size
) {
1623 error_setg(&local_err
, "not enough space, currently 0x%" PRIx64
1624 " in use of total 0x" RAM_ADDR_FMT
,
1625 existing_dimms_capacity
, machine
->maxram_size
);
1629 object_property_set_int(OBJECT(dev
), addr
, PC_DIMM_ADDR_PROP
, &local_err
);
1633 trace_mhp_pc_dimm_assigned_address(addr
);
1635 slot
= object_property_get_int(OBJECT(dev
), PC_DIMM_SLOT_PROP
, &local_err
);
1640 slot
= pc_dimm_get_free_slot(slot
== PC_DIMM_UNASSIGNED_SLOT
? NULL
: &slot
,
1641 machine
->ram_slots
, &local_err
);
1645 object_property_set_int(OBJECT(dev
), slot
, PC_DIMM_SLOT_PROP
, &local_err
);
1649 trace_mhp_pc_dimm_assigned_slot(slot
);
1651 if (!pcms
->acpi_dev
) {
1652 error_setg(&local_err
,
1653 "memory hotplug is not enabled: missing acpi device");
1657 if (kvm_enabled() && !kvm_has_free_slot(machine
)) {
1658 error_setg(&local_err
, "hypervisor has no free memory slots left");
1662 memory_region_add_subregion(&pcms
->hotplug_memory
,
1663 addr
- pcms
->hotplug_memory_base
, mr
);
1664 vmstate_register_ram(mr
, dev
);
1666 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1667 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1669 error_propagate(errp
, local_err
);
1672 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
1673 DeviceState
*dev
, Error
**errp
)
1675 HotplugHandlerClass
*hhc
;
1676 Error
*local_err
= NULL
;
1677 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
1679 if (!dev
->hotplugged
) {
1683 if (!pcms
->acpi_dev
) {
1684 error_setg(&local_err
,
1685 "cpu hotplug is not enabled: missing acpi device");
1689 hhc
= HOTPLUG_HANDLER_GET_CLASS(pcms
->acpi_dev
);
1690 hhc
->plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
1695 /* increment the number of CPUs */
1696 rtc_set_memory(pcms
->rtc
, 0x5f, rtc_get_memory(pcms
->rtc
, 0x5f) + 1);
1698 error_propagate(errp
, local_err
);
1701 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1702 DeviceState
*dev
, Error
**errp
)
1704 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
1705 pc_dimm_plug(hotplug_dev
, dev
, errp
);
1706 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1707 pc_cpu_plug(hotplug_dev
, dev
, errp
);
1711 static HotplugHandler
*pc_get_hotpug_handler(MachineState
*machine
,
1714 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1716 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
1717 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
1718 return HOTPLUG_HANDLER(machine
);
1721 return pcmc
->get_hotplug_handler
?
1722 pcmc
->get_hotplug_handler(machine
, dev
) : NULL
;
1726 pc_machine_get_hotplug_memory_region_size(Object
*obj
, Visitor
*v
, void *opaque
,
1727 const char *name
, Error
**errp
)
1729 PCMachineState
*pcms
= PC_MACHINE(obj
);
1730 int64_t value
= memory_region_size(&pcms
->hotplug_memory
);
1732 visit_type_int(v
, &value
, name
, errp
);
1735 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1736 void *opaque
, const char *name
,
1739 PCMachineState
*pcms
= PC_MACHINE(obj
);
1740 uint64_t value
= pcms
->max_ram_below_4g
;
1742 visit_type_size(v
, &value
, name
, errp
);
1745 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
1746 void *opaque
, const char *name
,
1749 PCMachineState
*pcms
= PC_MACHINE(obj
);
1750 Error
*error
= NULL
;
1753 visit_type_size(v
, &value
, name
, &error
);
1755 error_propagate(errp
, error
);
1758 if (value
> (1ULL << 32)) {
1759 error_set(&error
, ERROR_CLASS_GENERIC_ERROR
,
1760 "Machine option 'max-ram-below-4g=%"PRIu64
1761 "' expects size less than or equal to 4G", value
);
1762 error_propagate(errp
, error
);
1766 if (value
< (1ULL << 20)) {
1767 error_report("Warning: small max_ram_below_4g(%"PRIu64
1768 ") less than 1M. BIOS may not work..",
1772 pcms
->max_ram_below_4g
= value
;
1775 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, void *opaque
,
1776 const char *name
, Error
**errp
)
1778 PCMachineState
*pcms
= PC_MACHINE(obj
);
1779 OnOffAuto vmport
= pcms
->vmport
;
1781 visit_type_OnOffAuto(v
, &vmport
, name
, errp
);
1784 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, void *opaque
,
1785 const char *name
, Error
**errp
)
1787 PCMachineState
*pcms
= PC_MACHINE(obj
);
1789 visit_type_OnOffAuto(v
, &pcms
->vmport
, name
, errp
);
1792 static bool pc_machine_get_aligned_dimm(Object
*obj
, Error
**errp
)
1794 PCMachineState
*pcms
= PC_MACHINE(obj
);
1796 return pcms
->enforce_aligned_dimm
;
1799 static void pc_machine_initfn(Object
*obj
)
1801 PCMachineState
*pcms
= PC_MACHINE(obj
);
1803 object_property_add(obj
, PC_MACHINE_MEMHP_REGION_SIZE
, "int",
1804 pc_machine_get_hotplug_memory_region_size
,
1805 NULL
, NULL
, NULL
, NULL
);
1806 pcms
->max_ram_below_4g
= 1ULL << 32; /* 4G */
1807 object_property_add(obj
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
1808 pc_machine_get_max_ram_below_4g
,
1809 pc_machine_set_max_ram_below_4g
,
1812 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
1813 object_property_add(obj
, PC_MACHINE_VMPORT
, "OnOffAuto",
1814 pc_machine_get_vmport
,
1815 pc_machine_set_vmport
,
1818 pcms
->enforce_aligned_dimm
= true;
1819 object_property_add_bool(obj
, PC_MACHINE_ENFORCE_ALIGNED_DIMM
,
1820 pc_machine_get_aligned_dimm
,
1824 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
1826 MachineClass
*mc
= MACHINE_CLASS(oc
);
1827 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
1828 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1830 pcmc
->get_hotplug_handler
= mc
->get_hotplug_handler
;
1831 mc
->get_hotplug_handler
= pc_get_hotpug_handler
;
1832 hc
->plug
= pc_machine_device_plug_cb
;
1835 static const TypeInfo pc_machine_info
= {
1836 .name
= TYPE_PC_MACHINE
,
1837 .parent
= TYPE_MACHINE
,
1839 .instance_size
= sizeof(PCMachineState
),
1840 .instance_init
= pc_machine_initfn
,
1841 .class_size
= sizeof(PCMachineClass
),
1842 .class_init
= pc_machine_class_init
,
1843 .interfaces
= (InterfaceInfo
[]) {
1844 { TYPE_HOTPLUG_HANDLER
},
1849 static void pc_machine_register_types(void)
1851 type_register_static(&pc_machine_info
);
1854 type_init(pc_machine_register_types
)